WO2023089958A1 - Élément d'imagerie à semi-conducteurs - Google Patents

Élément d'imagerie à semi-conducteurs Download PDF

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Publication number
WO2023089958A1
WO2023089958A1 PCT/JP2022/035881 JP2022035881W WO2023089958A1 WO 2023089958 A1 WO2023089958 A1 WO 2023089958A1 JP 2022035881 W JP2022035881 W JP 2022035881W WO 2023089958 A1 WO2023089958 A1 WO 2023089958A1
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Prior art keywords
transistor
voltage
capacitor
switch
amplifier
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PCT/JP2022/035881
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English (en)
Japanese (ja)
Inventor
裕介 池田
パリット カンチャナウィローグン
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2023089958A1 publication Critical patent/WO2023089958A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present disclosure relates to solid-state imaging devices.
  • a single-slope ADC Analog to Digital Converter
  • a current source is generally connected to the node on the installation side of the vertical signal line wired along the column, and the analog signal from this node is input to the ADC and converted to a digital signal.
  • solid-state imaging devices are being researched in which an amplifier is inserted between the node between the vertical signal line and the current source and the ADC.
  • the voltage of the analog signal is amplified by inserting an amplifier.
  • this amplifier it is necessary to provide a power supply on the power supply side of the amplifier in addition to the current source on the installation side of the vertical signal line.
  • the addition of the current source on the power supply side may increase the power consumption compared to the case where the voltage is not amplified.
  • Research is being conducted to suppress this increase in power consumption and shorten the settling time, but there is the problem that the amplifier output voltage changes depending on the DC voltage level (reset voltage level) of the input signal from the pixel. Occur. Therefore, when the reset level differs for each pixel, it becomes fixed pattern noise. Also, if each column circuit has an offset calibration mechanism, it affects the accuracy of calibration.
  • the present disclosure provides a solid-state imaging device that suppresses the above offset.
  • a solid-state imaging device includes a pixel circuit, a first transistor, an input-side current source, a second transistor, an amplifier, a first capacitor, and a first switch.
  • a pixel circuit generates an input voltage by photoelectric conversion.
  • the first transistor receives the input voltage from its source and outputs a voltage corresponding to the voltage between the source and gate from its drain.
  • the input-side current source is connected to a reference node of a predetermined reference voltage and supplies a predetermined current.
  • the second transistor is cascode-connected to an output-side current source that determines the potential of the amplifier output node according to the output of the first transistor, and to transistors of the output-side current source.
  • the amplifier amplifies the voltage at the amplifier output, comprises a third transistor and a fourth transistor, and outputs an amplified voltage from a node between the third transistor and the fourth transistor.
  • a first capacitor is connected between the gate of the third transistor and the amplifier output node.
  • a first switch supplies an output-side reference voltage between the gate of the third transistor and the first capacitor.
  • the output-side current source includes a fifth transistor having a source connected to a power supply voltage and a gate to which a bias voltage is applied, a source connected to the drain of the fifth transistor, and a drain connected to the amplifier output node. , and a sixth transistor having a cascode control voltage applied to its gate.
  • the bias voltage is applied through a second switch, one terminal is connected between the second switch and the gate of the fifth transistor, and the other terminal is connected to the power supply voltage. and a second capacitor.
  • the second switch may be connected to the drain of the sixth transistor, and the potential of the drain of the sixth transistor may be applied to the gate of the fifth transistor as a bias voltage.
  • a feedback circuit connecting between the amplifier output node and the gate of the first transistor may be provided.
  • a third capacitor, one end of which is connected to the first transistor, and the third capacitor a third switch connected between the other end and an input-side reference voltage; and a fourth switch connected between the other end of the third capacitor and the amplifier output node.
  • a feedback circuit connecting between the amplifier output node and the gate of the first transistor may be provided.
  • a third capacitor one end of which is connected to the first transistor, and the third capacitor a fifth switch connected between the other end and an output node that outputs the amplified voltage; and a sixth switch connected between the other end of the third capacitor and the amplifier output node. You may have more.
  • a solid-state imaging device includes a pixel circuit, a first transistor, an input-side current source, a second transistor, and a feedback circuit.
  • a pixel circuit generates an input voltage by photoelectric conversion.
  • the first transistor receives the input voltage from its source and outputs a voltage corresponding to the voltage between the source and gate from its drain.
  • the input-side current source is connected to a reference node of a predetermined reference voltage and supplies a predetermined current.
  • a second transistor is cascode-connected with an output current source and an output current source transistor that determines the potential of the amplifier output node according to the output of the first transistor.
  • the feedback circuit is a circuit connecting between the amplifier output node and the gate of the first transistor, and includes a third capacitor, a third switch, a fourth switch, a fourth capacitor, and a seventh switch. and an eighth switch.
  • a third capacitor has one end connected to the first transistor.
  • a third switch is connected between the other end of the third capacitor and an input-side reference voltage.
  • a fourth switch is connected between the other end of the third capacitor and the amplifier output node, turns on at the same timing as the third switch, and turns off at a different timing.
  • a fourth capacitor has one end connected to the first transistor.
  • a seventh switch is connected between the other end of the fourth capacitor and the input-side reference voltage.
  • An eighth switch is connected between the other end of the fourth capacitor and the amplifier output node.
  • the amplifier may further include an amplifier that amplifies the voltage at the amplifier output, includes a third transistor and a fourth transistor, and outputs an amplified voltage from a node between the third transistor and the fourth transistor.
  • a solid-state imaging device includes a pixel circuit, a first transistor, an input-side current source, a second transistor, a ninth switch, and a feedback circuit.
  • a pixel circuit generates an input voltage by photoelectric conversion.
  • the first transistor receives the input voltage from its source and outputs a voltage corresponding to the voltage between the source and gate from its drain.
  • the input-side current source is connected to a reference node of a predetermined reference voltage and supplies a predetermined current.
  • a second transistor is cascode-connected with an output current source and an output current source transistor that determines the potential of the amplifier output node according to the output of the first transistor.
  • a ninth switch is connected between the gate and the drain of the first transistor.
  • the feedback circuit is a feedback circuit connecting between the amplifier output node and the gate of the first transistor, and includes a third capacitor, a third switch, a fourth capacitor, a seventh switch, and an eighth switch. And prepare.
  • a third capacitor has one end connected to the first transistor.
  • a third switch is connected between the other end of the third capacitor and an input-side reference voltage.
  • a fourth capacitor has one end connected to the first transistor.
  • a seventh switch is connected between the other end of the fourth capacitor and the input-side reference voltage.
  • An eighth switch is connected between the other end of the fourth capacitor and the amplifier output node.
  • the output-side current source includes a fifth transistor having a source connected to a power supply voltage and a gate to which a bias voltage is applied, and a source connected to the drain of the fifth transistor and a drain connected to the amplifier output node. a sixth transistor connected and having a gate to which a cascode control voltage is applied.
  • the solid-state imaging device further includes a second switch that is connected to the drain of the sixth transistor and applies the potential of the drain of the sixth transistor as a bias voltage to the gate of the fifth transistor.
  • An amplifier that amplifies the voltage at the amplifier output may further include a third transistor and a fourth transistor, and outputting an amplified voltage from a node between the third transistor and the fourth transistor.
  • a solid-state imaging device includes a pixel circuit, a first transistor, an input-side current source, a second transistor, and a period circuit.
  • a pixel circuit generates an input voltage by photoelectric conversion.
  • the first transistor receives the input voltage from its source and outputs a voltage corresponding to the voltage between the source and gate from its drain.
  • the input-side current source is connected to a reference node of a predetermined reference voltage and supplies a predetermined current.
  • a second transistor is cascode-connected with an output current source and an output current source transistor that determines the potential of the amplifier output node according to the output of the first transistor.
  • the feedback circuit is a circuit connecting between the amplifier output node and the gate of the first transistor, and includes a third capacitor, a third switch, a fourth switch, a fourth capacitor, and a seventh switch. and an eighth switch.
  • a third capacitor has one end connected to the first transistor.
  • a third switch is connected between the other end of the third capacitor and an input-side reference voltage.
  • a fourth switch is connected between the other end of the third capacitor and the amplifier output node, turns on at the same timing as the third switch, and turns off at a different timing.
  • a fourth capacitor has one end connected to the first transistor.
  • a seventh switch is connected between the other end of the fourth capacitor and the input-side reference voltage.
  • An eighth switch is connected between the other end of the fourth capacitor and the amplifier output node. and a seventh transistor connected between the amplifier output node and a power supply voltage, the seventh transistor applying a voltage for reset speed-up control to the amplifier output node.
  • FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to one embodiment
  • FIG. FIG. 2 is a diagram showing an example of a configuration of a laminated structure of an imaging element according to one embodiment
  • 1 is a diagram showing an example of the configuration of a solid-state imaging device according to one embodiment
  • FIG. 3 is a diagram showing an example of a pixel configuration according to one embodiment
  • FIG. 2 is a diagram showing an example of a constant current source circuit according to one embodiment;
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a timing chart of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a timing chart of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a timing chart of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing
  • FIG. 4 is a diagram showing an example of a timing chart of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a timing chart of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a timing chart of a column amplifier according to one embodiment
  • FIG. 4 is a diagram showing an example of a column amplifier according to one embodiment
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system
  • FIG. FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
  • FIG. 1 is a block diagram showing an example of the configuration of an imaging device 1 according to one embodiment.
  • the imaging device 1 is a device that captures image data (including frame data in moving images), and includes an optical system 100, a solid-state imaging device 20, and a processing circuit 120.
  • the imaging device 1 also includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180.
  • the imaging device 1 may be a solid-state imaging device.
  • the imaging device 1 may be implemented in, as non-limiting examples, a digital camera such as a digital still camera, a terminal such as a smartphone having an imaging function, a personal computer, or an in-vehicle camera.
  • a digital camera such as a digital still camera
  • a terminal such as a smartphone having an imaging function
  • a personal computer or an in-vehicle camera.
  • the optical system 100 controls the light from the subject and guides it to the pixel area of the solid-state imaging device 20.
  • Optical system 100 comprises, for example, a lens and an aperture.
  • the solid-state image sensor 20 synchronizes with the vertical synchronization signal, acquires an analog signal based on the intensity of the light received by photoelectric conversion, converts it to a digital image signal by an ADC (Analog to Digital Converter), and outputs it.
  • the vertical synchronizing signal is a periodic signal with a predetermined frequency that indicates the timing of imaging.
  • the solid-state imaging device 20 outputs the generated image data to the processing circuit 120 via the signal line 190 .
  • the processing circuit 120 performs predetermined signal processing on the image data output from the solid-state imaging device 20.
  • This processing circuit 120 outputs the processed image via bus 150 to a suitable component, eg frame memory 160 or storage 170 .
  • the processing circuit 120 may be provided in the same chip as the solid-state image sensor 20, or may be provided in a chip different from the solid-state image sensor 20. Also, the processing circuit 120 may be partly provided in the same chip as the solid-state imaging device 20 and other parts may be provided in a different chip.
  • the display unit 130 displays image data.
  • the display unit 130 may be, as non-limiting examples, a liquid crystal panel or an organic EL (Electro Luminescence) panel.
  • the operation unit 140 generates an operation signal based on the user's operation.
  • the operation unit 140 includes, as non-limiting examples, input interfaces such as a touch panel, keyboard, mouse, and microphone.
  • the bus 150 is a path shared by the optical system 100, the solid-state image pickup device 20, the processing circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other. .
  • the frame memory 160 temporarily stores, for example, image data for processing.
  • the storage unit 170 stores various data such as image data.
  • an executable file or program of the software may be stored in the storage unit 170 .
  • the power supply unit 180 supplies power to the solid-state imaging device 20, the processing circuit 120, the display unit 130, and so on.
  • FIG. 2 is a diagram showing an example of the laminated structure of the solid-state imaging device 20 according to one embodiment.
  • the solid-state imaging device 20 includes a pixel layer 22 and a circuit layer 24.
  • the pixel layer 22 and the circuit layer 24 are constructed as stacked semiconductor layers. These layers are electrically connected through connections such as vias. Instead of vias, they may be connected by Cu--Cu bonds, micro-bumps, as non-limiting examples.
  • the laminated structure is not limited to the example in Fig. 2.
  • it may be configured with three or more layers.
  • a part of the pixel layer 22 may be provided with a circuit.
  • FIG. 3 is a block diagram showing a non-limiting configuration example of the solid-state imaging device 20 according to one embodiment.
  • the solid-state imaging device 20 includes a pixel array 200, a line selection circuit 210, a DAC (Digital to Analog Converter) 220, a timing control circuit 230, a constant current source circuit 30, an ADC 240, a line transfer circuit 250, An image processing circuit 260 is provided.
  • DAC Digital to Analog Converter
  • a plurality of pixels 202 including pixel circuits are arranged in a two-dimensional lattice.
  • a set of pixels 202 arranged horizontally in the drawing is referred to as a row (line)
  • a set of pixels 202 arranged vertically to the horizontal direction is referred to as a column (column).
  • lines and columns are defined as described above for the sake of explanation in the drawings, the definitions of lines and columns are not limited to this.
  • the pixel 202 includes at least a light receiving element and a circuit for outputting at appropriate timing the voltage or current output by the light receiving element through photoelectric conversion. Also, the pixel 202 may have an optical system such as a microlens that appropriately guides light to each light receiving element.
  • the pixels 202 generate analog pixel signals through photoelectric conversion under the control of the line selection circuit 210 . Each pixel 202 outputs a pixel signal to the constant current source circuit 30 via the vertical signal line 204 .
  • the line selection circuit 210 sequentially selects and drives the lines, and outputs analog pixel signals to the ADC 240 via the constant current source circuit 30.
  • DAC 220 generates a reference signal by DA (Digital to Analog) conversion and supplies it to ADC 240.
  • a reference signal as a non-limiting example, a signal such as a sawtooth wave, a square wave, or the like may be used.
  • the timing control circuit 230 controls the operation timing of each of the line selection circuit 210, DAC 220, constant current source circuit 30, ADC 240 and line transfer circuit 250 in synchronization with the vertical synchronization signal Vsync.
  • the ADC 240 uses the reference signal output by the DAC 220 to convert the analog input signal into a digital signal for each column.
  • ADC 240 supplies digital signals to image processing circuit 260 under the control of line transfer circuit 250 .
  • the line transfer circuit 250 controls the ADC 240 to sequentially output digital signals.
  • the image processing circuit 260 performs predetermined image processing on image data in which digital signals are arranged. This image processing circuit 260 outputs the processed image data to the processing circuit 120 .
  • the above-described circuits in the solid-state imaging device 20 are appropriately dispersed and arranged in the pixel layer 22 and the circuit layer 24.
  • the pixel array 200 may be placed on the pixel layer 22 and circuits other than the pixel array 200, such as the ADC 240, may be placed on the circuit layer 24.
  • the circuits arranged in each of the pixel layer 22 and the circuit layer 24 are not limited to this combination.
  • the pixel array 200, the constant current source circuit 30, and the comparator in the ADC 240 can be placed on the pixel layer 22, and the other circuits can be placed on the circuit layer 24.
  • FIG. 4 is a circuit diagram showing an example of a pixel 202 according to one embodiment.
  • the pixel 202 includes a photoelectric conversion element 205, a transfer transistor 206, a reset transistor 207, an amplification transistor 208, and a selection transistor 209.
  • the photoelectric conversion element 205 photoelectrically converts incident light to generate electric charges.
  • the photoelectric conversion element 205 includes, as non-limiting examples, a photodiode and an organic photoelectric conversion film.
  • the transfer transistor 206 is a transistor that transfers charges from the photoelectric conversion element 205 to the floating diffusion layer FD according to the transfer signal TRG from the line selection circuit 210.
  • the floating diffusion layer FD is a layer for accumulating the charge output from the photoelectric conversion element 205 and generating a voltage according to the amount of charge.
  • the voltage by the floating diffusion layer FD is reset and set at appropriate timing, and an appropriate analog signal is output through the vertical signal line 204 according to the height of the voltage.
  • the reset transistor 207 initializes the charges held in the floating diffusion layer FD according to the reset signal RST from the line selection circuit 210.
  • the amplification transistor 208 outputs a current of magnitude based on the voltage applied to the gate from the floating diffusion layer FD.
  • the selection transistor 209 is a transistor that outputs an amplified voltage signal as the pixel signal SIG according to the selection signal from the line selection circuit 210 .
  • N integer
  • the pixel signal of the n-th (n: integer of [1, N]) column is applied to the vertical signal line at the timing when the selection transistor 209 turns on.
  • 204-n to the constant current source circuit 30.
  • circuit of the pixel 202 may be configured as a circuit that is not limited to the one illustrated in FIG. 4 as long as it is a circuit that can appropriately generate pixel signals by photoelectric conversion.
  • FIG. 5 is a block diagram showing a non-limiting example of the constant current source circuit 30 according to one embodiment.
  • a column amplifier 300 is arranged for each column in the constant current source circuit 30 . That is, the constant current source circuit 30 has N column amplifiers 300 .
  • a pixel signal of the corresponding column is input to the n-th column amplifier 300-n via the vertical signal line 204-n.
  • the column amplifier 300-n amplifies the voltage of the pixel signal and outputs it to the ADC 240 via the signal line 302-n.
  • the column amplifier 300 is initialized at the timing when the auto-zero signal AZ from the timing control circuit 230 is input.
  • FIG. 6 is a block diagram illustrating a non-limiting example ADC 240 according to one embodiment.
  • a column ADC 241 and a latch circuit 246 are arranged for each column of the ADC 240 . That is, ADC 240 comprises N column ADCs 241 and latch circuits 246 respectively.
  • the column ADC 241 is a circuit that converts analog pixel signals into digital signals.
  • This column ADC 241 comprises capacitors 242 , 243 , a comparator 244 and a counter 245 .
  • CDS Correlated Double Sampling
  • processing may also be performed by the column ADC 241 .
  • the comparator 244 is a comparator that compares the reference signal output from the DAC 220 and the pixel signal of the corresponding column.
  • the comparator 244 has a pair of input terminals, one of which receives the reference signal via the capacitor 242 and the other receives the pixel signal via the capacitor 243 .
  • Comparator 244 supplies the comparison result to counter 245 .
  • the counter 245 counts the count value until the comparison result is reversed.
  • the counter 245 outputs a signal indicating the count value to the latch circuit 246 as a digital signal.
  • the latch circuit 246 is a circuit that holds digital signals.
  • the latch circuit 246 outputs the digital signal to the image processing circuit 260 in synchronization with the sync signal output from the line transfer circuit 250 .
  • Fig. 7 is a diagram showing another example of ADC 240. As shown in FIG. 7, in column ADC 241, capacitors 242 and 243 can be connected in parallel to one of the input terminals (inverting input terminal or non-inverting input terminal) of comparator 244. This also allows the input amplitude of comparator 244 to be reduced compared to ADC 240 of FIG.
  • FIG. 8 is a circuit diagram showing one configuration example of the column amplifier 300 according to one embodiment
  • FIG. 9 is a diagram showing one example of a timing chart in the column amplifier 300 of FIG.
  • the column amplifier 300 includes transistors MP01, MP02, MP03, MN01, MN02, MN03, MN04, MN05, capacitors C01, C02, C03, C04, C05, C06, C07, C08, C09, and switches Sw01, Sw02, Sw03. , Sw04, Sw05, Sw06, Sw07, Sw08, and Sw09 are provided.
  • the column amplifier 300 is a circuit that appropriately amplifies the signals output from the pixels 202 belonging to each column and outputs them to the column ADCs 241 corresponding to the columns of the ADCs 240, as described above.
  • the transistor when the transistor is indicated as MNxx, it may be an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor), and when MPxx is indicated, it may be a p-channel It may be a MOSFET.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • the transistor MP01 is a transistor that controls the signal input to the column amplifier 300.
  • Transistor MP01 has a source connected to vertical signal line 204 and a drain connected to a reference voltage (eg, ground voltage) via transistors MN01 and MN02.
  • Pixel 202 generates a pixel signal by photoelectric conversion, and applies this voltage as input voltage Vin to the source of transistor MP01 via vertical signal line 204 .
  • the switch Sw02 is a switch that opens and closes the path between the gate and drain of the transistor MP01 according to the auto-zero signal PAZOUT.
  • a capacitor C01 is placed between the gate of the transistor MP01 and the reference node of the reference voltage. Capacitor C01 holds the potential difference between the Vgate potential and the amplifier output potential.
  • a capacitor C02 is provided between the transistor MP01 and the reference voltage Vss. Capacitor C02 holds the potential of Vgate with respect to reference voltage Vss.
  • Transistors MN01, MN02 and capacitor C03 operate as a reference-side current source that flows current from the drain of transistor MP01 according to bias voltage Vbn. These elements combine to act as a current source. Therefore, the combination is not limited as long as it operates appropriately as a current source.
  • the transistors MP02 and MP03 are connected in series with the power supply voltage. That is, the transistor MP02 has a source connected to the power supply voltage Vdd and a drain connected to the source of the transistor MP03.
  • the transistor MP03 has a source connected to the drain of the transistor MP02 and a drain connected to the amplifier output node.
  • the bias voltage Vbp rectified by the capacitor C07 is applied to the gate of the transistor MP02 at the timing when the switch Sw07 turns on. This transistor MP02 acts as a current source on the power supply side.
  • Transistor MP03 and transistor MN03 share a drain and are cascode-connected. A voltage is applied to the gates of these transistors so that they operate properly as a cascode connection. A voltage Vcp for cascode connection rectified by a capacitor C08 is applied to the gate of the transistor MP03 at the timing when the switch Sw08 turns on. Similarly, the voltage Vcn for cascode connection rectified by the capacitor C05 is applied to the gate of the transistor MN03 at the timing when the switch Sw05 turns on. From a node between these cascode-connected transistors, an output voltage is appropriately controlled by a buffer and output.
  • the switch Sw04 is a switch that controls the reset of the output side of the column amplifier 300 based on the auto-zero signal PAZVR1.
  • switch Sw04 is turned on by auto-zero signal PAZVR1, current flows so that the voltage at one end of capacitor C01 becomes Vr1.
  • the switch Sw03 is a switch that is turned on exclusively with the switch Sw04. For example, as shown in FIG. 9, PAZVR1 and POPD are controlled so that switch Sw03 and switch Sw04 are not turned on at the same timing. For this reason, the switch Sw03 is turned on in the state of being appropriately reset to Vr1, and an appropriate signal is output to the output terminal. That is, it is reset by the auto-zero signal PAZVR1 at the timing before reading the pixel signal, and the reset state is released appropriately at the timing at which the pixel signal is read.
  • the transistors MN04 and MN05 act as buffers (or amplifiers) that amplify the voltage applied to the gate of the transistor MN04 and output it.
  • the transistor MN04 has a drain connected to the power supply voltage Vdd and a source connected to the drain of the transistor MN05.
  • the source of transistor MN05 is connected to reference voltage Vss.
  • a capacitor C06 is provided between the gate of the transistor MN04 and the drains (amplifier output nodes) of the cascode-connected transistors MP03 and MN03.
  • a node between the capacitor C06 and the gate of the transistor MN04 is connected to Vr2 through the switch Sw06.
  • the drain of transistor MN05 is connected to transistor MN04 and the source of transistor MN02, which is the current source in the input stage, via capacitor C04, and the source is connected to reference voltage Vss.
  • a switch Sw09 Connected to the gate of transistor MN05 are a switch Sw09 for applying a driving voltage to boost the output signal and a capacitor C09.
  • a boost voltage VBbst is applied to the gate of transistor MN05 via switch Sw09.
  • the gate potential Vgate of transistor MP01 is reset to Vr1 and Vr2, and appropriate potentials determined by the performance of the capacitor.
  • the switches Sw02, Sw03, and Sw04 are turned off to complete the reset of the transistor MP01. After that, by turning off the switch Sw06, the offset voltage (reset voltage) - (set voltage) and pixel current offset (reset current) - (set current) independent of the reset voltage level of the pixel can be obtained.
  • the offset can be removed by arranging the capacitor between the amplifier and the output stage amplifier.
  • the output level shift and offset removal of the auto-zero switch (switch Sw02) are performed at the timing of reset settling.
  • This offset is stored on capacitor C06 on reset and canceled at the node of Vout on set.
  • an offset can be set in the column amplifier 300 that is independent of pixel reset.
  • FIG. 10 is a circuit diagram showing one configuration example of the column amplifier 300 according to one embodiment
  • FIG. 11 is a diagram showing one example of a timing chart in the column amplifier 300 of FIG.
  • the column amplifier 300 implements the reset to Vr2, which was performed at the output stage in the first embodiment, at the input stage.
  • the column amplifier 300 has a feedback circuit from the output stage to the input stage including a capacitor C10 and a switch Sw10 between the gate of the transistor MP01 and the amplifier output.
  • the feedback circuit further includes a capacitor C11 connected to one end of the voltage VSshsn at a node between the capacitor C10 and the switch Sw10, and a switch Sw11 connected to the potential Vr1 when turned on.
  • the voltage Vgate is reset by turning on the switch Sw02 with the auto-zero signal PAZOUT and then turning it off. Switch the switch Sw11 on and off at the same timing. After switches Sw02, Sw11 have been switched off, signal PF2 switches switch Sw10 from off to on. By switching in this way, the potential of Vout is fixed at the timing of reset settling.
  • offset can be removed by arranging a feedback circuit from the output stage of the amplifier output. Output level shift and autozero signal switch removal occurs at reset. Therefore, as in the first embodiment described above, this offset is stored in capacitor C11 at reset and canceled at the node of Vout at set. As a result, an offset can be set in the column amplifier 300 that is independent of pixel reset. Furthermore, since the load capacitance in the amplifier output can be made smaller than in the first embodiment, it is also possible to achieve faster settling.
  • FIG. 12 is a diagram showing another example of the second embodiment.
  • the output stage buffer amplifier
  • Vout may be output from the output node of the amplifier.
  • FIG. 13 is a circuit diagram showing one configuration example of the column amplifier 300 according to one embodiment
  • FIG. 14 is a diagram showing one example of a timing chart in the column amplifier 300 of FIG.
  • the column amplifier 300 is reset by a switch connecting the gate and drain of the transistor MP01.
  • the potential that serves as the reference for the amplifier output is determined by self-bias.
  • the switches Sw01, Sw05, Sw08, and Sw09 may be turned on at appropriate timing, for example, when the switch Sw13 is turned on, and turned off earlier than when the switch Sw13 is turned off.
  • transistor MN06 is connected to the source of transistor MN03.
  • Transistor MN06 is a transistor provided in parallel with transistor MN02, its source is connected to the drain of transistor MN07 and its gate is shared with the gates of transistors MN01, MN02 and MN07.
  • Transistor MN07 has its source connected to reference voltage Vss. In this configuration, transistors MN06 and MN07 form a current source in the amplifier output stage.
  • Vgate and transistor MP02 are determined according to the autozero signal.
  • switches Sw12 and Sw13 turn on switches Sw04 and Sw10 turn on and switch Sw14 turns off, so the amplifier output is also reset.
  • the level shift of the amplifier output can be performed at the timing of the pixel signal setting from the reset settling.
  • switches Sw12 and Sw13 are turned off and switch Sw14 is turned on.
  • Vgate starts up.
  • Sw04 and Sw10 are turned off and the reset is completed.
  • the Vgate and amplifier output current sources are determined at the timing of pixel reset settling. After that, the amplifier output voltage at reset is fixed. Therefore, an offset voltage (reset voltage) - (set voltage) and a pixel current offset (reset current) - (set current) independent of the pixel reset voltage level are obtained. As a result, it is possible to omit the bias of the current source on the p-channel side (for example, Vpb in FIG. 8).
  • FIG. 15 is a diagram showing another example of the third embodiment. As in the second embodiment described above, the output stage may be omitted.
  • FIG. 16 is a circuit diagram showing one configuration example of the column amplifier 300 according to one embodiment
  • FIG. 17 is a diagram showing one example of a timing chart in the column amplifier 300 of FIG.
  • the column amplifier 300 may perform bias control of the current source of the amplifier output stage of the third embodiment in the configuration including the output stage amplifier of the first embodiment.
  • the switches Sw01, Sw05, Sw08, and Sw09 may be turned on at appropriate timing, for example, when the switch Sw13 is turned on, and turned off earlier than when the switch Sw13 is turned off.
  • the output level shift and switch removal by the auto-zero signal are performed at the timing of reset settling.
  • the offset is stored in capacitor C06 and canceled when the pixel signal is set.
  • the Vgate and amplifier output current sources are determined by the auto-zero signal.
  • the amplifier output is also reset because the switch Sw14 is turned off at the timing when the switches Sw12 and Sw13 are turned on. Then, by turning off the switch Sw06 during reset settling, the amplifier output voltage is fixed. Therefore, an offset voltage (reset voltage) - (set voltage) and a pixel current offset (reset current) - (set current) independent of the pixel reset voltage level are obtained.
  • the transistor MP02 is self-biased, it is possible to reduce the number of circuits connected to the voltage Vr1 compared to the first embodiment.
  • FIG. 18 is a circuit diagram showing one configuration example of the column amplifier 300 according to one embodiment
  • FIG. 19 is a diagram showing one example of a timing chart in the column amplifier 300 of FIG.
  • the column amplifier 300 is configured to feed back the output voltage Vout of the output stage instead of the reference for setting Vr1 in the first embodiment.
  • the level shift of the output and the removal of the switch by the autozel signal are performed at the timing of reset settling.
  • the offset is stored in capacitor C06 and canceled when the pixel signal is set.
  • the Vgate and amplifier output current sources are determined by the auto-zero signal. Since switch Sw15 turns on at the same timing as Vgate is reset, the potential of output voltage Vout can be referenced via capacitor C01. After that, by turning on the switch Sw03, the amplifier output settles to the voltage at the timing when the switch Sw15 is turned on. After that, by turning off the switch Sw06, an offset voltage (reset voltage) - (set voltage) and a pixel current offset (reset current) - (set current) independent of the pixel reset voltage level are obtained.
  • FIG. 20 is a circuit diagram showing one configuration example of the column amplifier 300 according to one embodiment
  • FIG. 21 is a diagram showing one example of a timing chart in the column amplifier 300 of FIG.
  • the column amplifier 300 has a transistor MN08 that performs reset speed-up control on the amplifier output.
  • the transistor MN08 has a drain connected to the power supply voltage Vdd, a source connected to the amplifier output, and a gate to which a voltage Patch for reset speed-up control is applied.
  • Vgate settling time may be insufficient.
  • Vgate is forcibly raised at Vgate reset timing via transistor MN08. As a result, a sufficient settling time can be ensured.
  • Fig. 22 shows a p-channel transistor MP04 that replaces the transistor that controls reset acceleration control.
  • the transistor MP04 has a source connected to the power supply voltage Vdd, a drain connected to the amplifier output, and a gate to which a signal XPatch for controlling reset acceleration control is applied.
  • the signal XPatch may be the signal Patch with the High and Low switched.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display section 12062 and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 24 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 24 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided in the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above.
  • the imaging device 1 in FIG. 1 can be applied to the imaging unit 12031.
  • FIG. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to suppress the power consumption of the column amplifier, so it is possible to reduce the power consumption of the entire vehicle system.
  • the output-side current source is a fifth transistor MP02, the source of which is connected to the supply voltage and the gate of which a bias voltage is applied; a sixth transistor MP03 having a source connected to the drain of the fifth transistor MP02, a drain connected to the amplifier output node, and a gate to which a cascode control voltage is applied;
  • the solid-state imaging device according to (1) comprising:
  • the second switch Sw13 is connected to the drain of the sixth transistor MP03, and applies the potential of the drain of the sixth transistor MP03 as a bias voltage to the gate of the fifth transistor MP02.
  • the solid-state imaging device according to (3) is connected to the drain of the sixth transistor MP03, and applies the potential of the drain of the sixth transistor MP03 as a bias voltage to the gate of the fifth transistor MP02.
  • a feedback circuit connecting between the amplifier output node and the gate of the first transistor MP01, a third capacitor C01, one end of which is connected to the first transistor MP01; a fifth switch Sw15 connected between the other end of the third capacitor C01 and an output node that outputs the amplified voltage; a sixth switch Sw03 connected between the other end of the third capacitor C01 and the amplifier output node;
  • a pixel circuit that generates an input voltage Vin by photoelectric conversion; a first transistor MP01 to which the input voltage is applied from the source and which outputs a voltage corresponding to the voltage between the source and the gate from the drain; input-side current sources MN01 and MN02 connected to a reference node of a predetermined reference voltage and supplying a predetermined current; output-side current sources MP02 and MP03 that determine the potential of the amplifier output node according to the output of the first transistor MP01, and a second transistor MN03 that is cascode-connected to the output-side current source transistors; A feedback circuit connecting between the amplifier output node and the gate of the first transistor MP01, a third capacitor C01, one end of which is connected to the first transistor MP01; a third switch Sw04 connected between the other end of the third capacitor C01 and the input-side reference voltage Vr1; a fourth switch Sw03 connected between the other end of the third capacitor C01 and the amplifier output node, turned on at the same timing as the third switch, and turned off at
  • an amplifier for amplifying the voltage at the amplifier output comprising a third transistor MN04 and a fourth transistor MN05 and outputting an amplified voltage from a node between the third transistor MN04 and the fourth transistor MN05;
  • (9) a pixel circuit that generates an input voltage Vin by photoelectric conversion; a first transistor MP01 to which the input voltage is applied from the source and which outputs a voltage corresponding to the voltage between the source and the gate from the drain; input-side current sources MN01 and MN02 connected to a reference node of a predetermined reference voltage and supplying a predetermined current; output-side current sources MP02 and MP03 that determine the potential of the amplifier output node according to the output of the first transistor MP01, and a second transistor MN03 that is cascode-connected to the output-side current source transistors; a ninth switch Sw12 connected between the gate and drain of the first transistor MP01; A feedback circuit connecting between the amplifier output node and the gate of the first transistor MP01, a third capacitor C01, one end of which is connected to the first transistor MP01; a third switch Sw04 connected between the other end of the third capacitor C01 and the input-side reference voltage Vr1; a fourth capacitor C10, one end of which is connected to the first transistor MP01;
  • (11) a pixel circuit that generates an input voltage Vin by photoelectric conversion; a first transistor MP01 to which the input voltage is applied from the source and which outputs a voltage corresponding to the voltage between the source and the gate from the drain; input-side current sources MN01 and MN02 connected to a reference node of a predetermined reference voltage and supplying a predetermined current; output-side current sources MP02 and MP03 that determine the potential of the amplifier output node according to the output of the first transistor MP01, and a second transistor MN03 that is cascode-connected to the output-side current source transistors; A feedback circuit connecting between the amplifier output node and the gate of the first transistor MP01, a third capacitor C01, one end of which is connected to the first transistor MP01; a third switch Sw04 connected between the other end of the third capacitor C01 and the input-side reference voltage Vr1; a fourth switch Sw03 connected between the other end of the third capacitor C01 and the amplifier output node, turned on at the same timing as the third switch, and turned off at

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Abstract

Le problème décrit par la présente invention concerne un élément d'imagerie à semi-conducteurs avec lequel le décalage est supprimé. La solution selon l'invention concerne un circuit de pixel, un premier et un second transistor, une source de courant côté entrée, un amplificateur, un premier condensateur et un premier commutateur. Le circuit de pixel génère une tension d'entrée par conversion photoélectrique. Dans le premier transistor, la tension d'entrée est appliquée à partir de la source, et une tension correspondant à la tension entre la source et la grille est délivrée à partir du drain. La source de courant côté entrée est connectée à un nœud de référence ayant une tension de référence prescrite, et fournit un courant prescrit. Le deuxième transistor est connecté en cascade à une source de courant côté sortie et à un transistor de la source de courant côté sortie qui détermine le potentiel d'un nœud de sortie de l'amplificateur en fonction de la sortie du premier transistor. L'amplificateur : amplifie la tension de la sortie de l'amplificateur ; comprend un troisième transistor et un quatrième transistor ; et émet une tension amplifiée à partir d'un nœud entre le troisième transistor et le quatrième transistor. Le premier condensateur est connecté entre la grille du troisième transistor et le nœud de sortie d'amplificateur. Le premier commutateur fournit une tension de référence côté sortie entre la grille du troisième transistor et le premier condensateur.
PCT/JP2022/035881 2021-11-22 2022-09-27 Élément d'imagerie à semi-conducteurs WO2023089958A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018021053A1 (fr) * 2016-07-28 2018-02-01 ソニーセミコンダクタソリューションズ株式会社 Élément de capture d'image
WO2021157148A1 (fr) * 2020-02-03 2021-08-12 ソニーセミコンダクタソリューションズ株式会社 Élément de capture d'image à semi-conducteurs et dispositif de capture d'image
WO2022074940A1 (fr) * 2020-10-08 2022-04-14 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs et dispositif d'imagerie
WO2022196079A1 (fr) * 2021-03-15 2022-09-22 ソニーセミコンダクタソリューションズ株式会社 Capteur d'imagerie à semi-conducteurs et dispositif d'imagerie

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018021053A1 (fr) * 2016-07-28 2018-02-01 ソニーセミコンダクタソリューションズ株式会社 Élément de capture d'image
WO2021157148A1 (fr) * 2020-02-03 2021-08-12 ソニーセミコンダクタソリューションズ株式会社 Élément de capture d'image à semi-conducteurs et dispositif de capture d'image
WO2022074940A1 (fr) * 2020-10-08 2022-04-14 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs et dispositif d'imagerie
WO2022196079A1 (fr) * 2021-03-15 2022-09-22 ソニーセミコンダクタソリューションズ株式会社 Capteur d'imagerie à semi-conducteurs et dispositif d'imagerie

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