WO2022004125A1 - Élément d'imagerie à semi-conducteurs, dispositif d'imagerie et procédé de contrôle d'élément d'imagerie à semi-conducteurs - Google Patents

Élément d'imagerie à semi-conducteurs, dispositif d'imagerie et procédé de contrôle d'élément d'imagerie à semi-conducteurs Download PDF

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Publication number
WO2022004125A1
WO2022004125A1 PCT/JP2021/017435 JP2021017435W WO2022004125A1 WO 2022004125 A1 WO2022004125 A1 WO 2022004125A1 JP 2021017435 W JP2021017435 W JP 2021017435W WO 2022004125 A1 WO2022004125 A1 WO 2022004125A1
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Prior art keywords
transistor
source
switch
transistors
current source
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PCT/JP2021/017435
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English (en)
Japanese (ja)
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拓朗 古坂
洋介 植野
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ソニーセミコンダクタソリューションズ株式会社
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Priority to US18/003,183 priority Critical patent/US20230254609A1/en
Priority to DE112021003535.5T priority patent/DE112021003535T5/de
Priority to CN202180044992.6A priority patent/CN116057957A/zh
Publication of WO2022004125A1 publication Critical patent/WO2022004125A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70—Circuitry for compensating brightness variation in the scene
    • H04N23/71—Circuitry for evaluating the brightness variation

Definitions

  • This technology relates to a solid-state image sensor. More specifically, the present invention relates to a solid-state image sensor that performs analog-to-digital conversion using a comparator and a counter, an image pickup device, and a control method for the solid-state image sensor.
  • a single slope type ADC Analog to Digital Converter
  • AD Analog to Digital
  • This single-slope ADC is generally composed of a comparator and a counter that counts based on the comparison result of the comparator.
  • a solid-state image sensor in which a pMOS (p-channel Metal-Oxide-Semiconductor) transistor, a current source, and an inverter are arranged in this comparator has been proposed (see, for example, Patent Document 1).
  • a reference signal is input to the gate of the pMOS transistor, a pixel signal is input to the source via a vertical signal line, and a current source is connected to the drain. Then, the voltage of the connection node of the pMOS transistor and the current source is output to the counter via the inverter as a comparison result of the pixel signal and the reference signal.
  • the power consumption of the pixel circuit is shared by the comparator, so that the power consumption is reduced as compared with the configuration in which the comparator is also provided with the power supply separately from the pixel circuit.
  • the dynamic range of the pixel signal is lower than when they are not connected. Further, as the conductance is increased in order to expand the dynamic range, the noise generated in the current source increases.
  • This technology was created in view of such a situation, and aims to improve the image quality of image data in a solid-state image sensor using a comparator.
  • the present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a current source that generates a constant current and a predetermined lower limit voltage according to the conductance of the current source.
  • a pixel circuit that generates a pixel signal with a high voltage, a comparison circuit that amplifies the pixel signal at a predetermined amplification factor and compares it with a predetermined reference signal, and a control unit that reduces the conductance as the amplification factor increases.
  • It is a solid-state imaging device including a counter that counts and outputs a count value over a period of time until the comparison result of the comparison circuit is inverted, and a control method for the solid-state imaging device. This has the effect of improving the image quality of the image data.
  • the current source may include a plurality of transistors and a switching circuit for switching the connection form of the plurality of transistors. This has the effect of controlling the conductance of the current source.
  • the plurality of transistors refer to the first switch for connecting the connection node of the first and second transistors to a predetermined ground terminal and the comparison circuit for the source of the second transistor.
  • a second switch connecting to the ground terminal and a third switch connecting the source of the second transistor to the ground terminal may be provided. This has the effect that the conductance is controlled in two stages.
  • the plurality of transistors include first, second, third and fourth transistors connected in series with the comparison circuit, and the switching circuit includes the first and first transistors.
  • a first switch that connects the connection node of the two transistors to a predetermined ground terminal, a second switch that connects the connection node of the second and third transistors to the comparison circuit, and the second and third transistors.
  • a third switch that connects the connection node of the above to the ground terminal, a fourth switch that connects the connection node of the third and fourth transistors to the comparison circuit, and a connection node of the third and fourth transistors. It includes a fifth switch connected to the ground terminal, a sixth switch connecting the source of the fourth transistor to the comparison circuit, and a seventh switch connecting the source of the fourth transistor to the ground terminal. You may. This has the effect that the conductance is controlled in three stages.
  • the plurality of transistors include a first transistor having a drain connected to the comparison circuit and a second transistor having a source connected to a predetermined ground terminal, and the switching.
  • the circuit includes a first switch that connects the source of the first transistor to the ground terminal, a second switch that connects the source of the first transistor and the drain of the second transistor, and the second switch.
  • a third switch for connecting the drain of the transistor to the comparison circuit may be provided. This has the effect of suppressing the surge current.
  • the plurality of transistors are the first transistor to which the drain is connected to the comparison circuit, the second and third transistors, and the source to which the source is connected to a predetermined ground terminal.
  • the switching circuit connects a first switch that connects the source of the first transistor to the ground terminal, and the source of the first transistor and the drain of the second transistor.
  • a seventh switch, an eighth switch connecting the source of the third transistor and the drain of the fourth transistor, and a ninth switch connecting the drain of the fourth transistor to the comparison circuit are provided. You may. This has the effect of suppressing the surge current and controlling the conductance in three stages.
  • a bias circuit for generating a constant reference current may be further provided, and the reference current may be copied to the current source. This has the effect of keeping the amount of current constant.
  • an image processing unit for measuring the illuminance based on the image data in which the count values are arranged is further provided, and the control unit controls the amplification factor to a value corresponding to the illuminance. You may. This has the effect of controlling the conductance according to the illuminance.
  • the pixel circuit may be connected to the comparison circuit via a vertical signal line, and the comparison circuit may be inserted between the vertical signal line and the current source. This has the effect that the lower limit voltage becomes a value corresponding to the operating voltage of the comparison circuit and the current source.
  • the pixel circuit may be connected to the comparison circuit via a vertical signal line, and the current source may be connected to the vertical signal line. This has the effect that the lower limit voltage becomes a value corresponding to the operating voltage of the current source.
  • a generator that generates a sawtooth output signal and a source follower transistor that outputs a signal corresponding to the output signal as the reference signal from the source are further provided, and the current source is provided.
  • the in-comparator current source connected to the comparison circuit and the source follower current source connected to the source of the source follower transistor may be provided. This has the effect of increasing the control range of the amplitude of the reference signal.
  • the second aspect of the present technology is a current source that generates a constant current, a pixel circuit that generates a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source, and the pixel signal.
  • a comparison circuit that amplifies with a predetermined amplification factor and compares it with a predetermined reference signal, a control unit that reduces the conductance as the amplification factor increases, and a time until the comparison result of the comparison circuit is inverted.
  • It is an image pickup apparatus including a counter that counts and outputs a count value, and a storage unit that stores image data in which digital signals indicating the count values are arranged. This has the effect of capturing image data with improved image quality.
  • the third aspect of the present technology is that a pixel that outputs a pixel signal according to incident light, a vertical signal line that transmits the pixel signal, and one of a source and a drain are connected to the vertical signal line.
  • the gate comprises a comparator having a transistor that receives a reference signal, and a current source connected to the other of the source and the drain of the transistor, and the current source is a plurality of transistors and a connection form of the plurality of transistors. It is an optical detection device provided with a switching circuit for switching between. This has the effect of improving the image quality of the image data.
  • the plurality of transistors include first and second transistors connected in series with the comparison circuit, and the switching circuit is a connection node of the first and second transistors.
  • a first switch for connecting the source of the second transistor to a predetermined ground terminal, a second switch for connecting the source of the second transistor to the comparison circuit, and a third switch for connecting the source of the second transistor to the ground terminal. May be provided. This has the effect that the conductance is controlled in two stages.
  • the plurality of transistors include first, second, third and fourth transistors connected in series with the comparison circuit, and the switching circuit includes the first and first transistors.
  • a first switch that connects the connection node of the two transistors to a predetermined ground terminal, a second switch that connects the connection node of the second and third transistors to the comparison circuit, and the second and third transistors.
  • a third switch that connects the connection node of the above to the ground terminal, a fourth switch that connects the connection node of the third and fourth transistors to the comparison circuit, and a connection node of the third and fourth transistors. It includes a fifth switch connected to the ground terminal, a sixth switch connecting the source of the fourth transistor to the comparison circuit, and a seventh switch connecting the source of the fourth transistor to the ground terminal. You may. This has the effect that the conductance is controlled in three stages.
  • the plurality of transistors include a first transistor having a drain connected to the comparison circuit and a second transistor having a source connected to a predetermined ground terminal, and the switching.
  • the circuit includes a first switch that connects the source of the first transistor to the ground terminal, a second switch that connects the source of the first transistor and the drain of the second transistor, and the second switch.
  • a third switch for connecting the drain of the transistor to the comparison circuit may be provided. This has the effect of suppressing the surge current.
  • the plurality of transistors are the first transistor to which the drain is connected to the comparison circuit, the second and third transistors, and the source to which the source is connected to a predetermined ground terminal.
  • the switching circuit connects a first switch that connects the source of the first transistor to the ground terminal, and the source of the first transistor and the drain of the second transistor.
  • a seventh switch, an eighth switch connecting the source of the third transistor and the drain of the fourth transistor, and a ninth switch connecting the drain of the fourth transistor to the comparison circuit are provided. You may. This has the effect of suppressing the surge current and controlling the conductance in three stages.
  • Embodiment Example of controlling conductance of a current source in a comparator
  • Second embodiment example of controlling the conductance of the current source in the comparator in three stages
  • Third embodiment example of controlling the conductance of the current source in the comparator and suppressing the surge current
  • Fourth embodiment an example in which the conductance of the current source in the comparator is controlled and a current mirror circuit is used).
  • Fifth Embodiment Example of setting analog gain according to illuminance and controlling conductance of current source in comparator
  • Sixth Embodiment Example of controlling the conductance of the current source in the lamp generation unit
  • Seventh Embodiment Example of controlling conductance of a current source outside the comparator
  • FIG. 1 is a block diagram showing a configuration example of an image pickup apparatus 100 according to a first embodiment of the present technology.
  • the image pickup device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state image pickup element 200, and a DSP (Digital Signal Processing) circuit 120. Further, the image pickup apparatus 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180.
  • a camera mounted on a smartphone, an in-vehicle camera, or the like is assumed.
  • the optical unit 110 collects the light from the subject and guides it to the solid-state image sensor 200.
  • the solid-state image sensor 200 generates image data by photoelectric conversion.
  • the solid-state image sensor 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.
  • the DSP circuit 120 executes predetermined signal processing on the image data.
  • the DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150.
  • the display unit 130 displays image data.
  • a liquid crystal panel or an organic EL (ElectroLuminescence) panel is assumed.
  • the operation unit 140 generates an operation signal according to the operation of the user.
  • the bus 150 is a common route for the optical unit 110, the solid-state image sensor 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other.
  • the frame memory 160 holds image data.
  • the storage unit 170 stores various data such as image data.
  • the power supply unit 180 supplies power to the solid-state image sensor 200, the DSP circuit 120, the display unit 130, and the like.
  • FIG. 2 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the first embodiment of the present technology.
  • the solid-state image sensor 200 includes a circuit chip 202 and a light receiving chip 201 laminated on the circuit chip 202. These chips are electrically connected, for example, by Cu-Cu bonding. In addition to Cu-Cu bonding, it can also be connected by vias or bumps.
  • a pixel array unit 250 is arranged on the light receiving chip 201. Further, the circuit chip 202 is arranged with a vertical drive unit 210, a gain control unit 220, a lamp generation unit 230, a comparator control unit 240, a column ADC 270, a horizontal drive unit 280, and an image processing unit 290.
  • each of the light receiving chip 201 and the circuit chip 202 is not limited to the configuration illustrated in the figure.
  • the pixel array unit 250 and the comparator (not shown) in the column ADC 270 may be arranged on the light receiving chip 201, and other circuits may be arranged on the circuit chip 202.
  • a plurality of pixel circuits 260 are arranged in a two-dimensional grid pattern in the pixel array unit 250.
  • a set of pixel circuits 260 arranged in a predetermined horizontal direction is referred to as a “row”
  • a set of pixel circuits 260 arranged in a direction perpendicular to a row is referred to as a “column”.
  • the vertical drive unit 210 drives the rows in order and outputs an analog pixel signal to the column ADC 270.
  • the gain control unit 220 controls the analog gain based on the set data in synchronization with the vertical synchronization signal VSYNC.
  • the vertical synchronization signal VSYNC is a periodic signal having a predetermined frequency (60 hertz or the like) indicating the imaging timing.
  • the analog gain is an amplification factor when the comparator in the column ADC 270 amplifies the pixel signal.
  • the setting data is data indicating the setting value of the analog gain.
  • the vertical synchronization signal VSYNC and the setting data are generated by an external circuit (DSP circuit 120 or the like) of the solid-state image sensor 200 and input to the solid-state image sensor 200.
  • the gain control unit 220 generates a digital control signal CTRL for controlling the lamp generation unit 230 and supplies it to the lamp generation unit 230 and the comparator control unit 240.
  • the lamp generation unit 230 generates a sawtooth-shaped lamp signal according to the control signal CTRL and supplies it to the column ADC 270 as a reference signal.
  • the lamp generation unit 230 is realized by, for example, a DAC (Digital to Analog Converter) or the like.
  • the gain control unit 220 reduces the amplitude of the lamp signal by the control signal CTRL as the analog gain indicated by the setting data is higher.
  • the comparator control unit 240 controls the conductance of the comparator (not shown) in the column ADC 270 based on the control signal CTRL.
  • the control content of conductance will be described later.
  • An ADC (not shown) is arranged for each column in the column ADC 270.
  • Each of the ADCs converts the pixel signals of the corresponding columns into digital signals and supplies them to the image processing unit 290 under the control of the horizontal drive unit 280.
  • the horizontal drive unit 280 controls the column ADC 270 to output digital signals in order.
  • the image processing unit 290 performs various image processing such as demosaic processing and white balance processing on the image data in which digital signals are arranged.
  • the image processing unit 290 supplies the processed image data to the DSP circuit 120 via the signal line 209.
  • a circuit (DSP circuit 120 or the like) outside the solid-state image sensor 200 may execute a part or all of the processing in the image processing unit 290 instead of the image processing unit 290.
  • FIG. 3 is a circuit diagram showing a configuration example of the pixel circuit 260 according to the first embodiment of the present technology.
  • the pixel circuit 260 includes a photoelectric conversion element 261, a transfer transistor 262, a reset transistor 263, a stray diffusion layer 264, an amplification transistor 265, and a selection transistor 266. Further, in the pixel array unit 250, vertical signal lines 269 are wired for each row along the vertical direction.
  • the photoelectric conversion element 261 photoelectrically converts incident light to generate an electric charge.
  • the transfer transistor 262 transfers an electric charge from the photoelectric conversion element 261 to the stray diffusion layer 264 according to the drive signal TRG from the vertical drive unit 210.
  • the reset transistor 263 is initialized by extracting electric charges from the floating diffusion layer 264 according to the drive signal RST from the vertical drive unit 210.
  • the floating diffusion layer 264 accumulates electric charges and generates a voltage according to the amount of electric charges.
  • the amplification transistor 265 amplifies the voltage of the stray diffusion layer 264.
  • the selection transistor 266 outputs an amplified voltage signal as a pixel signal to the column ADC 270 via the vertical signal line 269 according to the drive signal SEL from the vertical drive unit 210.
  • the pixel circuit 260 is not limited to the circuit illustrated in the figure as long as it can generate an analog pixel signal by photoelectric conversion.
  • FIG. 4 is a block diagram showing a configuration example of the column ADC 270 according to the first embodiment of the present technology.
  • a capacitance 271, a comparator 300, a counter 272 and a latch 273 are arranged for each column.
  • N is an integer
  • the capacitance 271, the comparator 300, the counter 272, and the latch 273 are arranged N by N.
  • the comparator 300 compares the reference signal RMP (lamp signal) from the lamp generation unit 230 with the pixel signal SIG from the corresponding column.
  • the reference signal RMP is input to the comparator 300 via the capacitance 271, and the pixel signal is input via the vertical signal line 269.
  • the comparator 300 supplies the comparison result COMP of the reference signal RMP and the pixel signal SIG to the counter 272 in the corresponding column.
  • the level of the pixel signal when the pixel circuit 260 is initialized is hereinafter referred to as "reset level”
  • the level of the pixel signal when the charge is transferred to the floating diffusion layer 264 is hereinafter referred to as “signal level”. ".
  • the counter 272 counts the count value over the period until the comparison result COMP is reversed.
  • the counter 272 for example, counts down over the period until the comparison result COMP with the reset level is inverted, and upcounts over the period until the comparison result COMP with the signal level is inverted.
  • CDS Correlated Double Sampling
  • the counter 272 causes the latch 273 to hold a digital signal indicating the count value.
  • the comparator 300 and the counter 272 realize an AD conversion process for converting an analog pixel signal into a digital signal. That is, the comparator 300 and the counter 272 function as ADCs. ADCs that use comparators and counters in this way are commonly referred to as single-slope ADCs.
  • the counter 272 may perform only one of up-counting and down-counting, and the CDS process for obtaining the difference may be executed by the circuit in the subsequent stage.
  • the latch 273 holds a digital signal.
  • the latch 273 outputs the held digital signal to the image processing unit 290 under the control of the horizontal drive unit 280.
  • FIG. 5 is a diagram showing an example of the waveform of the reference signal RMP in the first embodiment of the present technology.
  • a is a diagram showing an example of the waveform of the reference signal RMP when controlling to a low gain which is an analog gain lower than a predetermined boundary value.
  • b is a diagram showing an example of the waveform of the reference signal RMP when controlling to a high gain which is an analog gain higher than the boundary value.
  • the reference signal RMP gradually decreases over the period from the timing t1 to t2 for AD conversion of the reset level. Further, even in the period from the timing t3 to t4 for AD conversion of the signal level, the reference signal RMP gradually decreases, and its amplitude is larger than the AD conversion period of the reset level.
  • the amplitude of the reference signal RMP when controlling to low gain, the amplitude of the reference signal RMP becomes a larger value than in the case of high gain. Further, as illustrated in b in the figure, when the high gain is controlled, the amplitude of the reference signal RMP becomes a smaller value than in the case of the low gain.
  • the smaller the amplitude of the reference signal RMP the longer the time until the comparison result of the comparator 300 is inverted, and the larger the count value of the counter 272.
  • the smaller the amplitude of the reference signal RMP the more the pixel signal is amplified in the ADC including the comparator 300 and the counter 272.
  • the amplification factor of this pixel signal corresponds to the above-mentioned analog gain.
  • the DSP circuit 120 When the illuminance of the ambient light is high, the ratio of the signal level to the reset level becomes large, so in order to suppress whitening, the DSP circuit 120 or the like generates setting data indicating low gain. On the other hand, when the illuminance of the ambient light is low, setting data indicating high gain is generated by the DSP circuit 120 or the like in order to improve the sensitivity. In this way, the higher the illuminance, the lower the analog gain is set.
  • FIG. 6 is a circuit diagram showing a configuration example of the comparator 300 according to the first embodiment of the present technology.
  • the comparator 300 includes a comparator circuit 310 and current sources 320 and 350 in the comparator.
  • the comparison circuit 310 compares the pixel signal SIG from the pixel circuit 260 with the reference signal RMP from the lamp generation unit 230, and supplies the comparison result COMP to the counter 272. Further, as described above, the pixel signal SIG is amplified by the analog gain corresponding to the amplitude of the reference signal RMP.
  • the comparison circuit 310 includes an input transistor 311, an auto-zero switch 312, a capacitance 313, a clamp transistor 314, and an output transistor 315.
  • the source of the input transistor 311 is connected to the vertical signal line 269, and the pixel signal SIG is input to the source. Further, a reference signal RMP is input to the gate of the input transistor 311 via the capacitance 271.
  • the input transistor 311 is in the same voltage state as at the time of auto zero when the voltage of the pixel signal input to the source and the voltage of the reference signal input to the gate substantially match, and the drain voltage corresponding to those voltages is drained. Output from.
  • substantially match means that the change from the voltage value in each auto-zero period is a perfect match, or the difference is within a predetermined allowable value.
  • a pMOS transistor is used as the input transistor 311 for example.
  • the back gate of the input transistor 311 and the source are short-circuited in order to suppress the back gate effect.
  • the auto zero switch 312 short-circuits between the gate of the input transistor 311 and the drain according to the control signal AZSW from the comparator control unit 240.
  • the capacitance 313 is inserted between the source and the drain of the input transistor 311.
  • the clamp transistor 314 is inserted between the source and drain of the input transistor 311.
  • a pMOS transistor is used as the clamp transistor 314, the gate of which is shorted to the drain. Further, it is desirable that the back gate and the source of the clamp transistor 314 are short-circuited.
  • the clamp transistor 314 can suppress a decrease in the drain voltage when the input transistor 311 is in a non-conducting state.
  • the source of the output transistor 315 is connected to the vertical signal line 269, and the pixel signal SIG is input to the source. Further, the gate of the output transistor 315 is connected to the drain of the input transistor 311 and the drain voltage thereof is input.
  • the output transistor 315 for example, a pMOS transistor is used. Further, it is desirable that the back gate of the output transistor 315 and the source are short-circuited.
  • the output transistor 315 outputs a signal indicating whether or not the difference between the voltage of the pixel signal SIG input to the source and the drain voltage input to the gate exceeds a predetermined threshold voltage as a comparison result COMP from the drain. ..
  • the comparison result COMP is supplied to the counter 272.
  • the drain voltage of the input transistor 311 fluctuates according to the level of the pixel signal SIG. Therefore, the timing at which the drain voltage is inverted may deviate from the ideal timing at which the pixel signal SIG and the reference signal RMP substantially match.
  • the drain-source voltage of the input transistor 311 is input as the gate-source voltage of the output transistor 315. Since the fluctuation amount of the drain voltage of the input transistor is equivalent to the fluctuation amount of the voltage of the pixel signal SIG, the comparison result COMP from the output transistor 315 is at an ideal timing at which the pixel signal SIG and the reference signal RMP substantially match. Invert. In this way, by adding the output transistor 315, it is possible to suppress the error of the inversion timing.
  • the current source 320 in the comparator is inserted between the drain of the input transistor 311 and a predetermined reference terminal (ground terminal or the like) to generate a constant current.
  • the current source 350 in the comparator is inserted between the drain of the output transistor 315 and a predetermined reference terminal (ground terminal or the like) to generate a constant current.
  • the comparator control unit 240 controls the conductance of the current sources 320 and 350 in the comparator by the switching signal CSW. These conductances are substantially the same.
  • clamp transistor 314 and the output transistor 315 are arranged in the comparison circuit 310, it is also possible to configure the configuration in which at least one of these is not provided. If the output transistor 315 is not provided, the current source 350 in the comparator becomes unnecessary. Further, although the comparator control unit 240 controls the conductance of both the current sources 320 and 350 in the comparator, it is also possible to control only one conductance and set the other conductance to a fixed value.
  • FIG. 7 is a diagram for explaining the control of the dynamic range in the first embodiment of the present technology.
  • the total of the drain-source voltage when the amplification transistor 265 and the selection transistor 266 in the pixel circuit 260 are in the ON state is defined as the “pixel Tr operating voltage”.
  • the upper limit of the voltage of the vertical signal line 269 (that is, the pixel signal SIG) is lower than the power supply voltage VDD by the pixel Tr operating voltage.
  • the drain-source voltage when the input transistor 311 in the comparison circuit 310 is in the ON state is defined as "pMOS operating voltage”.
  • the drain-source voltage when the output transistor 315 is on is substantially the same as that of the input transistor 311.
  • the voltage between the connection node of the input transistor 311 and the current source 320 in the comparator and the ground potential VSS is defined as the “current source operating voltage”.
  • the lower limit of the pixel signal SIG is the sum of the pMOS operating voltage and the current source operating voltage.
  • the ratio between the upper limit and the lower limit of the pixel signal SIG is referred to as "VSL dynamic range".
  • a connection node between the vertical signal line 269 and a current source outside the comparator is connected to the input terminal of the comparator. Therefore, when a differential amplifier circuit is used, the lower limit of the pixel signal SIG is the current source operating voltage.
  • the comparison circuit 310 is inserted between the vertical signal line 269 and the current source 320 in the comparator. Therefore, as compared with the case of using the differential amplifier, the lower limit of the pixel signal SIG is increased by the amount of the pMOS operating voltage, and the VSL dynamic range is narrowed.
  • the conductance may be increased in order to expand the VSL dynamic range.
  • RTS Random Telegraph Signal
  • the RTS noise is noise caused by random capture and emission of electrons by the interface state of the gate oxide film of the MOS transistor, and varies depending on the gate width and the gate length. If the gate width and gate length are adjusted so that the conductance increases, the RTS noise also increases.
  • the level of this RTS noise needs to be less than or equal to a predetermined target value, and the value is defined by the ratio to the level of random noise.
  • the random noise increases, so that the target value of RTS noise is relaxed to a larger value than in the case of high gain.
  • the random noise is reduced, so that the target value of RTS noise is set to a smaller value than in the case of low gain.
  • the VSL dynamic range may be relatively narrow.
  • the comparator control unit 240 increases the conductance of the current sources 320 and 350 in the comparator when the low gain is set by the setting data as compared with the case of the high gain. This makes it possible to expand the VSL dynamic range.
  • the increase in conductance increases the RTS noise, but as described above, the low gain relaxes the target value of the RTS noise, so that it does not matter.
  • the comparator control unit 240 reduces the conductance of the current sources 320 and 350 in the comparator as compared with the case of the low gain. This makes it possible to reduce RTS noise.
  • the decrease in conductance narrows the VSL dynamic range, but as described above, this is not a problem because the illuminance is low at low gain and the ratio of the signal level to the reset level is small.
  • the in-comparator current sources 320 and 350 generate a constant current.
  • the pixel circuit 260 generates a pixel signal SIG, and its lower limit voltage is a value according to conductance.
  • the comparison circuit 310 amplifies the pixel signal SIG with an analog gain and compares it with the reference signal RMP. The higher the analog gain of the comparator control unit 240, the lower the conductance of the current sources 320 and 350 in the comparator.
  • the counter 272 counts and outputs the count value over the time until the comparison result COMP is inverted.
  • the VSL dynamic range can be expanded at low gain and RTS noise can be reduced at high gain. This makes it possible to improve the image quality of the image data.
  • the comparator control unit 240 is an example of the control unit described in the claims. Further, the current sources 320 and 350 in the comparator are examples of the current sources described in the claims.
  • the comparator control unit 240 has the same analog gain boundary value when switching the conductances of the comparator internal current sources 320 and 350, but the configuration is not limited to this. It is also possible to make the boundary value of the analog gain at the time of switching different between the current source 320 in the comparator and the current source 350 in the comparator.
  • FIG. 8 is a diagram for explaining the control of conductance in the first embodiment of the present technology.
  • a low gain equal to or less than the boundary value is set by the DSP circuit 120 or the like.
  • the comparator control unit 240 makes the conductance of the current source 320 in the comparator larger than that at the time of high gain. The increased conductance increases the VSL dynamic range and the level of RTS noise.
  • the comparator control unit 240 makes the conductance of the current source 320 in the comparator smaller than that at the time of low gain. Due to the reduced conductance, the VSL dynamic range is narrowed and the level of RTS noise is reduced.
  • FIG. 9 is a circuit diagram showing a configuration example of the current source 320 in the comparator according to the first embodiment of the present technology.
  • the current source 320 in the comparator includes current source transistors 321 and 322 and a switching circuit 330.
  • the switching circuit 330 switches the connection form of the current source transistors 321 and 322 according to the switching signal CSW from the comparator control unit 240.
  • the switching signal CSW is a signal composed of switching signals CSW1, CSW2 and CSW3.
  • the switching circuit 330 includes switches 331, 332 and 333. As these switches, for example, an nMOS transistor is used. The size (gate width and gate length) of the nMOS transistor used in these switches may be smaller than that of the current source transistors 321 and 322. Therefore, the arrangement of the switches has little influence on the mounting surface of the current source 320 in the comparator.
  • the current source transistors 321 and 322 are connected in series to the comparison circuit 310, and a predetermined bias voltage Vb is applied to their gates.
  • the current source transistors 321 and 322 are examples of the first and second transistors described in the claims.
  • the switch 331 opens and closes the path between the connection node of the current source transistors 321 and 322 and the ground terminal according to the switching signal CSW1.
  • the switch 332 opens and closes the path between the source of the current source transistor 322 and the comparison circuit 310 according to the switching signal CSW2.
  • the switch 333 opens and closes the path between the source of the current source transistor 322 and the ground terminal according to the switching signal CSW3.
  • One of the logical values "0" and "1” is set for each of the switching signals CSW1, CSW2, and CSW3. For example, when the logical value is "0”, the corresponding switch is controlled to the open state, and when the logical value is "1", the corresponding switch is controlled to the closed state.
  • the configuration of the current source 350 in the comparator is the same as that of the current source 320 in the comparator.
  • FIG. 10 is a diagram showing an example of the state of the current source 320 in the comparator when the high gain is set in the first embodiment of the present technology.
  • a shows an example of the state of the switch when the high gain is set.
  • Reference numeral b in the figure shows an example of the connection form when the high gain is set.
  • the comparator control unit 240 opens the switches 331 and 332 and closes the switch 333.
  • the source of the current source transistor 322 is connected to the ground terminal.
  • the current source transistors 321 and 322 are connected in series to the comparison circuit 310.
  • the gate width of each of the current source transistors 321 and 322 is W 0 , and the gate length is 0.5 L 0 . Further, the mutual conductance of each is set to 2 gm 0 , and the operating voltage is set to 0.5 Vdsat.
  • the effective value of the gate width when connected in series remains W 0 , and the effective value of the gate length is L 0 . Since the combined conductance is proportional to (gate width) / (gate length), it becomes gm 0 , which is half that of a single current source transistor, by connecting in series. Further, since the conductance is halved, the current source operating voltage becomes Vdsat, which is twice the operating voltage of the current source transistor alone.
  • the current source transistors 321 and 322 have the same size (that is, the gate width and the gate length), they may be different. Further, the circuit configuration of the current source 320 in the comparator is not limited to the one illustrated in the figure as long as the connection configuration of the current source transistor can be switched.
  • FIG. 11 is a diagram showing an example of the state of the current source 320 in the comparator when the low gain is set in the first embodiment of the present technology.
  • a shows an example of the state of the switch when the low gain is set.
  • b shows an example of the connection form when the low gain is set.
  • the comparator control unit 240 closes the switches 331 and 332 and opens the switch 333.
  • the connection nodes of the current source transistors 321 and 322 are connected to the ground terminal, and the source of the current source transistor 322 is connected to the comparison circuit 310.
  • the current source transistors 321 and 322 are connected in parallel to the comparison circuit 310.
  • the effective value of the gate width when connected in parallel is 2W 0
  • the effective value of the gate length is 0.5L 0
  • the combined conductance is 2 gm 0 , which is the same as that of the current source transistor alone, by connecting in parallel.
  • the current source operating voltage is 0.5 Vdsat, which is the same as the operating voltage of the current source transistor alone.
  • bias voltages Vb are applied between the case of parallel connection and the case of series connection.
  • the bias voltage Vb twice the voltage is applied as the bias voltage Vb as compared with the case of parallel connection.
  • the comparator control unit 240 controls the conductance of the current source 320 in the comparator by switching the connection form of the current source transistors 321 and 322 in the current source 320 in the comparator. is doing.
  • the transconductance of the current source transistors must be 2 gm 0.
  • the gate area is adjusted to 2.2 1/2 W 0
  • the gate length is adjusted to (1/2) 2 1/2 L 0 .
  • the total gate area of the current source transistors 321 and 322 may be W 0 ⁇ L 0 as described above, and the mounting area can be made smaller than that of the comparative example.
  • FIG. 12 is a timing chart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology.
  • Image data (frame) is imaged in synchronization with the vertical synchronization signal VSYNC. Then, the analog gain is set for each frame according to the illuminance. For example, in the frame period from the timing T1 at which the vertical synchronization signal VSYS falls to the timing T3 at which the vertical synchronization signal falls next, the control signal CTRL for achieving high gain is output from the gain control unit 220. After timing T3, it is switched to low gain.
  • the period of timing T1 to T2 is set to the vertical blanking period VBK.
  • the pixel signal is AD-converted row by row.
  • the comparator control unit 240 switches the connection form by the switching signal CSW. Since the high gain is set at the timing T1, the comparator control unit 240 sets the switching signals CSW1 and CSW2 to the logical value "0", sets the switching signal CSW3 to the logical value "1", and sets the inside of the current source 320 in the comparator and the like. Switch the connection form of to series connection. Further, since the low gain is set at the timing T3, the comparator control unit 240 sets the switching signals CSW1 and CSW2 to the logical value "1”, sets the switching signal CSW3 to the logical value "0", and sets the current source 320 in the comparator to the current source 320 and the like. Switch the internal connection form of to parallel connection.
  • the comparator control unit 240 when the analog gain (amplification factor) is high, the comparator control unit 240 reduces the conductance of the current source 320 in the comparator, so that RTS noise is suppressed. be able to. Further, when the analog gain is low, the comparator control unit 240 increases the conductance of the current source 320 in the comparator, so that the dynamic range can be expanded. That is, the image quality of the image data can be improved by expanding the VSL dynamic range when the analog gain is low and suppressing RTS noise when the analog gain is high.
  • the comparator control unit 240 controls the conductance of the current source 320 in the comparator in two stages, but in the two-stage control, the adjustment range of the current source operating voltage is insufficient. I have something to do.
  • the comparator control unit 240 of the second embodiment is different from the first embodiment in that the conductance of the current source 320 in the comparator is controlled in three stages.
  • FIG. 13 is a circuit diagram showing a configuration example of the current source 320 in the comparator according to the second embodiment of the present technology.
  • the in-comparator current source 320 of the second embodiment is different from the first embodiment in that the current source transistors 323 and 324 are further provided and the switches 334 to 337 are further provided in the switching circuit 330.
  • the current source transistors 323 and 324 for example, nMOS transistors are used.
  • the current source transistors 323 and 324 are connected in series with the current source transistor 322. Further, a bias voltage Vb is applied to the gates of the current source transistors 323 and 324.
  • the current source transistors 323 and 324 are examples of the third and fourth transistors described in the claims.
  • the switch 334 opens and closes the path between the connection node of the current source transistors 323 and 324 and the comparison circuit 310 according to the switching signal CSW4 from the vertical drive unit 210.
  • the switch 335 opens and closes the path between the connection node of the current source transistors 323 and 324 and the ground terminal according to the switching signal CSW5 from the vertical drive unit 210.
  • the switch 336 opens and closes the path between the source of the current source transistor 324 and the comparison circuit 310 according to the switching signal CSW6 from the vertical drive unit 210.
  • the switch 337 opens and closes the path between the source of the current source transistor 324 and the ground terminal according to the switching signal CSW7 from the vertical drive unit 210.
  • the configuration of the current source 350 in the comparator is the same as that of the current source 320 in the comparator.
  • FIG. 14 is a diagram showing an example of the state of the current source 320 in the comparator when the high gain is set in the second embodiment of the present technology.
  • the comparator control unit 240 closes the switch 337 and opens the remaining switches.
  • the source of the current source transistor 324 is connected to the ground terminal.
  • the current source transistors 321 to 324 are connected in series to the comparison circuit 310.
  • the gate width of the current source transistor alone and W 0, the gate length is 0.25 L 0, the effective value of the gate width of the drawing W 0, and the effective value of the gate length is L 0.
  • the conductance is the same as that of the current source transistor alone, and the current source operating voltage is Vdsat.
  • FIG. 15 is a diagram showing an example of the state of the current source 320 in the comparator when the middle gain is set in the second embodiment of the present technology.
  • the middle gain is the gain between the high gain and the low gain.
  • the comparator control unit 240 closes the switches 333 and 336 and opens the remaining switches.
  • the connection nodes of the current source transistors 322 and 323 are connected to the ground terminal, and the source of the current source transistor 324 is connected to the comparison circuit 310.
  • the circuit in which the current source transistors 321 and 322 are connected in series and the circuit in which the current source transistors 323 and 324 are connected in series are connected in parallel.
  • the effective value of the gate width in the figure is 2W 0
  • the effective value of the gate length is 0.5L 0 .
  • the conductance is twice that of the current source transistor alone, and the current source operating voltage is 0.5 Vdsat.
  • FIG. 16 is a diagram showing an example of the state of the current source 320 in the comparator when the low gain is set in the second embodiment of the present technology.
  • the comparator control unit 240 closes the switches 331, 332, 335 and 336, and opens the remaining switches.
  • the connection node of the current source transistors 321 and 322 and the connection node of the current source transistors 323 and 324 are connected to the ground terminal.
  • the connection node of the current source transistors 322 and 323 and the source of the current source transistor 324 are connected to the comparison circuit 310.
  • the current source transistors 321 to 324 are connected in parallel.
  • the effective value of the gate width in the figure is 4W 0
  • the effective value of the gate length is 0.25L 0 .
  • the conductance is four times that of the current source transistor alone, and the current source operating voltage is 0.25 Vdsat.
  • the comparator control unit 240 can control the conductance of the current source 320 in the comparator in three stages by switching the connection form.
  • the adjustment range of the current source operating voltage can be expanded as compared with the case of controlling in two steps.
  • noise can be reduced to the maximum while ensuring the required VSL dynamic range.
  • the VSL dynamic range when the analog gain is 6 decibels (dB) may be half that of 0 decibels (dB), and noise can be further reduced by transferring that amount to the current source operating voltage. ..
  • the sizes of the current source transistors 321 to 324 are the same, they may be different.
  • the combination of transistors of different sizes allows the current source operating voltage to be fine-tuned.
  • the current source operating voltage is controlled in three stages, it can be controlled in four or more stages by adding a current source transistor and a switch.
  • the current source transistors are increased to four, and the comparator control unit 240 switches the connection form between them, so that the current source operating voltage is controlled in three stages. can do.
  • the VSL dynamic range and RTS noise can be controlled to more appropriate values than when the current source operating voltage is controlled in two stages.
  • the switches 332 and 332 switch the connection destination of the source of the current source transistor 322 to either the power supply side or the ground side.
  • the drain of the current source transistor 322 and the connection destination of the source are inverted from the power supply side, the ground side to the ground side, and the power supply side, so that a surge current may flow through the transistor.
  • the in-comparer current source 320 of the third embodiment is different from the first embodiment in that the surge current is suppressed.
  • FIG. 17 is a circuit diagram showing a configuration example of the current source 320 in the comparator according to the third embodiment of the present technology.
  • the drain of the current source transistor 321 is connected to the comparison circuit 310 as in the first embodiment, and the source of the current source transistor 322 is connected to the ground terminal. Be connected.
  • the switch 331 of the third embodiment opens and closes the path between the source of the current source transistor 321 and the ground terminal.
  • the switch 332 of the third embodiment opens and closes the path between the source of the current source transistor 321 and the drain of the current source transistor 322.
  • the switch 333 of the third embodiment opens and closes the path between the drain of the current source transistor 322 and the comparison circuit 310.
  • the configuration of the current source 350 in the comparator is the same as that of the current source 320 in the comparator.
  • FIG. 18 is a diagram showing an example of the state of the current source 320 in the comparator when the high gain is set in the third embodiment of the present technology.
  • the comparator control unit 240 opens the switches 331 and 333 and closes the switch 332.
  • the source of the current source transistor 321 and the drain of the current source transistor 322 are connected.
  • the current source transistors 321 and 322 are connected in series to the comparison circuit 310. Further, the current source operating voltage is Vdsat as in the first embodiment.
  • FIG. 19 is a diagram showing an example of the state of the current source 320 in the comparator when the low gain is set in the third embodiment of the present technology.
  • the comparator control unit 240 opens the switch 332 and closes the switches 331 and 333.
  • the source of the current source transistor 321 and the ground terminal are connected, and the drain of the current source transistor 322 and the comparison circuit 310 are connected.
  • the current source transistors 321 and 322 are connected in parallel to the comparison circuit 310.
  • the current source operating voltage is 0.5 Vdsat as in the first embodiment.
  • connection destinations of the drain and the source of the current source transistor 322 are fixed to the power supply side and the ground side at the time of switching, the connection destinations of the drain and the source are fixed at the time of switching. There is no need to invert from the power supply side or grounding side to the grounding side or power supply side. As a result, it is possible to suppress the flow of surge current through the transistor. The same applies to the current source transistor 321.
  • connection destinations of the drain and the source of the current source transistor 322 are fixed to the power supply side and the ground side, the connection destinations of the drain and the source are the power supplies at the time of switching. There is no need to invert from the side or ground side to the ground side or power supply side. As a result, the surge current flowing through the current source transistor 322 can be suppressed.
  • the comparator control unit 240 controls the conductance of the current source 320 in the comparator in two stages, but in the two-stage control, the adjustment range of the current source operating voltage is insufficient. I have something to do.
  • the comparator control unit 240 of the modification of the third embodiment is different from the third embodiment in that the conductance of the current source 320 in the comparator is controlled in three stages.
  • FIG. 20 is a circuit diagram showing a configuration example of the current source 320 in the comparator in the modified example of the third embodiment of the present technology.
  • the in-comparer current source 320 of the modification of the third embodiment further includes current source transistors 323 and 324, and further includes switches 334 to 339 in the switching circuit 330, as compared with the first embodiment. different.
  • connection configuration of the current source transistors 321 and 322 of the modified example of the third embodiment and the switches 331 to 333 is the same as that of the third embodiment.
  • the switch 334 opens and closes the path between the source of the current source transistor 322 and the ground terminal according to the switching signal CSW4.
  • the switch 335 opens and closes the path between the source of the current source transistor 322 and the drain of the current source transistor 323 according to the switching signal CSW5.
  • the switch 336 opens and closes the path between the drain of the current source transistor 323 and the comparison circuit 310 according to the switching signal CSW6.
  • the switch 337 opens and closes the path between the source of the current source transistor 323 and the ground terminal according to the switching signal CSW7.
  • the switch 338 opens and closes the path between the source of the current source transistor 323 and the drain of the current source transistor 324 according to the switching signal CSW8 from the vertical drive unit 210.
  • the switch 339 opens and closes the path between the drain of the current source transistor 324 and the comparison circuit 310 according to the switching signal CSW9 from the vertical drive unit 210. Further, the source of the current source transistor 324 is connected to the ground terminal.
  • the configuration of the current source 350 in the comparator is the same as that of the current source 320 in the comparator.
  • FIG. 21 is a diagram showing an example of the state of the current source 320 in the comparator when the high gain is set in the modified example of the third embodiment of the present technology.
  • the comparator control unit 240 closes the switches 332, 335 and 338, and opens the remaining switches.
  • the source of the current source transistor 321 and the drain of the current source transistor 322 are connected, and the source of the current source transistor 322 and the drain of the current source transistor 323 are connected.
  • the source of the current source transistor 323 and the drain of the current source transistor 324 are connected.
  • the current source transistors 321 to 324 are connected in series to the comparison circuit 310.
  • FIG. 22 is a diagram showing an example of the state of the current source 320 in the comparator when the middle gain is set in the modified example of the third embodiment of the present technology.
  • the comparator control unit 240 closes the switches 332, 334, 336 and 338, and opens the remaining switches.
  • the source of the current source transistor 321 and the drain of the current source transistor 322 are connected, and the source of the current source transistor 322 is connected to the ground terminal.
  • the drain of the current source transistor 323 is connected to the comparison circuit 310, and the source of the current source transistor 323 and the drain of the current source transistor 324 are connected.
  • the circuit in which the current source transistors 321 and 322 are connected in series and the circuit in which the current source transistors 323 and 324 are connected in series are connected in parallel.
  • FIG. 23 is a diagram showing an example of the state of the current source 320 in the comparator when the low gain is set in the modified example of the third embodiment of the present technology.
  • the comparator control unit 240 closes the switches 331, 333, 334, 336, 337 and 339, and opens the remaining switches.
  • the sources of the current source transistors 321, 322 and 323 are connected to the ground terminal, and the drains of the current source transistors 322, 323 and 324 are connected to the comparison circuit 310, respectively.
  • the current source transistors 321 to 324 are connected in parallel.
  • the comparator control unit 240 can control the conductance of the current source 320 in the comparator in three stages by switching the connection form. As a result, the adjustment range of the current source operating voltage can be expanded as compared with the case of controlling in two steps. Further, at the time of switching, the drain of the current source transistors 321 to 324 and the connection destination of the source are fixed to the power supply side and the ground side, so that the surge current can be suppressed.
  • the number of current source transistors is increased to four, and the comparator control unit 240 switches the connection form between them, so that the current source operating voltage is set to 3. It can be controlled in stages. As a result, the VSL dynamic range and RTS noise can be controlled to more appropriate values than when the current source operating voltage is controlled in two stages.
  • the current source transistors 321 and 322 to which a constant bias voltage Vb is applied to the gate are arranged in the current source 320 in the comparator.
  • the bias voltage Vb is set to a fixed value
  • the current amount of the current source 320 in the comparator may fluctuate when the connection mode is switched.
  • the solid-state image sensor 200 of the fourth embodiment is different from the first embodiment in that the current amount is made constant by using the current mirror circuit.
  • FIG. 24 is a circuit diagram showing a configuration example of the comparator control unit 240 according to the fourth embodiment of the present technology.
  • the comparator control unit 240 of the fourth embodiment includes a switching circuit 241 and a bias circuit 242.
  • the switching circuit 241 controls the conductance of the current sources 320 and 350 in the comparator by the switching signals CSW1 to CTRL3 based on the control signal CTRL from the gain control unit 220. Further, the switching signals CSW1 to CSW3 are also supplied to the bias circuit 242.
  • the bias circuit 242 includes a current source 243, current source transistors 244 and 245, and switches 246 to 248.
  • the current source 243 supplies a constant reference current.
  • the current source transistors 244 and 245 are connected in series with the current source 243. Further, the gates of these current source transistors 244 and 245 are connected to the connection nodes of the current source 243 and the current source transistor 244. Further, the gate voltage of the current source transistors 244 and 245 is supplied as a bias voltage Vb to the comparator internal current source 320 and the comparator internal current source 350 in each row.
  • the switch 246 opens and closes the path between the connection node of the current source transistors 244 and 245 and the ground terminal according to the changeover signal CSW1.
  • the switch 247 opens and closes the path between the source of the current source transistor 245 and the current source 243 according to the switching signal CSW2.
  • the switch 248 opens and closes the path between the source of the current source transistor 245 and the ground terminal according to the switching signal CSW3.
  • the circuit including the bias circuit 242 and the current sources 320 and 350 in the comparator functions as a current mirror circuit.
  • the reference current in the bias circuit 242 is copied to the in-comparator current sources 320 and 350.
  • the amount of current in the current sources 320 and 350 in the comparator can be kept constant before and after switching.
  • the circuit configuration of the bias circuit 242 may be changed according to the circuit of the current source 320 in the comparator of the second and third embodiments and the modified examples of the third embodiment.
  • the constant reference current in the bias circuit 242 is copied to the current source 320 in the comparator and operates as a current mirror circuit, so that the comparator is operated before and after switching.
  • the amount of current in the internal current sources 320 and 350 can be made constant.
  • the external circuit of the solid-state image sensor 200 sets the analog gain according to the illuminance, but in this configuration, the processing amount of the external circuit increases.
  • the image pickup device 100 of the fifth embodiment is different from the first embodiment in that the solid-state image pickup device 200 itself sets the analog gain according to the illuminance.
  • FIG. 25 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the fifth embodiment of the present technology.
  • the solid-state image sensor 200 of the fifth embodiment is different from the first embodiment in that the control unit 221 and the register 222 are provided instead of the gain control unit 220 and the comparator control unit 240.
  • the image processing unit 290 of the fifth embodiment is different from the first embodiment in that the illuminance is measured based on the image data.
  • the image processing unit 290 calculates, for example, a statistic such as an average value, a median value, and a mode value of pixel signals in the image data as an illuminance.
  • the image processing unit 290 supplies illuminance data indicating illuminance to the control unit 221.
  • the register 222 stores the setting data in association with each of the plurality of illuminance ranges.
  • the range of illuminance includes, for example, a range of high illuminance higher than a predetermined value and a range of low illuminance below the predetermined value.
  • the setting data includes a control signal CTRL for controlling the lamp generation unit 230 and a switching signal CTRL.
  • a control signal CTRL for generating a reference signal having a large amplitude (in other words, setting a low gain) and a switching signal CTRL for connecting in parallel are associated with each other in a high illuminance range.
  • a control signal CTRL for generating a reference signal having a small amplitude (in other words, setting a high gain) and a switching signal CTRL for connecting in series are associated with each other in a low illuminance range.
  • the control unit 221 controls the lamp generation unit 230 and the comparator 300 in each row based on the illuminance data.
  • the control unit 221 reads the control signal CTRL and the switching signal CTRL according to the illuminance from the register 222, supplies the control signal CTRL to the lamp generation unit 230, and supplies the switching signal CTRL to the comparator 300 in each row.
  • the analog gain is controlled to a value corresponding to the illuminance.
  • the switching signal CSW controls the conductance to a value corresponding to the analog gain.
  • FIG. 26 is a flowchart showing an example of the operation of the solid-state image sensor 200 according to the fifth embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.
  • the solid-state image sensor 200 performs photometric processing for measuring the illuminance of ambient light based on image data (step S910). Then, the solid-state image sensor 200 controls the conductances of the current sources 320 and 350 in the comparator according to the measured illuminance (step S920). The solid-state image sensor 200 performs an image pickup process for taking an image image (step S930). After step S930, the solid-state image sensor 200 ends the operation for imaging.
  • steps S910 to S930 are repeatedly executed in synchronization with the vertical synchronization signal.
  • FIG. 27 is a flowchart showing an example of photometric processing according to the fifth embodiment of the present technology.
  • the vertical drive unit 210 selects a read row (step S911) and exposes that row (step S912).
  • the column ADC 270 AD-converts the read line (step S913) and outputs line data under the control of the horizontal drive unit 280 (step S914).
  • the vertical drive unit 210 determines whether or not the read row is the last row (step S915). If it is not the last row (step S915: No), the vertical drive unit 210 repeats step S911 and subsequent steps.
  • step S915 when the read line is the last line (step S915: Yes), the image processing unit 290 generates illuminance data based on the image data and outputs it to the control unit 221 (step S916). After step S916, the solid-state image sensor 200 ends the photometric processing.
  • FIG. 28 is a flowchart showing an example of the imaging process according to the fifth embodiment of the present technology.
  • the vertical drive unit 210 selects a read row (step S931) and exposes that row (step S932).
  • the column ADC 270 AD-converts the read line (step S933) and outputs line data under the control of the horizontal drive unit 280 (step S934).
  • the vertical drive unit 210 determines whether or not the read row is the last row (step S935). If it is not the last row (step S935: No), the vertical drive unit 210 repeats step S931 and subsequent steps.
  • step S935 Yes
  • the image processing unit 290 processes the line data to generate and output the image data (step S936).
  • the solid-state image sensor 200 ends the photometric processing.
  • the image processing unit 290 measures the illuminance, and the control unit 221 controls the analog gain according to the illuminance, so that the outside of the solid-state image sensor 200 is used.
  • the circuit does not need to control the analog gain according to the illuminance. As a result, the amount of processing of the external circuit of the solid-state image sensor 200 can be reduced.
  • the comparator control unit 240 controls the conductance of the current sources 320 and 350 in the comparator to expand the VSL dynamic range.
  • the VSL dynamic range cannot be expanded unless the conductance of the current source outside the comparator is controlled.
  • the solid-state image sensor 200 of the sixth embodiment is different from the first embodiment in that the conductance of the current source outside the comparator is controlled.
  • FIG. 29 is a block diagram showing a configuration example of the column ADC 270 according to the sixth embodiment of the present technology.
  • the column ADC 270 of the sixth embodiment is different from the first embodiment in that the comparator 400 is provided instead of the comparator 300.
  • the comparator 400 compares the reference signal RMP input via the capacitance 271 with the pixel signal SIG input via the capacitance 274.
  • the comparator 400 supplies the comparison result COMP to the counter 272.
  • a differential amplifier circuit (not shown) is arranged in the comparator 400 instead of the circuit illustrated in FIG.
  • the differential amplifier circuit is an example of the comparison circuit described in the claims.
  • a load MOS current source 255 is connected to each of the vertical signal lines 269.
  • the circuit configuration of the load MOS current source 255 is the same as that of the comparator inner current source 320 of the first embodiment.
  • the comparator control unit 240 of the sixth embodiment controls the conductance of the load MOS current source 255 according to the analog gain.
  • the comparator control unit 240 reduces the conductance of the load MOS current source 255 to suppress RTS noise.
  • the comparator control unit 240 increases the conductance of the load MOS current source 255 to expand the VSL dynamic range. This makes it possible to improve the image quality of the image data.
  • the comparator control unit 240 in order for the comparator control unit 240 to control the conductance of the load MOS current source 255 according to the analog gain, the comparator 400 including a differential amplifier circuit is included. In the case of using, the image quality can be improved.
  • the reference signal is generated by the DAC in the lamp generation unit 230, but the amplitude control range may be insufficient only with the DAC.
  • the solid-state image sensor 200 of the seventh embodiment is different from the sixth embodiment in that the conductance of the current source in the lamp generation unit 230 is further controlled.
  • FIG. 30 is a circuit diagram showing a configuration example of the lamp generation unit 230 according to the seventh embodiment of the present technology.
  • the lamp generator 230 includes a lamp signal generator 231, a source follower current source 232, and a source follower transistor 233.
  • As the source follower transistor 233 for example, a pMOS transistor is used.
  • the lamp signal generator 231 generates a saw-like output signal Vout according to the control signal CTRL.
  • a DAC is used as the lamp signal generator 231.
  • the lamp signal generator 231 supplies the generated output signal Vout to the gate of the source follower transistor 233.
  • the source follower current source 232 and the source follower transistor 233 are connected in series between the power supply terminal and the ground terminal.
  • the source follower transistor 233 outputs a signal corresponding to the output signal Vout from the source to the column ADC 270 as a reference signal RMP.
  • the source follower current source 232 generates a constant current.
  • the circuit configuration of the source follower current source 232 is the same as that of the comparator inner current source 320 of the first embodiment.
  • the comparator control unit 240 of the seventh embodiment controls the conductance of the source follower current source 232 according to the analog gain. In the case of low gain, the comparator control unit 240 connects the current source transistors in the source follower current source 232 in parallel to increase the conductance. On the other hand, in the case of high gain, the comparator control unit 240 connects the current source transistors in the source follower current source 232 in series to reduce the conductance. By controlling the conductance of the source follower current source 232, the amplitude control range can be increased.
  • the seventh embodiment is applied to the column ADC 270 of the sixth embodiment
  • the present embodiment is not limited to this configuration, and the seventh embodiment is applied to the column ADC 270 of the first embodiment. You can also do it. Further, it is also possible to apply the second to fifth embodiments and modified examples of the third embodiment to the seventh embodiment.
  • the comparator control unit 240 further controls the conductance of the source follower current source 232, so that the control range of the amplitude of the reference signal RMP can be increased. can.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.
  • FIG. 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown as a functional configuration of the integrated control unit 12050.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 has a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, turn signals or fog lamps.
  • the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches.
  • the body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.
  • the outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image pickup unit 12031 is connected to the vehicle outside information detection unit 12030.
  • the vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image.
  • the out-of-vehicle information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.
  • the image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received.
  • the image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the image pickup unit 12031 may be visible light or invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects the in-vehicle information.
  • a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver has fallen asleep.
  • the microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit.
  • a control command can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.
  • the audio image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an onboard display and a head-up display.
  • FIG. 32 is a diagram showing an example of the installation position of the image pickup unit 12031.
  • the image pickup unit 12101, 12102, 12103, 12104, 12105 is provided.
  • the image pickup units 12101, 12102, 12103, 12104, 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100.
  • the image pickup unit 12101 provided in the front nose and the image pickup section 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the image pickup units 12102 and 12103 provided in the side mirror mainly acquire images of the side of the vehicle 12100.
  • the image pickup unit 12104 provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100.
  • the image pickup unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 32 shows an example of the shooting range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging range of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • the imaging range 12114 indicates the imaging range.
  • the imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the image pickup units 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.
  • At least one of the image pickup units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the image pickup units 12101 to 12104 may be a stereo camera including a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.
  • the microcomputer 12051 has a distance to each three-dimensional object within the image pickup range 12111 to 12114 based on the distance information obtained from the image pickup unit 12101 to 12104, and a temporal change of this distance (relative speed with respect to the vehicle 12100). By obtaining can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the image pickup units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
  • At least one of the image pickup units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging unit 12101 to 12104.
  • pedestrian recognition is, for example, a procedure for extracting feature points in an image captured by an image pickup unit 12101 to 12104 as an infrared camera, and pattern matching processing is performed on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine.
  • the audio image output unit 12052 determines the square contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.
  • the above is an example of a vehicle control system to which the technology according to the present disclosure can be applied.
  • the technique according to the present disclosure can be applied to the image pickup unit 12031 among the configurations described above.
  • the image pickup apparatus 100 of FIG. 1 can be applied to the image pickup unit 12031.
  • the present technology can have the following configurations.
  • a current source that generates a constant current
  • a pixel circuit that generates a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source, and a pixel circuit.
  • a comparison circuit that amplifies the pixel signal at a predetermined amplification factor and compares it with a predetermined reference signal.
  • a control unit that reduces the conductance as the amplification factor increases,
  • a solid-state image pickup device including a counter that counts and outputs a count value over a period of time until the comparison result of the comparison circuit is inverted.
  • the current source is With multiple transistors
  • the plurality of transistors include first and second transistors connected in series to the comparison circuit.
  • the switching circuit is A first switch that connects the connection node of the first and second transistors to a predetermined ground terminal, A second switch that connects the source of the second transistor to the comparison circuit,
  • the plurality of transistors include first, second, third and fourth transistors connected in series with the comparison circuit.
  • the switching circuit is A first switch that connects the connection node of the first and second transistors to a predetermined ground terminal, A second switch that connects the connection nodes of the second and third transistors to the comparison circuit, A third switch that connects the connection node of the second and third transistors to the ground terminal, A fourth switch that connects the connection nodes of the third and fourth transistors to the comparison circuit, A fifth switch that connects the connection node of the third and fourth transistors to the ground terminal, A sixth switch that connects the source of the fourth transistor to the comparison circuit,
  • the solid-state image pickup device according to (2) above, comprising a seventh switch for connecting the source of the fourth transistor to the ground terminal.
  • the plurality of transistors are The first transistor to which the drain is connected to the comparison circuit and Includes a second transistor with a source connected to a given ground terminal, including
  • the switching circuit is A first switch that connects the source of the first transistor to the ground terminal, A second switch connecting the source of the first transistor and the drain of the second transistor,
  • the plurality of transistors are The first transistor to which the drain is connected to the comparison circuit and With the second and third transistors, Includes a fourth transistor with a source connected to a given ground terminal, including
  • the switching circuit is A first switch that connects the source of the first transistor to the ground terminal, A second switch connecting the source of the first transistor and the drain of the second transistor, A third switch that connects the drain of the second transistor to the comparison circuit, A fourth switch that connects the source of the second transistor to the ground terminal, A fifth switch connecting the source of the second transistor and the drain of the third transistor, A sixth switch that connects the drain of the third transistor to the comparison circuit, A seventh switch that connects the source of the third transistor to the ground terminal, An eighth switch connecting the source of the third transistor and the drain of the fourth transistor,
  • the solid-state image pickup device according to (2) above, comprising a ninth switch for connecting the drain of the fourth transistor to the comparison circuit.
  • the solid-state imaging device according to any one of (1) to (6) above, wherein the reference current is copied to the current source.
  • an image processing unit for measuring the illuminance based on the image data in which the count values are arranged is provided.
  • the solid-state image pickup device according to any one of (1) to (7), wherein the control unit controls the amplification factor to a value corresponding to the illuminance.
  • the pixel circuit is connected to the comparison circuit via a vertical signal line, and is connected to the comparison circuit.
  • the solid-state imaging device according to any one of (1) to (8), wherein the comparison circuit is inserted between the vertical signal line and the current source.
  • the pixel circuit is connected to the comparison circuit via a vertical signal line.
  • the solid-state imaging device according to any one of (1) to (8), wherein the current source is connected to the vertical signal line.
  • a generator that generates a saw-like output signal, Further, a source follower transistor that outputs a signal corresponding to the output signal from the source as the reference signal is provided.
  • the current source is The current source in the comparator connected to the comparison circuit and
  • the solid-state imaging device according to any one of (1) to (10) above, comprising a source follower current source connected to the source of the source follower transistor.
  • a current source that generates a constant current
  • a pixel circuit that generates a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source, and a pixel circuit.
  • a comparison circuit that amplifies the pixel signal at a predetermined amplification factor and compares it with a predetermined reference signal.
  • a control unit that reduces the conductance as the amplification factor increases, A counter that counts and outputs the count value over the time until the comparison result of the comparison circuit is inverted, and
  • An image pickup apparatus including a storage unit for storing image data in which digital signals indicating the count values are arranged.
  • a pixel signal generation procedure in which the pixel circuit generates a pixel signal having a voltage higher than a predetermined lower limit voltage according to the conductance of the current source that generates a constant current.
  • a comparison procedure for amplifying the pixel signal at a predetermined amplification factor and comparing it with a predetermined reference signal.
  • a control procedure that reduces the conductance as the amplification factor increases, and
  • the current source is a plurality of transistors and A photodetector including a switching circuit for switching a connection form of the plurality of transistors.
  • the plurality of transistors include first and second transistors connected in series to the comparison circuit.
  • the switching circuit is A first switch that connects the connection node of the first and second transistors to a predetermined ground terminal, A second switch that connects the source of the second transistor to the comparison circuit, The solid-state image pickup device according to (14), further comprising a third switch for connecting the source of the second transistor to the ground terminal.
  • the plurality of transistors include first, second, third and fourth transistors connected in series with the comparison circuit.
  • the switching circuit is A first switch that connects the connection node of the first and second transistors to a predetermined ground terminal, A second switch that connects the connection nodes of the second and third transistors to the comparison circuit, A third switch that connects the connection node of the second and third transistors to the ground terminal, A fourth switch that connects the connection nodes of the third and fourth transistors to the comparison circuit, A fifth switch that connects the connection node of the third and fourth transistors to the ground terminal, A sixth switch that connects the source of the fourth transistor to the comparison circuit,
  • the solid-state image pickup device according to (14), further comprising a seventh switch for connecting the source of the fourth transistor to the ground terminal.
  • the plurality of transistors are The first transistor to which the drain is connected to the comparison circuit and Includes a second transistor with a source connected to a given ground terminal, including
  • the switching circuit is A first switch that connects the source of the first transistor to the ground terminal, A second switch connecting the source of the first transistor and the drain of the second transistor,
  • the plurality of transistors are The first transistor to which the drain is connected to the comparison circuit and With the second and third transistors, Includes a fourth transistor with a source connected to a given ground terminal, including
  • the switching circuit is A first switch that connects the source of the first transistor to the ground terminal, A second switch connecting the source of the first transistor and the drain of the second transistor, A third switch that connects the drain of the second transistor to the comparison circuit, A fourth switch that connects the source of the second transistor to the ground terminal, A fifth switch connecting the source of the second transistor and the drain of the third transistor, A sixth switch that connects the drain of the third transistor to the comparison circuit, A seventh switch that connects the source of the third transistor to the ground terminal, An eighth switch connecting the source of the third transistor and the drain of the fourth transistor,
  • the solid-state image pickup device according to (14), further comprising a ninth switch for connecting the drain of the fourth transistor to the comparison circuit.
  • Imaging device 110
  • Optical unit 120
  • DSP circuit 130 Display unit 140
  • Operation unit 150
  • Bus 160
  • Frame memory 170
  • Power supply unit 180
  • Solid-state image pickup element 201
  • Light receiving chip 202
  • Circuit chip 210
  • Vertical drive unit 220 Gain control unit 221
  • Control unit 222
  • Register 230
  • Lamp generator 231 Lamp signal generator 231
  • Lamp signal generator 232
  • Source follower current source 233
  • Source follower transistor 240
  • Comparer control unit 241
  • Switching circuit 242 Bias circuit 243
  • Current source 244, 245, 321 to 324
  • Switch 250 Pixel array part 255
  • Load MOS current source 260
  • Pixel circuit 261 Photoelectric conversion element 262 Transfer transistor 263 Reset transistor 264 Floating diffusion layer 265
  • Amplification transistor 266 Selective transistor 270 Column ADC 271, 274, 313 Capacity 272 Counter 273 Latch 280

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention améliore la qualité d'image de données d'image dans un élément d'imagerie à semi-conducteur qui utilise un comparateur.　L'élément d'imagerie à semi-conducteurs est équipé d'une source de courant, d'un circuit de pixel, d'un circuit comparateur, d'une unité de commande et d'un compteur. La source de courant génère un courant électrique constant. Le circuit de pixel génère un signal de pixel ayant une tension qui est supérieure à une tension limite inférieure prescrite correspondant à la conductance de la source de courant. Le circuit comparateur amplifie le signal de pixel par un facteur d'amplification prescrit et le compare à un signal de référence prescrit. L'unité de commande diminue la conductance au fur et à mesure que le facteur d'amplification augmente. Le compteur compte et délivre une valeur discrète pendant toute une période de temps jusqu'à ce que les résultats de la comparaison provenant du circuit comparateur soient inversés.
PCT/JP2021/017435 2020-07-01 2021-05-07 Élément d'imagerie à semi-conducteurs, dispositif d'imagerie et procédé de contrôle d'élément d'imagerie à semi-conducteurs WO2022004125A1 (fr)

Priority Applications (3)

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US18/003,183 US20230254609A1 (en) 2020-07-01 2021-05-07 Solid state imaging element, imaging apparatus, and method for controlling solid state imaging element
DE112021003535.5T DE112021003535T5 (de) 2020-07-01 2021-05-07 Festkörper-bildgebungselement, bildgebungseinrichtung und verfahren zum steuern eines festkörper-bildgebungselements
CN202180044992.6A CN116057957A (zh) 2020-07-01 2021-05-07 固态成像元件、成像装置和用于控制固态成像元件的方法

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015159730A1 (fr) * 2014-04-16 2015-10-22 ソニー株式会社 Élément d'imagerie, procédé de commande de gain, programme et dispositif électronique
WO2018030137A1 (fr) * 2016-08-08 2018-02-15 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image, et instrument électronique
US20180103222A1 (en) * 2016-10-06 2018-04-12 Semiconductor Components Industries, Llc Image pixels with in-column comparators

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015159730A1 (fr) * 2014-04-16 2015-10-22 ソニー株式会社 Élément d'imagerie, procédé de commande de gain, programme et dispositif électronique
WO2018030137A1 (fr) * 2016-08-08 2018-02-15 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image, et instrument électronique
US20180103222A1 (en) * 2016-10-06 2018-04-12 Semiconductor Components Industries, Llc Image pixels with in-column comparators

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