WO2022193536A1 - Dram及其形成方法 - Google Patents

Dram及其形成方法 Download PDF

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Publication number
WO2022193536A1
WO2022193536A1 PCT/CN2021/111920 CN2021111920W WO2022193536A1 WO 2022193536 A1 WO2022193536 A1 WO 2022193536A1 CN 2021111920 W CN2021111920 W CN 2021111920W WO 2022193536 A1 WO2022193536 A1 WO 2022193536A1
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Prior art keywords
silicon oxide
oxide layer
word line
thickness
trench
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PCT/CN2021/111920
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English (en)
French (fr)
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郭帅
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长鑫存储技术有限公司
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Priority to US17/456,073 priority Critical patent/US20220302119A1/en
Publication of WO2022193536A1 publication Critical patent/WO2022193536A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present application relates to the field of memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • the transistors in the dynamic random access memory usually adopt the trench type transistor structure.
  • the gate of the trench type transistor is connected to the word line, the drain region is connected to the bit line, and the source region is connected. connected to the capacitor.
  • the trench transistor of the existing dynamic random access memory (DRAM) consumes the substrate in the process of forming the gate dielectric layer, and the quality of the gate dielectric layer is poor, and there is a problem that the turn-on current decreases.
  • DRAM dynamic random access memory
  • the embodiments of the present application can/at least avoid the problem that the trench transistor has a drop in turn-on current.
  • a first aspect of the present application provides a method for forming a DRAM, including: providing a semiconductor substrate on which a plurality of discrete active regions are formed; and etching the active regions, forming a word line trench in the active region; forming a silicon nitride layer on the sidewall and bottom surface of the word line trench through a deposition process; A silicon oxide layer is formed on the sidewalls and bottom surfaces of the trench; word lines are formed on the silicon oxide layer.
  • a second aspect of the present application provides a DRAM, comprising: a semiconductor substrate on which a plurality of discrete active regions are formed; word line trenches in the active regions ; a silicon oxide layer on the sidewall and bottom surface of the wordline trench, the silicon oxide layer is formed by the following process: a silicon nitride layer is formed on the sidewall and bottom surface of the wordline trench by a deposition process ; Completely oxidizing the silicon nitride layer to form a silicon oxide layer on the sidewall and bottom surface of the word line trench; and a word line located on the silicon oxide layer.
  • the embodiments of the present disclosure may/at least have the following advantages: the formed word line silicon oxide layer is obtained by completely oxidizing the silicon nitride layer, and the silicon in the source and drain regions on both sides of the word line trench will not be consumed, so that the formation of The thickness of the silicon oxide layer is determined by the thickness of the silicon nitride layer, which ensures the stability of the thickness of the silicon oxide layer, so that the turn-on current of the trench transistor under the same turn-on voltage will not decrease, and the source region and the Drain size can remain unchanged.
  • FIGS. 1-8 are schematic structural diagrams of a memory formation process according to an embodiment of the present application.
  • the trench transistors of the existing dynamic random access memory have the problem of a drop in turn-on current.
  • a word line silicon oxide layer is generally formed on the sidewall and bottom of the word line trench in the semiconductor substrate by an atomic layer deposition process (Atomic Layer Deposition, ALD).
  • ALD atomic layer deposition
  • the quality of the silicon oxide layer of the word line formed in this way is poor (specifically, the compactness of the formed silicon oxide layer is not good, the defect density is high, and the roughness is high), and then in-situ water vapor generation and oxidation (In -Situ Steam Generation (ISSG)
  • ISSG In -Situ Steam Generation
  • H 2 /O 2 will pass through the deposited word line
  • the silicon oxide layer directly oxidizes the semiconductor substrate (the substrate will not be sufficient for ISSG oxidation when the line width is further reduced), which will lead to a decrease in the size of the source and drain regions and an increase in the thickness of the formed silicon oxide layer , so that the turn-on current of
  • the present application provides a DRAM and a method for forming the same, wherein the method for forming the DRAM includes providing a semiconductor substrate on which a plurality of discrete active regions are formed; forming a word line trench in the active region; forming a silicon nitride layer on the sidewall and bottom surface of the word line trench through a deposition process; completely oxidizing the silicon nitride layer, and A silicon oxide layer is formed on the sidewalls and bottom surfaces of the word line trenches; word lines are formed on the silicon oxide layer.
  • a silicon oxide layer is formed on the sidewall and bottom surface of the word line trench, and the silicon oxide layer is used as the silicon oxide layer formed in the subsequent word line trench.
  • the word line silicon oxide layer between the word line and the active region that is, the word line silicon oxide layer formed is obtained by completely oxidizing the silicon nitride layer, so the source and drain regions on both sides of the word line trench will not be consumed.
  • the thickness of the silicon oxide layer formed is determined by the thickness of the silicon nitride layer, which ensures the stability of the thickness of the silicon oxide layer, so that the turn-on current of the trench transistor under the same turn-on voltage will not decrease.
  • the quality of the formed word line silicon oxide layer will be better (specifically, compared with the silicon oxide layer formed by the deposition process, the density is high, the defect density is small, and the thickness is more uniform, compared with the silicon oxide silicon material.
  • the formed silicon oxide layer has high compactness, high surface flatness, small surface roughness and no particle defects on the surface), which can improve the reliability and life of the DRAM device.
  • the silicon nitride layer 212 is oxidized to silicon oxide, some N elements may remain, and the residual N elements will form SiON.
  • the dielectric constant of SiON is higher than that of silicon oxide (SiO 2 ), which can correspondingly improve the gate dielectric. Isolation properties of the electrical layer.
  • FIG. 2 is a schematic cross-sectional structure diagram of FIG. 1 along the cutting line AB, providing a semiconductor substrate 201 on which a plurality of discrete active regions 202 are formed.
  • the material of the semiconductor substrate 201 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); Or other materials, such as III-V group compounds such as gallium arsenide.
  • the material of the semiconductor substrate 201 is silicon.
  • the semiconductor substrate is doped with certain impurity ions as required, and the impurity ions may be N-type impurity ions or P-type impurity ions. In one embodiment, the doping includes well region doping and source and drain region doping.
  • the plurality of active regions 202 are isolated by isolation layers 203 .
  • the formation process of the active region 202 and the isolation layer 203 is as follows: forming a first mask layer (not shown in the figure) on the semiconductor substrate 201, the first mask layer There are several first mask openings distributed in parallel; using the first mask layer as a mask, the semiconductor substrate 201 is etched along the first mask opening, and several discrete openings are formed in the semiconductor substrate 201 There are first trenches between adjacent elongated active regions; the elongated active regions are etched, and a plurality of second trenches are formed in the elongated active regions, so that The second trench divides each strip-shaped active region into several active regions 202; the first trench and the second trench are filled with isolation material to form an isolation layer 203, the material of the isolation layer 203 It can be silicon oxide or other suitable isolation material (in other embodiments, the first trench can be filled with an isolation material to form a first isolation layer, and after the first isolation layer is formed, the strip-shaped active area, a plurality of second trenches are formed in the
  • the active region 202 may be formed by an epitaxy process.
  • the x-axis direction shown in FIG. 1 may be used as the row direction
  • the y-axis direction may be used as the column direction
  • the positions of the active regions 202 in adjacent rows may have a certain dislocation.
  • a mask layer 210 is formed on the active region 202 and the isolation layer 203 .
  • the material of the mask layer 210 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.
  • the mask layer 210 may be a single-layer or multi-layer stack structure.
  • the mask layer 210 includes a silicon nitride layer, an amorphous carbon layer on the silicon nitride layer, and the silicon nitride layer and the amorphous carbon layer are formed by a chemical vapor deposition process.
  • the extending direction of the openings 211 and the extending direction of the active region 202 are at an included angle, and each of the openings 211 exposes a part of the surface of the active region 202 and the two parts of the active region 202 . part of the surface of the isolation layer 203 on the side.
  • the mask layer 210 is patterned to form openings 211 in the mask layer 210. Specifically, a photoresist layer (not shown in the figure) is first formed on the mask layer 210; The photoresist layer is exposed and developed, and the photoresist is patterned; then the mask layer 210 is etched using the patterned photoresist layer as a mask, and an opening is formed in the mask layer 210 211.
  • a photoresist layer (not shown in the figure) is first formed on the mask layer 210; The photoresist layer is exposed and developed, and the photoresist is patterned; then the mask layer 210 is etched using the patterned photoresist layer as a mask, and an opening is formed in the mask layer 210 211.
  • an anisotropic plasma etching process is used to etch the mask layer 210 .
  • the mask layer 210 is used as a mask when the active region 202 and the isolation layer 203 are subsequently etched to form word line trenches.
  • the mask layer 210 on each active region 202 is correspondingly formed with The two openings 211 are subsequently etched to form two word line trenches in each active region 202 .
  • part of the active region 202 and the isolation layer 203 are removed by etching, and word line trenches 204 are formed in the active region 202 and the isolation layer 203 .
  • the word line trench 204 includes a first partial word line trench located in the active region 202 and a second partial word line trench located in the isolation layer.
  • a word line trench includes a first partial word line trench and a second partial word line trench. Two part word line trenches.
  • each active region 202 when two openings 211 are correspondingly formed in the mask layer 210 on each active region 202 , and two word line trenches 204 are correspondingly formed in each active region 202 to facilitate the subsequent formation of double trenches Specifically, the two word line trenches 204 divide each active region 202 into a drain region located in the middle and two source regions located on both sides of the drain region respectively.
  • Part of the active region 202 and the isolation layer 203 can be removed by etching using an anisotropic plasma etching process.
  • the etching gas used in the anisotropic plasma etching process includes Cl 2 . , a combination of one or more of HBr, CF 4 , and CHF 3
  • the etching gas used in the anisotropic plasma etching process step also includes one of helium or argon or a combination of more than one.
  • a silicon nitride layer 212 is formed on the sidewall and bottom surfaces of the wordline trenches 204 by a deposition process.
  • a silicon oxide layer is formed on the sidewall and bottom surface of the word line trench 204, and the silicon oxide layer serves as the subsequent word line trench
  • the word line silicon oxide layer between the word line and the active region 202 formed in 202 is obtained by completely oxidizing the silicon nitride layer 212 when the word line silicon oxide layer is formed by the aforementioned method, so the word line trench will not be consumed.
  • the silicon in the source region and the drain region on both sides of the trench 204 makes the thickness of the formed silicon oxide layer determined by the thickness of the silicon nitride layer 212, which ensures the stability of the thickness of the silicon oxide layer, so that the trench type transistor is equivalent to the thickness of the silicon oxide layer.
  • the turn-on current at turn-on voltage does not decrease, and the size of the source and drain regions can remain unchanged.
  • the quality of the silicon oxide layer formed on the word line will be better (specifically, compared with the silicon oxide layer formed by the deposition process, the density is high, the defect density is small, and the thickness is more uniform, compared with the silicon oxide material.
  • the formed silicon oxide layer has high compactness, high surface flatness, small surface roughness, and no particle defects on the surface), which can improve the reliability and life of the DRAM device.
  • the silicon nitride layer 212 is oxidized to silicon oxide, some N elements may remain, and the residual N elements will form SiON.
  • the dielectric constant of SiON is higher than that of silicon oxide (SiO 2 ), which can correspondingly improve the gate dielectric. Isolation properties of the electrical layer.
  • the deposition process for forming the silicon nitride layer 212 is an atomic layer deposition process.
  • the thickness T1 of the silicon nitride layer 212 on the sidewall surface of the wordline trench 204 is greater than the thickness T2 of the silicon nitride layer 212 at the bottom of the wordline trench 204 , and then the silicon nitride layer 212 is completely oxidized by , when the silicon oxide layer is formed on the sidewall and bottom surface of the wordline trench 204, correspondingly, the thickness of the silicon oxide layer formed on the sidewall surface of the wordline trench 204 is greater than the thickness of the silicon oxide layer formed at the bottom of the wordline trench 204 Therefore, when the trench transistor works, the electric field near the source and drain regions will be lower, while the electric field near the channel region will be higher, forming an electric field difference and reducing the gate-induced drain leakage current (GIDL, gate- Induced drain leakage), thereby further preventing the reduction of the turn-on current, so that the performance of the trench transistor is further improved, thereby further improving the performance of the DRAM.
  • GIDL gate-induced drain leak
  • the thickness of the silicon nitride layer 212 on the sidewall surface of the word line trench 204 gradually decreases from top to bottom.
  • the ratio of the thickness of the silicon nitride layer 212 on the sidewall surface of the wordline trench 204 to the thickness of the silicon nitride layer 212 at the bottom of the wordline trench 204 is 2:1-4:3.
  • the thickness of the silicon nitride layer 212 on the sidewall surface of the word line trench 204 is 8 nanometers to 10 nanometers
  • the thickness of the silicon nitride layer 212 at the bottom of the word line trench 204 is 5 nanometers to 7 nanometers.
  • the The atomic layer deposition process includes a silicon source gas and a nitrogen source gas
  • the silicon source gas includes DCS (dichlorosilane)
  • the nitrogen source gas includes NH3
  • the flow rate of the silicon source gas ranges from 200sccm to 600sccm.
  • the flow rate of nitrogen source gas is 2000sccm-15000sccm
  • a 5000L/min pump is used to extract the reaction by-products in the deposition chamber.
  • the silicon nitride layer 212 (refer to FIG. 6 ) is completely oxidized, and a silicon oxide layer 213 is formed on the sidewalls and bottom surfaces of the word line trenches 204 .
  • the silicon nitride layer 212 is completely oxidized to a silicon oxide layer 213 by an in-situ water vapor generation oxidation (ISSG) or rapid thermal oxidation process.
  • ISSG in-situ water vapor generation oxidation
  • the thickness T1 of the silicon oxide layer 213 on the surface of the sidewall of the word line trench 204 is greater than the thickness T2 of the silicon oxide layer 213 at the bottom of the word line trench 204.
  • the thickness of the silicon oxide layer 213 on the sidewall surface of the word line trench 204 gradually decreases from top to bottom.
  • the ratio of the thickness T1 of the silicon oxide layer 213 on the sidewall surface of the wordline trench 204 to the thickness of the silicon oxide layer 213 at the bottom of the wordline trench 204 is 2:1-4:3. Specifically, the thickness of the silicon oxide layer on the surface of the sidewall of the word line trench is 8 nanometers to 10 nanometers, and the thickness of the silicon oxide layer at the bottom of the word line trench is 5 nanometers to 7 nanometers.
  • the silicon nitride layer 212 is completely oxidized to the silicon oxide layer 213 by an in-situ water vapor generation and oxidation (ISSG) process.
  • ISSG in-situ water vapor generation and oxidation
  • oxygen and hydrogen are introduced into the reaction chamber.
  • the flow rate is more than 10 times the flow rate of hydrogen
  • the temperature of the reaction chamber is 900°C-1300°C
  • the pressure of the reaction chamber is 4torr-15torr.
  • oxygen and hydrogen are introduced in a certain proportion.
  • the reason why the proportion of oxygen is higher than that of hydrogen is to form a water vapor environment on the one hand, and to provide enough oxygen source to form silicon oxide on the other hand, and grow oxide through a high-temperature water vapor atmosphere.
  • the growth rate of the oxide layer is faster, and the gate oxide film grown by the in-situ water vapor generation method has better compactness.
  • word lines 214 are formed on the silicon oxide layer 213 .
  • the material of the word lines 214 may be W or other suitable metal materials.
  • the process of forming the word line 214 includes: forming a metal layer on the silicon oxide layer 213, the metal layer filling the word line trench; planarizing and removing the metal on the surface of the semiconductor substrate layer to form word lines 214 .
  • the word lines 214 may be flush with the surface of the active region 202 , or lower than the surface of the active region 202 , or slightly higher than the surface of the active region 202 .
  • Another embodiment of the present application also provides a DRAM, referring to FIG. 8 , including:
  • a semiconductor substrate 201 with a plurality of discrete active regions 202 formed on the semiconductor substrate 201;
  • a silicon oxide layer 213 on the sidewall and bottom surface of the wordline trench, the silicon oxide layer 213 is formed by the following process: forming silicon nitride on the sidewall and bottom surface of the wordline trench by a deposition process layer; completely oxidize the silicon nitride layer, and form a silicon oxide layer on the sidewall and bottom surface of the word line trench;
  • Word lines 214 on the silicon oxide layer 213 are .
  • the thickness T1 of the silicon oxide layer 213 on the sidewall surface of the wordline trench is greater than the thickness T2 of the silicon oxide layer 213 at the bottom of the wordline trench.
  • the thickness of the silicon oxide layer 213 on the sidewall surface of the word line trench gradually decreases from top to bottom.
  • the ratio of the thickness T1 of the silicon oxide layer 213 on the sidewall surface of the wordline trench to the thickness T2 of the silicon oxide layer 213 at the bottom of the wordline trench is 2:1-4:3. Specifically, the thickness T1 of the silicon oxide layer 213 on the sidewall surface of the wordline trench is 8 nm-10 nm, and the thickness T2 of the silicon oxide layer 213 at the bottom of the wordline trench is 5 nm-7 nm.
  • the plurality of active regions 202 are isolated by isolation layers 203 .
  • each active region 202 has two wordline trenches therein, and correspondingly each active region 202 has two wordline trenches 214 therein.

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Abstract

本申请实施例提供了一种DRAM及其形成方法，其中，DRAM的形成方法，包括提供半导体衬底，DRAM的形成方法半导体衬底上形成有的若干分立的有源区；刻蚀DRAM的形成方法有源区，在DRAM的形成方法有源区中形成字线沟槽；通过沉积工艺在DRAM的形成方法字线沟槽的侧壁和底部表面形成氮化硅层；将DRAM的形成方法氮化硅层完全氧化，在DRAM的形成方法字线沟槽的侧壁和底部表面形成氧化硅层；在DRAM的形成方法氧化硅层上形成字线。即形成的字线氧化硅层是通过将氮化硅层完全氧化获得，因而不会消耗字线沟槽两侧的源区和漏区中的硅，使得形成的氧化硅层的厚度由氮化硅层的厚度决定，保证了氧化硅层厚度的稳定，从而使得沟槽型的晶体管在同等开启电压下的开启电流不会减小。

Description

DRAM及其形成方法
交叉引用
本申请基于申请号为202110285121.5、申请日为2021年03月17日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及存储器领域。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
为了提高存储结构的集成度，动态随机存取存储器(DRAM)中的晶体管通常采用沟槽型的晶体管结构，沟槽型的晶体管的栅极与字线相连、漏区与位线相连、源区与电容器相连。
现有的动态随机存取存储器(DRAM)的沟槽型晶体管在形成栅极介电层的过程中会消耗衬底且栅极介电层的质量较差，存在开启电流下降的问题。
发明内容
本申请实施例可以/至少避免了沟槽型晶体管存在开启电流下降的问题。
根据一些实施例，本申请第一方面提供了一种DRAM的形成方法，包括：提供半导体衬底，所述半导体衬底上形成有的若干分立的有源区；刻蚀所述有源区，在所述有源区中形成字线沟槽；通过沉积工艺在所述字线沟槽的侧壁和底部表面形成氮化硅层；将所述氮化硅层完全氧化，在所述字线沟槽的侧壁和底部表面形成氧化硅层；在所述氧化硅层上形成字线。
根据一些实施例，本申请第二方面提供了一种DRAM，包括：半导体衬底，所述半导体衬底上形成有的若干分立的有源区；位于所述有源区中的字线沟槽；位于所述字线沟槽侧壁和底部表面的氧化硅层，所述氧化硅层通过下述工艺形成：通过沉积工艺在所述字线沟槽的侧壁和底部表面形成氮化硅层；将所述氮化硅层完全氧化，在所述字线沟槽的侧壁和底部表面形成氧化硅层；位于所述氧化硅层上的字线。
本公开实施例可以/至少具有以下优点，形成的字线氧化硅层是通过将氮化硅层完全氧化获得，不会消耗字线沟槽两侧的源区和漏区中的硅，使得形成的氧化硅层的厚度由氮化硅层的厚度决定，保证了氧化硅层厚度的稳定，从而使得沟槽型的晶体管在同等开启电压下的开启电流不会减小，并能使得源区和漏区大小能保持不变。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面 将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-图8为本申请实施例存储器形成过程的结构示意图。
具体实施方式
如背景技术所言，现有动态随机存取存储器(DRAM)的沟槽型晶体管存在开启电流下降的问题。
研究发现，现有形成沟槽型的晶体管结构的过程中，一般通过原子层沉积工艺(Atomic Layer Deposition，ALD)在半导体衬底中的字线沟槽的侧壁和底部形成字线氧化硅层，这种方式形成的字线氧化硅层的质量较差(具体表现为形成的氧化硅层的致密性不好，缺陷密度较高，粗糙度高)，后续再进行原位水汽生成氧化(In-Situ Steam Generation，ISSG)时(进行ISSG的目的是使得字线沟槽侧壁和底部上形成的氧化层厚度变得均匀，缺陷减少)，H 2/O 2会穿过沉积形成的字线氧化硅层直接氧化半导体衬底(当线宽进一步减小时衬底将不足以ISSG进行氧化)，这会导致源区和漏区的大小会减小，而形成的氧化硅层的厚度会增大，从而使得沟槽型的晶体管在同等开启电压下的开启电流下降。此外，字线氧化硅层的质量较差，对DRAM器件的长期的可靠性产生影响，DRAM器件的使用寿命相对较低。
为此，本申请提供了一种DRAM及其形成方法，其中所述DRAM的 形成方法，包括提供半导体衬底，所述半导体衬底上形成有的若干分立的有源区；刻蚀所述有源区，在所述有源区中形成字线沟槽；通过沉积工艺在所述字线沟槽的侧壁和底部表面形成氮化硅层；将所述氮化硅层完全氧化，在所述字线沟槽的侧壁和底部表面形成氧化硅层；在所述氧化硅层上形成字线。通过形成氮化硅层，然后将所述氮化硅层完全氧化，在所述字线沟槽的侧壁和底部表面形成氧化硅层，所述氧化硅层作为后续字线沟槽中形成的字线与有源区之间的字线氧化硅层，即形成的字线氧化硅层是通过将氮化硅层完全氧化获得，因而不会消耗字线沟槽两侧的源区和漏区中的硅，使得形成的氧化硅层的厚度由氮化硅层的厚度决定，保证了氧化硅层厚度的稳定，从而使得沟槽型的晶体管在同等开启电压下的开启电流不会减小，并能使得源区和漏区大小能保持不变。并且，这种方法，形成的字线氧化硅层质量会较好(具体的，相比于沉积工艺形成的氧化硅层致密性高，缺陷密度小，厚度更均匀，相比于氧化硅硅材料形成的氧化硅层致密性高，表面平整度高，表面粗糙度小，表面不存在颗粒缺陷)，能提高DRAM器件的可靠性和寿命。再次，将氮化硅层212氧化为氧化硅时可能会有部分N元素残留，残留的N元素会形成SiON，SiON的介电常数高于氧化硅(SiO 2)，相应的可提高栅极介电层的隔离性能。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在详述本申请实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请的保护范围。此外，在实际制作 中应包含长度、宽度及深度的三维空间尺寸。
参考图1-图2，图2为图1沿切割线AB方向的剖面结构示意图，提供半导体衬底201，所述半导体衬底201上形成有的若干分立的有源区202。
所述半导体衬底201的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中所述半导体衬底201材料为硅。所述半导体衬底中根据需要掺杂一定的杂质离子，所述杂质离子可以为N型杂质离子或P型杂质离子。在一实施例中，所述掺杂包括阱区掺杂和源漏区掺杂。
所述若干有源区202之间通过隔离层203隔离。
在一实施例中，所述有源区202和隔离层203的形成过程为：在所述半导体衬底201上形成第一掩膜层(图中未示出)，所述第一掩膜层中具有平行分布的若干第一掩膜开口；以所述第一掩膜层为掩膜，沿第一掩膜开口刻蚀所述半导体衬底201，在所述半导体衬底201中形成若干分立的长条形主动区，相邻的长条形主动区之间具有第一沟槽；刻蚀所述长条形主动区，在所述长条形主动区中形成若干第二沟槽，所述第二沟槽将每一个长条形主动区分割为若干有源区202；在所述第一沟槽和第二沟槽中填充隔离材料，形成隔离层203，所述隔离层203的材料可以为氧化硅或其他合适的隔离材料(在其他实施例中，可以先在第一沟槽中填充隔离材料，形成第一隔离层，形成第一隔离层后，刻蚀所述长条形主动区，在所述长条形主动区中形成若 干第二沟槽；然后在第二沟槽中填充隔离材料，形成第二隔离层，所述第一隔离层和第二隔离层构成隔离层)。需要说明的是，为了便于区分有源区202和半导体衬底201，图2中将有源区202和半导体衬底201通过虚线分开。
在其他实施例中，所述有源区202可以通过外延工艺形成。
本实施例中，可以将图1所示的x轴方向作为行方向，y轴方向作为列方向，相邻行中有源区202位置可以具有一定的错位。
参考图3，在所述有源区202和隔离层203上形成掩膜层210。
所述掩膜层210的材料可以为氧化硅、氮化硅、氮氧化硅中的一种或几种。所述掩膜层210可以为单层或多层堆叠结构。
在一实施例中，所述掩膜层210包括氮化硅层、位于氮化硅层上的无定形碳层、通过化学气相沉积工艺形成所述氮化硅层和无定形碳层。
参考图4，在所述掩膜层210中形成若干平行的开口211。
在一实施例中，所述开口211的延伸方向与有源区202的延伸方向呈一夹角，每一个所述开口211暴露出部分所述有源区202的表面，以及有源区202两侧的部分隔离层203的表面。
对所述掩膜层210进行图形化在所述掩膜层210中形成开口211，具体的先在所述掩膜层210上形成光刻胶层(图中未示出)；对所述光刻胶层进行曝光和显影，图形化所述光刻胶；然后以所述图形化的光刻胶层为掩膜，刻蚀所述掩膜层210，在所述掩膜层210中形成开口211。
在一实施例中，刻蚀所述掩膜层210采用各项异性的等离子体刻蚀工艺。
所述掩膜层210作为后续刻蚀有源区202和隔离层203形成字线沟槽时的掩膜，在一实施例中，每一个有源区202上的掩膜层210中对应形成有两个开口211，后续通过刻蚀在每个有源区202中对应形成两个字线沟槽。
参考图5，以所述掩膜层210为掩膜，刻蚀去除部分所述有源区202和隔离层203，在所述有源区202和隔离层203中形成字线沟槽204。
所述字线沟槽204包括位于有源区202中的第一部分字线沟槽和位于隔离层的第二部分字线沟槽，实际上一条字线沟槽包括第一部分字线沟槽和第二部分字线沟槽。
在一实施例中，当每一个有源区202上的掩膜层210中对应形成有两个开口211，每一个有源区202对应形成两个字线沟槽204，便于后续形成双沟槽晶体管，具体的所述两个字线沟槽204将每个有源区202分成位于中间的漏区和分别位于漏区两侧的两个源区。
刻蚀去除部分所述有源区202和隔离层203可以采用各项异性的等离子刻蚀工艺，在一实施例中，所述各项异性的等离子体刻蚀工艺采用的刻蚀气体包括Cl 2、HBr、CF 4、CHF 3中一种或多种的组合在一实施例中，所述各项异性的等离子体刻蚀工艺步骤中采用的刻蚀气体还包括氦气或氩气中一种或多种的组合。
参考图6，通过沉积工艺在所述字线沟槽204的侧壁和底部表面 形成氮化硅层212。
通过形成氮化硅层212，后续将所述氮化硅层212完全氧化，在所述字线沟槽204的侧壁和底部表面形成氧化硅层，所述氧化硅层作为后续字线沟槽中形成的字线与有源区202之间的字线氧化硅层，通过前述方法形成字线氧化硅层时，由于是通过将氮化硅层212完全氧化获得，因而不会消耗字线沟槽204两侧的源区和漏区中的硅，使得形成的氧化硅层的厚度由氮化硅层212的厚度决定，保证了氧化硅层厚度的稳定，从而使得沟槽型的晶体管在同等开启电压下的开启电流不会减小，并能使得源区和漏区大小能保持不变。并且，这种方法，形成的字线氧化硅层质量会较好(具体的，相比于沉积工艺形成的氧化硅层致密性高，缺陷密度小，厚度更均匀，相比于氧化硅硅材料形成的氧化硅层致密性高，表面平整度高，表面粗糙度小，表面不存在颗粒缺陷)，能提高DRAM器件的可靠性和寿命。再次，将氮化硅层212氧化为氧化硅时可能会有部分N元素残留，残留的N元素会形成SiON，SiON的介电常数高于氧化硅(SiO 2)，相应的可提高栅极介电层的隔离性能。
形成所述氮化硅层212的沉积工艺为原子层沉积工艺。
在一实施例中，所述字线沟槽204侧壁表面的氮化硅层212的厚度T1大于字线沟槽204底部的氮化硅212厚度T2，后续通过将氮化硅层212完全氧化，在字线沟槽204的侧壁和底部表面形成氧化硅层时，相应的使得字线沟槽204侧壁表面形成的氧化硅层的厚度大于字线沟槽204底部形成的氧化硅层厚度，因而在沟槽型晶体管工作时， 使得靠近源区和漏区的电场会低一些，而靠近沟道区域的电场会高一些，形成电场差，减少栅诱导漏极泄漏电流(GIDL，gate-induced drain leakage)，从而进一步防止开启电流的减小，以使得沟槽型晶体管的性能进一步提升，从而进一步提高DRAM的性能。
在一实施例中，所述字线沟槽204侧壁表面的氮化硅层212的厚度自上至下逐渐减小。
在一实施例中，所述字线沟槽204侧壁表面的氮化硅层212的厚度与字线沟槽204底部的氮化硅层212的厚度之比为2:1-4:3。研究发现，氮化硅层212的厚度不能太厚或太薄，太厚可能氧化不完全，太薄则无法满足电学要求。具体的所述字线沟槽204侧壁表面的氮化硅层212的厚度为8纳米-10纳米，所述字线沟槽204底部的氮化硅层212的厚度为5纳米-7纳米。
为了形成前述特定结构(所述字线沟槽204侧壁表面的氮化硅层212的厚度T1大于字线沟槽204底部的氮化硅212厚度T2)的氮化硅层212，所述所述原子层沉积工艺包括硅源气体和氮源气体，所述硅源气体包括DCS(二氯硅烷)，所述氮源气体包括NH3，所述硅源气体的流量范围为200sccm-600sccm，具体可以为350sccm-480sccm，氮源气体的流量范围为2000sccm-15000sccm，采用5000L/min的泵抽取沉积腔室中反应副产物。前述特性原子层沉积工艺条件下，在压力较低，供应用于薄膜沉积的源气体流量较小的情况下，气体自上向下流动，字线沟槽204上部分压力大于下部分压力，因而可以较简便的使得字线沟槽204侧壁表面的形成的氮化硅层212的厚度T1大于 字线沟槽204底部的形成的氮化硅212厚度T2。
参考图7，将所述氮化硅层212(参考图6)完全氧化，在所述字线沟槽204的侧壁和底部表面形成氧化硅层213。
通过原位水汽生成氧化(ISSG)或快速热氧化工艺将所述氮化硅层212完全氧化为氧化硅层213。
在一实施例中，所述字线沟槽204侧壁表面的氧化硅层213的厚度T1大于字线沟槽204底部的氧化硅层213厚度T2，后续在氧化硅213表面形成字线后，在沟槽型晶体管工作时，使得靠近源区和漏区的电场会低一些，而靠近沟道区域的电场会高一些，形成电场差，减少栅诱导漏极泄漏电流(GIDL，gate-induced drain leakage)，从而进一步防止开启电流的减小，以使得沟槽型晶体管的性能进一步提升，从而进一步提高DRAM的性能。
在一实施例中，所述字线沟槽204侧壁表面的氧化硅层213的厚度自上至下逐渐减小。
在一实施例中，所述字线沟槽204侧壁表面的氧化硅层213的厚度T1与字线沟槽204底部的氧化硅层213的厚度之比为2:1-4:3。具体的，所述字线沟槽侧壁表面的氧化硅层的厚度为8纳米-10纳米，所述字线沟槽底部的氧化硅层的厚度为5纳米-7纳米。
在一实施例中，通过原位水汽生成氧化(ISSG)工艺将所述氮化硅层212完全氧化为氧化硅层213，原位水汽生成氧化工艺时反应腔室中通入氧气和氢气，氧气的流量是氢气的流量的10倍以上，反应腔室的温度为900℃-1300℃，反应腔室的压力为4torr-15torr。 在低压环境下按一定比例通入氧气和氢气，之所以氧气比例高于氢气比例一方面是为了形成水汽环境，另一方面是为了形成氧化硅提供足够的氧源，通过高温水汽氛围来生长氧化层，其生长氧化层的速度较快，且采用原位水汽生成方法所生长出的栅氧化膜，其致密性更好。
参考图8，在所述氧化硅层213上形成字线214。
所述字线214的材料可以为W或者其他合适的金属材料。
在一实施例中，所述字线214的形成过程包括：在所述氧化硅层213上形成金属层，所述金属层填充满所述字线沟槽；平坦化去除半导体衬底表面的金属层，形成字线214。
在具体的实施例中，所述字线214可以与有源区202的表面齐平，或者低于所述有源区202的表面，或者略高于所述有源区202的表面。
本申请另一实施例还提供了一种DRAM，参考图8，包括：
半导体衬底201，所述半导体衬底201上形成有的若干分立的有源区202；
位于所述有源区202中的字线沟槽；
位于所述字线沟槽侧壁和底部表面的氧化硅层213，所述氧化硅层213通过下述工艺形成：通过沉积工艺在所述字线沟槽的侧壁和底部表面形成氮化硅层；将所述氮化硅层完全氧化，在所述字线沟槽的侧壁和底部表面形成氧化硅层；
位于所述氧化硅层213上的字线214。
在一实施例中，所述字线沟槽侧壁表面的氧化硅层213的厚度T1大于字线沟槽底部的氧化硅层213厚度T2。
在一实施例中，所述字线沟槽侧壁表面的氧化硅层213的厚度自上至下逐渐减小。
在一实施例中，所述字线沟槽侧壁表面的氧化硅层213的厚度T1与字线沟槽底部的氧化硅层213的厚度T2之比为2:1-4:3。具体的，所述字线沟槽侧壁表面的氧化硅层213的厚度T1为8纳米-10纳米，所述字线沟槽底部的氧化硅层213的厚度T2为5纳米-7纳米。
所述若干有源区202之间通过隔离层203隔离。
在一实施例中，每一个有源区202中具有两个字线沟槽，相应的每一个有源区202中具有两个字线214。
需要说明的是，本实施例中关于存储器(DRAM)其他限定或描述在本实施例中不再赘述，具体请参考前述存储器(DRAM)形成过程实施例中的相应限定或描述。
本申请虽然已以较佳实施例公开如上，但其并不是用来限定本申请，任何本领域技术人员在不脱离本申请的精神和范围内，都可以利用上述揭示的方法和技术内容对本申请技术方案做出可能的变动和修改，因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本申请技术方案的保护范围。

Claims (17)

  1. 一种DRAM的形成方法，包括：
    提供半导体衬底，所述半导体衬底上形成有的若干分立的有源区；
    刻蚀所述有源区，在所述有源区中形成字线沟槽；
    通过沉积工艺在所述字线沟槽的侧壁和底部表面形成氮化硅层；
    将所述氮化硅层完全氧化，在所述字线沟槽的侧壁和底部表面形成氧化硅层；
    在所述氧化硅层上形成字线。
  2. 如权利要求1所述的DRAM的形成方法，其中，通过原位水汽生成氧化工艺或快速热氧化工艺将所述氮化硅层完全氧化为氧化硅层。
  3. 如权利要求1所述的DRAM的形成方法，其中，所述字线沟槽侧壁表面的氧化硅层的厚度大于字线沟槽底部的氧化硅层厚度。
  4. 如权利要求3所述的DRAM的形成方法，其中，所述字线沟槽侧壁表面的氧化硅层的厚度自上至下逐渐减小。
  5. 如权利要求3所述的DRAM的形成方法，其中，所述字线沟槽侧壁表面的氧化硅层的厚度与字线沟槽底部的氧化硅层的厚度之比为2:1-4:3。
  6. 如权利要求3所述的DRAM的形成方法，其中，所述字线沟槽侧壁表面的氧化硅层的厚度为8纳米-10纳米，所述字线沟槽底部的氧化硅层的厚度为5纳米-7纳米。
  7. 如权利要求3所述的DRAM的形成方法，其中，所述氧化硅层的形成过程为：通过原子层沉积工艺在所述字线沟槽的侧壁和底部表面形成氮化硅层，所述字线沟槽侧壁表面的氮化硅层的厚度大于所述字线沟槽底部的氮化硅厚度；通过原位水汽生成氧化工艺将所述氮化硅层完全氧化为氧化硅层，在所述字线沟槽的侧壁和底部表面形成氧化硅层，所述字线沟槽侧壁表面的氧化硅层的厚度大于所述字线沟槽底部的氧化硅层厚度。
  8. 如权利要求7所述的DRAM的形成方法，其中，所述字线沟槽侧壁表面的氮化硅层的厚度自上至下逐渐减小。
  9. 如权利要求7所述的DRAM的形成方法，其中，所述原子层沉积工艺包括硅源气体和氮源气体，所述硅源气体包括二氯硅烷(DCS)，所述氮源气体包括NH 3，所述硅源气体的流量范围为200sccm-600sccm，氮源气体的流量范围为2000sccm-15000sccm，采用5000L/min的泵抽取沉积腔室中反应副产物。
  10. 如权利要求6所述的DRAM的形成方法，其中，原位水汽生成氧化工艺时反应腔室中通入氧气和氢气，氧气的流量是氢气的流量的10倍以上，反应腔室的温度为900℃-1300℃，反应腔室的压力为4torr-15torr。
  11. 如权利要求1所述的DRAM的形成方法，其中，所述若干有源区之间通过隔离层隔离。
  12. 如权利要求1所述的DRAM的形成方法，其中，每一个有源区中具有两个字线沟槽。
  13. 一种DRAM，包括：
    半导体衬底，所述半导体衬底上形成有的若干分立的有源区；
    位于所述有源区中的字线沟槽；
    位于所述字线沟槽侧壁和底部表面的氧化硅层，所述氧化硅层通过下述工艺形成：通过沉积工艺在所述字线沟槽的侧壁和底部表面形成氮化硅层；
    将所述氮化硅层完全氧化，在所述字线沟槽的侧壁和底部表面形成氧化硅层；
    位于所述氧化硅层上的字线。
  14. 如权利要求13所述的DRAM，其中，所述字线沟槽侧壁表面的氧化硅层的厚度大于字线沟槽底部的氧化硅层厚度。
  15. 如权利要求14所述的DRAM，其中，所述字线沟槽侧壁表面的氧化硅层的厚度自上至下逐渐减小。
  16. 如权利要求14所述的DRAM，其中，所述字线沟槽侧壁表面的氧化硅层的厚度与字线沟槽底部的氧化硅层的厚度之比为2:1-4:3。
  17. 如权利要求16所述的DRAM，其中，所述字线沟槽侧壁表面的氧化硅层的厚度为8纳米-10纳米，所述字线沟槽底部的氧化硅层的厚度为5纳米-7纳米。
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Publication number Priority date Publication date Assignee Title
CN112951827A (zh) * 2021-03-17 2021-06-11 长鑫存储技术有限公司 Dram及其形成方法
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04298075A (ja) * 1991-03-27 1992-10-21 Toshiba Corp 半導体装置およびその製造方法
US5380675A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Method for making closely spaced stacked capacitors on DRAM chips
CN105470202A (zh) * 2014-09-12 2016-04-06 上海华虹宏力半导体制造有限公司 分栅快闪存储器浮栅尖端的制造方法
CN110610940A (zh) * 2018-06-15 2019-12-24 长鑫存储技术有限公司 存储晶体管、存储晶体管的字线结构及字线制备方法
CN111587489A (zh) * 2018-12-17 2020-08-25 桑迪士克科技有限责任公司 具有应力竖直半导体沟道的三维存储器器件及其制备方法
CN112018115A (zh) * 2019-05-29 2020-12-01 三星电子株式会社 集成电路装置及其制造方法
CN112951827A (zh) * 2021-03-17 2021-06-11 长鑫存储技术有限公司 Dram及其形成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101003494B1 (ko) * 2008-04-10 2010-12-30 주식회사 하이닉스반도체 메모리 소자의 소자분리 구조 및 형성 방법
KR20160139301A (ko) * 2015-05-27 2016-12-07 삼성전자주식회사 스트레서를 가지는 반도체 소자 및 그 제조 방법
US9859298B1 (en) * 2016-06-23 2018-01-02 Sandisk Technologies Llc Amorphous silicon layer in memory device which reduces neighboring word line interference
CN109216359B (zh) * 2017-07-04 2022-06-03 华邦电子股份有限公司 存储器装置及其制造方法
CN112447605A (zh) * 2019-08-30 2021-03-05 长鑫存储技术有限公司 Dram存储器及其形成方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04298075A (ja) * 1991-03-27 1992-10-21 Toshiba Corp 半導体装置およびその製造方法
US5380675A (en) * 1994-03-21 1995-01-10 United Microelectronics Corporation Method for making closely spaced stacked capacitors on DRAM chips
CN105470202A (zh) * 2014-09-12 2016-04-06 上海华虹宏力半导体制造有限公司 分栅快闪存储器浮栅尖端的制造方法
CN110610940A (zh) * 2018-06-15 2019-12-24 长鑫存储技术有限公司 存储晶体管、存储晶体管的字线结构及字线制备方法
CN111587489A (zh) * 2018-12-17 2020-08-25 桑迪士克科技有限责任公司 具有应力竖直半导体沟道的三维存储器器件及其制备方法
CN112018115A (zh) * 2019-05-29 2020-12-01 三星电子株式会社 集成电路装置及其制造方法
CN112951827A (zh) * 2021-03-17 2021-06-11 长鑫存储技术有限公司 Dram及其形成方法

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