WO2022193490A1 - 刷新电路及存储器 - Google Patents

刷新电路及存储器 Download PDF

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Publication number
WO2022193490A1
WO2022193490A1 PCT/CN2021/105218 CN2021105218W WO2022193490A1 WO 2022193490 A1 WO2022193490 A1 WO 2022193490A1 CN 2021105218 W CN2021105218 W CN 2021105218W WO 2022193490 A1 WO2022193490 A1 WO 2022193490A1
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Prior art keywords
address
row
refresh
output
hammer
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PCT/CN2021/105218
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English (en)
French (fr)
Inventor
曹先雷
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长鑫存储技术有限公司
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Priority to US17/453,877 priority Critical patent/US11854595B2/en
Publication of WO2022193490A1 publication Critical patent/WO2022193490A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the present disclosure relates to, but is not limited to, a refresh circuit and a memory.
  • memory cells have the characteristics of shrinking physical volume, reduced storage charge, and reduced noise tolerance. Likelihood increases.
  • the embodiments of the present disclosure provide a refresh circuit and a memory, which are beneficial to refresh the line hammer address in time and ensure the accuracy of data storage of the line hammer address.
  • An embodiment of the present disclosure provides a refresh circuit, including: a row hammer address generation module, configured to receive a row activation command, a precharge command, and a single row address corresponding to the row activation command, and output a row hammer address corresponding to the single row address,
  • a row hammer address generation module configured to receive a row activation command, a precharge command, and a single row address corresponding to the row activation command, and output a row hammer address corresponding to the single row address
  • Each of the single row addresses corresponds to a word line
  • the row activation command is used to turn on the word line pointed to by the single row address
  • the precharge command is used to turn off the word line
  • the row hammer address is output
  • a signal selector is used to receive the row hammer address and the regular refresh address, and output at least the row hammer address, and the signal selector outputs the row hammer address.
  • the hammer address and the regular refresh address are used as
  • An embodiment of the present disclosure further provides a memory, including the refresh circuit described in any one of the above.
  • the pre-designed values can be dynamically adjusted according to the performance of capacitors in different memories, so that the refresh circuit is suitable for different memories.
  • FIG. 1 is a schematic functional structure diagram of a refresh circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the functional structure of the timing unit in the refresh circuit shown in FIG. 1 .
  • the refresh circuit includes: a row hammer address generation module 10 for receiving a row activation command 10a, a precharge command 10b and a single row address 10c corresponding to the row activation command 10a, and outputting a row hammer address 10d corresponding to the single row address 10c.
  • a single row address 10c corresponds to a word line
  • the row activation command 10a is used to turn on the word line pointed to by the single row address 10c
  • the precharge command 10b is used to turn off the word line; if the single turn-on time of the word line is greater than the preset time, the output row The hammer address 10d; the signal selector 20 is used to receive the row hammer address 10d and the regular refresh address 30d, and output at least the row hammer address 10d, and the row hammer address 10d and the regular refresh address 30d output by the signal selector 20 correspond to the refresh command Refresh the object.
  • the row hammer address generation module 10 is used for receiving a plurality of different single row addresses 10c.
  • the word line pointed to by the single row address 10c changes correspondingly, which is used to turn on and
  • the row activate command 10a and the precharge command 10b to turn off the word lines are changed accordingly.
  • the signal selector 20 outputs a line hammer address 10d or a regular refresh address 30d when a refresh command arrives, and each refresh command corresponds to a preset number of refresh lines, that is, under the excitation of a refresh command, the signal selector 20 can A preset number of addresses to be refreshed are output, and the addresses to be refreshed are hammer addresses 10d or regular refresh addresses 30d.
  • the value of the "preset number" may vary with the application environment of the refresh circuit, and the following description takes the preset number as m as an example.
  • Each row activation command 10a and each precharge command 10b corresponds to a specific word line, and the single turn-on duration of a specific word line can be determined by the receiving time interval of the row activation command 10a and the precharge command 10b corresponding to the specific word line.
  • the size of the preset time is related to the performance of the memory, specifically, it is related to the stored charge of the capacitor and the discharge rate of the capacitor under the row hammer effect, the more the stored charge, or the slower the discharge rate of the capacitor under the row hammer effect, The longer the single turn-on time a specific word line can withstand, the larger the threshold range of the preset time can be set.
  • the row hammer address 10d is the adjacent address of the single row address 10c. If the single row address 10c is m, and m is a positive integer, the row hammer address 10d includes the first single row address and the second single row address, and the first single row address is m-1. The second single row address is m+1.
  • the row hammer address 10d is a collective name for adjacent addresses, and the unit is "group".
  • a group of row hammer addresses 10d may include one or more adjacent addresses of a single row address 10c. In some embodiments, the row hammer address only includes m +1 or m-1, alternatively, also includes at least one of m+2 or m-2.
  • This disclosure mainly discusses the function of the refresh circuit after receiving the line hammer address 10d, that is, at least outputting the line hammer address 10d to realize the priority refresh of the line hammer address 10d; about the function of the refresh circuit before receiving the line hammer address 10d , that is, the refresh is performed according to the refresh order of the default conventional refresh addresses, which is known to those skilled in the art, and is only briefly described herein.
  • the line hammer address generation module 10 includes: a timing unit 11 for receiving the line activation command 10a and the precharge command 10b to obtain a single turn-on time, and if the single turn-on time is greater than the preset time, the output times out Signal 11a; the row address latch unit 12 is used to receive the single row address 10c and connect the output end of the timing unit 11, if the timeout signal 11a is received, latch and output the single row address 10c; the row hammer address generation unit 13 is used for The single row address 10c output by the row address latch unit 12 is received, and the row hammer address 10d corresponding to the single row address 10c is output.
  • the signal selector 20 before the refresh command arrives, the signal selector 20 only receives the newly generated set of row hammer addresses 10d as an example for detailed description, and the newly generated set of row hammer addresses 10d may include one or more phase Adjacent address; in other embodiments, the signal selector receives one or more groups of row hammer addresses generated first, or receives row hammer addresses corresponding to all single row addresses output by the row address latch unit.
  • the row address latch unit 12 Since the row address latch unit 12 is used for receiving a plurality of different single row addresses 10c, and the single turn-on time of the word line pointed to by each single row address 10c may be longer than the preset time, therefore, the row address latch unit 12 may need to Multiple single row addresses 10c are latched and output.
  • the row address latch unit 12 is used to sequentially output the single row address 10c corresponding to each timeout signal 11a, and the single row address 10c outputted later replaces the single row address 10c output earlier, and the row hammer address generating unit 13 uses The row hammer address 10d corresponding to each single row address 10c received is sequentially output, and the row hammer address 10d outputted later replaces the row hammer address 10d outputted earlier.
  • the line hammer address generating unit 13 only outputs the newly generated group of line hammer addresses 10d, and the signal selector 20 only receives the newly generated group of line hammer addresses 10d, and then when the refresh command arrives , the signal selector 20 only outputs a group of newly generated line hammer addresses 10d.
  • the row address latch unit after receiving the timeout signal, the row address latch unit outputs all the single row addresses corresponding to all the received timeout signals, or the row address latch unit sequentially outputs the single row address corresponding to each timeout signal,
  • the row hammer address generation unit has a storage function, or the row address latch unit sequentially outputs a single row address corresponding to each timeout signal, and the signal selector has a storage function.
  • the row hammer address generation unit can receive all single row addresses and output the row hammer addresses corresponding to all single row addresses, and the signal selector can receive the row hammer addresses corresponding to all single row addresses, so that when the refresh command arrives, output The line hammer address corresponding to all single line addresses.
  • restricting conditions can be added, so that when the refresh command arrives, the signal selector only outputs x groups of row hammer addresses corresponding to x single row addresses, where x is a positive integer.
  • the restriction conditions can be any of the following: First, restrict the latching capability or output capability of the row address latch unit, so that the row address latch unit can only latch and output x single row addresses, while the x+1th cannot. Latch and output; second, limit the storage capacity or output capability of the line hammer address generation unit, so that the line hammer address generation unit can only store and output x groups of line hammer addresses, and cannot store the x+1th single line address or output.
  • the signal selector can only receive the newly generated set of row hammer addresses, so as to output the first x-1 sets of row hammer addresses and the last set of row hammer addresses. A total of x groups.
  • the timing unit 11 includes: a first counting unit 111 , configured to receive the row activation command 10a, the precharge command 10b and the clock signal 10e, and after receiving the row activation command 10a, receive the precharge command 10a.
  • a first counting unit 111 configured to receive the row activation command 10a, the precharge command 10b and the clock signal 10e, and after receiving the row activation command 10a, receive the precharge command 10a.
  • the comparison unit 112 is used to receive the first count value 111a, if the first count value 111a is greater than the preset value, A timeout signal 11a is output; wherein the preset value is equal to the preset time divided by the period of the clock signal 10e.
  • the clock signal 10e is a periodic internal clock signal, and the period of the clock signal 10e of different memories may be different; wherein, when the preset time remains unchanged, the preset values of the refresh circuits applied to different memories may be different.
  • the first counting unit 111 may be an asynchronous binary addition counter composed of a plurality of D flip-flops connected in series, and counts the number of cycles of the clock signal 10e.
  • the timing unit 11 further includes: a storage subunit 113 for writing and storing the preset value 113a, the output end of the storage subunit 113 is connected to the input end of the comparison unit 112, and the comparison unit 112 is used for storing
  • the subunit 113 acquires the pre-designed value 113a.
  • the preset value 113a stored in the storage subunit 113 can be updated by writing a new preset value 113a, so that the preset value 113a has adjustable characteristics.
  • a fixed pre-designed value is stored in the comparison unit.
  • the pre-designed values for different refresh circuits can be different to apply to different types of memories.
  • the signal selector 20 on the basis that the signal selector 20 only receives the last set of row hammer addresses 10d, and the last set of row hammer addresses 10d only includes two adjacent addresses, the signal selector 20 outputs n-2 first.
  • the conventional refresh address 30d then outputs two adjacent addresses as an example for an actual output manner.
  • the actual output mode of the signal selector is: before receiving the line hammer address, receive and output each regular refresh address; if the line hammer address is received, stop outputting the regular refresh address, and output the received Each line hammer address; after outputting the line hammer address, continue to receive and output each regular refresh address.
  • the signal selector 20 is also used for receiving the selection signal 40a, and before receiving the selection signal 20a, sequentially receives and outputs each regular refresh address 30d, and stops outputting the regular refresh address 30d after receiving the selection signal 30d , receive and output each row hammer address 10d in turn; wherein, the selection signal 40a indicates that the signal selector 20 has received n-2 regular refresh addresses 30d, n is the number of refresh rows corresponding to each refresh command, n>2.
  • the select signal indicates that the signal selector has received n-k regular refresh addresses, n>k, k is multiplied by the number of sets of row hammer addresses output by the signal selector by the adjacent rows contained in each set of row hammer addresses The number of addresses is obtained.
  • the refresh circuit further includes: a second counting unit 40, configured to count the number of the regular refresh addresses 30d received by the signal selector 20, and obtain a second count value, if the second count value is equal to n- 2. Output the selection signal 40a.
  • a second counting unit 40 configured to count the number of the regular refresh addresses 30d received by the signal selector 20, and obtain a second count value, if the second count value is equal to n- 2. Output the selection signal 40a.
  • the selection signal 40a is the identification signal output by the second counting unit 40, and is used to switch the switch of the signal selector 20 to receive the row address information, so that the path between the signal selector 20 and the conventional refresh address generating unit 30 is closed, and the signal selector 20 is closed.
  • the path between the counter 20 and the line hammer address generating unit 13 is opened to receive and output the line hammer address 10d; in addition, the identification signal may be the value itself of the second count value.
  • the signal selector 20 is reset after outputting the regular refresh address 30d and the row hammer address 10d, to be precise, after outputting n-2 regular refresh addresses 30d and a set of row hammer addresses 10d.
  • the second count value is to stop outputting the selection signal 40a to wait for the arrival of the next refresh command, thereby repeating the above output steps, namely outputting n-2 regular refresh addresses 30d first, and then outputting a group of hammer addresses 10d.
  • the second counting unit 40 is also used to write and update the value of n-2; after updating the value of n-2, if the second counting value is equal to the updated n-2, the selection signal 40a is output .
  • the number of refresh lines is all used for the refresh of the line hammer address 10d.
  • the refresh circuit further includes: a conventional refresh address generation unit 30 for generating and outputting at least one conventional refresh address 30d, the output end of the conventional refresh address generation unit 30 is respectively connected with the input end of the signal selector 20 and the second The input end of the counting unit 40 is connected, and the second counting unit 40 is configured to receive at least one regular refresh address 30d output by the regular refresh address generating unit 30 .
  • the line hammer address in the case of receiving the line hammer address and the conventional refresh address, at least the line hammer address is output, and there is no need to refresh the line hammer address sequentially according to the default refresh order of the conventional refresh address, so as to realize the priority refresh of the line hammer address and avoid the line hammer address.
  • the corresponding capacitor loses data due to excessive charge loss, which ensures the accuracy of data storage.
  • an embodiment of the present disclosure further provides a memory including any one of the above refresh circuits.
  • the memory can preferentially refresh the row hammer address to avoid data loss due to excessive charge loss of the capacitor corresponding to the row hammer address before the refresh signal arrives, thereby improving the data storage accuracy of the memory.
  • the refresh circuit and memory provided by the embodiments of the present disclosure, in the case of receiving a line hammer address and a conventional refresh address, at least the line hammer address is output, and there is no need to perform sequential refresh according to the default refresh order of the conventional refresh address, so that the line hammer address can be refreshed. Prioritize refresh to avoid data loss due to excessive charge loss of the capacitor corresponding to the line hammer address before the refresh signal arrives, and to ensure the accuracy of data storage.

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Abstract

一种刷新电路及存储器，刷新电路包括：行锤地址生成模块（10），用于接收行激活命令（10a）、预充电命令（10b）以及所述行激活命令（10a）对应的单行地址（10c），输出所述单行地址（10c）对应的行锤地址（10d），每一所述单行地址（10c）与一字线对应，所述行激活命令（10a）用于开启所述单行地址（10c）指向的字线，所述预充电命令（10b）用于关闭所述字线；若所述字线的单次开启时间大于预设时间，输出所述行锤地址（10d）；信号选择器（20），用于接收所述行锤地址（10d）和常规刷新地址（30d），并至少输出所述行锤地址（10d），所述信号选择器（20）输出的所述行锤地址（10d）和所述常规刷新地址（30d）作为刷新命令对应的刷新对象。

Description

刷新电路及存储器
本公开要求在2021年03月15日提交中国专利局、申请号为202110277829.6、发明名称为“刷新电路及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种刷新电路及存储器。
背景技术
随着半导体存储装置的密度不断增加，存储器单元呈现物理体积缩小、存储电荷减少以及抗噪声容限降低的特点，存储器单元之间的电磁相互作用对存储器单元的影响增大，存储器单元数据丢失的可能性增加。
当存储器单元中某一单行地址的单次开启时间过长时，可能引发相邻地址(一般称为“行锤地址”)的电容器的放电速率高于自然放电速率，进而导致相邻地址的电容器在刷新信号到来之前因丢失过多电荷而发生数据丢失，这种情况一般称之为“行锤效应”；为抑制行锤效应，需要对行锤地址进行及时的刷新操作，以重新补充电荷，避免存储数据发生错误。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种刷新电路及存储器，有利于及时刷新行锤地址，保证行锤地址的数据存储准确性。
本公开实施例提供一种刷新电路，包括：行锤地址生成模块，用于接收行激活命令、预充电命令以及所述行激活命令对应的单行地址，输出所述单行地址对应的行锤地址，每一所述单行地址与一字线对应，所述行激活命令用于开启所述单行地址指向的字线，所述预充电命令用于关闭所述字线；若所述字线的单次开启时间大于预设时间，输出所述行锤地址；信号选择器， 用于接收所述行锤地址和常规刷新地址，并至少输出所述行锤地址，所述信号选择器输出的所述行锤地址和所述常规刷新地址作为刷新命令对应的刷新对象。
本公开实施例还提供一种存储器，包括上述任一项所述的刷新电路。
本公开实施例提供的技术方案具有以下优点：
上述技术方案中，在接收行锤地址和常规刷新地址的情况下，至少输出行锤地址，无需根据默认的常规刷新地址的刷新顺序进行依次刷新，实现行锤地址的优先刷新，避免行锤地址对应的电容器在刷新信号到来之前因丢失过多电荷而发生数据丢失，保证数据存储的准确性。
另外，可根据不同存储器中电容器的性能动态调整预设计数值，从而使得刷新电路适用于不同存储器。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本公开实施例提供的一种刷新电路的功能结构示意图；
图2为图1所示刷新电路中计时单元的功能结构示意图。
具体实施方式
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
参考图1，刷新电路包括：行锤地址生成模块10，用于接收行激活命令10a、预充电命令10b以及行激活命令10a对应的单行地址10c，输出单行地址10c对应的行锤地址10d，每一单行地址10c与一字线对应，行激活命令10a用于开启单行地址10c指向的字线，预充电命令10b用于关闭字线；若字线的单次开启时间大于预设时间，输出行锤地址10d；信号选择器20，用于接收行锤地址10d和常规刷新地址30d，并至少输出行锤地址10d，信号选择器20输出的行锤地址10d和常规刷新地址30d作为刷新命令对应的刷新对象。
其中，行锤地址生成模块10用于接收多个不同的单行地址10c，当行锤地址生成模块10接收到的单行地址10c发生变化时，单行地址10c指向的字线相应发生变化，用于开启和关闭字线的行激活命令10a和预充电命令10b相应发生变化。信号选择器20在刷新命令到来时输出行锤地址10d或常规刷新地址30d，每一刷新命令对应预设数量的刷新行数，也就是说，在一个刷新命令的激励下，信号选择器20可输出预设数量的待刷新地址，待刷新地址为行锤地址10d或常规刷新地址30d。“预设数量”的值可随着刷新电路应用环境的变化而变化，以下以预设数量为m作为示例进行说明。
每一行激活命令10a和每一预充电命令10b对应特定的字线，通过特定字线对应的行激活命令10a和预充电命令10b的接收时间间隔，可以确定特定字线的单次开启时长。预设时间的大小与存储器的性能有关，具体来说，与电容器的存储电荷以及电容器在行锤效应下的放电速率有关，存储电荷越多，或者电容器在行锤效应下的放电速率越慢，特定字线可承受的单次开启时间越长，可设置预设时间的阈值范围越大。
行锤地址10d为单行地址10c的相邻地址，若单行地址10c为m，m为正整数，则行锤地址10d包括第一单行地址和第二单行地址，第一单行地址为m-1，第二单行地址为m+1。行锤地址10d是相邻地址的统称，单位为“组”，一组行锤地址10d可包括一个单行地址10c的一个或多个相邻地址，在一些实施例中，行锤地址仅包括m+1或m-1，或者，还包括m+2或m-2中的至少一者。
本公开主要讨论的是刷新电路在接收到行锤地址10d之后的功能，即至少输出行锤地址10d，以实现行锤地址10d的优先刷新；关于刷新电路在接 收到行锤地址10d之前的功能，即按照默认的常规刷新地址的刷新顺序进行刷新，属于本领域技术人员已经知晓的内容，本文仅做简单描述。
本实施例中，行锤地址生成模块10包括：计时单元11，用于接收行激活命令10a和预充电命令10b，以获取单次开启时间，若单次开启时间大于预设时间，则输出超时信号11a；行地址锁存单元12，用于接收单行地址10c并连接计时单元11的输出端，若接收到超时信号11a，则锁存并输出单行地址10c；行锤地址生成单元13，用于接收行地址锁存单元12输出的单行地址10c，并输出单行地址10c对应的行锤地址10d。
本实施例中，以信号选择器20在刷新命令到来之前，仅接收最新生成的一组行锤地址10d作为示例进行详细说明，最新生成的一组行锤地址10d中可以包括一个或多个相邻地址；在其他实施例中，信号选择器接收最先产生的一组或多组行锤地址，或者，接收行地址锁存单元输出的所有单行地址对应的行锤地址。
由于行地址锁存单元12用于接收多个不同的单行地址10c，而每一单行地址10c指向的字线的单次开启时间都可能大于预设时间，因此，行地址锁存单元12可能需要锁存并输出多个单行地址10c。
本实施例中，行地址锁存单元12用于顺序输出每一超时信号11a对应的单行地址10c，且在后输出的单行地址10c代替在先输出的单行地址10c，行锤地址生成单元13用于顺序输出接收到的每一单行地址10c对应的行锤地址10d，且在后输出的行锤地址10d代替在先输出的行锤地址10d。如此，可在刷新命令到来之前，行锤地址生成单元13仅输出最新生成的一组行锤地址10d，信号选择器20仅接收最新生成的一组行锤地址10d，进而在刷新命令到来之时，信号选择器20仅输出最新生成的一组行锤地址10d。
在其他实施例中，行地址锁存单元在接收到超时信号之后，输出已经接收到的所有超时信号对应的所有单行地址，或者，行地址锁存单元顺序输出每一超时信号对应的单行地址，行锤地址生成单元具有存储功能，或者，行地址锁存单元顺序输出每一超时信号对应的单行地址，信号选择器具有存储功能。如此，可使得行锤地址生成单元接收到所有单行地址并输出所有单行地址对应的行锤地址，以及使得信号选择器接收到所有单行地址对应的行锤地址，从而在刷新命令到来之时，输出所有单行地址对应的行锤地址。
其中，可通过增加限制条件，使得在刷新命令到来之时，信号选择器仅输出x个单行地址对应的x组行锤地址，x为正整数。限制条件可以为以下任意一种：第一，限制行地址锁存单元的锁存能力或输出能力，使得行地址锁存单元仅能锁存并输出x个单行地址，而第x+1个无法锁存并输出；第二，限制行锤地址生成单元的存储能力或输出能力，使得行锤地址生成单元仅能存储并输出x组行锤地址，无法存储第x+1个单行地址或者无法输出第x+1组行锤地址；第三，限制信号选择器的存储能力，使得信号选择器仅能存储x-1组行锤地址，如此，除了已经存储的x-1组行锤地址，基于在后输出代替在先输出的规则，在刷新命令到来之时，信号选择器仅能接收最新生成的一组行锤地址，从而输出前x-1组行锤地址以及最后一组行锤地址，共x组。
本实施例中，参考图2，计时单元11包括：第一计数单元111，用于接收行激活命令10a、预充电命令10b以及时钟信号10e，并在接收到行激活命令10a之后、接收到预充电命令10b之前，对接收到的时钟信号10e的周期个数进行计数，输出第一计数值111a；比较单元112，用于接收第一计数值111a，若第一计数值111a大于预设计数值，输出超时信号11a；其中，预设计数值等于预设时间除以时钟信号10e的周期。
时钟信号10e为周期性的内部时钟信号，不同存储器的时钟信号10e的周期可能不同；其中，在预设时间不变的情况下，应用于不同存储器的刷新电路的预设计数值可能不同。此外，第一计数单元111可以是由多个D触发器串联组成的异步二进制加法计数器，对时钟信号10e的周期个数进行计数。
本实施例中，计时单元11还包括：存储子单元113，用于写入并存储预设计数值113a，存储子单元113的输出端与比较单元112的输入端连接，比较单元112用于通过存储子单元113获取预设计数值113a。其中，可通过写入新的预设计数值113a的方式更新存储子单元113存储的预设计数值113a，使得预设计数值113a具有可调整的特性。
在其他实施例中，比较单元内存储有固定的预设计数值。不同刷新电路的预设计数值可以不同，以应用于不同类型的存储器。
本实施例中，以信号选择器20仅接收最后生成的一组行锤地址10d，且 最后一组行锤地址10d仅包含2个相邻地址为基础，以信号选择器20先输出n-2个常规刷新地址30d再输出2个相邻地址作为实际输出方式进行示例性说明。
在其他实施例中，信号选择器的实际输出方式为：在接收到行锤地址之前，接收并输出每一常规刷新地址；若接收到行锤地址，中止输出常规刷新地址，并输出接收到的每一行锤地址；在输出完行锤地址之后，继续接收并输出每一常规刷新地址。
本实施例中，信号选择器20还用于接收选择信号40a，在接收到选择信号20a之前，依次接收并输出每一常规刷新地址30d，在接收到选择信号30d之后，中止输出常规刷新地址30d，依次接收并输出每一行锤地址10d；其中，选择信号40a表征信号选择器20已接收到n-2个常规刷新地址30d，n为每一刷新命令对应的刷新行数，n>2。
在其他实施例中，选择信号表征信号选择器已接收到n-k个常规刷新地址，n>k，k由信号选择器输出的行锤地址的组数乘以每一组行锤地址包含的相邻地址的个数得到。
本实施例中，刷新电路还包括：第二计数单元40，用于对信号选择器20接收到的常规刷新地址30d的个数进行计数，获取第二计数值，若第二计数值等于n-2，输出选择信号40a。
其中，选择信号40a为第二计数单元40输出的标识信号，用于切换信号选择器20接收行地址信息的开关，使得信号选择器20与常规刷新地址生成单元30之间的通路关闭，信号选择器20与行锤地址生成单元13之间的通路打开，从而接收并输出行锤地址10d；此外，该标识信号可以是第二计数值这一数值本身。
本实施例中，信号选择器20在输出完常规刷新地址30d和行锤地址10d之后，准确来说，是在输出完n-2个常规刷新地址30d和一组行锤地址10d之后，重置第二计数值，中止输出选择信号40a，以等待下一个刷新命令到来，从而重复执行上述输出步骤，即先输出n-2个常规刷新地址30d，再输出一组行锤地址10d。
本实施例中，第二计数单元40还用于写入并更新n-2的值；在更新n-2的值以后，若第二计数值等于更新后的n-2，则输出选择信号40a。如此，有 利于根据信号选择器20输出行锤地址10d的策略及时更新n-2的值，保证能够在刷新命令对应的刷新行数内完成行锤地址10d的刷新，或者，将刷新命令对应的刷新行数全部用于行锤地址10d的刷新。
本实施例中，刷新电路还包括：常规刷新地址生成单元30，用于生成并输出至少一个常规刷新地址30d，常规刷新地址生成单元30的输出端分别与信号选择器20的输入端和第二计数单元40的输入端连接，第二计数单元40用于接收常规刷新地址生成单元30输出的至少一个常规刷新地址30d。
本实施例中，在接收行锤地址和常规刷新地址的情况下，至少输出行锤地址，无需根据默认的常规刷新地址的刷新顺序进行依次刷新，实现行锤地址的优先刷新，避免行锤地址对应的电容器在刷新信号到来之前因丢失过多电荷而发生数据丢失，保证数据存储的准确性。
相应地，本公开实施例还提供一种存储器，包含上述任一项的刷新电路。存储器可通过优先刷新行锤地址，避免行锤地址对应的电容器在刷新信号到来之前因丢失过多电荷而发生数据丢失，提高存储器的数据存储准确性。
本领域的技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的 方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的刷新电路及存储器，在接收行锤地址和常规刷新地址的情况下，至少输出行锤地址，无需根据默认的常规刷新地址的刷新顺序进行依次刷新，实现行锤地址的优先刷新，避免行锤地址对应的电容器在刷新信号到来之前因丢失过多电荷而发生数据丢失，保证数据存储的准确性。

Claims (15)

  1. 一种刷新电路，所述刷新电路包括：
    行锤地址生成模块，设置为接收行激活命令、预充电命令以及所述行激活命令对应的单行地址，输出所述单行地址对应的行锤地址，每一所述单行地址与一字线对应，所述行激活命令设置为开启所述单行地址指向的字线，所述预充电命令设置为关闭所述字线；若所述字线的单次开启时间大于预设时间，输出所述行锤地址；
    信号选择器，设置为接收所述行锤地址和常规刷新地址，并至少输出所述行锤地址，所述信号选择器输出的所述行锤地址和所述常规刷新地址作为刷新命令对应的刷新对象。
  2. 根据权利要求1所述的刷新电路，其中，所述单行地址为m，m为正整数；所述行锤地址包括：第一单行地址，所述第一单行地址为m-1；第二单行地址，所述第二单行地址为m+1。
  3. 根据权利要求1所述的刷新电路，其中，所述行锤地址生成模块包括：
    计时单元，设置为接收所述行激活命令和所述预充电命令，以获取所述单次开启时间，若所述单次开启时间大于所述预设时间，则输出超时信号；
    行地址锁存单元，设置为接收所述单行地址并连接所述计时单元的输出端，若接收到所述超时信号，则锁存并输出所述单行地址；
    行锤地址生成单元，设置为接收所述行地址锁存单元输出的所述单行地址，并输出所述单行地址对应的所述行锤地址。
  4. 根据权利要求3所述的刷新电路，其中，所述行地址锁存单元是设置为顺序输出每一所述超时信号对应的单行地址，且在后输出的单行地址代替在先输出的单行地址，所述行锤地址生成单元是设置为顺序输出接收到的每一所述单行地址对应的行锤地址，且在后输出的行锤地址替代在先输出的行锤地址。
  5. 根据权利要求3所述的刷新电路，其中，所述计时单元包括：
    第一计数单元，设置为接收所述行激活命令、所述预充电命令以及时钟信号，并在接收到所述行激活命令之后、接收到所述预充电命令之前，对接 收到的所述时钟信号的周期个数进行计数，输出第一计数值；
    比较单元，设置为接收第一计数值，若所述第一计数值大于预设计数值，输出所述超时信号；其中，所述预设计数值等于所述预设时间除以所述时钟信号的周期。
  6. 根据权利要求5所述的刷新电路，其中，所述第一计数单元包括由多个D触发器串联组成的异步二进制加法计数器。
  7. 根据权利要求5所述的刷新电路，所述计时单元还包括：存储子单元，设置为写入并存储所述预设计数值，所述存储子单元的输出端与所述比较单元的输入端连接，所述比较单元还设置为通过所述存储子单元获取所述预设计数值。
  8. 根据权利要求5或7所述的刷新电路，其中，所述预设计数值可调。
  9. 根据权利要求1所述的刷新电路，其中，所述信号选择器还设置为接收选择信号，在接收到所述选择信号之前，依次接收并输出每一所述常规刷新地址，在接收到所述选择信号之后，中止输出所述常规刷新地址，依次接收并输出每一所述行锤地址；
    其中，所述选择信号表征所述信号选择器已接收到n-2个所述常规刷新地址，n为每一所述刷新命令对应的刷新行数，n>2。
  10. 根据权利要求9所述的刷新电路，所述刷新电路还包括：第二计数单元，设置为对所述信号选择器接收到的所述常规刷新地址的个数进行计数，获取第二计数值，若所述第二计数值等于n-2，输出所述选择信号。
  11. 根据权利要求10所述的刷新电路，其中，所述信号选择器在输出完所述常规刷新地址和所述行锤地址之后，重置所述第二计数值，中止输出所述选择信号。
  12. 根据权利要求10所述的刷新电路，其中，所述第二计数单元还设置为写入并更新所述n-2的值，若所述第二计数值等于更新后的所述n-2，输出所述选择信号。
  13. 根据权利要求10所述的刷新电路，所述刷新电路，还包括：常规刷新地址生成单元，设置为生成并输出至少一个所述常规刷新地址，所述常规刷新地址生成单元的输出端分别与所述信号选择器的输入端和所述第二计数单元的输入端连接，所述第二计数单元设置为接收所述常规刷新地址生成单 元输出的至少一个所述常规刷新地址。
  14. 根据权利要求1所述的刷新电路，其中，在接收到所述行锤地址之前，所述信号选择器接收并输出每一所述常规刷新地址；若接收到所述行锤地址，所述信号选择器中止输出所述常规刷新地址，并输出接收到的每一所述行锤地址；在输出完所述行锤地址后，继续接收并输出每一所述常规刷新地址。
  15. 一种存储器，所述存储器包含权利要求1-14中任一项所述的刷新电路。
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