WO2023134132A1 - 一种提高数据读取的成功率的方法、装置及介质 - Google Patents

一种提高数据读取的成功率的方法、装置及介质 Download PDF

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WO2023134132A1
WO2023134132A1 PCT/CN2022/102868 CN2022102868W WO2023134132A1 WO 2023134132 A1 WO2023134132 A1 WO 2023134132A1 CN 2022102868 W CN2022102868 W CN 2022102868W WO 2023134132 A1 WO2023134132 A1 WO 2023134132A1
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reference voltage
data
success rate
target reference
sample data
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PCT/CN2022/102868
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English (en)
French (fr)
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张志彬
李瑞东
钟戟
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苏州浪潮智能科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/22—Indexing; Data structures therefor; Storage structures
    • G06F16/2282—Tablespace storage structures; Management thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket

Definitions

  • the present application relates to a method, device and medium for improving the success rate of data reading.
  • Nand Flash is a widely used storage medium at present. Its principle is to record data by presenting different voltage values with different charges stored in the storage unit. However, due to the electrical characteristics of Nand particles, in its life cycle, with the number of flash erase/write (Program/Erase counts, PE), data retention time (Retention Time, RT), read times (Read Disturb, RD), etc. The change of factors will change the characteristics of the storage cell charge storage, so the reference voltage axis will also change accordingly, otherwise it will cause the bit error rate (Bit Error Rate, BER) to be too high, beyond the decoding capability and lead to read failure.
  • Bit Error Rate Bit Error Rate
  • the fixed read tables are generated according to a candidate table with multiple reference voltages provided by the manufacturer, that is, step by step under each reference voltage according to the Nand
  • the three dimensions of PE, RT, and RD in different stages of the life cycle of the flash memory are generated by selecting the best three reference voltages.
  • the fixed look-up table generated by the reference voltage candidate table can improve the efficiency of reading data.
  • the success rate however, the inventor realized that the life cycle of Nand flash memory is limited, especially as the chip ages at the end of the period, the data storage capacity of the solid-state hard disk is reduced, and the reference voltage will be deflected, which reduces the read operation of the solid-state hard disk.
  • the success rate while the throughput required to be achieved is also very slow, resulting in a lower hit rate.
  • a method for improving the success rate of data reading including:
  • the data is read according to the target reference voltage of the fixed look-up table.
  • the reference voltage group includes a first target reference voltage, and a corresponding reference voltage group is selected according to each success rate to generate a fixed look-up table, including:
  • the reference voltage corresponding to the test sample data with the highest success rate in the first candidate table is selected as the first target reference voltage and a fixed look-up table is generated.
  • obtaining the read operation information of the test sample data in units of decoding units includes:
  • Multiple flash memory particles correspond to different flash memory erasing/writing times stages according to the preset interval of the flash memory erasing/writing times stage, and the storage block data corresponds to different data under the flash memory erasing/writing times stage according to the preset interval of the data retention time stage retention period;
  • the read operation information of the test sample data is converted into the read operation information of the test sample data in units of decoding units in the form of storage blocks.
  • the reference voltage group includes a first target reference voltage and a second target reference voltage, and a corresponding reference voltage group is selected according to each success rate to generate a fixed look-up table, including:
  • the first target reference voltage and the second target reference voltage are used as a reference voltage group to generate a fixed look-up table.
  • the reference voltage group includes a first target reference voltage, a second target reference voltage and a third target reference voltage, and a corresponding reference voltage group is selected according to each success rate to generate a fixed look-up table, including:
  • the first target reference voltage, the second target reference voltage and the third target reference voltage are used as a reference voltage group to generate a fixed look-up table.
  • a prompt message is output, wherein the critical value is greater than the limit value for decoding error correction.
  • the storage block data appears as an integral multiple of the interval number of the data retention time period, wherein the interval number is the limit value of the data retention time period divided by the preset interval of the data retention time period plus 1 data.
  • the present application also provides a device for improving the success rate of data reading, including:
  • An acquisition module configured to acquire multiple reference voltages in the reference voltage candidate table and read operation information of test sample data in units of decoding units;
  • a calculation module configured to read the number of successful samples of the read operation of the test sample data under each reference voltage and calculate each success rate, wherein the number of successful samples is the number of samples in which the number of error bits of the test sample data is less than the decoding error correction limit;
  • a generating module configured to select a corresponding reference voltage group according to each success rate to generate a fixed look-up table
  • the reading module is used for reading data according to the target reference voltage of the fixed look-up table.
  • the present application also provides a device for improving the success rate of data reading, including:
  • One or more processors configured to implement the steps of the method for improving the success rate of data reading according to any one of the above embodiments when executing computer-readable instructions.
  • the present application also provides one or more non-volatile computer-readable storage media storing computer-readable instructions.
  • the computer-readable instructions are executed by one or more processors, one or more processors can perform any of the above-mentioned operations.
  • FIG. 1 is a flow chart of a method for improving the success rate of data reading provided by an embodiment of the present application.
  • Fig. 2 is a flow chart of collecting sample data provided by the embodiment of the present application.
  • FIG. 3 is a structural diagram of an apparatus for improving the success rate of data reading provided by an embodiment of the present application.
  • FIG. 4 is a structural diagram of another device for improving the success rate of data reading provided by an embodiment of the present application.
  • FIG. 5 is a structural diagram of a computer-readable storage medium provided by an embodiment of the present application.
  • FIG. 6 is a flow chart of another method for improving the success rate of data reading provided by the embodiment of the present application.
  • the core of the present application is to provide a method, device and medium for improving the success rate of data reading. Improve the read operation success rate of solid-state drives, improve throughput and hit rate.
  • this application provides a method to improve the success rate of data reading based on the generation of the FRT table in the Nand flash memory characteristic test. Due to the electrical characteristics of Nand particles, the PE, RT, and RD factors change in its life cycle, and its When the characteristics of the stored charge change, the reference voltage axis also changes. It is necessary to read data through the reference voltage of the FRT meter to improve the success rate of reading.
  • Fig. 1 is a flowchart of a method for improving the success rate of data reading provided by the embodiment of the present application. As shown in Fig. 1, the method includes:
  • Nand flash memory chip is divided into multiple storage blocks (Block), and each Block is composed of multiple decoding units (Chunk).
  • Flash memory is composed of Block, which is the basic unit of erasing.
  • test sample data exists in the form of Block, so when reading the operation information, it needs to be converted into the test sample number data in the unit of Chunk, and the read operation of the test sample data is obtained, that is, the processed test sample data is imported into the memory
  • PE flash memory life cycle
  • the read operation information includes the read operation of each environment point in the life cycle of the Nand flash memory under all reference voltages, including the position of the read data, the number of error bits/decoding unit (Error bit/Chunk), etc., for the data of different environment points
  • the read operation information obtained under all reference voltages may be the same, and even the read success rate is very small. It is necessary to combine the data of different PE stages to obtain test sample data to simplify the data volume.
  • the read operation information for obtaining the test sample data in units of storage units mentioned in this embodiment is only for one PE stage, and the method for other PE stages is the same, and will not be repeated here.
  • the multiple reference voltages in the reference voltage candidate table are based on the reference voltage candidate table provided by the Nand flash memory manufacturer. Due to the electronic aging at the end of the life cycle of the Nand flash memory, the reference voltage axis is deflected, and the success rate of reading data is not good. Therefore, the FRT table is generated on the basis of the reference voltage of the reference voltage candidate table provided by the manufacturer.
  • S12 Read the number of successful samples of the read operation of the test sample data under each reference voltage and calculate each success rate, wherein the number of successful samples is the number of samples in which the number of error bits of the test sample data is less than the decoding error correction limit.
  • the test sample data of a stage After obtaining the test sample data of a stage, according to the multiple reference voltages in the reference voltage candidate table, calculate the number of successful samples of the read operation of the test sample data under each reference voltage, because the test sample data is in Chunk, for example, 1
  • the binary data of a Chunk data is 30,000. In the binary data, the third number should be 0 according to the correct reading, and the reverse bit is 1 under the reading of the reference voltage, which is recorded as the third binary number reading. Error, count the inversion of a Chunk. If the inversion of a Chunk is greater than the decoding error correction limit, the read fails and is recorded as failed sample data.
  • LDPC is divided into two types: hard decoding and soft decoding.
  • Hard decoding is widely used in the early, middle and late stages of life, and soft and hard decoding is used for some data at the end of life, which has the same low delay characteristics.
  • the error correction capability of hard decoding is 2 times that of BCH. -3 times. Therefore, the present application realizes the number of successful samples of the read operation of reading test sample data under each reference voltage based on the LDPC decoding error correction mechanism.
  • the setting of the decoding error correction limit is set according to the specific Nand flash memory particle model, usually set to 200, that is, if the Error bit/Chunk does not exceed the LDPC decoding error correction limit, the reading is successful.
  • the number of successful samples as a read operation For example: the test sample data has a total of 30,000 Chunks. When reading the data in a Chunk, if the bit inversion exceeds 200, it means that the data reading of the Chunk failed, and the position of the Chunk is recorded. Record the number of successful samples of the read operation of Chunk test sample data under multiple reference voltages, and divide the number of successful samples by the total number of samples to obtain the success rate.
  • S13 Select a corresponding reference voltage group according to each success rate to generate a fixed look-up table.
  • the selection method can arrange the success rates in order from large to small or from small to large, and select the corresponding one of the highest success rate among the success rates.
  • the reference voltage is used as the reference voltage group, or the reference voltage corresponding to the first few higher success rates in the success rate is selected as the reference voltage group.
  • the reference voltage of the reference voltage group can be 1, 2, or 3 One, no specific requirements, it needs to be set according to the granular characteristics of the specific Nand flash memory, of course, considering the read speed of the solid state drive, there is no need to set too many reference voltages.
  • the selection rule of the reference voltage group is to select the reference voltage corresponding to the success rate greater than the success rate limit, and the success rate limit is set according to the actual situation of the particle model of the Nand flash memory, which is not required here.
  • ⁇ FRT1 represents the success rate of reading the reference voltage FRT1 in the reference voltage group
  • ⁇ FRT1+FRT2 represents the success rate of reading the reference voltage FRT1+FRT2 in the reference voltage group
  • ⁇ FRT1+FRT2+FRT3 represents the success rate in the reference voltage group The success rate of reading the reference voltage FRT1+FRT2+FRT3.
  • the target reference voltage is selected according to the reference voltage group in the FRT table to read data.
  • a method for improving the success rate of data reading is to obtain multiple reference voltages in the reference voltage candidate table and the read operation information of the test sample data in units of decoding units; read the test samples under each reference voltage The number of successful samples of the data read operation and calculate each success rate, wherein, the number of successful samples is the number of samples in which the number of error bits of the test sample data is less than the limit value of decoding error correction; select the corresponding reference voltage group according to each success rate to generate a fixed look-up table; and read data according to the target reference voltage of the fixed look-up table.
  • This method selects the reference voltage group to generate a fixed look-up table by collecting the success rate of the read operation information of all reference voltages in the reference voltage candidate table at different stages in the Nand flash cycle, so as to avoid the reference voltage caused by the aging of the chip at the end of the Nand flash memory.
  • the problem of reading data failure due to voltage deflection improves the success rate of read operations of solid-state drives, improves throughput and hit rate, and ensures the data storage capacity of solid-state drives.
  • the reference voltage group includes the first target reference voltage, and the corresponding reference voltage group is selected according to each success rate to generate a fixed look-up table, specifically including:
  • the reference voltage corresponding to the test sample data with the highest success rate in the first candidate table is selected as the first target reference voltage and a fixed look-up table is generated.
  • each success rate is sorted from large to small to generate a success rate table, and the reference voltage corresponding to each success rate greater than the first limit value ⁇ FRT1 is selected in the success rate table, and the success rate is greater than
  • the reference voltage of the first limit value is added in the first candidate table, and the reference voltage corresponding to the test sample data with the highest success rate is selected in the first candidate table as the first target reference voltage (V1), and the first target reference voltage is used as The reference voltage group generates an FRT table and then reads data according to the first target reference voltage.
  • each reference voltage group has a target reference voltage, but there will be multiple reference voltage groups, that is, multiple target reference voltages.
  • the first target reference voltage mentioned in this application is relative to the reading of data As long as the reference voltage with the highest success rate is greater than the first limit value, it can appear as the first target reference voltage, and no specific description will be given.
  • the reference voltage group provided in this embodiment includes the first target reference voltage, select the corresponding reference voltage group according to each success rate to generate the FRT table, improve the read data speed of the solid-state hard disk, read data with a target reference voltage, when When reading data fails, it will jump out directly.
  • obtaining the read operation information of the test sample data in units of decoding units specifically includes:
  • Multiple flash memory particles correspond to different flash memory erasing/writing times stages according to the preset interval of the flash memory erasing/writing times stage, and the storage block data corresponds to different data under the flash memory erasing/writing times stage according to the preset interval of the data retention time stage retention period;
  • the read operation information of the test sample data is converted into the read operation information of the test sample data in units of decoding units in the form of storage blocks.
  • flash memory particles are a kind of non-volatile memory, which is the medium responsible for capacity storage and transmission in solid-state hard disks, that is, the written data can still be saved in the case of power failure, and it is stored in a fixed area.
  • Block (Block) is the unit, not a single byte. According to the difference in the density of electronic units in Nand flash memory, it can be divided into SLC, MLC and TLC. These three storage units have obvious differences in lifespan and cost. Among them, Nand flash memory includes 2D and 3D. The difference lies in the number of particle layers stacked in the vertical direction and the type of particles selected. 3D NAND technology can provide more storage space under the same volume. This application does not make specific requirements for the particle type, and it is set according to the actual situation.
  • 3D TLC particles as an example, assume that the maximum values of PE, RT, and RDD of 3D TLC are 7K, 90d, and 10K respectively, the LDPC decoding error correction limit is 200, and the number of reference voltages in the reference voltage candidate table is y. Set the test intervals of PE, RT, and RDD stages to 500, 10d, and 5000 respectively. Each particle has n block data, and one particle corresponds to one PE stage.
  • the more RDD read disturbances the higher the bit error rate.
  • y reference voltages are respectively read to collect sample data.
  • the number of RDD operations is accumulated according to the y value of the reference voltage.
  • the RDD operation needs to be executed for the current number of read disturbances plus the preset interval and then subtracted from the value of y to reach the next RDD operation. If the value of y is small, you need to execute the RDD operation to add the preset interval to the current number of read disturbances to reach the next RDD operation execution, which is set according to the actual situation.
  • the RT stage has different limits for different types of particles, which are related to the operating temperature of the SSD. If the actual temperature is higher, the RT limit will be shortened, and the actual temperature and the RT limit will appear in a linear relationship. The retention time in the RT stage is short and should be set according to the specific situation.
  • Erase and write the test block to the corresponding PE stage For example, if it corresponds to 1000PE particles, it needs to erase and write the test block to 1000 times.
  • Fig. 2 is a flow chart of collecting sample data provided by the embodiment of the present application. As shown in Fig. 2, the steps are specifically:
  • step S23 Judging whether the RT stage pair is greater than the critical value of RT, if so, then end, if not, then enter step S24;
  • step S24 judge whether the current Block data is the test Block of the current RT stage, if not, then enter step S25, if so, then enter step S26;
  • test samples collected for the read operation in one PE stage need to be collected for read operations in multiple PE stages at the same time.
  • the test sample data is split/merged according to the interval of the FRT table.
  • Each stage corresponds to a test data sample set.
  • the PE interval 0-1500 in the FRT table is a stage, and the corresponding test samples of multiple PE stages (0-500, 500-1000, 1000-1500) in the test need to be combined into a sample set, that is, the corresponding A PE stage in the FRT table.
  • the read operation information of the test sample data is converted into the read operation information of the test sample data in the form of a Chunk in the form of a block.
  • the conversion algorithm is mentioned in the above embodiment, and will not be repeated here.
  • the read operation information provided by this embodiment to obtain the test sample data with the decoding unit as the unit, pre-process the data, and simultaneously process the storage block data in different stages of flash memory erasing/writing times, reducing the test cycle, because each data corresponds to reading
  • the difference in the success rate is very small, and the data with a small difference in the success rate are combined in advance to improve the reading speed.
  • the reference voltage group includes two target reference voltages, which are respectively the first target reference voltage and the second target reference voltage, and the corresponding reference voltage group is selected according to each success rate to generate a fixed look-up table, including :
  • the first target reference voltage and the second target reference voltage are used as a reference voltage group to generate a fixed look-up table.
  • the test sample data will be read with the first target reference voltage (V1), and the position information of the read failed samples will be recorded.
  • the number of failed samples is and the total number of successful samples N V1 .
  • V1 has been selected, and for the first candidate table except V1 Add the remaining references to the FRT2 table, and find the reference voltage corresponding to the test sample data with the highest success rate as the second target reference voltage V2.
  • Ns is the total number of samples in units of Chunk, is calculated as:
  • the FRT table is generated by using the first target reference voltage and the second target reference voltage as a reference voltage group.
  • each reference voltage group has two target reference voltages, but there will be multiple reference voltage groups, that is, multiple target reference voltages, the first target reference voltage and the second target reference voltage mentioned in this application It is the reference voltage with the highest read success rate relative to the data. As long as the reference voltage is greater than the first limit value, it can be used as the first target reference voltage, and the reference voltage greater than the second limit value can be used as the second target reference voltage.
  • the combination of A+B corresponds to the highest reading success rate.
  • the reference voltage group provided in this embodiment includes two target reference voltages, they are the first target reference voltage and the second target reference voltage respectively, and the corresponding reference voltage group is selected according to each success rate to generate a fixed look-up table to ensure that the data read
  • the success rate obtained when reading data with the first target reference voltage fails, it will read data according to the second target reference voltage, if the reading fails, it will directly jump out, if the reading is successful, it will be used as the target reference Voltage.
  • the reference voltage group includes a first target reference voltage, a second target reference voltage and a third target reference voltage, and a corresponding reference voltage group is selected according to each success rate to generate a fixed look-up table, including:
  • the first target reference voltage, the second target reference voltage and the third target reference voltage are used as a reference voltage group to generate a fixed look-up table.
  • Ns is the total number of samples in units of Chunk, is calculated as:
  • each reference voltage group has three target reference voltages, and there are five reference voltages (A, B, C, D, E) in the first candidate table that meet the first limit value, and A is the first Target reference voltage, then there are 4 reference voltages except A in the second candidate table, according to the reading calculation, B is used as the second target reference voltage, and in one or more embodiments, the combination of A+B corresponds to the highest reading Success rate, there are only C, D, and E3 reference voltages in the third candidate table, and the success rate is calculated according to the reading, assuming that C is the corresponding reference voltage with the highest success rate in the third candidate table, that is, in one or more embodiments The combination of A+B+C corresponds to the highest reading success rate.
  • this application can select a reference voltage combination greater than 3 target reference voltages according to the actual situation and the model of the flash memory particle. If the fourth reference voltage is selected, a fourth candidate table needs to be generated and then in the fourth candidate The reference voltage corresponding to the test sample with the highest success rate selected from the table appears as the fourth target reference voltage. Usually, there are at most 3 target reference voltages. If more target reference voltages are selected, it means that the read success rate of the SSD is low and the byte error rate is high, so it should not be used for the next attempt.
  • the corresponding reference voltage group is selected according to each success rate to generate a fixed Look up the table to improve the success rate of reading data from the SSD.
  • the first target reference voltage fails, it will read data according to the second target reference voltage. If the reading fails, it will read data according to the third target reference voltage. Read the data, if the reading fails, it will jump out directly, if the reading is successful, it will be used as the target reference voltage.
  • the number of successful samples in step S12 is data whose number of error bits in the test sample data is less than the decoding error correction limit, and the decoding error correction limit also includes:
  • a prompt message is output, wherein the critical value is greater than a limit value for decoding error correction.
  • the reading fails. There is a critical value for decoding error correction.
  • the decoding error correction limit When the Error bit/Chunk is greater than the decoding error correction limit, it means that the test sample data is There are other errors in reading, which may be due to the failure of reading data in the life cycle of the solid state drive, resulting in too high BER and too many error messages in decoding. Therefore, when the Error bit/Chunk of the test sample data is greater than the critical value of decoding error correction , output a prompt message to remind the user to check in time.
  • the decoding error correction limit is set to 200, and its critical value is set to 250. It should be noted that the decoding error correction threshold is set according to the specific Nand flash memory particle model, which is not required here.
  • the form of the prompt information can be a dialog box popping up on the display page, or a code program can be set.
  • a code program can be set.
  • the storage block data of multiple flash memory particles is obtained, and the storage block data appears in integer multiples of the interval number of the data retention time period, wherein the interval number The data that is the limit of the data retention time period divided by the preset interval of the data retention time period plus 1.
  • each particle has n Block data
  • one particle corresponds to one PE stage
  • 15 3D TLC particles are selected to correspond to 15 PE stages (0-500, 500-1000, 1000-1500...)
  • the number of RT stages under the PE stage is obtained.
  • the data of n blocks is divided into 10 Appears in multiples of , in order to realize the equal distribution of n test blocks during the RT stage, to ensure the integrity of the data test.
  • the storage block data provided by this embodiment appears in integral multiples of the intervals in the data retention time period, so that the storage block test data can be evenly divided according to the corresponding intervals in the data retention time period to ensure the completeness test of the data.
  • FIG. 3 is an embodiment of the present application A structural diagram of a device for improving the success rate of data reading is provided. As shown in Figure 3, the devices for improving the success rate of data reading include:
  • An acquisition module 11 configured to acquire a plurality of reference voltages in the reference voltage candidate table and read operation information of test sample data in units of decoding units;
  • the calculation module 12 is used to read the number of successful samples of the read operation of the test sample data under each reference voltage and calculate each success rate, wherein the number of successful samples is the number of samples in which the number of error bits of the test sample data is less than the decoding error correction limit ;
  • Generating module 13 is used for selecting corresponding reference voltage group to generate fixed look-up table according to each success rate
  • the reading module 14 is used for reading data according to the target reference voltage of the fixed look-up table.
  • the generation module 13 is specifically configured to sort each success rate from large to small to generate a success rate table; select a reference voltage corresponding to each success rate greater than the first limit value in the success rate table , and adding the reference voltage into the first candidate table; and selecting the reference voltage corresponding to the test sample data with the highest success rate in the first candidate table as the first target reference voltage and generating a fixed look-up table.
  • the reference voltage group includes a first target reference voltage
  • the acquisition module 11 is specifically used to acquire the storage block data of a plurality of flash memory particles
  • the interval corresponds to different stages of flash memory erase/write times
  • the storage block data is stored according to the preset interval of the data retention time stage corresponding to different data retention time stages under the stage of flash memory erase/write times; according to the storage block data in different data retention time stages
  • the corresponding data retention time operation according to the multiple reference voltages in the reference voltage candidate table, read the memory block data under the read disturbance operation phase corresponding to the data retention time phase and record the read operation information; according to the flash memory erase of the fixed look-up table /Writing times interval Merge the corresponding read operation information in the erasing/writing times stage of the flash memory to obtain the read operation information of the test sample data; Read operation information of sample data.
  • the reference voltage group includes a first target reference voltage and a second target reference voltage
  • the acquisition module 11 is specifically configured to record a successful sample of a read operation of reading test sample data under the first target reference voltage and take the failed data of the test sample data as the first position information; select the remaining reference voltages except the first target reference voltage in the reference voltage candidate table and add them to the second candidate table; select the success rate in the second candidate table
  • the reference voltage corresponding to the largest test sample data is used as the second target reference voltage
  • the test sample data in the first position information is read under the second target reference voltage, and in response to the test sample data in the first position information in the second Reading failure under the target reference voltage is recorded as the second position information
  • the successful sample data read in the first position information and the failed sample data read in the second position information under the second target reference voltage are counted and calculated First success rate; judging whether the first success rate is greater than the second limit value in the second candidate table, wherein the second limit value is greater than the first limit value; in response to the first success rate
  • the reference voltage group includes a first target reference voltage, a second target reference voltage and a third target reference voltage
  • the acquisition module 11 is specifically configured to select the first target reference voltage from the second candidate list and other voltages other than the second target reference voltage are added to the third candidate table; the reference voltage corresponding to the test sample data with the largest success rate in the third candidate table is selected as the third target reference voltage; in the third target reference voltage Next, read the test sample data in the second position information, and record it as the third position information in response to the test sample data in the second position information failing to be read under the third target reference voltage; The successful sample data read in the second position information and the failed sample data read in the third position information and calculate the second success rate; determine whether the second success rate is greater than the third limit value, wherein the third limit value greater than the second limit; in response to the second success rate being greater than the third limit, saving the third target reference voltage; and using the first target reference voltage, the second target reference voltage, and the third target reference voltage as a reference voltage group to generate Fixed
  • the reading module 14 is also configured to output prompt information in response to the number of error bits of the test sample data read under multiple reference voltages is greater than the critical value of decoding error correction, wherein the critical The value is greater than the decoding error correction limit.
  • Each module in the above-mentioned device for improving the success rate of data reading may be realized in whole or in part by software, hardware or a combination thereof.
  • the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, and can also be stored in the memory of the computer device in the form of software, so that the processor can invoke and execute the corresponding operations of the above-mentioned modules.
  • a device for improving the success rate of data reading obtains multiple reference voltages in the reference voltage candidate table and the read operation information of the test sample data in units of decoding units; reads the test samples under each reference voltage The number of successful samples of the read operation of the data and calculate each success rate, wherein the number of successful samples is the number of samples whose error bits of the test sample data are less than the limit value of decoding error correction; select the corresponding reference voltage group according to each success rate to generate a fixed query Table; read data according to the target reference voltage of the fixed look-up table.
  • the device selects the reference voltage group to generate a fixed look-up table by collecting the success rate of reading operation information of all reference voltages in the reference voltage candidate table at different stages in the Nand flash memory cycle, so as to avoid the reference voltage caused by the aging of the chip at the end of the Nand flash memory
  • the occurrence of deflection will affect the problem of failure to read data, improve the success rate of read operations of solid-state drives, improve throughput and hit rate, and ensure the data storage capacity of solid-state drives.
  • FIG. 4 is a structural diagram of another device for improving the success rate of data reading provided by the embodiment of the present application. As shown in FIG. 4, the device includes:
  • memory 21 for storing computer readable instructions
  • the processor 22 is configured to implement the steps of the method for improving the success rate of data reading in any of the above embodiments when executing computer-readable instructions.
  • the device for improving the success rate of data reading may include, but not limited to, a tablet computer, a notebook computer, or a desktop computer.
  • the processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like.
  • the processor 22 can adopt at least one hardware form in a digital signal processor (Digital Signal Processor, DSP), a field programmable gate array (Field-Programmable Gate Array, FPGA), and a programmable logic array (Programmable Logic Array, PLA). to fulfill.
  • DSP Digital Signal Processor
  • FPGA Field-Programmable Gate Array
  • PLA programmable logic array
  • Processor 22 may also include a main processor and a coprocessor, the main processor is a processor for processing data in a wake-up state, and is also called a central processing unit (Central Processing Unit, CPU); the coprocessor is Low-power processor for processing data in standby state.
  • CPU Central Processing Unit
  • the processor 22 may be integrated with a graphics processor (Graphics Processing Unit, GPU), and the GPU is used for rendering and drawing the content that needs to be displayed on the display screen.
  • the processor 22 may also include an artificial intelligence (Artificial Intelligence, AI) processor, which is used to process computing operations related to machine learning.
  • AI Artificial Intelligence
  • Memory 21 may include one or more computer-readable storage media, which may be non-transitory.
  • the memory 21 may also include high-speed random access memory and non-volatile memory, such as one or more magnetic disk storage devices and flash memory storage devices.
  • the memory 21 is at least used to store the following computer-readable instructions 201, wherein, after the computer-readable instructions are loaded and executed by the processor 22, the success rate of data reading disclosed in any of the foregoing embodiments can be improved. relevant steps of the method.
  • the resources stored in the memory 21 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage.
  • the operating system 202 may include Windows, Unix, Linux and so on.
  • the data 203 may include, but is not limited to, data involved in a method for improving the success rate of data reading, and the like.
  • the device for improving the success rate of data reading may further include a display screen 23 , an input/output interface 24 , a communication interface 25 , a power supply 26 and a communication bus 27 .
  • FIG. 4 is a structural diagram of another device for improving the success rate of data reading provided by the embodiment of the present application.
  • the structure shown in FIG. 4 does not constitute a limitation to the device for improving the success rate of data reading, and may include more or less components than those shown in the illustration.
  • the processor 22 invokes the instructions stored in the memory 21 to implement the method for improving the success rate of data reading provided by any of the above embodiments.
  • a device for improving the success rate of data reading obtains multiple reference voltages in the reference voltage candidate table and the read operation information of the test sample data in units of decoding units; reads the test samples under each reference voltage The number of successful samples of the read operation of the data and calculate each success rate, wherein the number of successful samples is the number of samples whose error bits of the test sample data are less than the limit value of decoding error correction; select the corresponding reference voltage group according to each success rate to generate a fixed query Table; read data according to the target reference voltage of the fixed look-up table.
  • the device selects the reference voltage group to generate a fixed look-up table by collecting the success rate of reading operation information of all reference voltages in the reference voltage candidate table at different stages in the Nand flash memory cycle, so as to avoid the reference voltage caused by the aging of the chip at the end of the Nand flash memory
  • the occurrence of deflection will affect the problem of failure to read data, improve the success rate of read operations of solid-state drives, improve throughput and hit rate, and ensure the data storage capacity of solid-state drives.
  • the present application also provides a computer-readable storage medium.
  • the computer-readable storage medium 51 stores computer-readable instructions 52, and when the computer-readable instructions 52 are executed by the processor 22, any of the above-mentioned Steps of a method for improving the success rate of data reading in an embodiment.
  • the methods in the above embodiments are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , executing all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .
  • Fig. 6 is a flowchart of another method for improving the success rate of data reading provided by the embodiment of the present application. As shown in Fig. 6, the flowchart includes:
  • step S34 Traversing the FRT1 candidate list, and selecting a reference voltage in the FRT1 candidate list as V1, judging whether it is the last reference voltage, if so, then end, if not, then enter step S35;
  • step S35 Judging whether the success rate of V1 is 1, if yes, proceed to step S36, if not, proceed to step S37;
  • step S39 traverse the FRT2 candidate list, and select a reference voltage in the FRT2 candidate list as V2, judge whether it is the last reference voltage, if so, return to step S34, if not, enter step S40;
  • step S41 Judging whether the success rate of V2 is 1, if yes, proceed to step S42, if not, proceed to step S43;
  • step S45 traverse the FRT3 candidate list, and select a reference voltage in the FRT3 candidate list as V3, judge whether it is the last reference voltage, if so, return to step S39, if not, enter step S46; and
  • the reference voltage group provided in this embodiment selects three target reference voltages, traverses y reference voltages, saves all combinations of reference voltages that meet the success rate requirements to generate an FRT table, and finally sorts them according to the success rate , select the optimal combination of reference voltages FRT1, FRT2, and FRT3.

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Abstract

一种提高数据读取的成功率的方法、装置及介质，方法包括：获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息（S11），读取各参考电压下测试样本数据的读操作的成功样本数并计算各成功率，其中，成功样本数为测试样本数据的错误比特数小于解码纠错限值的数据（S12）；根据各成功率选取对应的参考电压组以生成固定查表（S13）；以及根据固定查表的目标参考电压读取数据（S14）。

Description

一种提高数据读取的成功率的方法、装置及介质
相关申请的交叉引用
本申请要求于2022年01月13日提交中国专利局，申请号为202210034592.3，申请名称为“一种提高数据读取的成功率的方法、装置及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种提高数据读取的成功率的方法、装置及介质。
背景技术
Nand闪存(Nand Flash)是目前应用广泛的存储介质，其原理是通过存储在存储单元中不同的电荷量呈现出不同的电压值来记录数据。但由于Nand颗粒的电气特性，在其生命周期中随着闪存擦/写次数(Program/Erase counts，PE)，数据的保留时间(Retention Time，RT)，读取次数(Read Disturb，RD)等因素的变化，会使存储单元存储电荷的特性发生改变，因此参考电压轴也要随之改变，否则会导致比特出错率(Bit Error Rate，BER)过高，超出解码能力导致读取失败。
通常情况下，普遍通过固定查表(Fixed Read Tables，FRT)解决上述情况，固定查表根据生产厂家提供的一份具有多个参考电压的候选表生成，即逐步在每个参考电压下根据Nand闪存的生命周期不同阶段的PE、RT、RD三个维度选择最优的三个参考电压而生成，在Nand闪存的生命周期的前期选用参考电压候选表生成的固定查表可以提高读取数据的成功率，但是，发明人意识到，Nand闪存的生命周期有限，尤其在终期时随着芯片的老化，固态硬盘对于数据的存储能力降低，参考电压会发生偏转，降低了固态硬盘的读操作成功率，同时要求达到的吞吐量也很慢，导致命中率降低。
因此，如何提高数据读取的成功率是本领域技术人员亟需要解决的。
发明内容
根据本申请公开的各种实施例，提供一种提高数据读取的成功率的方法，包括：
获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；
读取各参考电压下测试样本数据的读操作的成功样本数并计算各成功率，其中，成功样本数为测试样本数据的错误比特数小于解码纠错限值的样本数；
根据各成功率选取对应的参考电压组以生成固定查表；以及
根据固定查表的目标参考电压读取数据。
在一个或多个实施例中，参考电压组包括第一目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，包括：
将各成功率从大到小排序以生成成功率表；
在成功率表中选取大于第一限值的各成功率所对应的参考电压，并将参考电压加入第一候选表中；以及
选取第一候选表中成功率最大的测试样本数据所对应的参考电压作为第一目标参考电压并生成固定查表。
在一个或多个实施例中，获取以解码单元为单位的测试样本数据的读操作信息，包括：
获取多个闪存颗粒的存储块数据；
将多个闪存颗粒根据闪存擦/写次数阶段的预设间隔对应不同的闪存擦/写次数阶段，将存储块数据根据数据保留时间阶段的预设间隔对应闪存擦/写次数阶段下的不同数据保留时间阶段；
根据不同数据保留时间阶段的存储块数据执行对应的数据保留时间操作；
根据参考电压候选表中的多个参考电压对数据保留时间阶段对应的读干扰操作阶段下的存储块数据进行读操作并记录读操作信息；
根据固定查表的闪存擦/写次数间隔将闪存擦/写次数阶段的对应的读操作信息进行合并得到测试样本数据的读操作信息；以及
将测试样本数据的读操作信息以存储块形式转换为以解码单元为单位的测试样本数据的读操作信息。
在一个或多个实施例中，参考电压组包括第一目标参考电压和第二目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，包括：
记录在第一目标参考电压下读取测试样本数据的读操作的成功样本数并将测试样本数据失败的数据作为第一位置信息；
在参考电压候选表中选取除第一目标参考电压之外的剩余参考电压并加入第二候选表中；
选取第二候选表中成功率最大的测试样本数据所对应的参考电压作为第二目标参考电压；
在第二目标参考电压下读取第一位置信息中的测试样本数据，响应于第一位置信息中的测试样本数据在第二目标参考电压下读取失败，记录为第二位置信息；
统计在第二目标参考电压下在第一位置信息中读取的成功样本数据和在第二位置信息中读取的失败样本数据并计算第一成功率；
在第二候选表中判断第一成功率是否大于第二限值，其中，第二限值大于第一限值；
响应于第一成功率大于第二限值，保存第二目标参考电压；以及
将第一目标参考电压与第二目标参考电压作为参考电压组以生成固定查表。
在一个或多个实施例中，参考电压组包括第一目标参考电压、第二目标参考电压和第三目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，包括：
在第二候选表中选取除第一目标参考电压和第二目标参考电压之外的其他电压并加入第三候选表中；
选取第三候选表中成功率最大的测试样本数据所对应的参考电压作为第三目标参考电压；
在第三目标参考电压下读取第二位置信息中的测试样本数据，响应于第二位置信息中的测试样本数据在第三目标参考电压下读取失败，记录为第三位置信息；
统计在第三目标参考电压下在第二位置信息中读取的成功样本数据和在第三位置信息中读取的失败样本数据并计算第二成功率；
判断第二成功率是否大于第三限值，其中，第三限值大于第二限值；
响应于第二成功率大于第三限值，保存第三目标参考电压；以及
将第一目标参考电压、第二目标参考电压和第三目标参考电压作为参考电压组以生成固定查表。
在一个或多个实施例中，还包括：
响应于读取到多个参考电压下的测试样本数据的错误比特数大于解码纠错的临界值时，输出提示信息，其中，临界值大于解码纠错限值。
在一个或多个实施例中，存储块数据以数据保留时间阶段的间隔数的整倍数出现，其中，间隔数为数据保留时间阶段的限值除以数据保留时间阶段的预设间隔加1的数据。
本申请还提供一种提高数据读取的成功率的装置，包括：
获取模块，用于获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；
计算模块，用于读取各参考电压下测试样本数据的读操作的成功样本数并计算各成功率，其中，成功样本数为测试样本数据的错误比特数小于解码纠错限值的样本数；
生成模块，用于根据各成功率选取对应的参考电压组以生成固定查表；以及
读取模块，用于根据固定查表的目标参考电压读取数据。
本申请还提供一种提高数据读取的成功率的装置，包括：
存储器，用于存储计算机可读指令；
一个或多个处理器，用于执行计算机可读指令时实现如上述任一个实施例的提高数据读取的成功率的方法的步骤。
本申请还提供一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，计算机可读指令被一个或多个处理器执行时，使得一个或多个处理器执行如上述任一个实施例的提高数据读取的成功率的方法的步骤。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种提高数据读取的成功率的方法的流程图。
图2为本申请实施例提供的一种采集样本数据的流程图。
图3为本申请实施例提供的一种提高数据读取的成功率的装置的结构图。
图4为本申请实施例提供的另一种提高数据读取的成功率的装置的结构图。
图5为本申请实施例提供的一种计算机可读存储介质的结构图。
图6为本申请实施例提供的另一种提高数据读取的成功率的方法的流程图。
具体实施方式
为下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下，所获得的所有其他实施例，都属于本申请保护范围。
本申请的核心是提供一种提高数据读取的成功率的方法、装置及介质。提高固态硬盘的读操作成功率，提高吞吐量和命中率。
为了使本技术领域的人员更好地理解本申请方案，下面结合附图和具体实施方式对本申请作进一步的详细说明。
需要说明的是，本申请基于Nand闪存特性测试中FRT表生成的情况提供一种提高数据读取成功率的方法，由于Nand颗粒的电气特性，其生命周期中PE、RT、RD因素变化，其存储电荷特性发生改变，参考电压轴也随之改变，需要通过FRT表的参考电压读取数据，提高读取成功率。
图1为本申请实施例提供的一种提高数据读取的成功率的方法的流程图，如图1所示，该方法包括：
S11：获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息。
可以理解的是，一块Nand闪存芯片分为多个存储块(Block)，而每一个Block又由多个解码单元(Chunk)构成。闪存由Block组成，是擦除的基本单元。一个Block包含若干个页(Page)，本申请基于3维三层单元(3 Dimensions Triple-Level Cell，3D TLC)闪存，一个Block包括n个字线(wordline)，一个wordline包含3个page，一个page包含4个Chunk，也就是说一个Block包含n*3*4＝12n个Chunk。
具体地，测试样本数据以Block形式存在，故在读操作信息时需要转换为以Chunk为单位的测试样本数数据，获取测试样本数据的读操作，也就是将处理好的测试样本数据进行导入至内存 的某一区域以便后续的读操作，读取包括数据的文本格式、二进制格式等，对测试样本数据根据参考电压候选表中的多个参考电压进行读取，根据闪存生命周期的不同阶段(PE、RT、RD)形成的三维数据，即一个PE阶段包括多个RT阶段，而一个RT阶段包括多个RD对应的读干扰(Read Disturb，RDD)操作，对于RT阶段中形成了多个环境点，针对每个环境点对应多个参考电压进行读取RDD操作。
读操作信息包括所有参考电压下对Nand闪存生命周期内的各个环境点进行的读操作，包括读取数据的位置，错误比特数/解码单元(Error bit/Chunk)等，对于不同环境点的数据得到的所有参考电压下的读操作信息可能相同，甚至读取的成功率相差极小，需要将不同PE阶段的数据进行合并得到测试样本数据以简化数据量。
本实施例提到的获取以存储单元为单位的测试样本数据的读操作信息，只是获取一个PE阶段的，其他PE阶段的方法相同，不再赘述。参考电压候选表中的多个参考电压是根据Nand闪存的生产厂商提供的参考电压候选表，由于Nand闪存的生命周期终期的电子老化，导致参考电压轴发生偏转，读取数据的成功率不高，因此，在生产厂商提供的参考电压候选表的参考电压的基础上进行生成FRT表。
S12：读取各参考电压下测试样本数据的读操作的成功样本数并计算各成功率，其中，成功样本数为测试样本数据的错误比特数小于解码纠错限值的样本数。
获取一个阶段的测试样本数据后，根据参考电压候选表中的多个参考电压，计算各参考电压下测试样本数据的读操作的成功样本数，由于测试样数据是以Chunk为单位，例如，1个Chunk数据的二进制数据为3万个，在二进制数据中，第3个数按照正确读取应该为0，在参考电压的读取下反位为1，则记为第3个二进制数读取错误，统计1个Chunk的反位情况，如果1个Chunk数据的反位情况大于解码纠错限值，则读取失败，作为失败样本数据记录。
在Nand闪存中都存在BER的问题，随着PE擦写次数增加，BER将逐渐变大，在2D(2 Dimensions，二维)NAND闪存中BCH(Bose、Ray-Chaudhuri与Hocquenghem的缩写)编码还可以完成纠正，对于TLC出错率太高造成硬盘寿命达不到要求，若为3D TLC Nand出错率比2D MLC(2 Dimensions Multi-level cell，二维多层单元)Nand高出很多，低密度奇偶校验码(Low Density Parity Check Code，LDPC)可以充分利用Nand的错误偏移特点进行解码。LDPC分为硬解码和软解码两种，在寿命前中后期大量使用硬解码，到了寿命末期部分数据使用软硬解码，具有同样的低延时特性，其硬解码的纠错能力是BCH的2-3倍。因此，本申请基于LDPC解码纠错机制实现读取各参考电压下测试样本数据的读操作的成功样本数。
需要说明的是，解码纠错限值的设置根据具体Nand闪存的颗粒型号进行设定，通常情况下设置为200，也就是Error bit/Chunk不超过LDPC解码纠错限值即为读取成功，作为读操作的成功样本数。例如：测试样本数据共有3万个Chunk，读一个Chunk里的数据，如果bit反位超过200，表示该Chunk数据读取失败，并记录该Chunk的位置。记录多个参考电压下的Chunk测试样本数据的读操作的成功样本数，根据成功样本数除以总样本数以得到成功率。
S13：根据各成功率选取对应的参考电压组以生成固定查表。
根据得到的各成功率，选取合适的参考电压组，生成FRT表，其选取方式可以将各成功率进行排列，其顺序从大到小或者从小到大，选取成功率中最高的成功率对应的参考电压作为参考电压组，或者选取成功率中前几个较高的成功率对应的参考电压作为参考电压组，需要说明的是，参考电压组的参考电压可以为1个，2个，或者3个，不做具体要求，需要根据具体的Nand闪存的颗粒特性进行设置，当然考虑固态硬盘的读取速度，不需要设置过多的参考电压。
当设置为1个参考电压(A)进行读取数据时，读取速度较快，成功率较高，若1个参考电压读取数据失败则直接跳出读取指令；当设置为2个参考电压(A和B)进行读取数据时，若A参考电压读取数据失败，则在B参考电压下继续读取数据，在B参考电压下读取数据失败时直接跳出读取指令；当设置为3个参考电压(A、B和C)，当A、B参考电压下读取数据失败时，可以用C参考电压继续读取数据。
可以理解的是，参考电压组的选取规则是选取大于成功率限值的成功率对应的参考电压，其成功率限值根据Nand闪存的颗粒型号的实际情况进行设定，在此不做要求。如：参考电压组的目标参考电压为1个，则成功率限值为ρ FRT1＝99％，参考电压组的目标参考电压为2个，则成功率限值为ρ FRT1＝99％和ρ FRT1+FRT2＝99.9％，参考电压组的目标参考电压为3个，则成功率限值为ρ FRT1＝99％、ρ FRT1+FRT2＝99.9％和ρ FRT1+FRT2+FRT3＝99.99％。
式中，ρ FRT1表示参考电压组中参考电压FRT1读取的成功率，ρ FRT1+FRT2表示参考电压组中参考电压FRT1+FRT2读取的成功率，ρ FRT1+FRT2+FRT3表示参考电压组中参考电压FRT1+FRT2+FRT3读取的成功率。
将FRT1，FRT2，FRT3读取成功率分别记为事件A、B、C，读取失败记为非A、非B、非C，根据统计概率公式：
Figure PCTCN2022102868-appb-000001
Figure PCTCN2022102868-appb-000002
Figure PCTCN2022102868-appb-000003
根据上述公式计算参考电压组合的成功率，选取各阶段成功率最高的组合来生成FRT表。
S14：根据固定查表的目标参考电压读取数据。
在生成FRT表后，根据FRT表中的参考电压组选取目标参考电压进行读取数据。
本申请提供的一种提高数据读取的成功率的方法，获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；读取各参考电压下测试样本数据的读操作的成 功样本数并计算各成功率，其中，成功样本数为测试样本数据的错误比特数小于解码纠错限值的样本数；根据各成功率选取对应的参考电压组以生成固定查表；以及根据固定查表的目标参考电压读取数据。该方法通过收集Nand闪存周期内不同阶段的参考电压候选表所有参考电压的读操作信息的成功率来选取参考电压组以生成固定查表，避免在Nand闪存的终期由于芯片的老化导致的参考电压发生偏转从而读取数据失败的问题，提高固态硬盘的读操作成功率，提高吞吐量和命中率，保证固态硬盘的数据存储能力。
在一个或多个实施例中，参考电压组中包括第一目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，具体包括：
将各成功率从大到小排序以生成成功率表；
在成功率表中选取大于第一限值的各成功率所对应的参考电压，并将参考电压加入第一候选表中；
选取第一候选表中成功率最大的测试样本数据所对应的参考电压作为第一目标参考电压并生成固定查表。
在上述实施例的基础上，将各成功率从大到小排序生成一个成功率表，在成功率表中选取大于第一限值ρ FRT1的各成功率所对应的参考电压，将成功率大于第一限值的参考电压加入第一候选表中，在第一候选表中选取成功率最大的测试样本数据所对应的参考电压作为第一目标参考电压(V1)，将第一目标参考电压作为参考电压组生成FRT表进而根据第一目标参考电压读取数据。
需要说明的是，每个参考电压组有一个目标参考电压，但是会有多个参考电压组，也就是多个目标参考电压，本申请提到的第一目标参考电压是相对于数据的读取成功率最高的参考电压，只要是大于第一限值的参考电压都可作为第一目标参考电压出现，不做具体说明。
本实施例提供的参考电压组中包括第一目标参考电压，根据各成功率选取对应的参考电压组以生成FRT表，提升固态硬盘的读取数据速度，以一个目标参考电压读取数据，当读取数据失败时，则会直接跳转出。
在一个或多个实施例中，获取以解码单元为单位的测试样本数据的读操作信息，具体包括：
获取多个闪存颗粒的存储块数据；
将多个闪存颗粒根据闪存擦/写次数阶段的预设间隔对应不同的闪存擦/写次数阶段，将存储块数据根据数据保留时间阶段的预设间隔对应闪存擦/写次数阶段下的不同数据保留时间阶段；
根据不同数据保留时间阶段的存储块数据执行对应的数据保留时间操作；
根据参考电压候选表中的多个参考电压对数据保留时间阶段对应的读干扰操作阶段下的存储块数据进行读操作并记录读操作信息；
根据固定查表的闪存擦/写次数间隔将闪存擦/写次数阶段的对应的读操作信息进行合并以得到测试样本数据的读操作信息；以及
将测试样本数据的读操作信息以存储块形式转换为以解码单元为单位的测试样本数据的读操作信息。
需要说明的是，闪存颗粒是一种非易失性存储器，是固态硬盘中负责容量存储和传输的介质，即在断电的情况下依旧可以保存已经写入的数据，而且是以固定的区块(Block)为单位，而不是以单个字节为单位，根据Nand闪存中电子单元密度的差异，可以分为SLC、MLC以及TLC，此三种存储单元在寿命以及造价上有着明显的区别。其中对于Nand闪存包括2D和3D，不同点在于垂直方向堆叠的颗粒层数不同和选用的颗粒种类不同。3D NAND技术能够在同等体积下，提供更多的存储空间。本申请对于颗粒类型不做具体要求，根据实际情况进行设定。
以3D TLC颗粒为例，假设3D TLC的PE、RT、RDD最大值分别为7K、90d、10K，LDPC解码纠错限值为200，参考电压候选表中参考电压数为y。将PE、RT、RDD阶段测试间隔分别设置为500、10d和5000，每个颗粒有n个block数据，一个颗粒对应一个PE阶段，选取15个3D TLC颗粒对应15个PE阶段(0-500、500-1000、1000-1500……)，将一个颗粒对应的n个Block根据RT预设间隔以及最大值的关系，得出PE阶段下的RT阶段数量，最大值90d除以预设间隔得到的数量加1为RT阶段数量(90d/10d+1＝10)，也就是一个PE阶段下包括10个RT阶段(0、10d、20d、30d……)，将n个测试Block均分为10份对应不同的RT阶段，一个RT阶段下根据RDD最大值10K与对应的RDD预设间隔得到(10K/5000+1＝3)，也就是一个RT阶段有3个RDD阶段(0、5000、10K)，需要说明的是，RDD读干扰越多，其bit错误率越高，针对一个环境点(0-500，0，0)分别对y个参考电压进行读取采集样本数据。同时，根据参考电压的y值进行累加RDD操作次数，如果y值较大，则需要执行RDD操作为当前的读干扰次数加预设间隔再减去y的值以到达下一个RDD操作进行执行，如果y值较小，则需要执行RDD操作为当前的读干扰次数加预设间隔以到达下一个RDD操作执行，具体根据实际情况进行设定。
需要说明的是，RT阶段对于不同型号的颗粒其限值不同，与固态硬盘运行时的温度有关，若实际温度较高，则RT限值缩短，实际温度与RT限值呈线性关系出现，实际RT阶段的保留时间较短，根据具体情况进行设置。
将测试Block擦写到对应的PE阶段，如对应1000PE的颗粒，需将其测试Block擦写到1000次。对应不同RT阶段的Block数据执行对应的RT操作，在RT操作下对应不同的RDD操作，用参考电压候选表中的y个参考电压依次对测试Block进行读操作并记录读操作信息，同时执行RDD读干扰操作，当一个环境点读取完成时，则继续遍历下一个环境点直到所有的环境点读取完成。
图2为本申请实施例提供的一种采集样本数据的流程图，如图2所示，该步骤具体为：
S21：输入对应的PE阶段；
S22：执行对应PE次数的PE操作；
S23：判断RT阶段对否大于RT的临界值，若是，则结束，若否，则进入步骤S24；
S24：判断当前的Block数据是否为当前的RT阶段的测试Block，若否，则进入步骤S25， 若是，则进入步骤S26；
S25：在当前RT操作的基础上增加一个RT操作对应的预设间隔进行执行并返回至步骤S23；
S26：判断当前的RDD操作是否大于RDD操作的临界值，若是，则结束，若否，则进入步骤S27；
S27：参考电压候选表中的y个参考电压依次对测试Block进行读操作并记录读操作信息；
S28：在当前执行RDD操作的基础上增加一个RDD操作对应的预设间隔减去y进行执行并返回至步骤S26。
需要说明的是，图2针对一个PE阶段进行的读取操作采集的测试样本，需要对多个PE阶段同时进行读操作采集，最后，按照FRT表间隔拆分/合并测试样本数据，FRT表中每个阶段对应一个测试数据样本集。例如：FRT表中PE间隔0-1500为一个阶段，则需要将测试中多个PE阶段(0-500，500-1000，1000-1500)的对应的测试样本合并为一个样本集，也就是对应FRT表中的一个PE阶段。将测试样本数据的读操作信息以Block形式转换为以Chunk单位的测试样本数据的读操作信息，其转换算法在上述实施例中提到，在此不再赘述。
本实施例提供的获取以解码单元为单位的测试样本数据的读操作信息，对数据预先处理，对于不同闪存擦/写次数阶段的存储块数据同时处理，减少测试周期，由于各个数据对应读取的成功率相差极小，预先对相差较小的成功率的数据进行合并，提高读取速度。
在一个或多个实施例中，参考电压组包括两个目标参考电压，分别为第一目标参考电压和第二目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，包括：
记录在第一目标参考电压下读取测试样本数据的读操作的成功样本数并将测试样本数据失败的数据作为第一位置信息；
在参考电压候选表中选取除第一目标参考电压之外的剩余参考电压并加入第二候选表中；
选取第二候选表中成功率最大的测试样本数据所对应的参考电压作为第二目标参考电压；
在第二目标参考电压下读取第一位置信息中的测试样本数据，响应于第一位置信息中的测试样本数据在第二目标参考电压下读取失败，记录为第二位置信息；
统计在第二目标参考电压下在第一位置信息中读取的成功样本数据和在第二位置信息中读取的失败样本数据并计算第一成功率；
在第二候选表中判断第一成功率是否大于第二限值，其中，第二限值大于第一限值；
响应于第一成功率大于第二限值，保存第二目标参考电压；以及
将第一目标参考电压与第二目标参考电压作为参考电压组以生成固定查表。
在选出第一目标参考电压后，将以第一目标参考电压(V1)读取测试样本数据，记录读取失败样本的位置信息，其失败样本数为
Figure PCTCN2022102868-appb-000004
和成功样本总数N V1。可以理解的是，在第一候选表中有多个参考电压，其中在多个参考电压下读取数据的成功率大于第一限值ρ FRT1，已经选取 V1，对于第一候选表中除V1之外的剩余参考加入FRT2表，并找到成功率最大的测试样本数据对应的参考电压作为第二目标参考电压V2，在失败样本数
Figure PCTCN2022102868-appb-000005
标记为第一位置信息，在第一位置信息上以V2第二目标参考电压读取失败样本数，若读取失败，则记录失败的位置信息为第二位置信息，并统计失败样本总数
Figure PCTCN2022102868-appb-000006
和成功样本总数
Figure PCTCN2022102868-appb-000007
其中
Figure PCTCN2022102868-appb-000008
为在第一位置信息上以V2读取成功的样本数，计算v 1+v 2组合的第一成功率ρ (v1+v2)，其计算方式为：
Figure PCTCN2022102868-appb-000009
在上式中，Ns为以Chunk为单位的样本总数，
Figure PCTCN2022102868-appb-000010
的计算方式为：
Figure PCTCN2022102868-appb-000011
判断第一成功率ρ (v1+v2)是否大于第二限值，其中第二限值大于第一限值，若ρ (v1+v2)大于第二限值，则说明V2可以作为第二目标参考电压并进行保存。将第一目标参考电压与第二目标参考电压作为参考电压组生成FRT表。
需要说明的是，每个参考电压组有两个目标参考电压，但是会有多个参考电压组，也就是多个目标参考电压，本申请提到的第一目标参考电压和第二目标参考电压是相对于数据的读取成功率最高的参考电压，只要是大于第一限值的参考电压都可作为第一目标参考电压出现，大于第二限值的参考电压都可作为第二目标参考电压出现，例如：第一候选表中满足大于第一限值的有5个参考电压(A、B、C、D、E)，其中A作为第一目标参考电压，则第二候选表中有除A之外的4个参考电压，根据读取计算，B作为第二目标参考电压，在一个或多个实施例中A+B组合对应最高读取成功率，在此情况下，需要在A作为第一目标参考电压的基础上，遍历C、D、E是否满足大于第二限值，若大于，则保存，除此之外，在B作为第一目标参考电压的基础上，遍历剩余的4个参考电压作为第二目标参考电压，以此类推，得到20种组合，找到满足限值的情况生成FRT表，不做具体说明。
本实施例提供的参考电压组中包括两个目标参考电压时，分别为第一目标参考电压和第二目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，保证数据读取的成功率，以第一目标参考电压读取数据失败时，则会根据第二目标参考电压进行读取数据，若读取失败，则直接跳转出，若读取成功，则作为目标参考电压。
在一个或多个实施例中，参考电压组包括第一目标参考电压、第二目标参考电压和第三目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，包括：
在第二候选表中选取除第一目标参考电压和第二目标参考电压之外的其他电压并加入第三候选表中；
选取第三候选表中成功率最大的测试样本数据所对应的参考电压作为第三目标参考电压；
在第三目标参考电压下读取第二位置信息中的测试样本数据，响应于第二位置信息中的测试样本数据在第三目标参考电压下读取失败，记录为第三位置信息；
统计在第三目标参考电压下在第二位置信息中读取的成功样本数据和在第三位置信息中读取的失败样本数据并计算第二成功率；
判断第二成功率是否大于第三限值，其中，第三限值大于第二限值；
响应于第二成功率大于第三限值，保存第三目标参考电压；以及
将第一目标参考电压、第二目标参考电压和第三目标参考电压作为参考电压组以生成固定查表。
在选出第一目标参考电压和第二目标参考电压后，在上述实施例的基础上，在第二候选表中去掉V2剩余的其他参考电压加入第三候选表中，进而选取第三候选表中成功率最大的样本数据对应的参考电压作为第三目标参考电压(V3)，以V3目标参考电压读取第二位置信息上的失败数据，并统计失败样本总数
Figure PCTCN2022102868-appb-000012
和成功的样本总数
Figure PCTCN2022102868-appb-000013
其中
Figure PCTCN2022102868-appb-000014
为在第一位置信息上以V1读取失败的基础上，再以V2读取失败得到的第二位置信息，进而以V3读取第二位置信息成功的样本数，计算v1+v2+v3组合的第二成功率ρ (v1+v2+v3)，其计算方式为：
Figure PCTCN2022102868-appb-000015
式中，Ns为以Chunk为单位的样本总数，
Figure PCTCN2022102868-appb-000016
的计算方式为：
Figure PCTCN2022102868-appb-000017
判断第二成功率ρ (v1+v2+v3)是否大于第三限值ρ FRT1+FRT2+FRT3，其中第三限值大于第二限值，若ρ (v1+v2+v3)大于第三限值，则说明V3可以作为第三目标参考电压并进行保存，将第一目标参考电压、第二目标参考电压和第三目标参考电压作为参考电压组生成FRT表。
结合上述的例子，每个参考电压组有三个目标参考电压，第一候选表中满足大于第一限值的有5个参考电压(A、B、C、D、E)，其中A作为第一目标参考电压，则第二候选表中有除A之外的4个参考电压，根据读取计算，B作为第二目标参考电压，在一个或多个实施例中A+B组合对应最高读取成功率，第三候选表中只存在C、D、E3个参考电压，根据读取计算成功率，假设C为第三候选表中成功率最大的对应参考电压，即在一个或多个实施例中A+B+C组合对应最高 读取成功率，在此情况下，需要在B作为第二目标参考电压的基础上，遍历D、E是否大于第三限值，若大于，则保存，进而回到需要在A作为第一目标参考电压的基础上，遍历C、D、E是否大于第二限值，若大于，则保存，除此之外，在B作为第一目标参考电压的基础上，遍历剩余的4个参考电压作为第二目标参考电压，以此类推，得到60种组合，找到满足限值的情况生成FRT表，不做具体说明。
需要说明的是，本申请可以根据实际情况，闪存颗粒的型号选取参考电压组合的大于3个目标参考电压的参考电压，若选取第四参考电压，则需要生成第四候选表进而在第四候选表中选取成功率最大的测试样本对应的参考电压作为第四目标参考电压出现。通常情况下，3个目标参考电压居多，若选取较多的目标参考电压，则说明固态硬盘的读取成功率较低，字节错误率较高，不作为下一次的尝试。
本实施例提供的参考电压组中包括三个目标参考电压时，分别为第一目标参考电压、第二目标参考电压和第三目标参考电压，根据各成功率选取对应的参考电压组以生成固定查表，提升固态硬盘的读取数据成功率，以第一目标参考电压读取数据失败时，则会根据第二目标参考电压进行读取数据，若读取失败，根据第三目标参考电压进行读取数据，若读取失败，则直接跳转出，若读取成功，则作为目标参考电压。
在一个或多个实施例中，步骤S12中的成功样本数为测试样本数据的错误比特数小于解码纠错限值的数据，其解码纠错限值还包括：
响应于读取到多个参考电压下的测试样本数据的错误比特数大于解码纠错的临界值，输出提示信息，其中，临界值大于解码纠错限值。
当测试样本数据的Error bit/Chunk大于解码纠错限值时，则读取失败，对于解码纠错存在临界值，当Error bit/Chunk大于解码纠错的临界值时，则说明测试样本数据的读取出现其他错误，可能是固态硬盘的生命周期读取数据失败，导致BER过高，解码出现的错误信息过多，因此，当测试样本数据的Error bit/Chunk大于解码纠错的临界值时，则输出提示信息以提醒用户及时检查。通常情况下，解码纠错限值设置为200，其临界值设置为250，需要说明的是，解码纠错的临界值根据具体Nand闪存的颗粒型号进行设定，在此不做要求。
提示信息的形式不做具体要求，可以是在显示页面弹出对话框，还可以是设置代码程序，当超出解码纠错的临界值时，则显示错误提示运行代码错误等形式，本申请不做具体要求。
本实施例提供的当读取到多个参考电压下的测试样本数据的错误字节存储单元大于解码纠错的临界值时，则输出提示信息，方便用户了解当前数据的读取情况，以便用户及时检查固态硬盘。
具体地，在获取以存储单元为单位的测试样本数据的读操作信息中，获取多个闪存颗粒的存储块数据，存储块数据以数据保留时间阶段的间隔数的整倍数出现，其中，间隔数为数据保留时间阶段的限值除以数据保留时间阶段的预设间隔加1的数据。
在上述的实施例中，每个颗粒有n个Block数据，一个颗粒对应一个PE阶段，选取15个3D TLC颗粒对应15个PE阶段(0-500、500-1000、1000-1500……)，将一个颗粒对应的n个Block 根据RT预设间隔以及最大值的关系，得出PE阶段下的RT阶段数量，最大值90d除以测试间隔得到的数量加1为RT阶段数量(90d/10d+1＝10)，也就是一个PE阶段下包括10个RT阶段(0、10d、20d、30d……)，将n个测试Block均分为10份对应不同的RT阶段，n个Block数据以10的倍数形式出现，以便实现对n个测试Block在进行RT阶段时进行均分，保证数据的完整性测试。
本实施例提供的存储块数据以数据保留时间阶段的间隔数的整倍数出现，便于存储块测试数据在数据保留时间阶段根据对应的间隔数进行均分，保证数据的完成性测试。
上述详细描述了提高数据读取的成功率的方法对应的各个实施例，在此基础上，本申请还公开与上述方法对应的提高数据读取的成功率的装置，图3为本申请实施例提供的一种提高数据读取的成功率的装置的结构图。如图3所示，提高数据读取的成功率的装置包括：
获取模块11，用于获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；
计算模块12，用于读取各参考电压下测试样本数据的读操作的成功样本数并计算各成功率，其中，成功样本数为测试样本数据的错误比特数小于解码纠错限值的样本数；
生成模块13，用于根据各成功率选取对应的参考电压组以生成固定查表；以及
读取模块14，用于根据固定查表的目标参考电压读取数据。
在一个或多个实施例中，生成模块13具体用于将各成功率从大到小排序以生成成功率表；在成功率表中选取大于第一限值的各成功率所对应的参考电压，并将参考电压加入第一候选表中；以及选取第一候选表中成功率最大的测试样本数据所对应的参考电压作为第一目标参考电压并生成固定查表。
在一个或多个实施例中，参考电压组包括第一目标参考电压，获取模块11具体用于获取多个闪存颗粒的存储块数据；将多个闪存颗粒根据闪存擦/写次数阶段的预设间隔对应不同的闪存擦/写次数阶段，将存储块数据根据数据保留时间阶段的预设间隔对应闪存擦/写次数阶段下的不同数据保留时间阶段；根据不同数据保留时间阶段的存储块数据执行对应的数据保留时间操作；根据参考电压候选表中的多个参考电压对数据保留时间阶段对应的读干扰操作阶段下的存储块数据进行读操作并记录读操作信息；根据固定查表的闪存擦/写次数间隔将闪存擦/写次数阶段的对应的读操作信息进行合并得到测试样本数据的读操作信息；以及将测试样本数据的读操作信息以存储块形式转换为以解码单元为单位的测试样本数据的读操作信息。
在一个或多个实施例中，参考电压组包括第一目标参考电压和第二目标参考电压，获取模块11具体用于记录在第一目标参考电压下读取测试样本数据的读操作的成功样本数并将测试样本数据失败的数据作为第一位置信息；在参考电压候选表中选取除第一目标参考电压之外的剩余参考电压并加入第二候选表中；选取第二候选表中成功率最大的测试样本数据所对应的参考电压作为第二目标参考电压；在第二目标参考电压下读取第一位置信息中的测试样本数据，响应于第一位置信息中的测试样本数据在第二目标参考电压下读取失败，记录为第二位置信息；统计在第二目 标参考电压下在第一位置信息中读取的成功样本数据和在第二位置信息中读取的失败样本数据并计算第一成功率；在第二候选表中判断第一成功率是否大于第二限值，其中，第二限值大于第一限值；响应于第一成功率大于第二限值，保存第二目标参考电压；以及将第一目标参考电压与第二目标参考电压作为参考电压组以生成固定查表。
在一个或多个实施例中，参考电压组包括第一目标参考电压、第二目标参考电压和第三目标参考电压，获取模块11具体用于在第二候选表中选取除第一目标参考电压和第二目标参考电压之外的其他电压并加入第三候选表中；选取第三候选表中成功率最大的测试样本数据所对应的参考电压作为第三目标参考电压；在第三目标参考电压下读取第二位置信息中的测试样本数据，响应于第二位置信息中的测试样本数据在第三目标参考电压下读取失败，记录为第三位置信息；统计在第三目标参考电压下在第二位置信息中读取的成功样本数据和在第三位置信息中读取的失败样本数据并计算第二成功率；判断第二成功率是否大于第三限值，其中，第三限值大于第二限值；响应于第二成功率大于第三限值，保存第三目标参考电压；以及将第一目标参考电压、第二目标参考电压和第三目标参考电压作为参考电压组以生成固定查表。
在一个或多个实施例中，读取模块14还用于响应于读取到多个参考电压下的测试样本数据的错误比特数大于解码纠错的临界值时，输出提示信息，其中，临界值大于解码纠错限值。
关于提高数据读取的成功率的装置的具体限定可以参见上文中对于提高数据读取的成功率的方法的限定，在此不再赘述。上述提高数据读取的成功率的装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器中，也可以以软件形式存储于计算机设备中的存储器中，以便于处理器调用执行以上各个模块对应的操作。
本申请提供的一种提高数据读取的成功率的装置，获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；读取各参考电压下测试样本数据的读操作的成功样本数并计算各成功率，其中成功样本数为测试样本数据的错误比特数小于解码纠错限值的样本数；根据各成功率选取对应的参考电压组以生成固定查表；根据固定查表的目标参考电压读取数据。该装置通过收集Nand闪存周期内不同阶段的参考电压候选表所有参考电压的读操作信息的成功率来选取参考电压组生成固定查表，避免在Nand闪存的终期由于芯片的老化导致的参考电压发生偏转从而影响读取数据失败的问题，提高固态硬盘的读操作成功率，提高吞吐量和命中率，保证固态硬盘的数据存储能力。
请参照图4，图4为本申请实施例提供的另一种提高数据读取的成功率的装置的结构图，如图4所示，该装置包括：
存储器21，用于存储计算机可读指令；
处理器22，用于执行计算机可读指令时实现上述任一实施例的提高数据读取的成功率的方法的步骤。
本实施例提供的提高数据读取的成功率的装置可以包括但不限于平板电脑、笔记本电脑或者 台式电脑等。
其中，处理器22可以包括一个或多个处理核心，比如4核心处理器、8核心处理器等。处理器22可以采用数字信号处理器(Digital Signal Processor，DSP)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)、可编程逻辑阵列(Programmable Logic Array，PLA)中的至少一种硬件形式来实现。处理器22也可以包括主处理器和协处理器，主处理器是用于对在唤醒状态下的数据进行处理的处理器，也称中央处理器(Central Processing Unit，CPU)；协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施例中，处理器22可以在集成有图像处理器(Graphics Processing Unit，GPU)，GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中，处理器22还可以包括人工智能(Artificial Intelligence，AI)处理器，该AI处理器用于处理有关机器学习的计算操作。
存储器21可以包括一个或多个计算机可读存储介质，该计算机可读存储介质可以是非暂态的。存储器21还可包括高速随机存取存储器，以及非易失性存储器，比如一个或多个磁盘存储设备、闪存存储设备。本实施例中，存储器21至少用于存储以下计算机可读指令201，其中，该计算机可读指令被处理器22加载并执行之后，能够实现前述任一实施例公开的提高数据读取的成功率的方法的相关步骤。另外，存储器21所存储的资源还可以包括操作系统202和数据203等，存储方式可以是短暂存储或者永久存储。其中，操作系统202可以包括Windows、Unix、Linux等。数据203可以包括但不限于提高数据读取的成功率的方法所涉及到的数据等等。
在一些实施例中，提高数据读取的成功率的装置还可包括有显示屏23、输入输出接口24、通信接口25、电源26以及通信总线27。
领域技术人员可以理解，图4为本申请实施例提供的另一种提高数据读取的成功率的装置的结构图。图4中示出的结构并不构成对提高数据读取的成功率的装置的限定，可以包括比图示更多或更少的组件。
处理器22通过调用存储于存储器21中的指令以实现上述任一实施例所提供的提高数据读取的成功率的方法。
本申请提供的一种提高数据读取的成功率的装置，获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；读取各参考电压下测试样本数据的读操作的成功样本数并计算各成功率，其中成功样本数为测试样本数据的错误比特数小于解码纠错限值的样本数；根据各成功率选取对应的参考电压组以生成固定查表；根据固定查表的目标参考电压读取数据。该装置通过收集Nand闪存周期内不同阶段的参考电压候选表所有参考电压的读操作信息的成功率来选取参考电压组生成固定查表，避免在Nand闪存的终期由于芯片的老化导致的参考电压发生偏转从而影响读取数据失败的问题，提高固态硬盘的读操作成功率，提高吞吐量和命中率，保证固态硬盘的数据存储能力。
进一步地，本申请还提供了一种计算机可读存储介质，参考图5，计算机可读存储介质51上存储有计算机可读指令52，计算机可读指令52被处理器22执行时实现如上述任一实施例的提高 数据读取的成功率的方法的步骤。
可以理解的是，如果上述实施例中的方法以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
对于本申请提供的一种计算机可读存储介质的介绍请参照上述方法实施例，本申请在此不再赘述，其具有上述提高数据读取的成功率的方法相同的有益效果。
为了使本领域的技术人员更好的理解本申请的技术方案，下面结合附图、本申请实施例提供的提高数据读取的成功率的方法、装置及介质，作进一步的详细说明。
图6为本申请实施例提供的另一种提高数据读取的成功率的方法的流程图，如图6所示，该流程图包括：
S31：输入当前阶段的数据样本集；
S32：计算y个参考电压的读成功率并排序生成成功率表；
S33：选取成功率表中符合FRT1限值成功率要求的参考电压生成FRT1候选表；
S34：遍历FRT1候选表，并选取FRT1候选表中的一个参考电压记为V1，判断是否为最后一个参考电压，若是，则结束，若否，则进入步骤S35；
S35：判断V1的成功率是否为1，若是，则进入步骤S36，若否，则进入步骤S37；
S36：保存V1并进入步骤S34；
S37：统计V1读取失败位置及失败样本总数；
S38：将成功率表中V1位置之后的参考电压生成FRT2候选表；
S39：遍历FRT2候选表，并选取FRT2候选表中的一个参考电压记为V2，判断是否为最后一个参考电压，若是，则返回至步骤S34，若否，则进入步骤S40；
S40：计算在V1位置失败的基础上读取V2的成功率；
S41：判断V2的成功率是否为1，若是，则进入步骤S42，若否，则进入步骤S43；
S42：保存V1+V2并进入步骤S39；
S43：当成功率满足FRT1+FRT2要求的V1+V2组合时，统计V2读取失败位置及样本总数；
S44：FRT2候选表去掉当前遍历的V2，生成FRT3候选表；
S45：遍历FRT3候选表，并选取FRT3候选表中的一个参考电压记为V3，判断是否为最后一个参考电压，若是，则返回至步骤S39，若否，则进入步骤S46；以及
S46：计算在V2位置失败的基础上读取V3的成功率并满足FRT1+FRT2+FRT3成功率要求时，则保存V1+V2+V3组合，并返回至步骤S45。
需要说明的是，本实施例提供的参考电压组选取三个目标参考电压，对y个参考电压进行遍 历，将满足成功率要求的所有参考电压组合进行保存生成FRT表，最后按照成功率进行排序，选择最优的参考电压FRT1，FRT2，FRT3组合。
上文通过对本申请实施例提供的另一种提高数据读取的成功率的方法的流程图进行了介绍，具有与上述提到的提高数据读取的成功率的方法相同的有益效果。
以上对本申请所提供的一种提高数据读取的成功率的方法、装置及介质进行了详细介绍。说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。

Claims (10)

  1. 一种提高数据读取的成功率的方法，其特征在于，包括：
    获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；
    读取各所述参考电压下所述测试样本数据的读操作的成功样本数并计算各成功率，其中，所述成功样本数为所述测试样本数据的错误比特数小于解码纠错限值的样本数；
    根据各所述成功率选取对应的参考电压组以生成固定查表；以及
    根据所述固定查表的目标参考电压读取数据。
  2. 根据权利要求1所述的方法，其特征在于，所述参考电压组包括第一目标参考电压，所述根据各所述成功率选取对应的参考电压组以生成固定查表，包括：
    将各所述成功率从大到小排序以生成成功率表；
    在所述成功率表中选取大于第一限值的各所述成功率所对应的参考电压，并将所述参考电压加入第一候选表中；以及
    选取所述第一候选表中成功率最大的测试样本数据所对应的参考电压作为所述第一目标参考电压并生成所述固定查表。
  3. 根据权利要求1或2所述的方法，其特征在于，所述获取以解码单元为单位的测试样本数据的读操作信息，包括：
    获取多个闪存颗粒的存储块数据；
    将多个所述闪存颗粒根据闪存擦/写次数阶段的预设间隔对应不同的闪存擦/写次数阶段，将所述存储块数据根据数据保留时间阶段的预设间隔对应所述闪存擦/写次数阶段下的不同数据保留时间阶段；
    根据不同所述数据保留时间阶段的所述存储块数据执行对应的数据保留时间操作；
    根据所述参考电压候选表中的多个参考电压对所述数据保留时间阶段下对应的读干扰操作阶段下的所述存储块数据进行读操作并记录所述读操作信息；
    根据所述固定查表的闪存擦/写次数间隔将所述闪存擦/写次数阶段的对应的所述读操作信息进行合并以得到所述测试样本数据的读操作信息；以及
    将所述测试样本数据的读操作信息以存储块形式转换为以所述解码单元为单位的所述测试样本数据的读操作信息。
  4. 根据权利要求2所述的方法，其特征在于，所述参考电压组包括所述第一目标参考电压和第二目标参考电压，所述根据各所述成功率选取对应的参考电压组以生成固定查表，包括：
    记录在所述第一目标参考电压下读取所述测试样本数据的读操作的成功样本数并将所述测试样本数据失败的数据作为第一位置信息；
    在所述参考电压候选表中选取除所述第一目标参考电压之外的剩余参考电压并加入第二候选表中；
    选取所述第二候选表中成功率最大的测试样本数据所对应的参考电压作为所述第二目标参考电压；
    在所述第二目标参考电压下读取所述第一位置信息中的测试样本数据，响应于所述第一位置信息中的测试样本数据在所述第二目标参考电压下读取失败，记录为第二位置信息；
    统计在所述第二目标参考电压下在所述第一位置信息中读取的成功样本数据和在所述第二位置信息中读取的失败样本数据并计算第一成功率；
    在所述第二候选表中判断所述第一成功率是否大于第二限值，其中，所述第二限值大于所述第一限值；
    响应于所述第一成功率大于第二限值，保存所述第二目标参考电压；以及
    将所述第一目标参考电压与所述第二目标参考电压作为所述参考电压组以生成所述固定查表。
  5. 根据权利要求4所述的方法，其特征在于，所述参考电压组包括所述第一目标参考电压、所述第二目标参考电压和第三目标参考电压，所述根据各所述成功率选取对应的参考电压组以生成固定查表，包括：
    在所述第二候选表中选取除所述第一目标参考电压和所述第二目标参考电压之外的其他电压并加入第三候选表中；
    选取所述第三候选表中成功率最大的测试样本数据所对应的参考电压作为所述第三目标参考电压；
    在所述第三目标参考电压下读取所述第二位置信息中的测试样本数据，响应于所述第二位置信息中的测试样本数据在所述第三目标参考电压下读取失败，记录为第三位置信息；
    统计在所述第三目标参考电压下在所述第二位置信息中读取的成功样本数据和在所述第三位置信息中读取的失败样本数据并计算第二成功率；
    判断所述第二成功率是否大于第三限值，其中，所述第三限值大于所述第二限值；
    响应于所述第二成功率大于第三限值，保存所述第三目标参考电压；以及
    将所述第一目标参考电压、所述第二目标参考电压和所述第三目标参考电压作为所述参考电压组以生成所述固定查表。
  6. 根据权利要求1至5任意一项所述的方法，其特征在于，还包括：
    响应于读取到多个所述参考电压下的所述测试样本数据的错误比特数大于所述解码纠错的临界值，输出提示信息，其中，所述临界值大于所述解码纠错限值。
  7. 根据权利要求3所述的方法，其特征在于，所述存储块数据以所述数据保留时间阶段的间隔数的整倍数出现，其中，所述间隔数为所述数据保留时间阶段的限值除以所述数据保留时间阶段的预设间隔加1的数据。
  8. 一种提高数据读取的成功率的装置，其特征在于，包括：
    获取模块，用于获取参考电压候选表中的多个参考电压和以解码单元为单位的测试样本数据的读操作信息；
    计算模块，用于读取各所述参考电压下所述测试样本数据的读操作的成功样本数并计算各成功率，其中，所述成功样本数为所述测试样本数据的错误比特数小于解码纠错限值的样本数；
    生成模块，用于根据各所述成功率选取对应的参考电压组以生成固定查表；以及
    读取模块，用于根据所述固定查表的目标参考电压读取所述数据。
  9. 一种提高数据读取的成功率的装置，其特征在于，包括：
    存储器，用于存储计算机可读指令；
    一个或多个处理器，用于执行所述计算机可读指令时实现如权利要求1至7任一项所述的方法的步骤。
  10. 一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，其特征在于，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行如权利要求1至7任一项所述的方法的步骤。
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