WO2022193371A1 - 一种阵列基板、显示面板及显示装置 - Google Patents

一种阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2022193371A1
WO2022193371A1 PCT/CN2021/084636 CN2021084636W WO2022193371A1 WO 2022193371 A1 WO2022193371 A1 WO 2022193371A1 CN 2021084636 W CN2021084636 W CN 2021084636W WO 2022193371 A1 WO2022193371 A1 WO 2022193371A1
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WIPO (PCT)
Prior art keywords
sub
pixel
pixels
array substrate
data lines
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PCT/CN2021/084636
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English (en)
French (fr)
Inventor
袁学斌
管延庆
杨从星
田超
汤富雄
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武汉华星光电技术有限公司
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Publication of WO2022193371A1 publication Critical patent/WO2022193371A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.
  • liquid crystal display panel Liquid crystal display, LCD
  • organic light-emitting semiconductors Organic Electroluminesence Display, OLED
  • a light shielding layer is usually added between the channel region of the thin film transistor (Thin Film Transistor, TFT) active layer of the display panel and the base substrate, and the light shielding layer can block the light emitted to the active layer.
  • shading thereby reducing the increase in leakage current caused by photogenerated carriers generated by light irradiating the active layer; however, the material of the shading layer is usually a metal or a non-metal that does not transmit light, so the shading layer is different from the active layer.
  • the source layers will overlap to generate capacitance. When the display panel is working, the source-level electrical signal changes, which affects the stored charge of the display panel pixels through the capacitive coupling effect, causing the pixel voltage to fluctuate. The brightness of the pixels changes, so that the corresponding display panel flickers abnormally.
  • the present application provides an array substrate, a display panel and a display device, which can effectively reduce the change of pixel brightness caused by capacitive coupling and improve problems such as screen flicker.
  • An array substrate comprising:
  • a plurality of data lines extending in a vertical direction, the plurality of data lines comprising a plurality of first type data lines and a plurality of second type data lines arranged in parallel with the first type data lines, the first type data lines
  • the data lines and the second type of data lines are respectively configured as data voltages with opposite polarities;
  • each of the pixel units comprising a plurality of sub-pixels defined by the intersection of the scan line and the data line, the plurality of sub-pixels comprising a plurality of sub-pixels electrically connected to the first type of data line a first sub-pixel, and a plurality of second sub-pixels electrically connected to the second type of data lines;
  • any one of the sub-pixels is correspondingly provided with a thin film transistor and a light shielding layer located between the thin film transistor and the base substrate, and the light shielding layer corresponding to any one of the first sub-pixels is at least connected to one of the light shielding layers.
  • the light shielding layers corresponding to the second sub-pixels are electrically connected through connecting lines.
  • the first type of data lines and the second type of data lines are respectively configured to transmit data voltages of equal magnitudes.
  • the first type of data lines and the second type of data lines are arranged alternately in a horizontal direction;
  • the first sub-pixels and the second sub-pixels are arranged alternately in the horizontal direction to form a pixel row, and the light shielding layer corresponding to any one of the first sub-pixels is at least one adjacent to the second sub-pixel.
  • the corresponding light shielding layers are electrically connected through the connecting wires.
  • a plurality of the adjacent sub-pixels in any of the pixel rows form a pixel group, and the light-shielding layers corresponding to the sub-pixels in the same pixel group are connected through the connection.
  • Line electrical connection
  • any one of the pixel rows includes one or more of the pixel groups.
  • any one of the pixel rows includes a plurality of the pixel groups, and any of the pixel groups includes the same number of the sub-pixels.
  • any one of the pixel rows includes a plurality of consecutively arranged first pixel groups, and any one of the first pixel groups includes N adjacent sub-pixels, where N is greater than or equal to 2 positive integer of .
  • the first pixel groups located in the adjacent pixel rows are arranged in a staggered manner.
  • N is an even number
  • the dislocation distance is a distance between 1 and (N ⁇ 1) of the sub-pixels.
  • the dislocation distance between the first pixel groups located in the adjacent pixel rows is the distance between N/2 adjacent sub-pixels.
  • the first pixel group includes at least one red sub-pixel, one blue sub-pixel and one green sub-pixel.
  • the pixel rows further include a second pixel group located at the edge of the pixel row and adjacent to one of the first pixel groups, and the second pixel group includes M adjacent pixel groups , where M is a positive integer greater than or equal to 1, M ⁇ N, and M ⁇ 2N.
  • the thin film transistor in any of the sub-pixels, includes an active layer, a gate electrode, a source electrode and a drain electrode that are stacked and arranged;
  • the active layer includes a channel region, a lightly doped region and a heavily doped region
  • the orthographic projection of the light shielding layer on the active layer covers the channel region, the lightly doped region and the heavily doped region.
  • the range a of the distance a between the boundary of the light shielding layer on the base substrate and the boundary of the orthographic projection of the adjacent channel regions on the base substrate is a ⁇ 2 microns.
  • the orthographic projection of the connection line on the base substrate does not overlap with the orthographic projection of the gate electrode on the base substrate.
  • the width of the connection lines ranges from 1 ⁇ m to 15 ⁇ m.
  • the thicknesses of the light shielding layer and the connecting lines are both in the range of 300 ⁇ to 1500 ⁇ .
  • connection lines and the light shielding layer are disposed in the same layer, and the connection lines and the light shielding layer have the same material.
  • the present application provides a display panel, the display panel includes an array substrate and a second substrate disposed above thin film transistors of the array substrate, and a black matrix is disposed on a side of the second substrate close to the array substrate ;
  • the array substrate includes:
  • a plurality of data lines extending in a vertical direction, the plurality of data lines comprising a plurality of first type data lines and a plurality of second type data lines arranged in parallel with the first type data lines, the first type data lines
  • the data lines and the second type of data lines are respectively configured as data voltages with opposite polarities;
  • each of the pixel units comprising a plurality of sub-pixels defined by the intersection of the scan line and the data line, the plurality of sub-pixels comprising a plurality of sub-pixels electrically connected to the first type of data line a first sub-pixel, and a plurality of second sub-pixels electrically connected to the second type of data lines;
  • any one of the sub-pixels is correspondingly provided with a thin film transistor and a light shielding layer located between the thin film transistor and the base substrate, and the light shielding layer corresponding to any one of the first sub-pixels is at least connected to one of the light shielding layers.
  • the light shielding layer corresponding to the second sub-pixel is electrically connected through a connecting line
  • the orthographic projection of the black matrix on the array substrate covers the connection lines.
  • the present application provides a display device including any of the above-mentioned display panels.
  • a light shielding layer is added between the active layer of the array substrate and the base substrate, so as to reduce the light emitted to the active layer in the corresponding display panel, thereby reducing the photogenerated current caused by the light irradiating the active layer.
  • the first-type data lines are electrically connected by lines
  • the second type of data lines are electrically connected to a plurality of second sub-pixels
  • the light-shielding layer of any one of the first sub-pixels is at least connected to the light-shielding layer of one of the second sub-pixels.
  • the layers are electrically connected by connecting lines, so that when the corresponding display panel is working, the capacitive coupling directions of the first sub-pixel and the second sub-pixel are opposite, reducing the voltage on the sub-pixel, thereby effectively reducing the capacitive coupling.
  • Pixel brightness changes caused by the change improve the screen flicker and other issues.
  • FIG. 1 is a schematic diagram of an equivalent circuit of a sub-pixel of a conventional array substrate
  • FIG. 2 is a schematic diagram of an equivalent circuit of a sub-pixel of the array substrate provided by the present application
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a top view of an active layer and a light-shielding layer of an array substrate provided by an embodiment of the present application;
  • FIG. 5 is a schematic diagram of an equivalent circuit of a sub-pixel of an array substrate provided by an embodiment of the present application.
  • FIG. 6 is a top cross-sectional view of an array substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a first arrangement of sub-pixels at the edge of the array substrate provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a second arrangement of sub-pixels at the edge of the array substrate according to the embodiment of the present application.
  • FIG. 9 is a schematic diagram of a third arrangement of sub-pixels at the edge of the array substrate provided by the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the present application provides an array substrate, a display panel and a display device.
  • the present application will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.
  • FIG. 1 is a schematic diagram of an equivalent circuit of a sub-pixel of a conventional array substrate.
  • an array substrate includes a base substrate, a plurality of data lines Data extending in a vertical direction, a plurality of scanning lines Gate extending in a horizontal direction, and a plurality of pixel units, each of which includes A plurality of sub-pixels defined by the intersection of the scan line Gate and the data line Data, the sub-pixels include a thin film transistor TFT, a storage capacitor Cst and a liquid crystal capacitor Clc, and the gate of the thin film transistor TFT is connected to the corresponding scan line Gate , the source of the thin film transistor TFT is connected to the corresponding data line Data, the drain of the thin film transistor TFT is connected to the first plate of the liquid crystal capacitor Clc and the first plate of the storage capacitor Cst, in order to reduce the corresponding The light emitted to the active layer of the thin film transistor TFT in the display panel, thereby reducing the leakage current caused by the photogenerated carriers generated by the light irradiating the active layer, usually occurs between the thin film transistor TFT and the base substrate
  • a first capacitor CP1 is formed between the light-shielding layer LS and the source electrode, and the light-shielding layer LS and the drain electrode are formed with a first capacitor CP1.
  • a second capacitor CP2 will be formed between them.
  • FIG. 2 is a schematic diagram of an equivalent circuit of a sub-pixel of the array substrate provided in the present application.
  • the present application provides an array substrate, the array substrate includes a base substrate (not shown in the figure); a plurality of data lines Data extending in a vertical direction, the plurality of data lines Data include a plurality of first-type data lines Data and a plurality of second-type data lines Data2 arranged in parallel with the first-type data lines Data1, the first-type data lines Data1 and the second-type data lines Data2 are respectively configured as data voltages with opposite polarities ; Multiple scan lines Gate extending in the horizontal direction.
  • each of the pixel units includes a plurality of sub-pixels (not shown in the figure) defined by the intersection of the scan line Gate and the data line Data, the The sub-pixels include a plurality of first sub-pixels P1 electrically connected to the first type of data lines Data1, and a plurality of second sub-pixels P2 electrically connected to the second type of data lines Data2.
  • any one of the sub-pixels is correspondingly provided with a thin film transistor TFT and a light shielding layer LS between the thin film transistor TFT and the base substrate, and the light shielding layer corresponding to any one of the first sub-pixels P1
  • the LS is electrically connected to at least one of the light shielding layers LS corresponding to the second sub-pixels P2 through a connecting line Ls.
  • the present application does not specifically limit the number of the sub-pixels, the number of the first sub-pixels P1 and the number of the second sub-pixels P2.
  • the first sub-pixel P1 and the second sub-pixel P2 further include a storage capacitor Cst and a liquid crystal capacitor Clc
  • the gate of the thin film transistor TFT is connected to the corresponding scan line Gate
  • the thin film transistor TFT The source electrode of the TFT is connected to the corresponding data line Data
  • the drain electrode of the thin film transistor TFT is connected to the first electrode plate of the liquid crystal capacitor Clc and the first electrode plate of the storage capacitor Cst
  • the light shielding layer LS is connected to the A first capacitor CP1 is formed between the source electrodes of the thin film transistor TFT
  • a second capacitor CP2 is formed between the light shielding layer LS and the drain electrode of the thin film transistor TFT.
  • the array substrate provided by the present application includes a plurality of data lines extending in a vertical direction, and the plurality of data lines includes a plurality of first type data lines Data1 and a plurality of second type data lines Data1 arranged in parallel with the first type data lines Data1 Type data lines Data2, the first type data lines Data1 and the second type data lines Data2 are respectively configured as data voltages with opposite polarities; a plurality of pixel units, each of which includes A plurality of sub-pixels defined by crossing the data lines, the plurality of sub-pixels include a plurality of first sub-pixels P1 electrically connected to the first type of data lines Data1, and a plurality of first sub-pixels P1 electrically connected to the second type of data lines Data2 A plurality of second sub-pixels P2 that are electrically connected; wherein, the light-shielding layer LS corresponding to any one of the first sub-pixels P1 and the light-shielding layer LS corresponding to at least one of the second sub-pixels
  • the first sub-pixel P1 and the second sub-pixel P2 include but are not limited to red sub-pixels (R), green sub-pixels (G) and blue sub-pixels (B) .
  • the types of the first sub-pixel P1 and the second sub-pixel P2 are not further limited, that is, the first sub-pixel P1 and the second sub-pixel P2 The types can be the same or different.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • This embodiment provides an array substrate, the array substrate includes a base substrate 10 and a plurality of pixel units (not shown in the figure) located on the base substrate 10 , each of the pixel units includes a plurality of sub-pixels (not shown in the figure), any of the sub-pixels is correspondingly provided with a thin film transistor TFT located on the base substrate 10 and a light shielding layer LS located between the thin film transistor TFT and the base substrate 10 .
  • the material of the base substrate 10 includes but is not limited to polyethylene terephthalate, polyimide, triacetate film or other flexible materials.
  • the base substrate 10 is 10 is a PI substrate, mainly polyimide, and the PI material can effectively improve the light transmittance of the substrate.
  • the thin film transistor TFT includes an active layer 30 , a gate insulating layer 40 , a gate 50 , an interlayer insulating layer 60 , a source electrode 71 , and a drain electrode that are sequentially stacked on the light shielding layer LS. 72.
  • the material of the active layer 30 includes but is not limited to indium gallium zinc oxide; the gate insulating layer 40 and the interlayer insulating layer 60 have strong water and oxygen barrier capability and insulating capability, and the materials include But not limited to silicon oxide, silicon nitride, silicon oxynitride, etc. or their stacks; the materials of the gate electrode 50, the source electrode 71 and the drain electrode 72 include but are not limited to metals such as molybdenum, silver, aluminum, etc., or their stacks. Laminate; the materials of the passivation layer 100 include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, etc. or their stacks; the materials of the common electrode layer 90 and the pixel electrode 110 include but are not limited to indium oxide tin.
  • the array substrate further includes a buffer layer 20 located between the active layer 30 and the light shielding layer LS, and the buffer layer 20 may be composed of silicon oxide or silicon nitride.
  • the array substrate includes a buffer layer 20 , an active layer 30 , a gate insulating layer 40 , a gate 50 , and an interlayer insulating layer 60 , which are sequentially stacked on the light shielding layer LS.
  • the source electrode 71 , the drain electrode 72 , the planarization layer 80 , the common electrode layer 90 , the passivation layer 100 and the pixel electrode 110 are only used for illustration.
  • the pixel electrode 110 and the drain electrode 72 are electrically connected only for
  • the pixel electrode 110 may also be connected to the source electrode 71 , which is not specifically limited in this embodiment.
  • FIG. 4 is a top view of the active layer and the light shielding layer of the array substrate provided by the embodiment of the present application.
  • the active layer 30 includes a channel region 31 , a lightly doped region 32 and a heavily doped region 33 , and the channel region 31 is located between the two lightly doped regions 32 , so The channel region 31 and the lightly doped region 32 are located between the two heavily doped regions 33 ; wherein the projection of the light shielding layer LS on the active layer 30 covers the channel region 31 , the lightly doped region 32 and the heavily doped region 33 .
  • the projection of the light shielding layer LS on the active layer 30 at least overlaps with the boundary of the heavily doped region 33 away from the lightly doped region 32; wherein the thickness of the light shielding layer LS The range is 300 ⁇ 1500 ⁇ .
  • the range a of the distance a between the orthographic projection boundary of the light shielding layer LS on the base substrate 10 and the orthographic projection boundary of the channel region 31 on the base substrate 10 is a ⁇ 2
  • the range of a to reduce the incidence of light from the side of the base substrate 10 away from the active layer 30 into the channel region 31 and the lightly doped region 32 of the active layer 30, ensuring that The light shielding properties of the channel region 31 and the lightly doped region 32; at the same time, in order to obtain the light shielding layer LS with good light shielding performance and high mass production feasibility, preferably, the thickness range of the light shielding layer LS is 600 ⁇ 1000 ⁇ .
  • the projection of the light shielding layer LS on the active layer 30 at least overlaps with the boundary of the heavily doped region 33 on the side away from the lightly doped region 32 , so that the active The side of the layer 30 close to the base substrate 10 plays a role of planarization, thereby preventing the occurrence of defects such as disconnection of the active layer 30 .
  • the light shielding layer LS is added between the active layer 30 of the array substrate and the base substrate 10, and the orthographic projection of the active layer 30 on the base substrate 10 is located in the The light shielding layer LS is in the orthographic projection of the base substrate 10, thereby reducing the light emitted to the active layer 30 in the array substrate, thereby reducing the photogenerated carriers generated by the light irradiating the active layer 30 resulting leakage current.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a sub-pixel of an array substrate provided by an embodiment of the present application.
  • the array substrate further includes a plurality of data lines Data extending in a vertical direction, and the plurality of data lines Data includes a plurality of first type data lines Data1 and a plurality of data lines related to the first type of data.
  • a second type of data line Data2 arranged in parallel with the line Data1, the first type of data line Data1 and the second type of data line Data2 are respectively configured as data voltages with opposite polarities; a plurality of scan lines Gate extending in the horizontal direction ;
  • Each of the pixel units (not marked in the figure) includes a plurality of sub-pixels P defined by the intersection of the scan line Gate and the data line Data, and the plurality of sub-pixels P include the same data as the first type of data.
  • the layer LS is electrically connected to at least one of the light shielding layers LS corresponding to the adjacent second sub-pixels P2 through the connection line Ls.
  • the first-type data lines Data1 by arranging a plurality of first-type data lines Data1 with opposite polarities of data voltages and a plurality of second-type data lines Data2 arranged in parallel with the first-type data lines Data1, the first-type data lines Data1
  • the plurality of first sub-pixels P1 are electrically connected to each other
  • the second type of data line Data2 is electrically connected to the plurality of second sub-pixels P2
  • the light shielding layer LS corresponding to any one of the first sub-pixels P1 is connected to at least one phase.
  • the light shielding layer LS corresponding to the adjacent second sub-pixel P2 is electrically connected through the connecting line Ls, so that when the corresponding display panel is working, the first sub-pixel P1 and the second sub-pixel P2 The direction of capacitive coupling is opposite, and the voltage on the sub-pixel P is reduced, which can effectively reduce the pixel brightness change caused by capacitive coupling, and improve the problem of picture flicker and the like.
  • first type of data line Data1 and the second type of data line Data2 are respectively configured to transmit data voltages of equal magnitudes.
  • the first type of data line Data1 and the second type of data line Data2 are alternately arranged in sequence along the horizontal direction; the first sub-pixel P1 and the second sub-pixel P2 are arranged along the horizontal direction.
  • the horizontal directions are arranged alternately in sequence, and the light shielding layer LS corresponding to any one of the first sub-pixels P1 and the light shielding layer LS corresponding to at least one adjacent second sub-pixel P2 are electrically connected through the connecting line Ls. so that when the corresponding display panel is working, the capacitive coupling directions of the first sub-pixel P1 and the second sub-pixel P2 are opposite, and the data voltage in the first sub-pixel P1 changes with the second sub-pixel P2.
  • the data voltage change in the pixel P2 is all 0, which can effectively reduce the pixel brightness change caused by capacitive coupling, and improve the problem of picture flickering and the like.
  • the first sub-pixel P1 and the second sub-pixel P2 further include a storage capacitor Cst and a liquid crystal capacitor Clc
  • the gate 50 of the thin film transistor TFT is connected to the corresponding scan line Gate
  • the The source electrode 71 of the thin film transistor TFT is connected to the corresponding data line Data
  • the drain electrode 72 of the thin film transistor TFT is connected to the first electrode plate of the liquid crystal capacitor Clc and the first electrode plate of the storage capacitor Cst
  • a first capacitor CP1 is formed between LS and the source electrode 71 of the thin film transistor TFT
  • a second capacitor CP2 is formed between the light shielding layer LS and the drain electrode 72 of the thin film transistor TFT
  • the first sub-pixel P1 corresponds to
  • the light shielding layer LS is electrically connected with the light shielding layer LS corresponding to the adjacent second sub-pixel P2 through the connecting line Ls.
  • FIG. 6 is a top cross-sectional view of an array substrate provided by an embodiment of the present application.
  • connection line Ls and the light-shielding layer LS are disposed in the same layer, and the material of the connection line Ls and the light-shielding layer LS is the same, wherein, when the material of the connection line Ls is a metal material, the orthographic projection of the connection line Ls on the base substrate 10 and the scan line Gate on the base substrate The orthographic projections on 10 do not overlap.
  • connection line Ls and the light shielding layer LS are the same, so the connection line Ls and the light shielding layer LS can be integrally formed, thereby reducing the number of array substrates.
  • the technological process of the preparation method improves the preparation efficiency.
  • the connection line Ls and the light shielding layer LS can also be formed separately, which is not further limited in this embodiment.
  • connection line Ls on the base substrate 10 and the orthographic projection of the scan line Gate on the base substrate 10 not to overlap, thereby avoiding when the connection line Ls is
  • the material is a metal material
  • parasitic capacitance is generated by overlapping with the scanning line Gate, thereby affecting the display effect of the corresponding display panel.
  • the width b of the connection line Ls is in the range of 1 ⁇ m to 15 ⁇ m, and the thickness of the connection line Ls is in the range of 300 ⁇ to 1500 ⁇ . Further, the thickness of the connection line Ls is the same as the thickness of the light shielding layer Ls. Same thickness.
  • FIG. 7 is a schematic diagram of a first arrangement of sub-pixels of the array substrate provided by the embodiment of the present application.
  • the first type of data lines Data1 and the second type of data lines Data2 are arranged alternately in the horizontal direction; the first sub-pixels P1 and the second sub-pixels P2 are alternately arranged in the horizontal direction A first pixel row 120 is formed, and the light shielding layer LS corresponding to any one of the first sub-pixels P1 and the light shielding layer LS corresponding to at least one adjacent second sub-pixel P2 pass through the connecting line Ls Electrically connected.
  • a plurality of the sub-pixels P adjacent to any of the pixel rows 120 form a pixel group 121 , and the light-shielding layers LS corresponding to the sub-pixels P in the same pixel group 121 are between the light-shielding layers LS. They are electrically connected through the connecting line Ls.
  • any one of the pixel rows 120 includes one or more of the pixel groups 121 .
  • any of the pixel rows 120 includes a plurality of the pixel groups 121, and any of the pixel groups 121 includes the same number of the sub-pixels P; wherein, any of the pixel rows 120 includes consecutively arranged A plurality of first pixel groups 1211, any one of the first pixel groups 1211 includes N adjacent sub-pixels P, where N is a positive integer greater than or equal to 2.
  • the first pixel groups 1211 located in adjacent pixel rows 120 are arranged in a staggered manner.
  • the dislocation distance is the distance between 1 ⁇ (N-1) sub-pixels P, preferably the dislocation between the first pixel groups 1211 of the adjacent pixel rows 120 The distance is the distance between N/2 adjacent sub-pixels P.
  • the capacitive coupling directions of the first sub-pixel P1 and the second sub-pixel P2 are opposite, according to the sub-pixel voltage change [2V*CP1* It can be known from N+(-2V*CP1)*N]/2N that the data voltage change in the first sub-pixel P1 and the data voltage change in the second sub-pixel P2 are both zero.
  • the corresponding display by electrically connecting the light shielding layer LS corresponding to any of the first sub-pixels P1 and the light shielding layer LS corresponding to the second sub-pixel P2 through a connecting line Ls, the corresponding display
  • the capacitive coupling directions of the first sub-pixel P1 and the second sub-pixel P2 are opposite, which reduces the voltage on the sub-pixel, thereby effectively reducing the pixel brightness change caused by capacitive coupling and improving the picture flicker, etc. question.
  • the pixel row 120 includes a first pixel row 123 and a second pixel row 124 staggered along the vertical direction
  • the first pixel row 123 includes a plurality of first pixels arranged in a row group 1211, and a second pixel group 1212 located at the edge of the pixel row 120 and adjacent to a first pixel group 1211
  • the second pixel row 124 includes a plurality of first pixel groups 1211 arranged in a row
  • the first pixel group 1211 includes 6 adjacent sub-pixels P
  • the second pixel group 1212 includes 3 adjacent sub-pixels P, wherein the first pixel located in the adjacent pixel row 120
  • the offset distance between a pixel group 1211 is the distance between three adjacent sub-pixels P
  • the first pixel group 1211 at least includes a red sub-pixel, a blue sub-pixel and a green sub-pixel.
  • the pixel rows 120 further include a second pixel group 1212 located at the edge of the pixel row 120 and adjacent to the first pixel group 1211 , and the second pixel group 1212 includes M adjacent sub-pixels P, where M is a positive integer greater than or equal to 1, M ⁇ N, and M ⁇ 2N.
  • the case where the first pixel row 123 , the second pixel row 124 , and the first pixel row 123 are alternately arranged is only used for illustration.
  • the order in which the pixel rows 123 and the second pixel rows 124 are alternately arranged is not specifically limited; meanwhile, this embodiment does not specifically limit the number of the first pixel rows 123 and the number of the second pixel rows 124 .
  • FIG. 8 is a schematic diagram of a second arrangement of sub-pixels at the edge of the array substrate provided by the embodiment of the present application.
  • the arrangement of the sub-pixels is similar/same as the first arrangement of the sub-pixels provided in the above-mentioned embodiment.
  • the only difference between the two is that:
  • FIG. 9 is a schematic diagram of a third arrangement of sub-pixels at the edge of the array substrate provided by the embodiment of the present application.
  • the arrangement of the sub-pixels is similar/same as the first arrangement of the sub-pixels provided in the above-mentioned embodiment.
  • the only difference between the two is that:
  • the uniformity of the arrangement at the interval between the adjacent pixel groups can be improved, so as to avoid when the adjacent pixel rows
  • the connecting lines Ls are not set between the adjacent first pixel groups 1211, resulting in the arrangement of the adjacent first pixel groups 1211 at intervals.
  • the uniformity of the cloth is poor, and the phenomenon of poor display effect in this area occurs.
  • the first pixel group 1211 includes 6 sub-pixels P
  • the The second pixel group 1212 includes 3 adjacent sub-pixels P
  • the first pixel group 1211 includes 6 sub-pixels P
  • the second pixel group 1212 includes 9 adjacent sub-pixels P
  • the The first pixel group 1211 includes 2 adjacent sub-pixels P
  • the second pixel group 1212 includes 3 adjacent sub-pixels P, all of which are only used for illustration, and the number of the sub-pixels P can be based on The actual product needs to be selected.
  • the dislocation distance between the first pixel groups 1211 located in the adjacent pixel rows 120 is N/2 the distance between the adjacent sub-pixels P is only for illustration, and the embodiment of the present application
  • the dislocation distance between the first pixel groups 1211 of the adjacent pixel rows 120 is not specifically limited.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • This embodiment also provides a display panel, including the array substrate in the first embodiment, and a second substrate 130 disposed above the thin film transistors TFT of the array substrate, the second substrate 130 being close to one of the array substrates A black matrix 131 is provided on the side.
  • the projection of the black matrix 131 on the array substrate covers the connection line Ls.
  • the array substrate has been described in detail in the above embodiments, and the description is not repeated here.
  • the projection of the black matrix 131 on the array substrate covers the connection line Ls, that is, the connection line Ls is located directly under the black matrix 131, thereby avoiding the opening of the display panel rate loss, to achieve the purpose of improving the display effect of the display panel.
  • This embodiment further provides a display device, the display device includes the display panel in the above-mentioned second embodiment or the array substrate in the above-mentioned first embodiment.
  • the display device may be a display screen of a smart phone, tablet computer, notebook computer, smart bracelet, smart watch, smart glasses, smart helmet, desktop computer, smart TV, or digital camera, etc. Applied to electronic devices with flexible displays.
  • the present application provides an array substrate, a display panel and a display device.
  • the array substrate includes a base substrate, a plurality of data lines, a plurality of scanning lines, and a plurality of pixel units; the plurality of data lines include a plurality of first-type data lines and a plurality of second-type data lines arranged in parallel with the first-type data lines.
  • each of the pixel units includes the scan lines and the data
  • a plurality of sub-pixels defined by line crossings, the plurality of sub-pixels include a plurality of first sub-pixels electrically connected to the first type of data lines, and a plurality of first sub-pixels electrically connected to the second type of data lines
  • the light-shielding layer corresponding to any one of the first sub-pixels is electrically connected to at least one light-shielding layer corresponding to the second sub-pixel through a connecting line.

Abstract

一种阵列基板、显示面板以及显示装置，阵列基板具有极性相反的数据电压的多条第一类数据线(Data1)和多条第二类数据线(Data2)，任一第一子像素(P1)的遮光层(LS)至少与一第二子像素(P2)的遮光层(LS)通过连接线(Ls)电性连接，从而可有效减少电容耦合引起的像素亮度变化，改善画面闪烁问题。

Description

一种阵列基板、显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
 背景技术
当今社会科技迅猛发展，手机、电脑和电视等电子产品广泛应用于生活中的各个方面。因此，液晶显示面板（Liquid crystal display，LCD）和有机发光半导体（Organic Electroluminesence  Display，OLED）等电子显示屏被广泛采用。
现有技术通常在显示面板的薄膜晶体管（Thin Film Transistor，TFT）有源层沟道区与衬底基板之间增设一遮光层，所述遮光层可以对射向所述有源层的光进行遮挡，从而减少因光照射有源层产生的光生载流子导致的漏电流增加；然而，所述遮光层的材料通常为金属或不透光的非金属，因此所述遮光层与所述有源层之间会交叠产生电容，当显示面板工作时，所述源级电信号发生变化，通过电容耦合效应对所述显示面板像素的存储电荷产生影响，造成所述像素电压的波动，从而使所述像素产生亮度变化，进而使对应的显示面板出现闪烁异常。
 技术问题
本申请提供了一种阵列基板、显示面板及显示装置，可有效减少电容耦合引起的像素亮度变化，改善画面闪烁等问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
一种阵列基板，包括：
衬底基板；
沿竖直方向延伸的多条数据线，所述多条数据线包括多条第一类数据线和多条与所述第一类数据线平行设置的第二类数据线，所述第一类数据线和所述第二类数据线分别被配置为极性相反的数据电压；
沿水平方向延伸的多条扫描线；以及
多个像素单元，每个所述像素单元包括由所述扫描线和所述数据线交叉限定出的多个子像素，所述多个子像素包括与所述第一类数据线电性连接的多个第一子像素、及与所述第二类数据线电性连接的多个第二子像素；
其中，任一所述子像素对应设置有一薄膜晶体管、及位于所述薄膜晶体管与所述衬底基板之间的遮光层，任一所述第一子像素对应的所述遮光层至少与一所述第二子像素对应的所述遮光层通过连接线电性连接。
本申请的阵列基板中，所述第一类数据线和所述第二类数据线分别被配置为传输大小相等的数据电压。
本申请的阵列基板中，所述第一类数据线和所述第二类数据线沿水平方向依次交替设置；
所述第一子像素和所述第二子像素沿水平方向依次交替设置形成一像素行，任一所述第一子像素对应的所述遮光层至少与一相邻的所述第二子像素对应的所述遮光层通过所述连接线电性相连接。
本申请的阵列基板中，任一所述像素行中相邻的若干所述子像素组成一像素组，同一所述像素组内的所述子像素对应的所述遮光层之间通过所述连接线电性连接。
本申请的阵列基板中，任一所述像素行包括一个或多个所述像素组。
本申请的阵列基板中，任一所述像素行包括多个所述像素组，且任一所述像素组包括相同数量的所述子像素。
本申请的阵列基板中，任一所述像素行包括连续布置的多个第一像素组，任一所述第一像素组包括N个相邻的所述子像素，其中，N为大于等于2的正整数。
本申请的阵列基板中，位于相邻所述像素行的所述第一像素组之间错位布置。
本申请的阵列基板中，N为偶数，所述错位距离为1~（N-1）个所述子像素的距离。
本申请的阵列基板中，位于相邻所述像素行的所述第一像素组之间的错位距离为N/2个相邻所述子像素的间距。
本申请的阵列基板中，N=6，且所述第一像素组至少包括一个红色子像素、一个蓝色子像素和一个绿色子像素。
本申请的阵列基板中，至少部分所述像素行还包括位于所述像素行的边缘并与一所述第一像素组相邻的第二像素组，所述第二像素组包括M个相邻的子像素，其中，M为大于等于1的正整数，M≠N，且M<2N。
本申请的阵列基板中，任一所述子像素中，所述薄膜晶体管包括层叠设置的有源层、栅极、源极和漏极；
所述有源层包括沟道区、轻掺杂区以及重掺杂区；
其中，所述遮光层在所述有源层上的正投影覆盖所述沟道区、所述轻掺杂区以及所述重掺杂区。
本申请的阵列基板中，所述遮光层在所述衬底基板上正投影的边界和相邻所述沟道区在所述衬底基板上正投影的边界之间的间距a的范围为a≥2微米。
本申请的阵列基板中，所述连接线在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影不重叠。
本申请的阵列基板中，所述连接线的宽度范围为1微米~15微米。
本申请的阵列基板中，所述遮光层和所述连接线的厚度范围均为300Å~1500Å。
本申请的阵列基板中，所述连接线与所述遮光层同层设置，且所述连接线与所述遮光层材料相同。
本申请提供了一种显示面板，所述显示面板包括阵列基板、及设置于所述阵列基板的薄膜晶体管上方的第二基板，所述第二基板靠近所述阵列基板的一侧设置有黑色矩阵；
所述阵列基板包括：
衬底基板；
沿竖直方向延伸的多条数据线，所述多条数据线包括多条第一类数据线和多条与所述第一类数据线平行设置的第二类数据线，所述第一类数据线和所述第二类数据线分别被配置为极性相反的数据电压；
沿水平方向延伸的多条扫描线；以及
多个像素单元，每个所述像素单元包括由所述扫描线和所述数据线交叉限定出的多个子像素，所述多个子像素包括与所述第一类数据线电性连接的多个第一子像素、及与所述第二类数据线电性连接的多个第二子像素；
其中，任一所述子像素对应设置有一薄膜晶体管、及位于所述薄膜晶体管与所述衬底基板之间的遮光层，任一所述第一子像素对应的所述遮光层至少与一所述第二子像素对应的所述遮光层通过连接线电性连接
其中，所述黑色矩阵在所述阵列基板上的正投影覆盖所述连接线。
本申请提供了一种显示装置，包括上述任一所述的显示面板。
 有益效果
本申请通过在阵列基板的有源层和衬底基板之间增加遮光层，从而减少对应显示面板内射向所述有源层的光，进而减少因光照射所述有源层产生的光生载流子导致的漏电流；同时，通过设置具有极性相反数据电压的多条第一类数据线和多条与所述第一类数据线平行设置的第二类数据线，所述第一类数据线电性连接多个第一子像素，所述第二类数据线电性连接多个第二子像素，任一所述第一子像素的遮光层至少与一所述第二子像素的遮光层通过连接线电性连接，从而使对应显示面板工作时，所述第一子像素和所述第二子像素的电容耦合方向相反，降低所述子像素上的电压，进而可有效减少电容耦合引起的像素亮度变化，改善画面闪烁等问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有阵列基板的子像素的等效电路示意图；
图2为本申请所提供的阵列基板的子像素的等效电路示意图；
图3为本申请实施例所提供的阵列基板的结构示意图；
图4为本申请实施例所提供的阵列基板的有源层和遮光层的俯视图；
图5为本申请实施例所提供的阵列基板的子像素的等效电路示意图；
图6为本申请实施例所提供的阵列基板的俯视剖面图；
图7为本申请实施例所提供的阵列基板边缘处的子像素第一种排列示意图；
图8为本申请实施例所提供的阵列基板边缘处的子像素第二种排列示意图；
图9为本申请实施例所提供的阵列基板边缘处的子像素第三种排列示意图；
图10为本申请实施例所提供的显示面板的结构示意图。
 本发明的实施方式
本申请提供一种阵列基板、显示面板及显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1，现有阵列基板的子像素的等效电路示意图。
现有技术中，阵列基板包括衬底基板、沿竖直方向延伸的多条数据线Data、沿水平方向延伸的多条扫描线Gate以及多个像素单元，每个所述像素单元包括由所述扫描线Gate和所述数据线Data交叉限定出的多个子像素，所述子像素包括一薄膜晶体管TFT、存储电容Cst以及液晶电容Clc，所述薄膜晶体管TFT的栅极与相应的扫描线Gate连接，所述薄膜晶体管TFT的源极与相应的数据线Data连接，所述薄膜晶体管TFT的漏极与所述液晶电容Clc的第一极板和存储电容Cst的第一极板连接，为了减少对应显示面板内射向所述薄膜晶体管TFT有源层的光，进而减少因光照射所述有源层产生的光生载流子导致的漏电流，通常在所述薄膜晶体管TFT与所述衬底基板之间增加遮光层LS。
然而，由于所述遮光层LS的材料为金属或不透光的非金属，因此所述遮光层LS与所述源极之间会形成第一电容CP1，所述遮光层LS与所述漏极之间会形成第二电容CP2，当对应的显示面板工作时，所述源级电信号发生变化，通过电容耦合效应对所述子像素的存储电荷产生影响，造成所述子像素电压的波动，从而使所述子像素产生亮度变化，进而使对应的显示面板出现闪烁异常。基于此，本申请提供了一种阵列基板、显示面板及显示装置，用以解决上述问题。
请参阅图2，本申请所提供的阵列基板的子像素的等效电路示意图。
本申请提供一阵列基板，所述阵列基板包括衬底基板（图中未标出）；沿竖直方向延伸的多条数据线Data，所述多条数据线Data包括多条第一类数据线Data和多条与所述第一类数据线Data1平行设置的第二类数据线Data2，所述第一类数据线Data1和所述第二类数据线Data2分别被配置为极性相反的数据电压；沿水平方向延伸的多条扫描线Gate。
以及多个像素单元（图中未标出），每个所述像素单元包括由所述扫描线Gate和所述数据线Data交叉限定出的多个子像素（图中未标出），所述多个子像素包括与所述第一类数据线Data1电性连接的多个第一子像素P1、及与所述第二类数据线Data2电性连接的多个第二子像素P2。
其中，任一所述子像素对应设置有一薄膜晶体管TFT、及位于所述薄膜晶体管TFT与所述衬底基板之间的遮光层LS，任一所述第一子像素P1对应的所述遮光层LS至少与一所述第二子像素P2对应的所述遮光层LS通过连接线Ls电性连接。
需要说明的是，本申请对所述子像素的个数、所述第一子像素P1的个数以及所述第二子像素P2个数均不做具体限制。
在本申请中，所述第一子像素P1和所述第二子像素P2还包括存储电容Cst和液晶电容Clc，所述薄膜晶体管TFT的栅极与相应的扫描线Gate连接，所述薄膜晶体管TFT的源极与相应的数据线Data连接，所述薄膜晶体管TFT的漏极与所述液晶电容Clc的第一极板和存储电容Cst的第一极板连接，所述遮光层LS与所述薄膜晶体管TFT的源极之间形成第一电容CP1，所述遮光层LS与所述薄膜晶体管TFT的漏极之间形成第二电容CP2。
本申请提供的阵列基板包括沿竖直方向延伸的多条数据线，所述多条数据线包括多条第一类数据线Data1和多条与所述第一类数据线Data1平行设置的第二类数据线Data2，所述第一类数据线Data1和所述第二类数据线Data2分别被配置为极性相反的数据电压；多个像素单元，每个所述像素单元包括由所述扫描线和所述数据线交叉限定出的多个子像素，所述多个子像素包括与所述第一类数据线Data1电性连接的多个第一子像素P1、及与所述第二类数据线Data2电性连接的多个第二子像素P2；其中，任一所述第一子像素P1对应的所述遮光层LS至少与一所述第二子像素P2对应的所述遮光层LS通过连接线Ls电性连接，从而使对应显示面板工作时，所述第一子像素P1和所述第二子像素P2的电容耦合方向相反，降低所述子像素上的电压，进而可有效减少电容耦合引起的像素亮度变化，改善画面闪烁等问题。
需要说明的是，在本申请中，所述第一子像素P1和所述第二子像素P2包括但不限于红色子像素（R）、绿色子像素(G)以及蓝色子像素（B）。
可以理解的是，在本申请中，对所述第一子像素P1和所述第二子像素P2的种类不做进一步限制，即，所述第一子像素P1和所述第二子像素P2的种类可以相同也可以不同。
现结合具体实施例对本申请的技术方案进行描述。
实施例一
请结合图3，本申请实施例所提供的阵列基板的结构示意图。
本实施例提供一阵列基板，所述阵列基板包括衬底基板10、及位于所述衬底基板10上的多个像素单元（图中未标出），每个所述像素单元包括多个子像素（图中未标出），任一所述子像素对应设置有位于所述衬底基板10上的薄膜晶体管TFT、及位于所述薄膜晶体管TFT与所述衬底基板10之间的遮光层LS。
在本实施例中，所述衬底基板10的材料包括但不限于聚对苯二甲酸乙二醇酯、聚酰亚胺、三醋酸纤维薄膜或其他柔性材料，进一步的，所述衬底基板10为PI基板，主要为聚酰亚胺，PI材料可以有效的提高基板的透光率。
在本实施例中，所述薄膜晶体管TFT包括依次层叠设置于所述遮光层LS上的有源层30、栅极绝缘层40、栅极50、层间绝缘层60、源极71、漏极72、平坦层80、公共电极层90、钝化层100以及像素电极110，其中，所述源极71和所述漏极72同层且间隔设置，所述像素电极110通过一过孔（图中未标出）与所述漏极72电性连接。
在本实施例中，所述有源层30的材料包括但不限于铟镓锌氧化物；所述栅极绝缘层40和层间绝缘层60具有强水氧阻隔能力和绝缘能力，其材料包括但不限于氧化硅、氮化硅、氮氧化硅等或其层叠；所述栅极50、所述源极71和所述漏极72的材料包括但不限于钼、银、铝等金属或其叠层；所述钝化层100的材料包括但不限于氧化硅、氮化硅、氮氧化硅等或其层叠；所述公共电极层90和所述像素电极110的材料包括但不限于氧化铟锡。
在本实施例中，所述阵列基板还包括位于所述有源层30和所述遮光层LS之间的缓冲层20，所述缓冲层20可以由氧化硅或氮化硅所构成。
需要说明的是，本实施例中，所述阵列基板包括依次层叠设置于所述遮光层LS上的缓冲层20、有源层30、栅极绝缘层40、栅极50、层间绝缘层60、源极71、漏极72、平坦层80、公共电极层90、钝化层100以及像素电极110仅用于举例说明，同时，所述像素电极110与所述漏极72电性连接也仅用于举例说明，所述像素电极110也可连接所述源极71，本实施例对此不做具体限制。
请结合图4，本申请实施例所提供的阵列基板的有源层和遮光层的俯视图。
在本实施例中，所述有源层30包括沟道区31、轻掺杂区32以及重掺杂区33，所述沟道区31位于两个所述轻掺杂区32之间，所述沟道区31和所述轻掺杂区32位于两个所述重掺杂区33之间；其中，所述遮光层LS在所述有源层30上的投影覆盖所述沟道区31、所述轻掺杂区32以及所述重掺杂区33。
具体地，所述遮光层LS在所述有源层30上的投影至少与所述重掺杂区33远离所述轻掺杂区32一侧的边界重叠；其中，所述遮光层LS的厚度范围为300Å~1500Å。
具体地，所述遮光层LS在所述衬底基板10上正投影的边界和所述沟道区31在所述衬底基板10上正投影的边界之间的间距a的范围为a≥2微米，通过限制所述a的范围，从而减少光线从衬底基板10远离所述有源层30的一侧入射到所述有源层30的沟道区31以及轻掺杂区32中，保证所述沟道区31以及所述轻掺杂区32的遮光性；同时，为了得到遮光性能较好且量产可行性高的所述遮光层LS，优选地，所述遮光层LS的厚度范围为600Å~1000Å。
在本实施例中，所述遮光层LS在所述有源层30上的投影至少与所述重掺杂区33远离所述轻掺杂区32一侧的边界重叠，从而对所述有源层30靠近所述衬底基板10的一侧起到平坦化的作用，进而防止所述有源层30发生断线等不良现象。
本实施例通过在所述阵列基板的有源层30和所述衬底基板10之间增加所述遮光层LS，所述有源层30在所述衬底基板10上的正投影位于所述遮光层LS在所述衬底基板10上的正投影内，从而减少所述阵列基板内射向所述有源层30的光，进而减少因光照射所述有源层30产生的光生载流子导致的漏电流。
请参阅图5，本申请实施例所提供的阵列基板的子像素的等效电路示意图。
在本实施例中，所述阵列基板还包括沿竖直方向延伸的多条数据线Data，所述多条数据线Data包括多条第一类数据线Data1和多条与所述第一类数据线Data1平行设置的第二类数据线Data2，所述第一类数据线Data1和所述第二类数据线Data2分别被配置为极性相反的数据电压；沿水平方向延伸的多条扫描线Gate；每个所述像素单元（图中未标出）包括由所述扫描线Gate和所述数据线Data交叉限定出的多个子像素P，所述多个子像素P包括与所述第一类数据线Data1电性连接的多个第一子像素P1、及与所述第二类数据线Data2电性连接的多个第二子像素P2，任一所述第一子像素P1对应的所述遮光层LS至少与一相邻的所述第二子像素P2对应的所述遮光层LS通过所述连接线Ls电性相连接。
本实施例通过设置具有极性相反数据电压的多条第一类数据线Data1和多条与所述第一类数据线Data1平行设置的第二类数据线Data2，所述第一类数据线Data1电性连接多个第一子像素P1，所述第二类数据线Data2电性连接多个第二子像素P2，任一所述第一子像素P1对应的所述遮光层LS至少与一相邻的所述第二子像素P2对应的所述遮光层LS通过所述连接线Ls电性相连接，从而使对应显示面板工作时，所述第一子像素P1和所述第二子像素P2的电容耦合方向相反，降低所述子像素P上的电压，进而可有效减少电容耦合引起的像素亮度变化，改善画面闪烁等问题。
进一步地，所述第一类数据线Data1和所述第二类数据线Data2分别被配置为传输大小相等的数据电压。
具体地，在一种实施例中，所述第一类数据线Data1和所述第二类数据线Data2沿水平方向依次交替设置；所述第一子像素P1和所述第二子像素P2沿水平方向依次交替设置，任一所述第一子像素P1对应的所述遮光层LS至少与一相邻的所述第二子像素P2对应的所述遮光层LS通过所述连接线Ls电性相连接，从而使对应显示面板工作时，所述第一子像素P1和所述第二子像素P2的电容耦合方向相反，所述第一子像素P1中的数据电压变化和所述第二子像素P2中的数据电压变化均为0，进而可有效减少电容耦合引起的像素亮度变化，改善画面闪烁等问题。
在本实施例中，所述第一子像素P1和所述第二子像素P2还包括存储电容Cst和液晶电容Clc，所述薄膜晶体管TFT的栅极50与相应的扫描线Gate连接，所述薄膜晶体管TFT的源极71与相应的数据线Data连接，所述薄膜晶体管TFT的漏极72与所述液晶电容Clc的第一极板和存储电容Cst的第一极板连接，所述遮光层LS与所述薄膜晶体管TFT的源极71之间形成第一电容CP1，所述遮光层LS与所述薄膜晶体管TFT的漏极72之间形成第二电容CP2，所述第一子像素P1对应的所述遮光层LS与相邻的所述第二子像素P2对应的所述遮光层LS通过所述连接线Ls电性相连接。
请结合图6，本申请实施例所提供的阵列基板的俯视剖面图。
在本实施例中，所述连接线Ls与所述遮光层LS同层设置，且所述连接线Ls与所述遮光层LS的材料相同，其中，当所述连接线Ls的材料为金属材料时，为了避免所述连接线Ls与所述扫描线Gate交叠产生寄生电容，因此所述连接线Ls在所述衬底基板10上的正投影与所述扫描线Gate在所述衬底基板10上的正投影不重叠。
可以理解的是，在本实施例中，所述连接线Ls与所述遮光层LS的材料相同，因此所述连接线Ls与所述遮光层LS可以为一体成型结构，从而减少所述阵列基板制备方法的工艺流程，提高制备效率。当然，所述连接线Ls与所述遮光层LS也可以单独成型，本实施例对此不做进一步限制。
本实施例通过设置所述连接线Ls在所述衬底基板10上的正投影与所述扫描线Gate在所述衬底基板10上的正投影不重叠，从而避免当所述连接线Ls的材料为金属材料时，与所述扫描线Gate交叠产生寄生电容，从而影响对应显示面板显示效果的问题。
具体地，所述连接线Ls的宽度b的范围为1微米~15微米，所述连接线Ls的厚度范围为300Å~1500Å，进一步地，所述连接线Ls的厚度与所述遮光层Ls的厚度相同。
请参阅图7，本申请实施例所提供的阵列基板的子像素第一种排列示意图。
在本实施例中，所述第一类数据线Data1和所述第二类数据线Data2沿水平方向依次交替设置；所述第一子像素P1和所述第二子像素P2沿水平方向依次交替设置形成第一像素行120，任一所述第一子像素P1对应的所述遮光层LS至少与一相邻的所述第二子像素P2对应的所述遮光层LS通过所述连接线Ls电性相连接。
在本实施例中，任一所述像素行120中相邻的若干所述子像素P组成一像素组121，同一所述像素组121内的所述子像素P对应的所述遮光层LS之间通过所述连接线Ls电性连接。
在本实施例中，任一所述像素行120包括一个或多个所述像素组121。
具体地，任一所述像素行120包括多个所述像素组121，且任一所述像素组121包括相同数量的所述子像素P；其中，任一所述像素行120包括连续布置的多个第一像素组1211，任一所述第一像素组1211包括N个相邻的所述子像素P，其中，N为大于等于2的正整数。
在本实施例中，位于相邻所述像素行120的所述第一像素组1211之间错位布置。
其中，当N为偶数时，所述错位距离为1~（N-1）个所述子像素P的距离，优选位于相邻所述像素行120的所述第一像素组1211之间的错位距离为N/2个相邻所述子像素P的间距，此时，所述第一子像素P1和所述第二子像素P2的电容耦合方向相反，根据子像素电压变化[2V*CP1*N+(-2V*CP1)*N]/2N可知，所述第一子像素P1中的数据电压变化和所述第二子像素P2中的数据电压变化均为0。
当N为奇数时，所述错位距离为1~（N-1）个所述子像素P的距离，优选位于相邻所述像素行120的所述第一像素组1211之间的错位距离为（N+1）/2个相邻所述子像素P的间距，此时，所述第一子像素P1和所述第二子像素P2的电容耦合方向相反，根据子像素电压变化[2V*CP1*（N+1）+(-2V*CP1)*N]/2N=（2V*CP1）/（2N+1）可知，当N为奇数时，所述子像素上的电压降低，进一步地，当N足够大时，所述第一子像素P1中的数据电压变化和所述第二子像素P2中的数据电压变化近似于0。
本实施例，通过将任一所述第一子像素P1对应的所述遮光层LS与一所述第二子像素P2对应的所述遮光层LS通过连接线Ls电性连接，从而使对应显示面板工作时，所述第一子像素P1和所述第二子像素P2的电容耦合方向相反，降低所述子像素上的电压，进而可有效减少电容耦合引起的像素亮度变化，改善画面闪烁等问题。
具体地，在本实施例中，所述像素行120包括沿竖直方向交错设置的第一像素行123和第二像素行124，所述第一像素行123包括连续布置的多个第一像素组1211，及位于所述像素行120的边缘并与一所述第一像素组1211相邻的第二像素组1212，所述第二像素行124包括连续布置的多个第一像素组1211，所述第一像素组1211包括6个相邻的所述子像素P，所述第二像素组1212包括3个相邻的子像素P，其中，位于相邻所述像素行120的所述第一像素组1211之间的错位距离为3个相邻所述子像素P的间距，且所述第一像素组1211至少包括一个红色子像素、一个蓝色子像素和一个绿色子像素。
在本实施例中，至少部分所述像素行120还包括位于所述像素行120的边缘并与一所述第一像素组1211相邻的第二像素组1212，所述第二像素组1212包括M个相邻的子像素P，其中，M为大于等于1的正整数，M≠N，且M<2N。
可以理解的是，图7中，所述第一像素行123、所述第二像素行124以及所述第一像素行123交错设置的情况仅用作举例说明，本实施例对所述第一像素行123和所述第二像素行124交错设置的顺序不做具体限制；同时，本实施例对所述第一像素行123的数量和所述第二像素行124的数量均不做具体限制。
请参阅图8，本申请实施例所提供的阵列基板边缘处的子像素第二种排列示意图。
在本实施例中，所述子像素的排列方式与上述实施例所提供的子像素的第一种排列方式相似/相同，具体请参照上述实施例中的子像素排列方式的描述，此处不再赘述，两者的区别仅在于：
在本实施例中，N=6，M=9，即所述第一像素组1211包括6个相邻的所述子像素P，所述第二像素组1212包括9个相邻的子像素P，其中，位于相邻所述像素行120的所述第一像素组1211之间的错位距离为3个相邻所述子像素P的间距。
请参阅图9，本申请实施例所提供的阵列基板边缘处的子像素第三种排列示意图。
在本实施例中，所述子像素的排列方式与上述实施例所提供的子像素的第一种排列方式相似/相同，具体请参照上述实施例中的子像素排列方式的描述，此处不再赘述，两者的区别仅在于：
在本实施例中，N=2，M=3，即所述第一像素组1211包括2个相邻的所述子像素P，所述第二像素组1212包括3个相邻的子像素P，其中，位于相邻所述像素行120的所述第一像素组1211之间的错位距离为1个相邻所述子像素P的间距。
本实施例通过将相邻所述像素行120的所述第一像素组1211之间错位布置，可以提高相邻所述像素组间隔处的排布均匀性，从而避免当相邻所述像素行120中的所述第一像素组1211对应排布时，相邻所述第一像素组1211之间因没有设置所述连接线Ls，从而造成相邻所述第一像素组1211间隔处的排布均匀性较差，进而出现的该区域显示效果不良的现象。
需要说明的是，上述图7、图8以及图9只是对本申请技术方案的示例性的描述，即在本实施例中，所述第一像素组1211包括6个所述子像素P，所述第二像素组1212包括3个相邻的子像素P；所述第一像素组1211包括6个所述子像素P，所述第二像素组1212包括9个相邻的子像素P；所述第一像素组1211包括2个相邻的所述子像素P，所述第二像素组1212包括3个相邻的子像素P均仅用作举例说明，所述子像素P的个数可以根据实际产品的需求来选定。
可以理解的是，位于相邻所述像素行120的所述第一像素组1211之间的错位距离为N/2个相邻所述子像素P的间距仅用于举例说明，本申请实施例对相邻所述像素行120的所述第一像素组1211之间的错位距离不做具体限制。
实施例二
请参阅图10，本申请实施例所提供的显示面板的结构示意图。
本实施例还提供一种显示面板，包括上述实施例一中阵列基板、及设置于所述阵列基板的薄膜晶体管TFT上方的第二基板130，所述第二基板130靠近所述阵列基板的一侧设置有黑色矩阵131。
其中，所述黑色矩阵131在所述阵列基板上的投影覆盖所述连接线Ls。
在本实施例中，所述阵列基板已经在上述实施例中进行了详细的说明，在此不在重复说明。
本实施例通过将所述黑色矩阵131在所述阵列基板上的投影覆盖所述连接线Ls，即所述连接线Ls位于所述黑色矩阵131的正下方，从而避免了所述显示面板的开口率损失，达到提升显示面板显示效果的目的。
实施例三
本实施例还提供了一种显示装置，所述显示装置包括上述实施例二中的显示面板或上述实施例一中的阵列基板。
其中，所述阵列基板已经在上述实施例中进行了详细的说明，在此不在重复说明。
在具体应用时，所述显示装置可以为智能手机、平板电脑、笔记本电脑、智能手环、智能手表、智能眼镜、智能头盔、台式机电脑、智能电视或者数码相机等设备的显示屏，甚至可以应用在具有柔性显示屏的电子设备上。
综上所述，本申请提供一种阵列基板、显示面板及显示装置。所述阵列基板包括衬底基板、多条数据线、多条扫描线以及多个像素单元；多条数据线包括多条第一类数据线和多条与第一类数据线平行设置的第二类数据线，所述第一类数据线和所述第二类数据线分别被配置为传输大小相等、极性相反的数据电压；每个所述像素单元包括由所述扫描线和所述数据线交叉限定出的多个子像素，所述多个子像素包括与所述第一类数据线电性连接的多个第一子像素、及与所述第二类数据线电性连接的多个第二子像素，任一所述第一子像素对应的遮光层至少与一所述第二子像素对应的遮光层通过连接线电性连接。本申请提供的显示面板和显示装置可有效改善电容耦合引起的画面闪烁问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    沿竖直方向延伸的多条数据线，所述多条数据线包括多条第一类数据线和多条与所述第一类数据线平行设置的第二类数据线，所述第一类数据线和所述第二类数据线分别被配置为极性相反的数据电压；
    沿水平方向延伸的多条扫描线；以及
    多个像素单元，每个所述像素单元包括由所述扫描线和所述数据线交叉限定出的多个子像素，所述多个子像素包括与所述第一类数据线电性连接的多个第一子像素、及与所述第二类数据线电性连接的多个第二子像素；
    其中，任一所述子像素对应设置有一薄膜晶体管、及位于所述薄膜晶体管与所述衬底基板之间的遮光层，任一所述第一子像素对应的所述遮光层至少与一所述第二子像素对应的所述遮光层通过连接线电性连接。
  2. 如权利要求1所述的阵列基板，其中，所述第一类数据线和所述第二类数据线分别被配置为传输大小相等的数据电压。
  3. 如权利要求1所述的阵列基板，其中，所述第一类数据线和所述第二类数据线沿水平方向依次交替设置；
    所述第一子像素和所述第二子像素沿水平方向依次交替设置形成一像素行，任一所述第一子像素对应的所述遮光层至少与一相邻的所述第二子像素对应的所述遮光层通过所述连接线电性相连接。
  4. 如权利要求3所述的阵列基板，其中，任一所述像素行中相邻的若干所述子像素组成一像素组，同一所述像素组内的所述子像素对应的所述遮光层之间通过所述连接线电性连接。
  5. 如权利要求4所述的阵列基板，其中，任一所述像素行包括一个或多个所述像素组。
  6. 如权利要求5所述的阵列基板，其中，任一所述像素行包括多个所述像素组，且任一所述像素组包括相同数量的所述子像素。
  7. 如权利要求5所述的阵列基板，其中，任一所述像素行包括连续布置的多个第一像素组，任一所述第一像素组包括N个相邻的所述子像素，其中，N为大于等于2的正整数。
  8. 如权利要求7所述的阵列基板，其中，位于相邻所述像素行的所述第一像素组之间错位布置。
  9. 如权利要求8所述的阵列基板，其中，N为偶数，所述错位距离为1~（N-1）个所述子像素的距离。
  10. 如权利要求9所述的阵列基板，其中，位于相邻所述像素行的所述第一像素组之间的错位距离为N/2个相邻所述子像素的间距。
  11. 如权利要求10所述的阵列基板，其中，N=6，且所述第一像素组至少包括一个红色子像素、一个蓝色子像素和一个绿色子像素。
  12. 如权利要求7所述的阵列基板，其中，至少部分所述像素行还包括位于所述像素行的边缘并与一所述第一像素组相邻的第二像素组，所述第二像素组包括M个相邻的子像素，其中，M为大于等于1的正整数，M≠N，且M<2N。
  13. 如权利要求1所述的阵列基板，其中，任一所述子像素中，所述薄膜晶体管包括层叠设置的有源层、栅极、源极和漏极；
    所述有源层包括沟道区、轻掺杂区以及重掺杂区；
    其中，所述遮光层在所述有源层上的正投影覆盖所述沟道区、所述轻掺杂区以及所述重掺杂区。
  14. 如权利要求13所述的阵列基板，其中，所述遮光层在所述衬底基板上正投影的边界和相邻所述沟道区在所述衬底基板上正投影的边界之间的间距a的范围为a≥2微米。
  15. 如权利要求13所述的阵列基板，其中，所述连接线在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影不重叠。
  16. 如权利要求1所述的阵列基板，其中，所述连接线的宽度范围为1微米~15微米。
  17. 如权利要求1所述的阵列基板，其中，所述遮光层和所述连接线的厚度范围均为300Å~1500Å。
  18. 如权利要求1所述的阵列基板，其特征在于，所述连接线与所述遮光层的厚度相同。
  19. 一种显示面板，其中，所述显示面板包括阵列基板、及设置于所述阵列基板的薄膜晶体管上方的第二基板，所述第二基板靠近所述阵列基板的一侧设置有黑色矩阵；
    所述阵列基板包括：
    衬底基板；
    沿竖直方向延伸的多条数据线，所述多条数据线包括多条第一类数据线和多条与所述第一类数据线平行设置的第二类数据线，所述第一类数据线和所述第二类数据线分别被配置为极性相反的数据电压；
    沿水平方向延伸的多条扫描线；以及
    多个像素单元，每个所述像素单元包括由所述扫描线和所述数据线交叉限定出的多个子像素，所述多个子像素包括与所述第一类数据线电性连接的多个第一子像素、及与所述第二类数据线电性连接的多个第二子像素；
    其中，任一所述子像素对应设置有一薄膜晶体管、及位于所述薄膜晶体管与所述衬底基板之间的遮光层，任一所述第一子像素对应的所述遮光层至少与一所述第二子像素对应的所述遮光层通过连接线电性连接；
    其中，所述黑色矩阵在所述阵列基板上的正投影覆盖所述连接线。
  20. 一种显示装置，其中，所述显示装置包括权利要求19所述的显示面板。
PCT/CN2021/084636 2021-03-15 2021-03-31 一种阵列基板、显示面板及显示装置 WO2022193371A1 (zh)

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