WO2022188272A1 - 声表面波滤波器与封装方法 - Google Patents

声表面波滤波器与封装方法 Download PDF

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WO2022188272A1
WO2022188272A1 PCT/CN2021/095874 CN2021095874W WO2022188272A1 WO 2022188272 A1 WO2022188272 A1 WO 2022188272A1 CN 2021095874 W CN2021095874 W CN 2021095874W WO 2022188272 A1 WO2022188272 A1 WO 2022188272A1
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layer
material layer
film layer
cover plate
acoustic wave
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PCT/CN2021/095874
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English (en)
French (fr)
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陈景
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展讯通信（上海）有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/25—Constructional features of resonators using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/64—Filters using surface acoustic waves

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  • the embodiments of the present application relate to the technical field of semiconductors, and in particular, to a surface acoustic wave filter and a packaging method.
  • the surface acoustic wave filter has the characteristics of high operating frequency, frequency bandwidth, good frequency selection characteristics, small size and light weight, and can use the same production process as integrated circuits, simple manufacturing, low cost, and good consistency of frequency characteristics. , so it is widely used in various electronic devices.
  • CA Carrier Aggregation
  • MIMO Multiple Input Multiple Output
  • QAM Quadrature Amplitude Modulation
  • RF front-end components in electronic equipment has not only increased significantly, but also put forward more and more stringent technical requirements for the performance of filter components, such as requiring better temperature stability and smaller packages. size for high integration with active devices such as power amplifiers, RF switches, etc. in the RF front-end. Therefore, how to design filter components with high temperature stability and high reliability is an urgent problem to be solved.
  • Embodiments of the present application provide a surface acoustic wave filter and a packaging method, which can effectively improve the temperature stability and reliability of the surface acoustic wave filter.
  • an embodiment of the present application provides a surface acoustic wave filter, and the surface acoustic wave filter includes a wafer, an electrode layer, a sealing wall, a plastic sealing structure, and a cover plate;
  • the wafer includes a substrate layer and a piezoelectric film layer, the top surface of the substrate layer and the bottom surface of the piezoelectric film layer are integrated by wafer bonding, and the electrode layer is disposed on the piezoelectric film layer. the top surface of the electrical thin film layer;
  • the plastic encapsulation structure covers the bottom surface of the substrate layer and the side surfaces of the substrate layer and the piezoelectric film layer;
  • the bottom surface of the sealing wall covers both the first surface of the plastic sealing structure and part of the top surface of the piezoelectric film layer, and the first surface is at least part of the top surface of the plastic sealing structure on the side of the piezoelectric film layer. surface, the sealing wall surrounds and forms a sealing cavity between the piezoelectric film layer and the cover plate;
  • the cover plate includes a first material layer and a second material layer, and the first material layer and the second material layer are integrated by wafer bonding; the second material layer is located on the cover The side of the plate close to the sealed cavity, the material used for the first material layer is the same as the material used for the substrate layer, and the material used for the second material layer is the same as the material used for the piezoelectric film layer .
  • the top surface of the plastic encapsulation structure on the side of the piezoelectric thin film layer is flush with the top surface of the piezoelectric thin film layer.
  • the plastic encapsulation structure is made of at least one of the following materials: polymer, resin, and plastic encapsulation film.
  • the electrode layer includes a lead-out electrode, a surface of the lead-out electrode is provided with a thickened electrode, and the bottom surface of the sealing wall covers the thickened electrode.
  • the cover plate further includes a third material layer, the third material layer is located between the first material layer and the second material layer, and the first material layer It is integrated with the second material layer by the third material layer, and the material used for the third material layer is an organic binder.
  • the piezoelectric thin film layer is made of at least one of the following materials: lithium tantalate LiTaO 3 , lithium niobate LiNbO 3 , aluminum nitride ALN, scandium Sc doped AlN
  • the substrate layer is made of at least one of the following materials: silicon Si, sapphire, glass, silicon carbide SiC.
  • an embodiment of the present application provides a method for packaging a surface acoustic wave filter, the method comprising:
  • the wafer includes a substrate layer and a piezoelectric film layer, and the top surface of the substrate layer and the bottom surface of the piezoelectric film layer are integrated by wafer bonding;
  • the plastic encapsulation structure is covered on the bottom surface of the substrate layer and the side surfaces of the substrate layer and the piezoelectric film layer;
  • a sealing wall is prepared, the bottom surface of the sealing wall covers both the first surface of the plastic sealing structure and part of the top surface of the piezoelectric film layer, and the first surface is the plastic sealing of the side of the piezoelectric film layer at least part of the top surface of the structure;
  • a cover plate is obtained, the cover plate includes a first material layer and a second material layer, and the first material layer and the second material layer are integrated by wafer bonding; the second material layer Located on the side of the cover plate close to the sealed cavity, the material used for the first material layer is the same as the material used for the substrate layer, and the material used for the second material layer is the same as the piezoelectric film layer. The same materials are used;
  • the sealing wall and the cover plate are sealed, so that the sealing wall surrounds the piezoelectric film layer and the cover plate to form a sealing cavity.
  • the top surface of the plastic encapsulation structure on the side of the piezoelectric thin film layer is flush with the top surface of the piezoelectric thin film layer.
  • the electrode layer includes an extraction electrode, and after the electrode layer is prepared on the top surface of the piezoelectric thin film layer, the electrode layer further includes:
  • a thickened electrode is arranged on the surface of the lead-out electrode
  • the preparation of the sealing wall includes:
  • the sealing wall is formed on the first surface of the plastic sealing structure and a part of the top surface of the piezoelectric film layer, and the bottom surface of the sealing wall covers the thickened electrode.
  • the cover plate further includes a third material layer, the third material layer is located between the first material layer and the second material layer, and the first material layer It is integrated with the second material layer by the third material layer, and the material used for the third material layer is an organic binder.
  • a plastic sealing structure is provided on the bottom surface of the substrate layer and the sides of the substrate layer and the piezoelectric film layer.
  • the sealing wall is arranged, the bottom surface of the sealing wall is simultaneously covered with The first surface of the plastic encapsulation structure and part of the top surface of the piezoelectric film layer can effectively increase the width of the sealing wall, so that a highly reliable sealing wall can be fabricated on a miniaturized chip, and the surface acoustic wave filter can be improved.
  • the material used for the above-mentioned cover plate is the same as the material used for the wafer, that is, the temperature expansion coefficient of the cover plate can be equal to or very close to the temperature expansion coefficient of the wafer, thereby preventing
  • the temperature expansion coefficient of the cover plate and the temperature expansion coefficient of the wafer are greatly different, the sealed cavity is damaged, and the influence of temperature changes on such packaging structures is eliminated, so that the temperature stability of the surface acoustic wave filter can be effectively enhanced.
  • FIG. 1 is a top-view structural schematic diagram of a surface acoustic wave filter packaging structure in an embodiment of the application;
  • FIG. 2 is a schematic diagram 1 of a cross-sectional structure of the package structure of the surface acoustic wave filter shown in FIG. 1 along the section line AB;
  • FIG. 3 is a second schematic cross-sectional structure diagram of the surface acoustic wave filter package structure shown in FIG. 1 along section line AB;
  • FIG. 4 is a schematic diagram 3 of a cross-sectional structure of the surface acoustic wave filter package structure shown in FIG. 1 along the section line AB;
  • FIG. 5 is a schematic cross-sectional view of a surface acoustic wave filter in an embodiment of the application.
  • FIG. 6 is a schematic flowchart of a method for packaging a surface acoustic wave filter in an embodiment of the present application
  • FIG. 7a to 7h are schematic diagrams of the packaging process of the surface acoustic wave filter in the embodiment of the present application.
  • SAW filters have become an indispensable key component in mobile phone radio frequency (RF) front-end applications due to their high operating frequency, pass-band bandwidth, good frequency selection characteristics, small size and light weight.
  • RF radio frequency
  • 5G core technologies such as carrier aggregation, MIMO antenna technology, and QAM
  • the number of RF front-end components in electronic equipment has not only increased significantly, but also put forward more and more stringent technical requirements for the performance of filter components, such as requirements It has higher reliability and temperature stability, and has a smaller package size for high integration with active devices such as power amplifiers and RF switches in the RF front-end.
  • the sealing wall cannot occupy too much chip area, and if the width of the sealing wall is small after the chip miniaturization, the reliability of the sealing cavity may change.
  • the performance of the surface acoustic wave filter is easily affected by temperature, and the temperature stability is not high.
  • an embodiment of the present application provides a surface acoustic wave filter, wherein a plastic sealing structure is provided on the bottom surface of the substrate layer and the side surfaces of the substrate layer and the piezoelectric film layer.
  • the bottom surface covers the first surface of the plastic sealing structure and part of the top surface of the piezoelectric film layer at the same time, which can effectively increase the width of the sealing wall, so that a highly reliable sealing wall can be produced on the miniaturized chip, and the sound can be improved.
  • the material used for the cover plate is the same as the material used for the wafer, that is, the temperature expansion coefficient of the cover plate can be equal to or very close to the temperature expansion coefficient of the wafer, which can prevent the
  • the sealed cavity is damaged due to the large difference between the temperature expansion coefficient of the cover plate and the temperature expansion coefficient of the wafer, eliminating the influence of temperature changes on such packaging structures, and effectively enhancing the temperature stability of the surface acoustic wave filter. sex.
  • the present application is illustrated in detail by the following examples.
  • FIG. 1 is a schematic top-view structural diagram of a surface acoustic wave filter packaging structure in an embodiment of the present application.
  • the surface acoustic wave filter packaging structure 100 is a layered fan
  • the surface acoustic wave filter device of the out-type packaging structure includes a protective layer 111, a metal solder ball 112, a substrate and a plastic sealing structure 113 on the side of the piezoelectric thin film bonding body.
  • the packaging structure can be applied to the wafer-level packaging of the surface acoustic wave filter, so as to realize the protection of the working surface of the surface acoustic wave filter and the extraction of electrodes.
  • FIG. 2 is a schematic diagram 1 of a cross-sectional structure of the package structure of the surface acoustic wave filter shown in FIG. 1 along the section line AB.
  • the above-mentioned SAW filter package structure 100 includes a wafer, an electrode layer 110 , a sealing wall 106 , a plastic sealing structure 113 and a cover plate.
  • the above-mentioned wafer includes a substrate layer 101 and a piezoelectric thin film layer 102, and the substrate layer 101 and the piezoelectric thin film layer 102 are integrated by wafer bonding.
  • the wafer bonding method refers to the close bonding of two mirror-polished homogeneous or heterogeneous wafers through chemical and physical action. After the wafers are bonded, the atoms at the interface are subjected to external forces to react to form covalent bonds. The bond is integrated and the bonding interface reaches a specific bond strength. In this embodiment, the wafer bonding method is beneficial to realize low temperature drift and improve the power tolerance performance of the surface acoustic wave filter.
  • the substrate layer 101 may be made of silicon Si, glass, silicon carbide SiC, sapphire (Saphire) and other materials.
  • the piezoelectric thin film layer 102 may be a thin film material with piezoelectric properties, such as lithium tantalate LiTaO 3 , lithium niobate LiNbO 3 , aluminum nitride ALN, scandium Sc doped AlN, and the like.
  • the above-mentioned electrode layer 110 is disposed on the surface of the piezoelectric thin film layer 102 , and the electrode layer 110 may be an interdigitated electrode, which includes an extraction electrode 104 .
  • a thickened electrode 105 is provided above the lead-out electrode 104 .
  • the material used for the electrode layer 110 , the lead-out electrode 104 , and the thickened electrode 105 may be metal materials such as aluminum, copper, gold, and aluminum-copper.
  • the plastic encapsulation structure 113 covers the bottom surface of the substrate layer 101 and the side surfaces of the substrate layer 101 and the piezoelectric film layer 102 .
  • the top surface of the plastic encapsulation structure on the side of the piezoelectric thin film layer 102 is flush with or slightly higher than the top surface of the piezoelectric thin film layer 102 .
  • the bottom surface of the sealing wall 106 covers both the first surface 1131 of the plastic sealing structure 113 and a part of the top surface of the piezoelectric film layer 102 . That is, the sealing wall 106 can be disposed on the surface of the plastic sealing structure 113 and the surface of the piezoelectric film layer 102 at the same time, so that less chip area can be occupied and the width of the sealing wall can be increased.
  • the bottom surface of the sealing wall 106 at least partially covers the thickened electrode 105 .
  • the sealing wall 106 can be made of insulating materials such as polymer, SiO2, and SIN.
  • the above-mentioned cover plate may include a first material layer 108 and a second material layer 107 , wherein the first material layer 108 and the second material layer 107 are integrated by wafer bonding.
  • the material used in the first material layer 108 The material used for the substrate layer 101 is the same as that used for the substrate layer 101 , and the material used for the second material layer 107 is the same as the material used for the piezoelectric thin film layer 102 .
  • the sealing wall 106 surrounds and forms a sealing cavity 103 between the piezoelectric film layer 102 and the above-mentioned cover plate.
  • the sealing wall 106 has a first opening for exposing part or all of the thickened electrode 105 .
  • the cover plate has a second opening, which is arranged opposite to the first opening on the sealing wall 106, and is led out to the upper surface of the cover plate structure through the metal layer 109, and a metal wiring layer is arranged on the upper surface of the cover plate.
  • an adhesive layer or isolation layer (not shown in the figure) can be provided between the electrical connection through hole and the connection metal, or under the metal wiring layer, and the material of the adhesive layer or isolation layer can be selected from titanium Ti, tantalum Ta, tantalum nitride TAN, TIW and other materials.
  • a protective layer 111 is provided on the cover plate and the wiring metal layer for protection, and the material of the protective layer 111 may be insulating materials such as package green oil, resin, and solder resist material.
  • the above-mentioned conductive through holes can be filled with processes such as electroplating, or the conductive metal layer in the through holes can be protected by using a protective layer green oil.
  • the protective layer 111 is provided with a third opening, and the lead-out port of the wiring metal layer is led out through the metal solder ball 112 as an external communication port.
  • the thicknesses of the material layers of the surface acoustic wave filter shown in FIG. 2 are only schematic representations, and do not represent actual thicknesses.
  • the thickness of each material layer of the cover plate can be reasonably set according to the temperature linear expansion coefficient, so as to reduce the influence of temperature on the performance of the device.
  • a plastic sealing structure is provided on the bottom surface of the substrate layer and the side surfaces of the substrate layer and the piezoelectric film layer.
  • the bottom surface of the sealing wall simultaneously covers the plastic sealing structure.
  • the first surface and part of the top surface of the piezoelectric film layer can effectively increase the width of the sealing wall by means of the plastic sealing structure, so that a highly reliable sealing wall can be produced on the miniaturized chip, and the surface acoustic wave filtering can be improved.
  • the material used for the cover plate is the same as the material used for the wafer, that is, the temperature expansion coefficient of the cover plate can be equal to or very close to the temperature expansion coefficient of the wafer, which can prevent the temperature change when the temperature changes.
  • the temperature expansion coefficient of the cover plate and the temperature expansion coefficient of the wafer are greatly different, the sealed cavity is damaged, and the influence of temperature changes on such packaging structures is eliminated, so that the temperature stability of the surface acoustic wave filter can be effectively enhanced. .
  • FIG. 3 is a second schematic cross-sectional structure diagram of the package structure of the surface acoustic wave filter shown in FIG. 1 along the section line AB.
  • the above-mentioned cover plate may also include only one layer of material, that is, only the first material layer 108 , and the material used for the first material layer 108 is the same as the material used for the substrate layer 101 .
  • the piezoelectric thin film layer 102 since the piezoelectric thin film layer 102 is relatively thin, the contribution to the temperature expansion coefficient of the entire wafer is relatively small, therefore, only the same single-layer material as the substrate material can be used to make the cover plate. , so that the temperature expansion coefficient of the cover plate can be close to the temperature expansion coefficient of the wafer, so that when the temperature changes, the temperature expansion coefficient of the cover plate and the temperature expansion coefficient of the wafer are greatly different.
  • the wafer is deformed in different magnitudes, which damages the sealed cavity 103 and reduces the influence of temperature changes on the surface acoustic wave filter, thereby effectively enhancing the temperature stability of the surface acoustic wave filter.
  • FIG. 4 is a third schematic cross-sectional structure diagram of the package structure of the surface acoustic wave filter shown in FIG. 1 along the section line AB.
  • the above-mentioned cover plate may include three layers of materials at the same time, that is, including a first material layer 108 , a second material layer 107 and a third material layer 114 .
  • the material used for the first material layer 108 is the same as the material used for the substrate layer 101
  • the material used for the second material layer 107 is the same as the material used for the piezoelectric film layer 102
  • the third material layer 114 is in the first material layer 108 .
  • the third material layer 114 can be made of materials such as organic adhesives.
  • the thickness of the above-mentioned three-layer materials can be adjusted and combined flexibly to achieve a temperature expansion coefficient close to that of the bonded wafer.
  • the large difference between the thermal expansion coefficient and the thermal expansion coefficient of the wafer damages the sealed cavity, reduces the impact of temperature changes on such packaging structures, and can effectively enhance the temperature stability of the surface acoustic wave filter.
  • the substrate material and the first material layer 108 of the cover plate are materials with certain electrical conductivity such as silicon
  • the An insulating layer is provided between the metal wiring layer and the first material layer 108 of the cover plate, and the insulating layer can be selected from insulating materials such as SiO2 and SiN.
  • FIG. 5 is a schematic transverse cross-sectional view of a surface acoustic wave filter in an embodiment of the present application.
  • 113 is a plastic encapsulation structure
  • 106 is a sealing wall
  • 104 is an extraction electrode
  • 105 is a thickened electrode
  • 115 is a resonator
  • 116 is an exemplary wiring.
  • the resonator 115 and the wiring 116 in FIG. 5 are only an illustrative example, for the purpose of better understanding the embodiments of the present application, and do not represent an actual wiring manner such as wiring or connection.
  • FIG. 6 is a flowchart of the surface acoustic wave filter packaging method in the embodiments of the present application. Schematic diagram, the method includes:
  • a plurality of filter core particles are arranged on the piezoelectric film layer, and each core particle has an extraction electrode and a thickened electrode.
  • an electrode layer is prepared on the top surface of the piezoelectric thin film layer.
  • the bottom surface of the sealing wall covers both the first surface of the plastic sealing structure and part of the top surface of the piezoelectric film layer, and the first surface is at least part of the top surface of the plastic sealing structure on the side of the piezoelectric film layer .
  • the cover plate includes a first material layer and a second material layer, and the first material layer and the second material layer are integrated by wafer bonding; the second material layer is located on the cover plate close to the seal
  • the material used for the first material layer is the same as the material used for the substrate layer
  • the material used for the second material layer is the same as the material used for the piezoelectric thin film layer.
  • FIGS. 7 a to 7 h are schematic diagrams of the packaging process of the surface acoustic wave filter in the embodiments of the present application.
  • a wafer is obtained, the wafer includes a substrate layer 101, a piezoelectric film layer 102, and a plurality of filter core particles are arranged on the piezoelectric film layer 102, and each filter core particle has an extraction electrode 104 and a The electrode 105 is thickened.
  • a plastic encapsulation structure 113 is formed on the backside of the chip and adding a plastic encapsulation material through a process such as coating.
  • the above-mentioned temporary carrier is separated, and then a sealing wall 106 is formed on the first surface of the plastic sealing structure and part of the top surface of the piezoelectric film layer, wherein a first opening 702 is formed in the sealing wall,
  • the electrode 105 is thickened to expose the portion.
  • the cover plate includes a first material layer 108 and a second material layer 107.
  • the first material layer 108 adopts the same material as the substrate layer 101
  • the second material layer 107 adopts the same material.
  • the material is the same as that used for the piezoelectric thin film layer 102 .
  • the sealing wall 106 and the cover plate are sealed, so that the sealing wall 106 surrounds the piezoelectric film layer 102 and the cover plate to form a sealing cavity 103 .
  • the above-mentioned cover plate may further include a third material layer, the third material layer is located between the first material layer and the second material layer, and the first material layer and the second material layer utilize The third material layer is integrated as a whole, and the material used for the third material layer is an organic binder.
  • a second opening 703 (through hole or groove) is formed on the above-mentioned cover plate to expose the thickened electrode 105 .
  • a metal layer is arranged in the second opening of the cover plate, and the thickened electrode 105 is connected to the surface of the cover plate by a wiring process; a protective layer 111 is arranged on the surface of the cover plate to cover the second opening 703 and the metal wiring. wire, and a third opening 704 is formed to expose the metal wire lead-out port.
  • the electrodes are drawn out through the metal solder balls 112 in the third opening 703 .
  • the packaged filter device is obtained by dicing.
  • a plastic sealing structure is arranged on the bottom surface of the substrate layer and the side surfaces of the substrate layer and the piezoelectric film layer.
  • the first surface of the structure and part of the top surface of the piezoelectric film layer can effectively increase the width of the sealing wall, so that a highly reliable sealing wall can be fabricated on a miniaturized chip, and the performance of the surface acoustic wave filter can be improved.
  • the material used for the cover plate is the same as the material used for the wafer, that is, the temperature expansion coefficient of the cover plate can be equal to or very close to the temperature expansion coefficient of the wafer, thus preventing Due to the large difference between the thermal expansion coefficient of the cover plate and the thermal expansion coefficient of the wafer, the sealed cavity is damaged, and the influence of temperature changes on this type of packaging structure is eliminated, thereby effectively enhancing the temperature stability of the surface acoustic wave filter.

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Abstract

一种声表面波滤波器与封装方法，声表面波滤波器包括晶圆、电极层（110）、密封墙体（106）、塑封结构（113）及盖板；其中，晶圆包括以晶圆键合方式结合的衬底层（101）与压电薄膜层（102），电极层（110）设置于压电薄膜层（102）的顶面；塑封结构（113）包覆于衬底层（101）的底面以及衬底层（101）与压电薄膜层（102）的侧面，密封墙体（106）的底面同时覆盖于塑封结构（113）的第一表面（1131）与压电薄膜层（102）的部分顶面，从而能够有效增加密封墙体（106）的宽度，提升声表面波滤波器的可靠性；密封墙体（106）在压电薄膜层（102）与盖板之间包围形成密封空腔（103），盖板包括第一材料层（108）与第二材料层（107），采用的材料分别与衬底层（101）与压电薄膜层（102）采用的材料相同，从而能够缩小盖板与晶圆的温度膨胀系数差异，有效的增强声表面波滤波器的温度稳定性。

Description

声表面波滤波器与封装方法
本申请要求于2021年03月11日提交中国专利局、申请号为202110266848.9、申请名称为“声表面波滤波器与封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种声表面波滤波器与封装方法。
背景技术
声表面波滤波器具有工作频率高、通频带宽、选频特性好、体积小和重量轻等特点，并且可采用与集成电路相同的生产工艺，制造简单，成本低，频率特性的一致性好，因此广泛应用于各种电子设备中。
目前，伴随着载波聚合(Carrier Aggregation，简称CA)、大量的多输入多输出(Multiple Input Multiple Output，简称MIMO)天线技术以及高阶正交幅度调制(Quadrature Amplitude Modulation，简称QAM)等5G核心技术的应用，电子设备的射频前端元器件数量不仅大幅度的增加，而且对于滤波器元件的性能提出了越来越严格的技术要求，比如要求具有更好的温度稳定性，以及具有更小的封装尺寸，以便与射频前端中的功率放大器、射频开关等有源器件高度集成。因此，如何设计温度稳定性高、可靠性强的滤波器元件是亟待解决的问题。
发明内容
本申请实施例提供一种声表面波滤波器与封装方法，可以有效提升声表面波滤波器的温度稳定性与可靠性。
第一方面，本申请实施例提供了一种声表面波滤波器，该声表面波滤波器包括晶圆、电极层、密封墙体、塑封结构及盖板；
所述晶圆包括衬底层与压电薄膜层，所述衬底层的顶面与所述压电薄膜层的底面之间以晶圆键合方式结合为一体，所述电极层设置于所述压电薄膜层的顶面；
所述塑封结构包覆于所述衬底层的底面以及所述衬底层与所述压电薄膜层的侧面；
所述密封墙体的底面同时覆盖于所述塑封结构的第一表面与所述压电薄膜层的部分顶面，所述第一表面为所述压电薄膜层侧面的塑封结构的至少部分顶面，所述密封墙体在所述压电薄膜层与所述盖板之间包围形成密封空腔；
所述盖板包括第一材料层与第二材料层，所述第一材料层与所述第二材料层之间以晶圆键合方式结合为一体；所述第二材料层位于所述盖板靠近所述密封空腔的一侧，所述第一材料层采用的材料与所述衬底层采用的材料相同，所述第二材料层采用的材料与所述压电薄膜层采用的材料相同。
在一种可行的实施方式中，所述压电薄膜层侧面的塑封结构的顶面与所述压电薄膜层的顶面齐平。
在一种可行的实施方式中，所述塑封结构采用以下材料中的至少一种材料制成：聚合物、树脂、塑封膜。
在一种可行的实施方式中，所述电极层包括引出电极，所述引出电极的表面设置有加厚电极，所述密封墙体的底面覆盖于所述加厚电极。
在一种可行的实施方式中，所述盖板还包括第三材料层，所述第三材料层位于所述第一材料层与所述第二材料层之间，且所述第一材料层与所述第二材料层之间利用所述第三材料层结合为一体，所述第三材料层采用的材料为有机粘结剂。
在一种可行的实施方式中，所述压电薄膜层采用以下材料中的至少一种材料制成：钽酸锂LiTaO 3、铌酸锂LiNbO 3、氮化铝ALN、钪Sc掺杂的AlN，所述衬底层采用以下材料中的至少一种材料制成：硅Si、蓝宝石、玻璃、碳化硅SiC。
第二方面，本申请实施例提供了一种声表面波滤波器封装方法，该方法包括：
获取晶圆，所述晶圆包括衬底层与压电薄膜层，所述衬底层的顶面与所述压电薄膜层的底面之间以晶圆键合方式结合为一体；
在所述压电薄膜层的顶面上制备电极层；
制备塑封结构，所述塑封结构包覆于所述衬底层的底面以及所述衬底 层与所述压电薄膜层的侧面；
制备密封墙体，所述密封墙体的底面同时覆盖于所述塑封结构的第一表面与所述压电薄膜层的部分顶面，所述第一表面为所述压电薄膜层侧面的塑封结构的至少部分顶面；
获取盖板，所述盖板包括第一材料层与第二材料层，所述第一材料层与所述第二材料层之间以晶圆键合方式结合为一体；所述第二材料层位于所述盖板靠近所述密封空腔的一侧，所述第一材料层采用的材料与所述衬底层采用的材料相同，所述第二材料层采用的材料与所述压电薄膜层采用的材料相同；
将所述密封墙体与所述盖板进行密封，使所述密封墙体在所述压电薄膜层与所述盖板之间包围形成密封空腔。
在一种可行的实施方式中，所述压电薄膜层侧面的塑封结构的顶面与所述压电薄膜层的顶面齐平。
在一种可行的实施方式中，所述电极层包括引出电极，在所述压电薄膜层的顶面上制备电极层之后，还包括：
在所述引出电极的表面设置加厚电极；
所述制备密封墙体包括：
在所述塑封结构的第一表面与所述压电薄膜层的部分顶面上制备所述密封墙体，所述密封墙体的底面覆盖于所述加厚电极。
在一种可行的实施方式中，所述盖板还包括第三材料层，所述第三材料层位于所述第一材料层与所述第二材料层之间，且所述第一材料层与所述第二材料层之间利用所述第三材料层结合为一体，所述第三材料层采用的材料为有机粘结剂。
本申请实施例提供的声表面波滤波器与封装方法，在衬底层的底面以及衬底层与压电薄膜层的侧面设置有塑封结构，在设置密封墙体时，密封墙体的底面同时覆盖于塑封结构的第一表面与压电薄膜层的部分顶面，由此能够有效增加密封墙体的宽度，从而可以在小型化芯片上制作出可靠性强的密封墙体，提升声表面波滤波器的可靠性；同时，上述盖板所采用的材料与晶圆所采用的材料相同，即盖板的温度膨胀系数能够等于或者非常接近于晶圆的温度膨胀系数，由此即可防止当温度变化时，因盖板的温度 膨胀系数与晶圆的温度膨胀系数差距较大而损坏密封空腔，消除温度变化对此类封装结构的影响，从而能够有效的增强声表面波滤波器的温度稳定性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对本申请实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例中一种声表面波滤波器封装结构的俯视结构示意图；
图2为图1中所示声表面波滤波器封装结构沿剖面线AB的剖面结构示意图一；
图3为图1中所示声表面波滤波器封装结构沿剖面线AB的剖面结构示意图二；
图4为图1中所示声表面波滤波器封装结构沿剖面线AB的剖面结构示意图三；
图5为本申请实施例中一种声表面波滤波器的横向剖面示意图；
图6为本申请实施例中声表面波滤波器封装方法的流程示意图；
图7a至图7h为本申请实施例中声表面波滤波器封装过程示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
声表面波滤波器由于具有工作频率高、通频带宽、选频特性好、体积小和重量轻等特点，已成为移动电话射频(RF)前端应用中不可或缺的关键元器件。伴随着载波聚合、MIMO天线技术以及QAM等5G核心技术 的应用，电子设备的射频前端元器件数量不仅大幅度的增加，而且对于滤波器元件的性能提出了越来越严格的技术要求，比如要求具有更高的可靠性与温度稳定性，以及具有更小的封装尺寸，以便与射频前端中的功率放大器、射频开关等有源器件高度集成。然而，随着目前芯片小型化需求越来越高，密封墙体无法过多的占用芯片面积，而芯片微型化之后如果密封墙体的宽度较小，则有可能导致密封空腔的可靠性变差；同时，由于压电材料温度系数较大，因此声表面波滤波器的性能很容易受温度的影响，温度稳定性不高。
为了解决上述技术问题，本申请实施例提供一种声表面波滤波器，在衬底层的底面以及衬底层与压电薄膜层的侧面设置有塑封结构，在设置密封墙体时，密封墙体的底面同时覆盖于塑封结构的第一表面与压电薄膜层的部分顶面，由此能够有效增加密封墙体的宽度，从而可以在小型化芯片上制作出可靠性强的密封墙体，提升声表面波滤波器的可靠性；同时，盖板所采用的材料与晶圆所采用的材料相同，即盖板的温度膨胀系数能够等于或者非常接近于晶圆的温度膨胀系数，由此即可防止当温度变化时，因盖板的温度膨胀系数与晶圆的温度膨胀系数差距较大而损坏密封空腔，消除温度变化对此类封装结构的影响，有效的增强声表面波滤波器的温度稳定性。本申请通过以下实施例进行详细说明。
参照图1，图1为本申请实施例中一种声表面波滤波器封装结构的俯视结构示意图，在一种可行的实施方式中，该声表面波滤波器封装结构100为一种层状扇出型封装结构的声表面波滤波器器件，包括保护层111、金属焊球112，衬底和压电薄膜键合体侧面的塑封结构113。该封装结构可应用于声表面波滤波器晶圆级的封装，实现对声表面波滤波器工作面的保护以及电极的引出。
参照图2，图2为图1中所示声表面波滤波器封装结构沿剖面线AB的剖面结构示意图一。
在图2中，上述声表面波滤波器封装结构100包括晶圆、电极层110、密封墙体106、塑封结构113及盖板。
其中，上述晶圆包括衬底层101与压电薄膜层102，衬底层101与压电薄膜层102之间以晶圆键合方式结合为一体。
其中，晶圆键合方式是指通过化学和物理作用将两块已镜面抛光的同质或异质的晶片紧密地结合起来，晶片接合后，界面的原子受到外力的作用而产生反应形成共价键结合成一体，并使接合界面达到特定的键合强度。本实施例中，采用晶圆健合方式有利于实现低温漂和提升声表面波滤波器的功率耐受性能。
可选的，衬底层101可以采用硅Si、玻璃、碳化硅SiC、蓝宝石(Saphire)等材料。压电薄膜层102可以采用钽酸锂LiTaO 3、铌酸锂LiNbO 3、氮化铝ALN、钪Sc掺杂的AlN等具有压电性能的薄膜材料。
上述电极层110设置于压电薄膜层102的表面，该电极层110可以为叉指电极，其包括引出电极104。引出电极104的上方设置有加厚电极105。
可选的，电极层110、引出电极104、加厚电极105采用的材料可以为铝、铜、金以及铝铜等金属材料。
塑封结构113包覆在衬底层101的底面以及衬底层101与压电薄膜层102的侧面。其中，压电薄膜层102侧面的塑封结构的顶面与压电薄膜层102的顶面齐平或略高。
密封墙体106的底面同时覆盖于塑封结构113的第一表面1131与压电薄膜层102的部分顶面，上述第一表面1131为压电薄膜层102侧面的塑封结构的至少部分顶面。即密封墙体106可以同时设置于塑封结构113的表面与压电薄膜层102的表面上，从而可以既可以占用较少芯片面积，又可以增加密封墙体的宽度。
可选的，密封墙体106的底面至少部分覆盖加厚电极105。
可选的，密封墙体106可以采用聚合物、SiO2，SIN等绝缘介质材料。
上述盖板可以包括第一层材料108与第二材料层107，其中，第一层材料108与第二材料层107之间以晶圆键合方式结合为一体，第一材料层108采用的材料与衬底层101采用的材料相同，第二材料层107采用的材料与压电薄膜层102采用的材料相同。
密封墙体106在压电薄膜层102与上述盖板之间包围形成密封空腔103。其中，密封墙体106上具有第一开口，用于将加厚电极105的部分或全部露出。
盖板上具有第二开口，与密封墙体106上的第一开口相对设置，并且通 过金属层109引出到盖板结构的上表面，并在盖板上表面设置有金属走线层。
可选的，可以在电连接通孔与连接金属之间，或金属走线层下方设置粘接层或隔离层(图中未示出)，粘接层或隔离层材料可选钛Ti、钽Ta，氮化钽TAN，TIW等材料。
可选的，盖板和走线金属层上有保护层111进行保护，保护层111的材料可以为封装绿油、树脂、防焊材料等绝缘材料。上述导电通孔内可以使用电镀等工艺将通孔填满，也可以使用保护层绿油将通孔内的导电金属层做保护。
保护层111上设置有第三开口，将走线金属层的引出端口通过金属焊球112引出，作为对外通讯端口。
需要说明的是，图2中所示声表面波滤波器的各材料层的厚度仅仅只是示意，并不代表实际厚度。在本申请实施例中，盖板各材料层的厚度可以根据温度线膨胀系数合理设置，以减小温度对器件性能的影响。
本申请实施例所提供的声表面波滤波器，在衬底层的底面以及衬底层与压电薄膜层的侧面设置有塑封结构，在设置密封墙体时，密封墙体的底面同时覆盖于塑封结构的第一表面与压电薄膜层的部分顶面，由此能够借助塑封结构有效增加密封墙体的宽度，从而可以在小型化芯片上制作出可靠性强的密封墙体，提升声表面波滤波器的可靠性；同时，盖板所采用的材料与晶圆所采用的材料相同，即盖板的温度膨胀系数能够等于或者非常接近于晶圆的温度膨胀系数，由此即可防止当温度变化时，因盖板的温度膨胀系数与晶圆的温度膨胀系数差距较大而损坏密封空腔，消除温度变化对此类封装结构的影响，从而能够有效的增强声表面波滤波器的温度稳定性。
基于上述实施例中所描述的内容，参照图3，图3为图1中所示声表面波滤波器封装结构沿剖面线AB的剖面结构示意图二。
在另一种可行的实施方式中，上述盖板也可以只包括一层材料，即只包括第一材料层108，该第一材料层108采用的材料与衬底层101采用的材料相同。
可以理解的是，本申请实施例中，由于压电薄膜层102比较薄，对于整个晶圆的温度膨胀系数贡献比较小，因此，可以仅采用与衬底材料相同 的单层材料来制作盖板，使盖板的温度膨胀系数能够接近于晶圆的温度膨胀系数，由此即可防止当温度变化时，因盖板的温度膨胀系数与晶圆的温度膨胀系数差距较大而导致盖板与晶圆产生不同幅度的形变，损坏密封空腔103，降低温度变化对声表面波滤波器的影响，从而能够有效增强声表面波滤波器的温度稳定性。
基于上述实施例中所描述的内容，参照图4，图4为图1中所示声表面波滤波器封装结构沿剖面线AB的剖面结构示意图三。
在另一种可行的实施方式中，上述盖板可以同时包括三层材料，即包括第一材料层108、第二材料层107以及第三材料层114。其中，该第一材料层108采用的材料与衬底层101采用的材料相同，第二材料层107采用的材料与压电薄膜层102采用的材料相同，第三材料层114在第一材料层108和第二材料层107中间，做为粘接层、键合层或媒介层中任意一种，例如，第三材料层114可以采用有机粘合剂等材料。
在本申请实施例中，上述三层材料的厚度通过灵活的调节和组合，也可以达到与键合的晶圆具有接近的温度膨胀系数，由此同样可以防止当温度变化时，因盖板的温度膨胀系数与晶圆的温度膨胀系数差距较大而损坏密封空腔，降低温度变化对此类封装结构的影响，从而能够有效增强声表面波滤波器的温度稳定性。
基于上述实施例中所描述的内容，在另一种可行的实施方式中，当衬底材料和盖板的第一材料层108为硅等具有一定导电性能的材料时，可选的，可以在金属布线层与盖板第一材料层108之间设置绝缘层，该绝缘层的可选择SiO2，SiN等绝缘材料。
基于上述实施例中所描述的内容，为了更好的理解本申请，参照图5，图5为本申请实施例中一种声表面波滤波器的横向剖面示意图。
在图5中，113为塑封结构，106为密封墙体，104为引出电极，105为加厚电极，115为谐振器，116为示例性走线。
可以理解的是，图5中的谐振器115和走线116仅为一种说明性示例，目的是为了更好的理解本申请实施例，并不代表实际的走线或者连接等布线方式。
进一步的，基于上述实施例中所描述的内容，本申请实施例还提供一 种声表面波滤波器封装方法，参照图6，图6为本申请实施例中声表面波滤波器封装方法的流程示意图，该方法包括：
S601、获取晶圆，该晶圆包括衬底层与压电薄膜层，衬底层的顶面与压电薄膜层的底面之间以晶圆键合方式结合为一体。
可选的，压电薄膜层上设置有多个滤波器芯粒，每个芯粒具有引出电极和加厚电极。
S602、在压电薄膜层的顶面上制备电极层。
S603、制备塑封结构，该塑封结构包覆于衬底层的底面以及衬底层与压电薄膜层的侧面。
S604、制备密封墙体，该密封墙体的底面同时覆盖于塑封结构的第一表面与压电薄膜层的部分顶面，该第一表面为压电薄膜层侧面的塑封结构的至少部分顶面。
S605、获取盖板，该盖板包括第一材料层与第二材料层，第一材料层与第二材料层之间以晶圆键合方式结合为一体；第二材料层位于盖板靠近密封空腔的一侧，第一材料层采用的材料与衬底层采用的材料相同，第二材料层采用的材料与压电薄膜层采用的材料相同。
S606、将密封墙体与盖板进行密封，使密封墙体在压电薄膜层与盖板之间包围形成密封空腔。
为了更好的理解本申请实施例，参照图7a至图7h，图7a至图7h为本申请实施例中声表面波滤波器封装过程示意图。
如图7a所示，获取晶圆，该晶圆包括衬底层101、压电薄膜层102，压电膜层102上设置有多个滤波器芯粒，每个滤波器芯粒具有引出电极104和加厚电极105。
如图7b所示，切割晶圆得到的单个滤波器芯片，通过拾取贴合工艺将单个滤波器芯片的加厚电极105表面与临时载片701的表面接合。
如图7c所示，通过涂覆等工艺在芯片背面以及添加塑封材料，形成塑封结构113。
如图7d所示，将上述临时载片分离，然后在塑封结构的第一表面与压电薄膜层的部分顶面上制作密封墙体106，其中，在密封墙体中形成第一开口702，以露出部分加厚电极105。
如图7e所示，获取盖板，该盖板包含第一材料层108与第二材料层107，第一材料层108采用的材料与衬底层101采用的材料相同，第二材料层107采用的材料与压电薄膜层102采用的材料相同。
将密封墙体106与盖板进行密封，使密封墙体106在压电薄膜层102与盖板之间包围形成密封空腔103。
在另一种实施方式中，上述盖板还可以包括第三材料层，该第三材料层位于第一材料层与第二材料层之间，且第一材料层与第二材料层之间利用第三材料层结合为一体，第三材料层采用的材料为有机粘结剂。
如图7f所示，在上述盖板上形成第二开口703(通孔或槽)，露出加厚电极105。
如图7g所示，在盖板的第二开口内设置金属层，并在盖板表面再走线工艺连接加厚电极105；盖板表面设置保护层111，盖住第二开口703与金属走线，并形成第三开口704，露出金属走线引出端口。
如图7h所示，在上述第三开口703通过金属焊球112引出电极。通过划片切割得到封装好的滤波器器件。
本申请实施例提供的声表面波滤波器封装方法，在衬底层的底面以及衬底层与压电薄膜层的侧面设置塑封结构，在设置密封墙体时，将密封墙体的底面同时覆盖于塑封结构的第一表面与压电薄膜层的部分顶面，由此能够有效增加密封墙体的宽度，从而可以在小型化芯片上制作出可靠性强的密封墙体，提升声表面波滤波器的可靠性；同时，盖板所采用的材料与晶圆所采用的材料相同，即盖板的温度膨胀系数能够等于或者非常接近于晶圆的温度膨胀系数，由此即可防止当温度变化时，因盖板的温度膨胀系数与晶圆的温度膨胀系数差距较大而损坏密封空腔，消除温度变化对此类封装结构的影响，从而能够有效的增强声表面波滤波器的温度稳定性。
以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种声表面波滤波器，其特征在于，所述声表面波滤波器包括晶圆、电极层、密封墙体、塑封结构及盖板；
    所述晶圆包括衬底层与压电薄膜层，所述衬底层的顶面与所述压电薄膜层的底面之间以晶圆键合方式结合为一体，所述电极层设置于所述压电薄膜层的顶面；
    所述塑封结构包覆于所述衬底层的底面以及所述衬底层与所述压电薄膜层的侧面；
    所述密封墙体的底面同时覆盖于所述塑封结构的第一表面与所述压电薄膜层的部分顶面，所述第一表面为所述压电薄膜层侧面的塑封结构的至少部分顶面，所述密封墙体在所述压电薄膜层与所述盖板之间包围形成密封空腔；
    所述盖板包括第一材料层与第二材料层，所述第一材料层与所述第二材料层之间以晶圆键合方式结合为一体；所述第二材料层位于所述盖板靠近所述密封空腔的一侧，所述第一材料层采用的材料与所述衬底层采用的材料相同，所述第二材料层采用的材料与所述压电薄膜层采用的材料相同。
  2. 根据权利要求1所述的声表面波滤波器，其特征在于，所述压电薄膜层侧面的塑封结构的顶面与所述压电薄膜层的顶面齐平。
  3. 根据权利要求1所述的声表面波滤波器，其特征在于，所述塑封结构采用以下材料中的至少一种材料制成：聚合物、树脂、塑封膜。
  4. 根据权利要求1所述的声表面波滤波器，其特征在于，所述电极层包括引出电极，所述引出电极的表面设置有加厚电极，所述密封墙体的底面覆盖于所述加厚电极。
  5. 根据权利要求1所述的声表面波滤波器，其特征在于，所述盖板还包括第三材料层，所述第三材料层位于所述第一材料层与所述第二材料层之间，且所述第一材料层与所述第二材料层之间利用所述第三材料层结合为一体，所述第三材料层采用的材料为有机粘结剂。
  6. 根据权利要求1至5任一项所述的声表面波滤波器，其特征在于，所述压电薄膜层采用以下材料中的至少一种材料制成：钽酸锂LiTaO 3、铌酸锂LiNbO 3、氮化铝ALN、钪Sc掺杂的AlN，所述衬底层采用以下材料 中的至少一种材料制成：硅Si、蓝宝石、玻璃、碳化硅SiC。
  7. 一种声表面波滤波器封装方法，其特征在于，所述方法包括：
    获取晶圆，所述晶圆包括衬底层与压电薄膜层，所述衬底层的顶面与所述压电薄膜层的底面之间以晶圆键合方式结合为一体；
    在所述压电薄膜层的顶面上制备电极层；
    制备塑封结构，所述塑封结构包覆于所述衬底层的底面以及所述衬底层与所述压电薄膜层的侧面；
    制备密封墙体，所述密封墙体的底面同时覆盖于所述塑封结构的第一表面与所述压电薄膜层的部分顶面，所述第一表面为所述压电薄膜层侧面的塑封结构的至少部分顶面；
    获取盖板，所述盖板包括第一材料层与第二材料层，所述第一材料层与所述第二材料层之间以晶圆键合方式结合为一体；所述第二材料层位于所述盖板靠近所述密封空腔的一侧，所述第一材料层采用的材料与所述衬底层采用的材料相同，所述第二材料层采用的材料与所述压电薄膜层采用的材料相同；
    将所述密封墙体与所述盖板进行密封，使所述密封墙体在所述压电薄膜层与所述盖板之间包围形成密封空腔。
  8. 根据权利要求7所述的方法，其特征在于，所述压电薄膜层侧面的塑封结构的顶面与所述压电薄膜层的顶面齐平。
  9. 根据权利要求7所述的方法，其特征在于，所述电极层包括引出电极，在所述压电薄膜层的顶面上制备电极层之后，还包括：
    在所述引出电极的表面设置加厚电极；
    所述制备密封墙体包括：
    在所述塑封结构的第一表面与所述压电薄膜层的部分顶面上制备所述密封墙体，所述密封墙体的底面覆盖于所述加厚电极。
  10. 根据权利要求7所述的方法，其特征在于，所述盖板还包括第三材料层，所述第三材料层位于所述第一材料层与所述第二材料层之间，且所述第一材料层与所述第二材料层之间利用所述第三材料层结合为一体，所述第三材料层采用的材料为有机粘结剂。
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