WO2022188019A1 - 移位寄存器、驱动电路和显示基板 - Google Patents

移位寄存器、驱动电路和显示基板 Download PDF

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Publication number
WO2022188019A1
WO2022188019A1 PCT/CN2021/079682 CN2021079682W WO2022188019A1 WO 2022188019 A1 WO2022188019 A1 WO 2022188019A1 CN 2021079682 W CN2021079682 W CN 2021079682W WO 2022188019 A1 WO2022188019 A1 WO 2022188019A1
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Prior art keywords
transistor
coupled
node
electrode
control
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PCT/CN2021/079682
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English (en)
French (fr)
Inventor
肖云升
青海刚
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/079682 priority Critical patent/WO2022188019A1/zh
Priority to US17/763,758 priority patent/US11967278B2/en
Priority to CN202180000441.XA priority patent/CN115398520A/zh
Priority to EP21929501.1A priority patent/EP4120229A4/en
Publication of WO2022188019A1 publication Critical patent/WO2022188019A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display, and in particular, to a shift register, a driving circuit and a display substrate.
  • a light-emitting control sub-circuit is set in the pixel circuit included in the pixel unit; the light-emitting control sub-circuit is generally set between the driving transistor and the light-emitting device. , to control the on-off between the driving transistor and the light-emitting device; wherein, the working state of the light-emitting control sub-circuit is controlled by the light-emitting control signal provided by the light-emitting control signal line, and the light-emitting control signal in the light-emitting control signal line is substantially located in the display A driving signal provided by a gate driving circuit in the peripheral area of the substrate.
  • the present disclosure proposes a shift register, a driving circuit and a display substrate.
  • an embodiment of the present disclosure provides a shift register, including:
  • control electrode of the first transistor is coupled to the first clock signal line to receive the first clock signal, the first electrode of the first transistor is coupled to the signal input terminal, the first electrode of the first transistor is The diode is coupled to the first node;
  • a second transistor the control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the first node a clock signal line coupled to receive the first clock signal;
  • control electrode of the third transistor is coupled to the first clock signal line to receive the first clock signal, the first electrode of the third transistor is coupled to the first power terminal, the The second pole of the third transistor is coupled to the second node;
  • control electrode of the fourth transistor is coupled to the second clock signal line to receive the second clock signal
  • first electrode of the fourth transistor is coupled to the second electrode of the fifth transistor
  • the second pole of the four transistors is coupled to the first node
  • control electrode of the fifth transistor is coupled to the third node, and the first electrode of the fifth transistor is coupled to the second power terminal;
  • the first pole of the first capacitor is coupled to the fourth node, the second pole of the first capacitor is coupled to the second clock signal line, and the first node is coupled to the fourth node catch;
  • control electrode of the impedance transistor is coupled to the first power supply terminal, the first electrode of the impedance transistor is coupled to the second node, the second electrode of the impedance transistor is coupled to the third node node coupling;
  • a first output control circuit coupled to the third node, the fourth node and the first signal output terminal, is configured to respond to the control of the signals at the third node and the fourth node to any The first signal output terminal outputs a first driving signal.
  • the shift register further includes:
  • a second output control circuit coupled to at least the first signal output terminal and the second signal output terminal, is configured to output to the second signal output terminal according to the first driving signal output from the first signal output terminal a second drive signal having an opposite phase to the first drive signal.
  • the first output control circuit includes:
  • the control electrode of the ninth transistor is coupled to the fifth node, the first electrode of the ninth transistor is coupled to the second power supply end, and the second electrode of the ninth transistor is coupled to the first The signal output terminal is coupled
  • a third capacitor, a first pole of the third capacitor is coupled to the fifth node, and a second pole of the third capacitor is coupled to the second power terminal.
  • the first output control circuit further includes:
  • control electrode of the sixth transistor is coupled to the third node
  • first electrode of the sixth transistor is coupled to the second clock signal line to receive the second clock signal, so the second pole of the sixth transistor is coupled to the sixth node
  • control electrode of the seventh transistor is coupled to the second clock signal line to receive the second clock signal, the first electrode of the seventh transistor is coupled to the sixth node, so the second pole of the seventh transistor is coupled to the fifth node;
  • control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the fifth node, and the second electrode of the eighth transistor is coupled to the the second power terminal is coupled;
  • a tenth transistor the control electrode of the tenth transistor is coupled to the fourth node, the first electrode of the tenth transistor is coupled to the first signal output end, and the second electrode of the tenth transistor is coupled to the the first power terminal is coupled, and the first node is coupled to the fourth node;
  • a second capacitor, a first pole of the second capacitor is coupled to the third node, and a second pole of the second capacitor is coupled to the sixth node.
  • the second output control circuit includes:
  • An eleventh transistor a control electrode of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the first power supply terminal, and a control electrode of the eleventh transistor is coupled to the fifth node.
  • the second pole is coupled to the seventh node;
  • a twelfth transistor the control electrode of the twelfth transistor is coupled to the first signal output terminal, the first electrode of the twelfth transistor is coupled to the seventh node, the twelfth transistor The second pole of is coupled to the second power terminal;
  • a thirteenth transistor the control electrode of the thirteenth transistor is coupled to the seventh node, the first electrode of the thirteenth transistor is coupled to the first clock signal line, the thirteenth transistor The second pole of is coupled to the first pole of the fourth capacitor;
  • the second pole of the fourth capacitor is coupled to the seventh node
  • a fourteenth transistor the control electrode of the fourteenth transistor is coupled to the seventh node, the first electrode of the fourteenth transistor is coupled to the first power supply terminal, and the fourteenth transistor is the second pole is coupled to the second signal output terminal;
  • a fifteenth transistor the control electrode of the fifteenth transistor is coupled to the first signal output end, the first electrode of the fifteenth transistor is coupled to the second signal output end, the tenth transistor The second pole of the five transistors is coupled to the second power supply terminal.
  • the second output control circuit includes:
  • An eleventh transistor a control electrode of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the first power supply terminal, and a control electrode of the eleventh transistor is coupled to the fifth node.
  • the second pole is coupled to the seventh node;
  • a twelfth transistor the control electrode of the twelfth transistor is coupled to the first signal output terminal, the first electrode of the twelfth transistor is coupled to the seventh node, the twelfth transistor The second pole of is coupled to the second power terminal;
  • a thirteenth transistor the control electrode of the thirteenth transistor is coupled to the seventh node, the first electrode of the thirteenth transistor is coupled to the second clock signal line, the thirteenth transistor The second pole of is coupled to the first pole of the fourth capacitor;
  • the second pole of the fourth capacitor is coupled to the seventh node
  • a fourteenth transistor the control electrode of the fourteenth transistor is coupled to the seventh node, the first electrode of the fourteenth transistor is coupled to the first power supply terminal, and the fourteenth transistor is the second pole is coupled to the second signal output terminal;
  • a fifteenth transistor the control electrode of the fifteenth transistor is coupled to the first signal output end, the first electrode of the fifteenth transistor is coupled to the second signal output end, the tenth transistor The second pole of the five transistors is coupled to the second power supply terminal.
  • the second output control circuit includes:
  • An eleventh transistor a control electrode of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the first power supply terminal, and a control electrode of the eleventh transistor is coupled to the fifth node.
  • the second pole is coupled to the seventh node;
  • a twelfth transistor the control electrode of the twelfth transistor is coupled to the first signal output terminal, the first electrode of the twelfth transistor is coupled to the seventh node, the twelfth transistor The second pole of is coupled to the second power terminal;
  • the first pole of the fourth capacitor is coupled to the first clock signal line or the second clock signal line, and the second pole of the fourth capacitor is coupled to the seventh node;
  • a fourteenth transistor the control electrode of the fourteenth transistor is coupled to the seventh node, the first electrode of the fourteenth transistor is coupled to the first power supply terminal, and the fourteenth transistor is the second pole is coupled to the second signal output terminal;
  • a fifteenth transistor the control electrode of the fifteenth transistor is coupled to the first signal output end, the first electrode of the fifteenth transistor is coupled to the second signal output end, the tenth transistor The second pole of the five transistors is coupled to the second power supply terminal.
  • the second output control circuit includes:
  • An eleventh transistor a control electrode of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the first power supply terminal, and a control electrode of the eleventh transistor is coupled to the fifth node.
  • the second pole is coupled to the seventh node;
  • a twelfth transistor the control electrode of the twelfth transistor is coupled to the first signal output terminal, the first electrode of the twelfth transistor is coupled to the seventh node, the twelfth transistor The second pole of is coupled to the second power terminal;
  • the first pole of the fourth capacitor is coupled to the second clock signal line, and the second pole of the fourth capacitor is coupled to the seventh node;
  • a fourteenth transistor the control electrode of the fourteenth transistor is coupled to the seventh node, the first electrode of the fourteenth transistor is coupled to the first power supply terminal, and the fourteenth transistor is the second pole is coupled to the second signal output terminal;
  • a fifteenth transistor the control electrode of the fifteenth transistor is coupled to the first signal output end, the first electrode of the fifteenth transistor is coupled to the second signal output end, the tenth transistor The second pole of the five transistors is coupled to the second power supply terminal.
  • the shift register further includes:
  • the first node is coupled to the fourth node through the voltage limiting transistor
  • the control electrode of the voltage-limiting transistor is coupled to the first power supply terminal, the first electrode of the voltage-limiting transistor is coupled to the first node, and the second electrode of the voltage-limiting transistor is coupled to the fourth Node coupling.
  • an embodiment of the present disclosure further provides a driving circuit, including: a plurality of shift registers arranged in cascade, and the shift register adopts the shift register provided in the first aspect;
  • the signal input terminal of the shift register in the first stage is coupled to the frame start signal terminal;
  • the signal input terminals of the shift registers at other stages are coupled to the first signal output terminal of the shift register at the previous stage.
  • an embodiment of the present disclosure further provides a display substrate, comprising a display area and a peripheral area surrounding the display area, a plurality of pixel units are arranged in the display area, and each pixel unit is configured with a corresponding light-emitting unit A control signal line, a light-emitting control driving circuit is provided in the peripheral area, and the light-emitting control driving circuit adopts the driving circuit in the above second aspect, and the first light-emitting control driving circuit of the shift registers of each stage in the light-emitting control driving circuit The signal output end is coupled to the corresponding light-emitting control signal line in the display area.
  • each pixel unit is further configured with a corresponding reset signal line
  • a second output control circuit is arranged in the shift register in the light emission control driving circuit, and the second signal output end of the shift register in the light emission control driving circuit is the same as the corresponding signal in the display area. Set the signal line to be coupled.
  • the pixel unit includes: a pixel circuit and a light-emitting device, the pixel circuit includes: a first reset sub-circuit, a second reset sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a light-emitting device Control sub-circuits and drive transistors;
  • the first reset sub-circuit is coupled to the initialization voltage terminal, the control electrode of the driving transistor, and the corresponding scan control signal line, and is configured to reset the initialization in response to the control of the scan control signal provided by the scan control signal line
  • the initialization voltage provided by the voltage terminal is written into the control electrode of the driving transistor
  • the second reset sub-circuit is coupled to the initialization voltage terminal, the first terminal of the light-emitting device, and the corresponding reset signal line, and is configured to reset the reset signal line in response to the control of the reset signal line. writing the initialization voltage to the first end of the light-emitting device;
  • the data writing sub-circuit is coupled to the first electrode of the driving transistor, the corresponding data line, and the corresponding scanning signal line, and is configured to respond to the control of the scanning signal line to write the data provided by the data line voltage is written to the first pole of the drive transistor;
  • the threshold compensation sub-circuit is coupled to the second working voltage terminal, the control electrode of the driving transistor, the first electrode of the driving transistor, the second electrode of the driving transistor, and the corresponding scanning signal line. connected, configured to write a data compensation voltage to the control electrode of the driving transistor in response to the control of the scan signal line, the data compensation voltage being equal to the sum of the data voltage and the threshold voltage of the driving transistor;
  • a light-emitting control sub-circuit located between the second pole of the driving transistor and the first end of the light-emitting device, and coupled to the light-emitting control signal line, is configured to respond to the light-emitting control signal provided by the light-emitting control signal line is controlled to make conduction between the second electrode of the driving transistor and the first end of the light emitting device;
  • the driving transistor is configured to output a corresponding driving current in response to the control of the data compensation voltage
  • the second end of the light emitting device is coupled to the first working voltage end.
  • the first reset sub-circuit includes a twenty-first transistor
  • the second reset sub-circuit includes a twenty-second transistor
  • the data writing sub-circuit includes a twenty-third transistor
  • the threshold compensation sub-circuit includes a twenty-fourth transistor, a twenty-fifth transistor and a storage capacitor
  • the light-emitting control sub-circuit includes a twenty-sixth transistor
  • the control electrode of the twenty-first transistor is coupled to the scan control signal line, the first electrode of the twenty-first transistor is coupled to the initialization voltage terminal, and the second electrode of the twenty-first transistor is coupled to the initializing voltage terminal.
  • the pole is coupled to the control pole of the driving transistor;
  • the control electrode of the twenty-second transistor is coupled to the reset signal line, the first electrode of the twenty-second transistor is coupled to the initialization voltage terminal, and the second electrode of the twenty-second transistor is coupled to the initializing voltage terminal.
  • the pole is coupled to the first end of the light emitting device;
  • the control electrode of the twenty-third transistor is coupled to the scan signal line, the first electrode of the twenty-third transistor is coupled to the data line, and the second electrode of the twenty-third transistor is coupled to the data line.
  • the first pole of the driving transistor is coupled;
  • the control electrode of the twenty-fourth transistor is coupled to the light-emitting control signal line, the first electrode of the twenty-fourth transistor is coupled to the second operating voltage terminal, and the The second electrode is coupled to the first electrode of the driving transistor;
  • the control electrode of the twenty-fifth transistor is coupled to the scan signal line, the first electrode of the twenty-fifth transistor is coupled to the control electrode of the driving transistor, and the first electrode of the twenty-fifth transistor is coupled to the control electrode of the driving transistor.
  • a diode is coupled to the second electrode of the driving transistor;
  • the first end of the storage capacitor is coupled to the second working voltage end, and the second end of the storage capacitor is coupled to the control electrode of the driving transistor;
  • the control electrode of the twenty-sixth transistor is coupled to the light-emitting control signal line
  • the first electrode of the twenty-sixth transistor is coupled to the second electrode of the driving transistor
  • the twenty-sixth transistor The second pole of the light emitting device is coupled to the first end of the light emitting device.
  • the scan control signal line to which the pixel unit is coupled is the scan control signal line configured for the pixel unit of the previous row. signal line.
  • each pixel unit is configured with a corresponding scan signal line, and a scan driving circuit is provided in the peripheral area;
  • the signal output terminals of the shift registers of each stage in the light emission control driving circuit are coupled to the corresponding scan signal lines in the display area.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a circuit structure of a shift register according to an embodiment of the present disclosure
  • Fig. 3 is a kind of working sequence diagram of the shift register shown in Fig. 2;
  • FIG. 4 is a schematic diagram of a circuit structure of another shift register provided by an embodiment of the present disclosure.
  • Fig. 5 is a kind of working sequence diagram of the shift register shown in Fig. 4;
  • FIG. 6 is a schematic diagram of a circuit structure of another shift register provided by an embodiment of the present disclosure.
  • Fig. 7 is a kind of working sequence diagram of the shift register shown in Fig. 6;
  • FIG. 8 is a schematic diagram showing the comparison of voltage changes of the first node, the second node and the third node when there is an impedance transistor and when there is no impedance transistor in the shift register shown in FIG. 6 ,
  • 9A is a schematic diagram of a circuit structure of still another shift register provided by an embodiment of the present disclosure.
  • 9B is a schematic diagram of a circuit structure of still another shift register provided by an embodiment of the present disclosure.
  • Fig. 10 is a kind of working sequence diagram of the shift register shown in Fig. 9B;
  • FIG. 11 is a schematic diagram of a circuit structure of still another shift register provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a circuit structure of still another shift register provided by an embodiment of the present disclosure.
  • Fig. 13 is a kind of working sequence diagram of the shift register shown in Fig. 12;
  • FIG. 14 is a schematic diagram of a circuit structure of still another shift register provided by an embodiment of the present disclosure.
  • 15 is a schematic diagram of a circuit structure of a driving circuit located in a peripheral area according to an embodiment of the disclosure.
  • 16 is a schematic diagram of another circuit structure of a driving circuit located in a peripheral area according to an embodiment of the disclosure.
  • FIG. 17 is a schematic diagram of a circuit structure of a pixel unit according to an embodiment of the disclosure.
  • FIG. 18 is a schematic diagram of a circuit connection between a pixel unit and a driving circuit located in a peripheral area according to an embodiment of the disclosure.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same or similar characteristics. There is no difference between source and drain.
  • the control electrode of the transistor specifically refers to the gate of the transistor; in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other is called the second electrode, and the gate is called the second electrode. called the control pole.
  • transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, P-type transistors are used for description. When P-type transistors are used, the first pole is the drain of the P-type transistor, and the second pole is the drain of the P-type transistor.
  • the "active level” in the present disclosure refers to a level that can control the conduction of the corresponding transistor; specifically, for a P-type transistor, the corresponding effective level is a low level; for an N-type transistor, the corresponding effective level is a low level. Active level is high level.
  • the power supply voltage provided by the first power supply terminal is a low-level voltage VGL (generally, VGL is less than 0V), and the power supply voltage provided by the second power supply terminal is a high-level voltage VGH (generally, VGL). ground, VGH is greater than 0V).
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a display area A and a non-display area B surrounding the display area A.
  • a plurality of pixel units are distributed, and a pixel circuit and a light-emitting device are arranged in the pixel unit, and each pixel circuit is configured with a corresponding plurality of driving signal lines DSL, such as scanning signal lines (also called gate lines), light-emitting control signal lines, Reset signal lines, etc., these drive signal lines DSL are used to control the pixel circuit to work.
  • scanning signal lines also called gate lines
  • light-emitting control signal lines Reset signal lines, etc.
  • a plurality of driving circuits DC (only one driving circuit is exemplarily drawn in the drawings) for providing driving signals to various driving signal lines are provided in the non-display area, wherein the driving circuit DC includes a plurality of cascaded shift registers SR , the signal output end of each shift register SR is connected to the corresponding driving signal line DSL, so as to output the corresponding driving signal to the corresponding driving signal line DSL.
  • FIG. 2 is a schematic diagram of a circuit structure of a shift register provided by an embodiment of the present disclosure.
  • the shift register provided by an embodiment of the present disclosure includes: a first transistor M1, a second transistor M2, and a third transistor M3 , a fourth transistor M4 , a fifth transistor M5 , an impedance transistor M_R, a first capacitor C1 and a first output control circuit 1 .
  • the control electrode of the first transistor M1 is coupled to the first clock signal line CK to receive the first clock signal, the first electrode of the first transistor M1 is coupled to the signal input terminal INPUT, and the second electrode of the first transistor M1 is coupled to the signal input terminal INPUT.
  • the first node N1 is coupled.
  • the control electrode of the second transistor M2 is coupled to the first node N1, the first electrode of the second transistor M2 is coupled to the second node N2, and the second electrode of the second transistor M2 is coupled to the first clock signal line CK for receiving first clock signal.
  • the control electrode of the third transistor M3 is coupled to the first clock signal line CK to receive the first clock signal, the first electrode of the third transistor M3 is coupled to the first power terminal, the second electrode of the third transistor M3 is coupled to the second power terminal Node N2 is coupled.
  • the control electrode of the fourth transistor M4 is coupled to the second clock signal line CKB to receive the second clock signal, the first electrode of the fourth transistor M4 is coupled to the second electrode of the fifth transistor M5, and the second electrode of the fourth transistor M4 The pole is coupled to the first node N1.
  • the control electrode of the fifth transistor M5 is coupled to the third node N3, and the first electrode of the fifth transistor M5 is coupled to the second power terminal.
  • the first pole of the first capacitor C1 is coupled to the fourth node N4, the second pole of the first capacitor C1 is coupled to the second clock signal line CKB, and the first node N1 is coupled to the fourth node N4.
  • the control electrode of the impedance transistor M_R is coupled to the first power supply terminal, the first electrode of the impedance transistor M_R is coupled to the second node N2, and the second electrode of the impedance transistor M_R is coupled to the third node N3.
  • the first output control circuit 1 is coupled to the third node N3, the fourth node N4 and the first signal output terminal OUT1, and the first output control circuit 1 is configured to respond to the control direction of the signals at the third node N3 and the fourth node N4.
  • the first signal output terminal OUT1 outputs the first driving signal.
  • Coupled in the present disclosure refers to electrical connection between two or more structures, and the connection manner is not limited to direct connection.
  • the first The clock signal will mischarge the second node N2 and the third node N3 through the second transistor M2, so that the voltage at the third node N3 is abnormally pulled up, and the fourth transistor M4 connected to the third node N3 and the first output
  • the control voltage works abnormally, thereby affecting the normal operation of the shift register; as the product usage time increases, the threshold voltage of the second transistor M2 drifts, and the second transistor M2 has a greater risk of being misconnected.
  • an impedance transistor M_R is provided between the second node N2 and the third node N3, and the control electrode of the impedance transistor M_R is connected to the first power supply terminal and is in a normally-on state, and is in a normally-on state.
  • the on-state impedance transistor M_R can block the current to a certain extent when there is a current between the second node N2 and the third node N3, that is, the impedance transistor M_R can generate an impedance effect to reduce when the second transistor M2 is mis-conducted
  • the pull-up effect of the first clock signal on the voltage at the third node N3 is conducive to maintaining the stability of the level state at the third node N3, so that the third node N3 is always at a low voltage during the false turn-on process of the second transistor M2. flat state.
  • FIG. 3 is a working timing diagram of the shift register shown in FIG. 2. As shown in FIG. 3, in the following description, only the working states of the first transistor M1 to the fifth transistor M5 will be described in detail, while the first output The specific working process of the control circuit 1 will be described later in conjunction with specific examples.
  • the working process of the shift register includes the following stages:
  • the first clock signal provided by the first clock signal line CK is in a low level state
  • the second clock signal provided by the second clock signal line CKB is in a high level state
  • the signal provided by the signal input terminal INPUT is in a high level state level status.
  • the first transistor M1 and the third transistor M3 are both turned on; the second clock signal is in a high level state, and the fourth transistor M4 is turned off.
  • the signal input terminal INPUT provides a signal in a high-level state and is written to the first node N1 through the first transistor M1, the first node N1 is in a high-level state, and the second transistor M2 is in an off state; at the same time, the second node N2 is discharged through the third transistor M3, the second node N2 is in a low level state (the voltage is slightly higher than VGL); the gate-source voltage of the impedance transistor M_R is negative, the impedance transistor M_R is in a conducting state, and the third node N3 passes through The second node N2 is discharged, and the third node N3 is in a low level state (the voltage is slightly higher than the voltage at the second node N2); since the third node N3 is in a low level state, the fifth transistor M5 is turned on.
  • the first node N1 When the first stage t1 ends, the first node N1 is in a high-level state, the second node N2 is in a low-level state, the third node N3 is in a low-level state, and the fourth node N4 is in a high-level state.
  • the first clock signal provided by the first clock signal line CK is in a high level state
  • the second clock signal provided by the second clock signal line CKB is in a low level state
  • the signal provided by the signal input terminal INPUT is in a high level state level status.
  • the first transistor M1 and the third transistor M3 are both turned off; the second clock signal is in a low level state, and the fourth transistor M4 is turned on.
  • the third node N3 is in a floating state to maintain the low level state in the first stage t1.
  • the second clock signal is switched from a high level to a low level.
  • the fourth node N4 and the first node N1 The voltage is pulled down, and at this time, the second transistor M2 has the risk of being misconnected.
  • the impedance transistor M_R is provided between the second node N2 and the third node N3, the first clock signal in the high-level state has no effect on the third
  • the influence of the voltage at the node N3 is very small, the level at the third node N3 can always be maintained at a low level state, and the fifth transistor M5 is kept on.
  • the voltage at the fourth node N4 will be affected by the high level voltage VGH through the fifth transistor M5 and the fourth transistor M4 to the first node N1 and the fourth node. N4 is charged, so that the first node N1 and the fourth node N4 are in a high level state, and the second transistor M2 in a false-on state is also immediately switched to an off state.
  • the first node N1 is in a high-level state
  • the second node N2 is in a low-level state
  • the third node N3 is in a low-level state
  • the fourth node N4 is in a high-level state.
  • the first clock signal provided by the first clock signal line CK is in a low level state
  • the second clock signal provided by the second clock signal line CKB is in a high level state
  • the signal provided by the signal input terminal INPUT is in a high level state level status.
  • the working process of the first transistor M1 to the fifth transistor M5 in the third stage t3 is the same as the working process in the first stage t1 , for details, please refer to the corresponding description of the first stage t1 above.
  • the first clock signal provided by the first clock signal line CK is in a high level state
  • the second clock signal provided by the second clock signal line CKB is in a low level state
  • the signal provided by the signal input terminal INPUT is in a low level state level status.
  • the working process of the first transistor M1 to the fifth transistor M5 in the fourth stage t4 is the same as the working process in the second stage t2 , for details, please refer to the corresponding description of the second stage t2 above.
  • the first clock signal provided by the first clock signal line CK is in a low level state
  • the second clock signal provided by the second clock signal line CKB is in a high level state
  • the signal provided by the signal input terminal INPUT is in a low level state level status.
  • the first transistor M1 and the third transistor M3 are both turned on; the second clock signal is in a high level state, and the fourth transistor M4 is turned off.
  • the signal input terminal INPUT provides a signal in a low level state and is written to the first node N1 through the first transistor M1, the first node N1 is in a low level state, the second transistor M2 is in a conducting state, and the second node N2 passes through the first node N1.
  • the second transistor M2 and the third transistor M3 are discharged, and the second node N2 is in a low level state; the gate-source voltage of the impedance transistor M_R is negative, the impedance transistor M_R is in a conducting state, and the third node N3 is connected through the second node N2. After discharging, the third node N3 is in a low level state; since the third node N3 is in a low level state, the fifth transistor M5 is turned on.
  • the first node N1 is in a low state
  • the second node N2 is in a low state
  • the third node N3 is in a low state
  • the fourth node N4 is in a low state.
  • the first clock signal provided by the first clock signal line CK is in a high level state
  • the second clock signal provided by the second clock signal line CKB is in a low level state
  • the signal provided by the signal input terminal INPUT is in a low level state level status.
  • the first transistor M1 and the third transistor M3 are both turned off; the second clock signal is in a low-level state, and the fourth transistor M4 is turned on.
  • the voltage at the fourth node N4 is pulled down from approximately equal to VGL to approximately equal to 2VGL, the first node N1 and the fourth node N4 are pulled down from approximately equal to VGL to approximately equal to 2VGL.
  • Node N4 is in a low state.
  • the second transistor M2 is in an on state (the second transistor M2 is normally turned on), the first clock signal in a high level state charges the second node N2 through the second transistor M2, the second node N2 and the third node N3 In a high level state, the fifth transistor M5 is turned off.
  • the first node N1 is in a low-level state
  • the second node N2 is in a high-level state
  • the third node N3 is in a high-level state
  • the fourth node N4 is in a low-level state.
  • the shift register alternately executes the fifth stage t5 and the sixth stage t6 described above until the next cycle starts.
  • the technical solution of the present disclosure can avoid the problem that the third node N3 is abnormally pulled up to a high level state due to the wrong turn-on of the second transistor M2 during the second stage t2 and the fourth stage t4, thereby It can be ensured that the third node N3 is always in a low level state during the second stage t2 and the fourth stage t4, thereby ensuring the normal operation of the shift register.
  • FIG. 4 is a schematic diagram of a circuit structure of another shift register provided by an embodiment of the present disclosure, as shown in FIG. 4 , the shift register shown in FIG. 4 is a specific optional implementation based on the shift register shown in FIG. 2 ; wherein, the first output control circuit 1 includes: a ninth transistor M9 and a third capacitor C3.
  • the control pole of the ninth transistor M9 is coupled to the fifth node N5, the first pole of the ninth transistor M9 is coupled to the second power supply terminal, and the second pole of the ninth transistor M9 is coupled to the first signal output terminal OUT1 ;
  • the first pole of the third capacitor C3 is coupled to the fifth node N5, and the second pole of the third capacitor C3 is coupled to the second power supply terminal.
  • the first output control circuit 1 further includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a tenth transistor M10 and a second capacitor C2.
  • the control electrode of the sixth transistor M6 is coupled to the third node N3, the first electrode of the sixth transistor M6 is coupled to the second clock signal line CKB to receive the second clock signal, and the second electrode of the sixth transistor M6 is coupled to the second clock signal line CKB.
  • the sixth node N6 is coupled; the control electrode of the seventh transistor M7 is coupled to the second clock signal line CKB to receive the second clock signal, the first electrode of the seventh transistor M7 is coupled to the sixth node N6, and the seventh transistor M7
  • the second pole of the eighth transistor M8 is coupled to the fifth node N5; the control pole of the eighth transistor M8 is coupled to the first node N1, the first pole of the eighth transistor M8 is coupled to the fifth node N5, and the second pole of the eighth transistor M8
  • the electrode of the tenth transistor M10 is coupled to the second power supply terminal; the control electrode of the tenth transistor M10 is coupled to the fourth node N4, the first electrode of the tenth transistor M10 is coupled to the first signal output terminal OUT1, and the second electrode of the tenth transistor M10 is coupled to the first power supply terminal, the first node N1 is coupled to the fourth node N4; the first pole of the second capacitor C2 is coupled to the third node N3, and the second pole of the second capacitor C2
  • FIG. 5 is a working timing diagram of the shift register shown in FIG. 4.
  • the first clock signal provided by the first clock signal line CK, the second clock signal and the signal provided by the second clock signal line CKB For the level state of the signal provided by the input terminal INPUT in each stage, and the working state of the first transistor M1 to the fifth transistor M5 in each stage, please refer to the corresponding descriptions of FIG. 2 and FIG. 3 and will not be repeated here. Only the specific working process of the first output control circuit 1 will be described in detail below.
  • the first clock signal provided by the first clock signal line CK is in a low-level state
  • the second clock signal provided by the second clock signal line CKB is in a high-level state
  • the first node N1 is in a high-level state
  • the second node N2 is in a low-level state
  • the third node N3 is in a low-level state
  • the fourth node N4 is in a high-level state.
  • the second clock signal is in a high level state
  • the seventh transistor M7 is turned off. Since the third node N3 is in the low level state, the sixth transistor M6 is turned on, the second clock signal in the high level state is written to the sixth node N6 through the sixth transistor M6, and the sixth node N6 is in the high level state state. At the same time, since both the first node N1 and the fourth node N4 are in a high level state, the eighth transistor M8 and the tenth transistor M10 are both turned off.
  • the fifth node N5 Since the seventh transistor M7 and the eighth transistor M8 are both turned off, the fifth node N5 is in a floating state, the fifth node N5 maintains the high level state of the previous stage (the last stage of the previous cycle), and the ninth transistor M9 deadline.
  • the first signal output terminal OUT1 is in a floating state, and the first signal output terminal OUT1 maintains the low level state of the previous stage (the last stage of the previous cycle). That is, the first signal output terminal OUT1 outputs a low level signal.
  • the first clock signal provided by the first clock signal line CK is in a high-level state
  • the second clock signal provided by the second clock signal line CKB is in a low-level state
  • the first node N1 is in a high-level state
  • the second node N2 is in a low-level state
  • the third node N3 is in a low-level state
  • the fourth node N4 is in a high-level state.
  • the seventh transistor M7 is turned on. Since the third node N3 is in the low level state, the sixth transistor M6 is turned on, the second clock signal in the low level state is written to the sixth node N6 through the sixth transistor M6, and the sixth node N6 is in the low level state state. Since the voltage at the sixth node N6 is switched from a high level state to a low level state, the voltage at the third node N3 is pulled down to a lower level under the bootstrapping action of the second capacitor C2.
  • the second capacitor C2 plays a leading role in the pull-down effect of the third node N3, so the voltage at the third node N3 has a tendency to be pulled down as a whole, so as to further ensure that the third node N3 is always at a low level during the second stage t2.
  • the voltage at the third node N3 is pulled down from approximately equal to VGL to approximately equal to 2VGL.
  • the gate-source voltage of the impedance transistor M_R will be greater than the impedance
  • the threshold voltage of the transistor M_R the impedance transistor M_R is switched from the on state to the off state.
  • the eighth transistor M8 and the tenth transistor M10 are both turned off.
  • the ninth transistor M9 is in an on state and the tenth transistor M10 is in an off state, the high-level voltage VGH is written to the first signal output terminal OUT1 through the ninth transistor M9, and the first signal output terminal OUT1 outputs a high-level signal .
  • the first clock signal provided by the first clock signal line CK is in a low level state
  • the second clock signal provided by the second clock signal line CKB is in a high level state
  • the first node N1 is in a high level state
  • the second node N2 is in a low-level state
  • the third node N3 is in a low-level state
  • the fourth node N4 is in a high-level state.
  • the second clock signal is in a high level state
  • the seventh transistor M7 is turned off. Since the third node N3 is in the low level state, the sixth transistor M6 is turned on, the second clock signal in the high level state is written to the sixth node N6 through the sixth transistor M6, and the sixth node N6 is in the high level state state. Since the third transistor M3 is turned on, the low-level voltage VGL is written to the third node N3 through the third transistor M3 and the resistance transistor M_R, and the third node N3 is still in a low-level state and the voltage is approximately equal to VGL. At the same time, since both the first node N1 and the fourth node N4 are in a high level state, the eighth transistor M8 and the tenth transistor M10 are both turned off.
  • the fifth node N5 is in a floating state, the fifth node N5 maintains the low level state of the previous stage (the second stage t2 ), and the ninth transistor M9 remains on deadline.
  • the first signal output terminal OUT1 is in a floating state, and the first signal output terminal OUT1 maintains the high level state of the previous stage (the last stage of the previous cycle). , that is, the first signal output terminal OUT1 outputs a high-level signal.
  • the ninth transistor M9 is in an on state and the tenth transistor M10 is in an off state, the high-level voltage VGH is written to the first signal output terminal OUT1 through the ninth transistor M9, and the first signal output terminal OUT1 maintains an output high level Signal.
  • the first clock signal provided by the first clock signal line CK is in a high-level state
  • the second clock signal provided by the second clock signal line CKB is in a low-level state
  • the first node N1 is in a high-level state
  • the second node N2 is in a low-level state
  • the third node N3 is in a low-level state
  • the fourth node N4 is in a high-level state.
  • the seventh transistor M7 is turned on. Since the third node N3 is in the low level state, the sixth transistor M6 is turned on, the second clock signal in the low level state is written to the sixth node N6 through the sixth transistor M6, and the sixth node N6 is in the low level state state. Since the voltage at the sixth node N6 is switched from a high level state to a low level state, the voltage at the third node N3 is pulled down to a lower level under the bootstrapping action of the second capacitor C2.
  • the second capacitor C2 will The influence of the third node N3 plays a leading role, so the voltage at the third node N3 has a tendency to be pulled down as a whole, to further ensure that the third node N3 is always in a low level state during the second stage t2.
  • the voltage at the third node N3 is pulled down from approximately equal to VGL to approximately equal to 2VGL.
  • the eighth transistor M8 and the tenth transistor M10 are both turned off.
  • the ninth transistor M9 is in an on state and the tenth transistor M10 is in an off state, the high-level voltage VGH is written to the first signal output terminal OUT1 through the ninth transistor M9, and the first signal output terminal OUT1 outputs a high-level signal .
  • the first clock signal provided by the first clock signal line CK is in a low-level state
  • the second clock signal provided by the second clock signal line CKB is in a high-level state
  • the first node N1 is in a low-level state
  • the second node N2 is in a low-level state
  • the third node N3 is in a low-level state
  • the fourth node N4 is in a low-level state.
  • the second clock signal is in a high level state, and the seventh transistor M7 is turned off. Since the third node N3 is in the low level state, the sixth transistor M6 is turned on, the second clock signal in the high level state is written to the sixth node N6 through the sixth transistor M6, and the sixth node N6 is in the high level state state. Since the third transistor M3 is turned on, the low-level voltage VGL is written to the third node N3 through the third transistor M3 and the resistance transistor M_R, and the third node N3 is still in a low-level state and the voltage is approximately equal to VGL.
  • the eighth transistor M8 Since the first node N1 is in the low level state, the eighth transistor M8 is turned on, the high level voltage VGH is written to the fifth node N5 through the eighth transistor M8, the fifth node N5 is in the high level state, and the ninth transistor M9 ends.
  • the fourth node N4 is in a low level state and the voltage is approximately equal to VGL, the tenth transistor M10 is turned on, and the first signal output terminal OUT1 is discharged through the tenth transistor M10.
  • the gate-source voltage of the tenth transistor M10 will be lower than the threshold voltage of the tenth transistor M10. At this time, the tenth transistor M10 M10 will be turned on again so that the voltage of the first signal output terminal OUT1 drops, until the gate-source voltage of the tenth transistor M10 is equal to the threshold voltage of the tenth transistor M10, the tenth transistor M10 is turned off again.
  • the first clock signal provided by the first clock signal line CK is in a high-level state
  • the second clock signal provided by the second clock signal line CKB is in a low-level state
  • the first node N1 is in a low-level state
  • the second node N2 is in a high-level state
  • the third node N3 is in a high-level state
  • the fourth node N4 is in a low-level state.
  • the seventh transistor M7 is turned on. Since the third node N3 is in a high level state, the sixth transistor M6 is turned off. Since the first node N1 is in a low-level state, the eighth transistor M8 is turned on, the high-level voltage VGH is written to the fifth node N5 through the eighth transistor M8, the fifth node N5 is in a high-level state, and the ninth transistor M9 At the same time, since the seventh transistor M7 is turned on, the high-level voltage VGH can charge the sixth node N6 through the eighth transistor M8 and the seventh transistor M7, and the sixth node N6 is in a high-level state.
  • the voltage at the fourth node N4 is pulled down from approximately equal to VGL to approximately equal to 2VGL,
  • the tenth transistor M10 is turned on again, and the first signal output terminal OUT1 is discharged through the tenth transistor M10; without considering the impedance of the tenth transistor M10, the voltage at the first signal output terminal OUT1 can drop to VGL, and the tenth transistor
  • the gate-source voltage of M10 is always lower than the threshold voltage of the tenth transistor M10, the tenth transistor M10 is continuously turned on, and the first signal output terminal OUT1 outputs a low-level signal and the voltage is approximately equal to VGL.
  • the first output control circuit 1 may also adopt other structures.
  • the first output control circuit 1 only includes the ninth transistor M9 and the tenth transistor M10, or includes the ninth transistor M9 and the tenth transistor M10.
  • the driving timing of the shift register is not limited to that shown in FIG. 4 .
  • FIG. 6 is a schematic diagram of a circuit structure of another shift register provided by an embodiment of the present disclosure.
  • the shift register shown in FIG. 6 unlike the shift register shown in FIG. 2 and FIG. 4 , in the shift register shown in FIG. It also includes a voltage limiting transistor M_V, wherein the first node N1 is coupled to the fourth node N4 through the voltage limiting transistor M_V.
  • the control electrode of the voltage limiting transistor M_V is coupled to the first power supply terminal
  • the first electrode of the voltage limiting transistor M_V is coupled to the first node N1
  • the second electrode of the voltage limiting transistor M_V is coupled to the fourth node N4.
  • FIG. 7 is a working timing diagram of the shift register shown in FIG. 6. As shown in FIG. 7, the difference from the synchronous change of the voltages at the first node N1 and the fourth node N4 shown in FIG. 3 and FIG. 5 is that at In the timing sequence shown in FIG.
  • FIG. 8 is a schematic diagram showing the comparison of voltage changes of the first node, the second node and the third node when there is an impedance transistor and when there is no impedance transistor in the shift register shown in FIG. 6 .
  • the first clock signal and the second The voltage when the clock signal is in the high level state is +7V, and the voltage when the clock signal is in the low level state is -7V as an example to perform the simulation test.
  • the voltage at the second node N2 is -4.551V, and the voltage at the third node N3 is -14.16V; when the impedance transistor M_R in the present disclosure is provided, at In the second stage t2, the voltage at the second node N2 is -5.245V, and the voltage at the third node N3 is -16.4V. It can be seen that by setting the above-mentioned impedance transistor M_R, the second node N2 and the third node N3 can be pulled down to a lower level in the second stage t2, which is beneficial to ensure the stability of the gate voltage of the fifth transistor M5.
  • FIG. 9A is a schematic diagram of a circuit structure of still another shift register provided by an embodiment of the present disclosure. As shown in FIG. 9A , different from the shift register shown in the previous embodiment, the shift register shown in FIG. 9A further includes : The second output control circuit 2.
  • the second output control circuit 2 is coupled to at least the first signal output terminal OUT1 and the second signal output terminal OUT2, and the second output control circuit 2 is configured to transmit to the first signal output terminal OUT1 according to the first driving signal output by the first signal output terminal OUT1.
  • the two signal output terminals OUT2 output a second driving signal whose phase is opposite to that of the first driving signal.
  • the second output control circuit 2 may specifically be an inversion processing circuit with an inversion processing function.
  • the first signal output terminal OUT1 is used as a signal input terminal of the inversion processing circuit, and the second signal output terminal OUT2 is used as a signal input terminal of the inversion processing circuit. signal output.
  • one shift register has two signal output terminals, and the two signal output terminals can output different driving signals, so they can provide driving signals for different driving signal lines, which is beneficial to reduce the amount of noise in the non-pixel area.
  • the number of arranged driving circuits is beneficial to the realization of the narrow frame of the product.
  • the first signal output end OUT1 of the shift register is connected to the light-emitting control signal line configured by the pixel circuit
  • the second signal output end OUT2 of the shift register is connected to the reset signal line configured by the pixel circuit
  • the first signal output end OUT2 of the shift register is connected to the reset signal line configured by the pixel circuit.
  • the first driving signal output by a signal output terminal OUT1 is a light-emitting control signal
  • the second driving signal output by the second signal output terminal OUT2 is a reset signal.
  • FIG. 9B is a schematic diagram of a circuit structure of another shift register provided by an embodiment of the present disclosure.
  • the shift register shown in FIG. 9B is a specific optional implementation based on the shift register shown in FIG. 9A .
  • the first output control circuit 1 shown in FIG. 9B adopts those shown in FIG. 4 and FIG. 6 , and the specific structure of the first output control circuit 1 will not be repeated here.
  • the second output control circuit 2 includes: an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a fourth capacitor C4.
  • the control electrode of the eleventh transistor M11 is coupled to the fifth node N5, the first electrode of the eleventh transistor M11 is coupled to the first power supply terminal, and the second electrode of the eleventh transistor M11 is coupled to the seventh node N7
  • the control pole of the twelfth transistor M12 is coupled to the first signal output terminal OUT1, the first pole of the twelfth transistor M12 is coupled to the seventh node N7, and the second pole of the twelfth transistor M12 is connected to the second power supply terminals are coupled;
  • the control electrode of the thirteenth transistor M13 is coupled to the seventh node N7, the first electrode of the thirteenth transistor M13 is connected to the first clock signal line CK, the second electrode of the thirteenth transistor M13 is connected to the fourth capacitor
  • the first pole of C4 is coupled; the fourteenth transistor M14, the control pole of the fourteenth transistor M14 is coupled to the seventh node N7, the first pole of the fourteenth transistor M14 is coupled to the first power supply terminal, the fourteenth transistor M
  • FIG. 10 is a working timing diagram of the shift register shown in FIG. 9B .
  • the working states of the first transistor M1 to the tenth transistor M10 at various stages can be referred to the corresponding descriptions in the previous embodiments. It is not repeated here, only the specific working process of the second output control circuit 2 will be described in detail below.
  • the first clock signal provided by the first clock signal line CK is in a low-level state
  • the second clock signal provided by the second clock signal line CKB is in a high-level state
  • the fifth node N5 is in a high-level state
  • the first signal output terminal OUT1 is in a low level state.
  • the eleventh transistor M11 is turned off, the twelfth transistor M12 and the fifteenth transistor M15 are turned on, and the high-level voltage VGH Writing to the seventh node N7 through the twelfth transistor M12, the seventh node N7 is in a high level state, and the fourteenth transistor M14 is turned off.
  • the fourteenth transistor M14 is in an off state and the fifteenth transistor M15 is in an on state, the high-level voltage VGH is written to the second signal output terminal OUT2 through the fifteenth transistor M15, and the second signal output terminal OUT2 outputs a high level. level signal.
  • the first clock signal provided by the first clock signal line CK is in a high-level state
  • the second clock signal provided by the second clock signal line CKB is in a low-level state
  • the fifth node N5 is in a low-level state
  • the first signal output terminal OUT1 is in a high level state.
  • the eleventh transistor M11 is turned on, the twelfth transistor M12 and the fifteenth transistor M15 are turned off, and the low-level voltage VGL Writing to the seventh node N7 through the twelfth transistor M12, the seventh node N7 is in a low level state and the voltage is approximately equal to VGL, the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, and the second signal output terminal OUT2 passes through
  • the fourteenth transistor M14 is discharged, when the voltage of the fourteenth transistor M14 drops to VGL-Vth_M14 (that is, when the gate-source power supply of the fourteenth transistor M14 is equal to Vth_M14, where VN7 is the voltage at the seventh node N7 and is approximately equal to VGL, Vth_M14 is the threshold voltage of the fourteenth transistor M14 and is negative), the fourteenth transistor M14 is switched to the off state, the second
  • the gate-source voltage of the fourteenth transistor M14 will be lower than the threshold voltage of the fourteenth transistor M14.
  • the fourteenth transistor M14 will be turned on again so that the voltage of the second signal output terminal OUT2 drops, until the gate-source voltage of the fourteenth transistor M14 is equal to the threshold voltage of the fourteenth transistor M14, the fourteenth transistor M14 is turned off again.
  • the first clock signal provided by the first clock signal line CK is in a low level state
  • the second clock signal provided by the second clock signal line CKB is in a high level state
  • the fifth node N5 is in a low level state
  • the first signal output terminal OUT1 is in a high level state.
  • the eleventh transistor M11 is turned on, the twelfth transistor M12 and the fifteenth transistor M15 is turned off, the low-level voltage VGL is written to the seventh node N7 through the twelfth transistor M12, the seventh node N7 is in a low-level state, and the thirteenth transistor M13 and the fourteenth transistor M14 are turned on.
  • the fourteenth The transistor M14 When the first clock signal is switched from a high level state to a low level state, under the bootstrapping action of the fourth capacitor C4, the voltage at the seventh node N7 is pulled down from approximately equal to VGL to approximately equal to 2VGL, and the fourteenth The transistor M14 is turned on again, and the second signal output terminal OUT2 is discharged through the fourteenth transistor M14; without considering the impedance of the fourteenth transistor M14, the voltage at the second signal output terminal OUT2 can drop to VGL, the fourteenth The gate-source voltage of the transistor M14 is always lower than the threshold voltage of the fourteenth transistor M14, the fourteenth transistor M14 is continuously turned on, and the second signal output terminal OUT2 outputs a low-level signal and the voltage is approximately equal to VGL.
  • the first clock signal provided by the first clock signal line CK is in a high-level state
  • the second clock signal provided by the second clock signal line CKB is in a low-level state
  • the fifth node N5 is in a low-level state
  • the first signal output terminal OUT1 is in a high level state.
  • the voltage at the seventh node N7 is pulled up from approximately equal to 2VGL to approximately equal to VGL, and the tenth A transistor M11 is turned on, the low-level voltage VGL is written to the seventh node N7 through the eleventh transistor M11, the seventh node N7 maintains the low-level state and the voltage is approximately equal to VGL, and the gate-source voltage of the fourteenth transistor M14 is approximately equal to 0, the lower fourteenth transistor is turned off; since the first signal output terminal OUT1 outputs a high level signal, the twelfth transistor M12 and the fifteenth transistor M15 are both turned off.
  • the second signal output terminal OUT2 is in a floating state to maintain the low level state of the previous stage (the third stage t3 ), the second signal output terminal OUT2 outputs a low level signal and the voltage is approximately equal to VGL.
  • the first clock signal provided by the first clock signal line CK is in a low-level state
  • the second clock signal provided by the second clock signal line CKB is in a high-level state
  • the fifth node N5 is in a high-level state
  • the first signal output terminal OUT1 is in a low level state.
  • the eleventh transistor M11 is turned off, the twelfth transistor M12 and the fifteenth transistor M15 are turned on, and the high-level voltage VGH Writing to the seventh node N7 through the twelfth transistor M12, the seventh node N7 is in a high level state, and the fourteenth transistor M14 is turned off.
  • the fourteenth transistor M14 is in an off state and the fifteenth transistor M15 is in an on state, the high-level voltage VGH is written to the second signal output terminal OUT2 through the fifteenth transistor M15, and the second signal output terminal OUT2 outputs a high level. level signal.
  • the first clock signal provided by the first clock signal line CK is in a high-level state
  • the second clock signal provided by the second clock signal line CKB is in a low-level state
  • the fifth node N5 is in a high-level state
  • the first signal output terminal OUT1 is in a low level state.
  • the working process of the second output control circuit 2 in the sixth stage t6 is the same as the working process in the fifth stage t5 , and for details, please refer to the corresponding description of the sixth stage t6 above.
  • FIG. 11 is a schematic diagram of the circuit structure of still another shift register provided by an embodiment of the present disclosure.
  • the shift register shown in FIG. 11 is different from the second output control circuit 2 in the shift register shown in FIG.
  • the second output control circuit 2 in the bit register only includes the eleventh transistor M11, the twelfth transistor M12, the fourteenth transistor M14, the fifteenth transistor M15 and the fourth capacitor C4 but does not include the thirteenth transistor M13, and the thirteenth transistor M13 is not included.
  • the first pole of the four capacitors C4 is coupled to the first clock signal line CK.
  • the working sequence of the shift register shown in FIG. 11 may be as shown in FIG. 10 , and the specific process will not be repeated here.
  • FIG. 12 is a schematic diagram of the circuit structure of still another shift register provided by an embodiment of the present disclosure. As shown in FIG. 12 , the difference from the second output control circuit 2 in the shift register shown in FIG. 9B is that the shift register shown in FIG. 12 is different from the second output control circuit 2 in the shift register shown in FIG. The first pole of the thirteenth transistor M13 in the bit register is coupled to the second clock signal line CKB.
  • FIG. 13 is a working timing diagram of the shift register shown in FIG. 12 .
  • the working states of the first transistor M1 to the tenth transistor M10 at various stages can be referred to the corresponding descriptions in the previous embodiments. It is not repeated here, only the specific working process of the second output control circuit 2 will be described in detail below.
  • the working process of the second control circuit in the shift register shown in FIG. 12 in the first stage t1 and the second stage t2 is the same as that of the second control circuit in the shift register shown in FIG. 9B in the first stage t1 and the second stage t2
  • the working process is the same, and will not be repeated here.
  • the first clock signal provided by the first clock signal line CK is in a low level state
  • the second clock signal provided by the second clock signal line CKB is in a high level state
  • the fifth node N5 is in a low level state
  • the first signal output terminal OUT1 is in a high level state.
  • the eleventh transistor M11 Since the fifth node N5 is in a low-level state and the first signal output terminal OUT1 is in a high-level state, the eleventh transistor M11 is turned on, the twelfth transistor M12 and the fifteenth transistor M15 are turned off, and the low-level voltage VGL Writing to the seventh node N7 through the eleventh transistor M11, the seventh node N7 is in a low level state and the voltage is approximately equal to VGL, the fourteenth transistor M14 maintains the off state of the previous stage (the second stage t2), the second The signal output terminal OUT2 outputs a low level signal and the voltage is approximately equal to VGL.
  • the first clock signal provided by the first clock signal line CK is in a high-level state
  • the second clock signal provided by the second clock signal line CKB is in a low-level state
  • the fifth node N5 is in a low-level state
  • the first signal output terminal OUT1 is in a high level state.
  • the fourteenth The transistor M14 When the second clock signal is switched from the high level state to the low level state, under the bootstrap action of the fourth capacitor C4, the voltage at the seventh node N7 is pulled down from approximately equal to VGL to approximately equal to 2VGL, and the fourteenth The transistor M14 is turned on again, and the second signal output terminal OUT2 is discharged through the fourteenth transistor M14; without considering the impedance of the fourteenth transistor M14, the voltage at the second signal output terminal OUT2 can drop to VGL, the fourteenth The gate-source voltage of the transistor M14 is always lower than the threshold voltage of the fourteenth transistor M14, the fourteenth transistor M14 is continuously turned on, and the second signal output terminal OUT2 outputs a low-level signal and the voltage is approximately equal to VGL.
  • the working process of the second control circuit in the shift register shown in FIG. 12 in the fifth stage t5 and the sixth stage t6 is the same as that of the second control circuit in the shift register shown in FIG. 9B in the fifth stage t5 and the sixth stage t6
  • the working process is the same, and will not be repeated here.
  • FIG. 14 is a schematic diagram of the circuit structure of still another shift register provided by an embodiment of the present disclosure.
  • the difference from the second output control circuit 2 in the shift register shown in FIG. 12 is that the shift register shown in FIG.
  • the second output control circuit 2 in the bit register only includes the eleventh transistor M11, the twelfth transistor M12, the fourteenth transistor M14, the fifteenth transistor M15 and the fourth capacitor C4 but does not include the thirteenth transistor M13, and the thirteenth transistor M13 is not included.
  • the first pole of the quad capacitor C4 is coupled to the second clock signal line CKB.
  • the working sequence of the shift register shown in FIG. 14 may be as shown in FIG. 13 , and the specific process will not be repeated here.
  • the second output control circuit 2 in the shift register may also adopt other circuit structures having an inversion processing function, which will not be exemplified here.
  • FIG. 15 is a schematic diagram of a circuit structure of a driving circuit located in a peripheral area in an embodiment of the disclosure.
  • the driving circuit includes a plurality of shift registers SR1/SR2.../SRm arranged in cascade , wherein the shift registers SR1/SR2.../SRm may adopt the shift registers provided in any of the foregoing embodiments.
  • the signal input terminal INPUT of the shift register SR1 located in the first stage is coupled to the frame start signal terminal STV. Except for the shift register SR1 located in the first stage, the shift registers/SR2..
  • the signal input terminal of ./SRm is connected to the first signal output terminal OUT1 of the shift register of the previous stage.
  • the first clock signal terminals CK of the shift registers SR1/SR3... in the odd-numbered stages are coupled to the first clock signal line CLK, and the second clock signal terminals CKB of the shift registers SR1/SR3... in the odd-numbered stages is coupled to the second clock signal line CLKB; the first clock signal terminal CK of the shift registers SR2/SR4 in the even-numbered stages is coupled to the second clock signal line CLKB, and the shift registers SR2/SR4 in the even-numbered stages are The second clock signal terminal CKB of ... is coupled to the first clock signal line CLK.
  • the first power supply terminals of the shift registers SR1/SR2.../SRm of each stage are coupled to the first power supply voltage supply line (not shown), and the second power supply terminals of the shift registers SR1/SR2.../SRm The terminal is connected to a second power supply voltage supply line (not shown).
  • the first signal output terminals OUT1 of the shift registers SR1/SR2.../SRm of each stage are coupled to the corresponding light-emitting control signal lines EM1/EM2.../EMm in the display area.
  • the first signal output terminal OUT1 of the i-th shift register SRi is coupled to the light-emitting control line EMi corresponding to the i-th row of pixel units in the display area, where i is a positive integer and less than or equal to m.
  • FIG. 16 is a schematic diagram of another circuit structure of a driving circuit located in the peripheral area according to an embodiment of the present disclosure.
  • the driving circuit A second output control circuit (including a second signal output terminal OUT2) is also provided in the shift registers SR1/SR2.../SRm at all levels in the circuit.
  • the shift register adopts Fig. 9A, Fig. 9B, Fig.
  • the first signal output terminals OUT1 of the shift registers SR1/SR2.../SRm of all levels are coupled to the corresponding light-emitting control signal lines EM1/EM2.../EMm in the display area
  • the second signal output terminals OUT2 of the shift registers SR1/SR2.../SRm of all levels are connected to the corresponding reset signal lines RST1/RST2.../RSTm in the display area.
  • the first signal output terminal OUT1 of the shift register SRi of the ith stage is coupled to the light-emitting control line EMi corresponding to the pixel unit of the ith row in the display area
  • the second signal output terminal OUT1 of the shift register SRi of the ith stage is
  • the signal output terminal OUT2 is coupled to the reset signal line RSTi corresponding to the pixel unit in the i-th row in the display area, where i is a positive integer and less than or equal to m.
  • an embodiment of the present disclosure further provides a display substrate, the display substrate includes: a display area A and a peripheral area B surrounding the display area A, and the display area A is provided with arrays arranged in an array A plurality of pixel units, each pixel unit is configured with a corresponding light-emitting control signal line, a light-emitting control driving circuit is provided in the peripheral area B, and the light-emitting control driving circuit includes a plurality of shift registers arranged in cascade, and the light-emitting control driving circuit
  • the shift register adopts the shift register provided in any of the previous embodiments, and the first signal output terminal OUT1 of the shift register in the light-emitting control driving circuit is coupled to the corresponding light-emitting control signal line in the display area.
  • a pixel circuit and a light-emitting device are provided in the pixel unit.
  • the light-emitting device in the present disclosure refers to a current-driven light-emitting element including an organic light-emitting diode (Organic Light Emitting Diode, OLED for short), a light-emitting diode (Light Emitting Diode, LED for short) and the like.
  • OLED Organic Light Emitting Diode
  • LED Light Emitting Diode
  • An OLED is taken as an example for exemplary description, wherein the first end and the second end of the light emitting device refer to the anode end and the cathode end, respectively.
  • the pixel unit includes: a pixel circuit and a light-emitting device, and the pixel circuit includes: a first reset sub-circuit 21 and a second reset sub-circuit 22.
  • Data writing sub-circuit 23 threshold compensation sub-circuit 24, light-emitting control sub-circuit 25 and driving transistor DTFT.
  • the first reset sub-circuit 21 is coupled to the initialization voltage terminal, the control electrode of the driving transistor DTFT, and the corresponding scan control signal line SC, and is configured to reset the initialization voltage in response to the control of the scan control signal provided by the scan control signal line SC.
  • the initialization voltage provided by the terminal is written to the control electrode of the driving transistor DTFT.
  • the second reset sub-circuit 22 is coupled to the initialization voltage terminal, the first terminal of the light emitting device OLED, and the corresponding reset signal line RST, and is configured to write the initialization voltage to the light emitting device OLED in response to the control of the reset signal line RST the first end.
  • the data writing sub-circuit 23 is coupled to the first electrode of the driving transistor DTFT, the corresponding data line DATA, and the corresponding scanning signal line GATE, and is configured to write the data voltage provided by the data line DATA in response to the control of the scanning signal line GATE to the first electrode of the driving transistor DTFT.
  • the threshold compensation sub-circuit 24 is coupled to the second working voltage terminal, the control electrode of the driving transistor DTFT, the first electrode of the driving transistor DTFT, the second electrode of the driving transistor DTFT, and the corresponding scanning signal line GATE, and is configured to respond to The control of the scanning signal line GATE writes a data compensation voltage to the gate electrode of the driving transistor DTFT, and the data compensation voltage is equal to the sum of the data voltage and the threshold voltage of the driving transistor DTFT.
  • the light-emitting control sub-circuit 25 is located between the second pole of the driving transistor DTFT and the first end of the light-emitting device OLED, and is coupled to the light-emitting control signal line EM, and is configured to respond to the control of the light-emitting control signal provided by the light-emitting control signal line EM So as to make conduction between the second electrode of the driving transistor DTFT and the first end of the light emitting device OLED.
  • the driving transistor DTFT is configured to output a corresponding driving current in response to the control of the data compensation voltage, and the second terminal of the light emitting device OLED is coupled to the first operating voltage terminal.
  • the first reset sub-circuit 21 includes a twenty-first transistor M21
  • the second reset sub-circuit 22 includes a twenty-second transistor M22
  • the data writing sub-circuit 23 includes a twenty-third transistor M23
  • the threshold compensation sub-circuit 24 includes a twenty-fourth transistor M24, a twenty-fifth transistor M25 and a storage capacitor CST
  • the light-emitting control sub-circuit 25 includes a twenty-sixth transistor M26.
  • the control electrode of the twenty-first transistor M21 is coupled to the scan control signal line SC, the first electrode of the twenty-first transistor M21 is coupled to the initialization voltage terminal, and the second electrode of the twenty-first transistor M21 is coupled to the driving transistor
  • the control electrode of the DTFT is coupled; the control electrode of the twenty-second transistor M22 is coupled to the reset signal line RST, the first electrode of the twenty-second transistor M22 is coupled to the initialization voltage terminal, and the first electrode of the twenty-second transistor M22 is coupled to the initialization voltage terminal.
  • the diode is coupled to the first end of the light-emitting device OLED; the control electrode of the twenty-third transistor M23 is coupled to the scanning signal line GATE, the first electrode of the twenty-third transistor M23 is coupled to the data line DATA, and the twentieth transistor M23 is coupled to the data line DATA.
  • the second pole of the three transistors M23 is coupled to the first pole of the driving transistor DTFT; the control pole of the twenty-fourth transistor M24 is coupled to the light-emitting control signal line EM, and the first pole of the twenty-fourth transistor M24 is connected to the second pole
  • the voltage terminal is coupled, the second electrode of the twenty-fourth transistor M24 is coupled to the first electrode of the driving transistor DTFT; the control electrode of the twenty-fifth transistor M25 is coupled to the scanning signal line GATE, and the The first electrode is coupled to the control electrode of the driving transistor DTFT, the second electrode of the twenty-fifth transistor M25 is coupled to the second electrode of the driving transistor DTFT; the first end of the storage capacitor CST is coupled to the second working voltage end, The second end of the storage capacitor CST is coupled to the control electrode of the driving transistor DTFT; the control electrode of the twenty-sixth transistor M26 is coupled to the light-emitting control signal line EM, and the first electrode of the twenty-sixth transistor
  • the initialization voltage terminal provides the initialization voltage VINIT
  • the first working voltage terminal provides the first working voltage VDD
  • the second working voltage terminal provides the second working voltage VSS.
  • the unit, the scan control signal line coupled to the pixel unit is the scan signal line configured for the pixel unit in the previous row.
  • the scanning signal lines can be multiplexed, and there is no need to additionally set the scanning control signal lines, which is beneficial to reduce the wiring space.
  • the peripheral area of the display substrate is configured with two driving circuits: a light-emitting control driving circuit GOA_1 and a scanning driving circuit GOA_2, wherein the light-emitting control driving circuit GOA_1 is used to provide a light-emitting control signal and a reset signal, and the scanning The driving circuit GOA_2 is used for providing scan signals.
  • the light-emitting control signal line EM(n) configured in the pixel unit and the light-emitting control driving circuit GOA_1 are located in the shift register SRn of the n-th stage.
  • a signal output terminal OUT1 is coupled, and the reset signal line RST(n) configured in the pixel unit is coupled to the second signal output terminal OUT2 of the shift register SRn at the nth stage in the light emission control driving circuit GOA_1.
  • the scanning signal line GATE(n) configured by the unit is coupled to the signal output terminal OUT of the shift register SR'n (the specific circuit structure is a conventional technique in the field) located at the nth stage in the scanning driving circuit GOA_2, and the pixel unit is
  • the configured scan control signal line is the scan signal line GATE(n-1) located in the n-1th row, the scan signal line GATE(n-1) and the shift register located in the n-1th stage in the scan drive circuit GOA_2
  • the signal output terminal OUT of SR'n-1 is coupled.
  • the reset signal and the lighting control signal are output by the same driving circuit, the synchronous output of the reset signal and the lighting control signal can be ensured; Modulation, abbreviated as PWM) function, so that it has the output of multiple pulses in one frame of display time.
  • PWM Modulation, abbreviated as PWM
  • the second reset sub-circuit 22 will be in a The frame display time is turned on multiple times to reset the light-emitting device OLED multiple times, thereby improving the service life of the light-emitting device OLED and reducing the difference in light-emitting brightness between the light-emitting devices controlled by different light-emitting control signal pulses under PWM.
  • the pixel circuit shown in FIG. 17 and FIG. 18 includes 7 transistors and 1 capacitor (also known as a 7T1C circuit) is only an example, and does not limit the technical solutions of the present disclosure.
  • the disclosed technical solutions can also be applied to other pixel circuits.

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Abstract

本公开提供了一种移位寄存器，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一电容和阻抗晶体管；第一晶体管的第一极与信号输入端耦接，第二极与第一节点耦接；第二晶体管的控制极与第一节点耦接，第一极与第二节点耦接，第二极与第一时钟信号线耦接；第三晶体管的第一极与第一电源端耦接，第二极与第二节点耦接；第四晶体管的第一极与第五晶体管的第二极耦接，第二极与第一节点耦接；第五晶体管的控制极与第三节点耦接，第一极与第二电源端耦接；第一电容的第一极与第四节点耦接，第二极与第二时钟信号线耦接；阻抗晶体管的控制极与第一电源端耦接，第一极与第二节点耦接，第二极与第三节点耦接。

Description

移位寄存器、驱动电路和显示基板 技术领域
本公开涉及显示领域，特别涉及一种移位寄存器、驱动电路和显示基板。
背景技术
在显示技术领域，为实现对像素单元内发光器件的发光状态的精准控制，会在像素单元所包含的像素电路内设置发光控制子电路；发光控制子电路一般设于驱动晶体管与发光器件之间，以控制驱动晶体管与发光器件之间的通断；其中，发光控制子电路的工作状态受控于发光控制信号线所提供的发光控制信号，发光控制信号线中的发光控制信号实质为位于显示基板的周边区域内一个栅极驱动电路所提供的一种驱动信号。
发明内容
本公开提出了一种移位寄存器、驱动电路和显示基板。
第一方面，本公开实施例提供了一种移位寄存器，其中，包括：
第一晶体管，所述第一晶体管的控制极与第一时钟信号线耦接以接收第一时钟信号，所述第一晶体管的第一极与信号输入端耦接，所述第一晶体管的第二极与第一节点耦接；
第二晶体管，所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与第二节点耦接，所述第二晶体管的第二极与所述第一时钟信号线耦接以接收所述第一时钟信号；
第三晶体管，所述第三晶体管的控制极与所述第一时钟信号线耦接以接收所述第一时钟信号，所述第三晶体管的第一极与第一电源端耦接，所述第三晶体管的第二极与所述第二节点耦接；
第四晶体管，所述第四晶体管的控制极与第二时钟信号线耦接以接收第二时钟信号，所述第四晶体管的第一极与第五晶体管的第二极耦接，所述第四晶体管的第二极与所述第一节点耦接；
第五晶体管，所述第五晶体管的控制极与第三节点耦接，所述第五晶体管的第一极与第二电源端耦接；
第一电容，所述第一电容的第一极与第四节点耦接，所述第一电容的第二极与所述第二时钟信号线耦接，第一节点与所述第四节点耦接；
阻抗晶体管，所述阻抗晶体管的控制极与所述第一电源端耦接，所述阻抗晶体管的第一极与所述第二节点耦接，所述阻抗晶体管的第二极与所述第三节点耦接；
以及，第一输出控制电路，与所述第三节点、所述第四节点和第一信号输出端耦接，配置为响应于所述第三节点、所述第四节点处信号的控制向所述第一信号输出端输出第一驱动信号。
在一些实施例中，所述的移位寄存器还包括：
第二输出控制电路，至少与所述第一信号输出端和第二信号输出端耦接，配置为根据所述第一信号输出端所输出的第一驱动信号向所述第二信号输出端输出与所述第一驱动信号的相位相反的第二驱动信号。
在一些实施例中，所述第一输出控制电路包括：
第九晶体管，所述第九晶体管的控制极与第五节点耦接，所述第九晶体管的第一极与第二电源端耦接，所述第九晶体管的第二极与所述第一信号输出端耦接
第三电容，所述第三电容的第一极与所述第五节点耦接，所述第三电容的第二极与所述第二电源端耦接。
在一些实施例中，所述第一输出控制电路还包括：
第六晶体管，所述第六晶体管的控制极与所述第三节点耦接，所述第六晶体管的第一极与所述第二时钟信号线耦接以接收所述第二时钟信号，所述第六晶体管的第二极与第六节点耦接；
第七晶体管，所述第七晶体管的控制极与所述第二时钟信号线耦接以接收所述第二时钟信号，所述第七晶体管的第一极与所述第六节点耦接，所述第七晶体管的第二极与第五节点耦接；
第八晶体管，所述第八晶体管的控制极与所述第一节点耦接， 所述第八晶体管的第一极与所述第五节点耦接，所述第八晶体管的第二极与所述第二电源端耦接；
第十晶体管，所述第十晶体管的控制极与第四节点耦接，所述第十晶体管的第一极与所述第一信号输出端耦接，所述第十晶体管的第二极与所述第一电源端耦接，所述第一节点与所述第四节点耦接；
第二电容，所述第二电容的第一极与所述第三节点耦接，所述第二电容的第二极与所述第六节点耦接。
在一些实施例中，所述第二输出控制电路包括：
第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一晶体管的第二极与第七节点耦接；
第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第十二晶体管的第二极与所述第二电源端耦接；
第十三晶体管，所述第十三晶体管的控制极与所述第七节点耦接，所述第十三晶体管的第一极与所述第一时钟信号线耦接，所述第十三晶体管的第二极与第四电容的第一极耦接；
第四电容，所述第四电容的第二极与所述第七节点耦接；
第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
在一些实施例中，所述第二输出控制电路包括：
第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一晶体管的第二极与第七节点耦接；
第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第 十二晶体管的第二极与所述第二电源端耦接；
第十三晶体管，所述第十三晶体管的控制极与所述第七节点耦接，所述第十三晶体管的第一极与所述第二时钟信号线耦接，所述第十三晶体管的第二极与第四电容的第一极耦接；
第四电容，所述第四电容的第二极与所述第七节点耦接；
第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
在一些实施例中，所述第二输出控制电路包括：
第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一晶体管的第二极与第七节点耦接；
第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第十二晶体管的第二极与所述第二电源端耦接；
第四电容，所述第四电容的第一极与所述第一时钟信号线或所述第二时钟信号线耦接，所述第四电容的第二极与所述第七节点耦接；
第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
在一些实施例中，所述第二输出控制电路包括：
第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一 晶体管的第二极与第七节点耦接；
第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第十二晶体管的第二极与所述第二电源端耦接；
第四电容，所述第四电容的第一极与所述第二时钟信号线耦接，所述第四电容的第二极与所述第七节点耦接；
第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
在一些实施例中，所述移位寄存器还包括：
限压晶体管，所述第一节点通过所述限压晶体管与所述第四节点耦接；
所述限压晶体管的控制极与所述第一电源端耦接，所述限压晶体管的第一极与所述第一节点耦接，所述限压晶体管的第二极与所述第四节点耦接。
第二方面，本公开过实施例还提供了一种驱动电路，包括：级联设置的多个移位寄存器，所述移位寄存器采用上述第一方面提供的所述移位寄存器；
位于第一级的移位寄存器的信号输入端与帧起始信号端耦接；
除位于第一级的移位寄存器外，位于其他级的移位寄存器的信号输入端与前一级移位寄存器的第一信号输出端耦接。
第三方面，本公开实施例还提供了一种显示基板，包括显示区域和围绕所述显示区域的周边区域，所述显示区域内设置有多个像素单元，每个像素单元配置有对应的发光控制信号线，所述周边区域内设置有发光控制驱动电路，所述发光控制驱动电路采用上述第二方面中所述驱动电路，所述发光控制驱动电路内各级所述移位寄存器的第一信号输出端与所述显示区域内对应的发光控制信号线耦接。
在一些实施例中，每个像素单元还配置有对应的重置信号线；
所述发光控制驱动电路内的所述移位寄存器内设置有第二输出控制电路，所述发光控制驱动电路内的所述移位寄存器的第二信号输出端与所述显示区域内对应的重置信号线耦接。
在一些实施例中，所述像素单元包括：像素电路和发光器件，所述像素电路包括：第一重置子电路、第二重置子电路、数据写入子电路、阈值补偿子电路、发光控制子电路和驱动晶体管；
所述第一重置子电路，与初始化电压端、所述驱动晶体管的控制极、对应的扫描控制信号线耦接，配置为响应于所述扫描控制信号线所提供扫描控制信号的控制将初始化电压端提供的初始化电压写入至所述驱动晶体管的控制极；
所述第二重置子电路，与所述初始化电压端、所述发光器件的第一端、对应的所述重置信号线耦接，配置为响应于所述重置信号线的控制将所述初始化电压写入至所述发光器件的第一端；
所述数据写入子电路，与所述驱动晶体管的第一极、对应的数据线、对应的扫描信号线耦接，配置为响应于所述扫描信号线的控制将所述数据线提供的数据电压写入至所述驱动晶体管的第一极；
所述阈值补偿子电路，与第二工作电压端、所述驱动晶体管的控制极、所述驱动晶体管的第一极、所述驱动晶体管的第二极耦接、对应的所述扫描信号线耦接，配置为响应于所述扫描信号线的控制将数据补偿电压写入至所述驱动晶体管的控制极，所述数据补充电压等于所述数据电压与所述驱动晶体管的阈值电压之和；
发光控制子电路，位于所述驱动晶体管的第二极和所述发光器件的第一端之间，且与发光控制信号线耦接，配置为响应于所述发光控制信号线所提供发光控制信号的控制以使得所述驱动晶体管的第二极与所述发光器件的第一端之间导通；
所述驱动晶体管配置为响应于所述数据补偿电压的控制输出相应的驱动电流；
所述发光器件的第二端与第一工作电压端耦接。
在一些实施例中，所述第一重置子电路包括第二十一晶体管， 所述第二重置子电路包括第二十二晶体管，所述数据写入子电路包括第二十三晶体管，所述阈值补偿子电路包括第二十四晶体管、第二十五晶体管和存储电容，所述发光控制子电路包括第二十六晶体管；
所述第二十一晶体管的控制极与所述扫描控制信号线耦接，所述第二十一晶体管的第一极与所述初始化电压端耦接，所述第二十一晶体管的第二极与所述驱动晶体管的控制极耦接；
所述第二十二晶体管的控制极与所述重置信号线耦接，所述第二十二晶体管的第一极与所述初始化电压端耦接，所述第二十二晶体管的第二极与所述发光器件的第一端耦接；
所述第二十三晶体管的控制极与所述扫描信号线耦接，所述第二十三晶体管的第一极与所述数据线耦接，所述第二十三晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第二十四晶体管的控制极与所述发光控制信号线耦接，所述第二十四晶体管的第一极与所述第二工作电压端耦接，所述第二十四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第二十五晶体管的控制极与所述扫描信号线耦接，所述第二十五晶体管的第一极与所述驱动晶体管的控制极耦接，所述第二十五晶体管的第二极与所述驱动晶体管的第二极耦接；
所述存储电容的第一端与所述第二工作电压端耦接，所述存储电容的第二端与所述驱动晶体管的控制极耦接；
所述第二十六晶体管的控制极与所述发光控制信号线耦接，所述第二十六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第二十六晶体管的第二极与所述发光器件的第一端耦接。
在一些实施例中，位于除第一行之外的其他行的任一所述像素单元，所述像素单元所耦接的所述扫描控制信号线，为前一行像素单元所配置的所述扫描信号线。
在一些实施例中，每个像素单元配置有对应的扫描信号线，所述周边区域内设置有扫描驱动电路；
所述发光控制驱动电路内各级所述移位寄存器的信号输出端与所述显示区域内对应的扫描信号线耦接。
附图说明
图1为本公开实施例所涉及的一种显示基板的结构示意图；
图2为本公开实施例提供的一种移位寄存器的电路结构示意图；
图3为图2所示移位寄存器的一种工作时序图；
图4为本公开实施例提供的另一种移位寄存器的电路结构示意图；
图5为图4所示移位寄存器的一种工作时序图；
图6为本公开实施例提供的又一种移位寄存器的电路结构示意图；
图7为图6所示移位寄存器的一种工作时序图；
图8为图6所示移位寄存器中存在阻抗晶体管与不存在阻抗晶体管时第一节点、第二节点以及第三节点电压变化对比示意图，
图9A为本公开实施例提供的再一种移位寄存器的电路结构示意图；
图9B为本公开实施例提供的再一种移位寄存器的电路结构示意图；
图10为图9B所示移位寄存器的一种工作时序图；
图11为本公开实施例提供的再一种移位寄存器的电路结构示意图；
图12为本公开实施例提供的再一种移位寄存器的电路结构示意图；
图13为图12所示移位寄存器的一种工作时序图；
图14为本公开实施例提供的再一种移位寄存器的电路结构示意图；
图15为本公开实施例中位于周边区域中的一个驱动电路的一种电路结构示意图；
图16为本公开实施例中位于周边区域中的一个驱动电路的另一种电路结构示意图；
图17为本公开实施例像素单元的一种电路结构示意图；
图18为本公开实施例中一个像素单元与位于周边区域内的驱动电路的电路连接示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种移位寄存器、显示基板和显示装置进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其他特征、整体、步骤、操作、元件、组件和/或其群组。
将理解的是，虽然本文可以使用术语第一、第二等来描述各种元件/指令/请求，但这些元件/指令/请求不应当受限于这些术语。这些术语仅用于区分一个元件元件/指令/请求和另一元件元件/指令/请求。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
需要说明的是，在本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他具有相同、类似特性的器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，晶体管的控制极具体是指晶体管的栅极；为区分晶 体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以P型晶体管进行说明的，当采用P型晶体管时，第一极为P型晶体管的漏极，第二极为P型晶体管的源极，N型相反。可以想到的是采用N型晶体管来实现下述实施例的技术方案，是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内。
本公开中的“有效电平”是指能够控制相应晶体管导通的电平；具体地，针对P型晶体管，其所对应的有效电平为低电平；针对N型晶体管，其所对应的有效电平为高电平。
在以晶体管采用P型晶体管的情况中，第一电源端提供的电源电压为低电平电压VGL(一般地，VGL小于0V)，第二电源端提供的电源电压为高电平电压VGH(一般地，VGH为大于0V)。
图1为本公开实施例所涉及的一种显示基板的结构示意图，如图1所示，显示基板包括显示区域A和围绕显示区域A的非显示区域B，显示区域A内设置有呈阵列排布的多个像素单元，像素单元内设置有像素电路和发光器件，每个像素电路配置有对应的多条驱动信号线DSL，例如扫描信号线(也称为栅线)、发光控制信号线、重置信号线等，这些驱动信号线DSL用于控制像素电路进行工作。非显示区域内设置有用于向各类驱动信号线提供驱动信号的多个驱动电路DC(附图中仅示例性画出一个驱动电路)，其中驱动电路DC包括级联的多个移位寄存器SR，每个移位寄存器SR的信号输出端与对应的驱动信号线DSL相连，以向对应的驱动信号线DSL输出相应驱动信号。
在实际应用中发现，现有栅极驱动电路内移位寄存器的工作状态不稳定，容易出现输出异常的问题，从而导致像素单元出现异常显示。针对上述技术问题，本公开实施例提供了相应的解决方案。
图2为本公开实施例提供的一种移位寄存器的电路结构示意图，如图2所示，本公开实施例提供的移位寄存器包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、阻抗晶体管M_R、第一电容C1和第一输出控制电路1。
其中，第一晶体管M1的控制极与第一时钟信号线CK耦接以接收第一时钟信号，第一晶体管M1的第一极与信号输入端INPUT耦接，第一晶体管M1的第二极与第一节点N1耦接。
第二晶体管M2的控制极与第一节点N1耦接，第二晶体管M2的第一极与第二节点N2耦接，第二晶体管M2的第二极和第一时钟信号线CK耦接以接收第一时钟信号。
第三晶体管M3的控制极与第一时钟信号线CK耦接以接收第一时钟信号，第三晶体管M3的第一极与第一电源端耦接，第三晶体管M3的第二极与第二节点N2耦接。
第四晶体管M4的控制极与第二时钟信号线CKB耦接以接收第二时钟信号，第四晶体管M4的第一极与第五晶体管M5的第二极耦接，第四晶体管M4的第二极与第一节点N1耦接。
第五晶体管M5的控制极与第三节点N3耦接，第五晶体管M5的第一极与第二电源端耦接。
第一电容C1的第一极与第四节点N4耦接，第一电容C1的第二极与第二时钟信号线CKB耦接，第一节点N1与第四节点N4耦接。
阻抗晶体管M_R的控制极与第一电源端耦接，阻抗晶体管M_R的第一极与第二节点N2耦接，阻抗晶体管M_R的第二极与第三节点N3耦接。
第一输出控制电路1与第三节点N3、第四节点N4和第一信号输出端OUT1耦接，第一输出控制电路1配置为响应于第三节点N3、第四节点N4处信号的控制向第一信号输出端OUT1输出第一驱动信号。
需要说明的是，本公开中的“耦接”表示两个或多个结构之间电连接，其连接方式并不限于直接连接。
在移位寄存器的工作过程中，当第二时钟信号线CKB中的第二时钟信号由高电平状态切换为低电平状态时，第四节点N4和第一节点N1处的电压会在极短的时间内被拉低，此时第二晶体管M2会存在因第一节点N1被拉低而出现误导通的风险，在第二晶体管M2误导通的时段内，处于高电平状态的第一时钟信号会通过第二晶体管M2对第二节点N2、第三节点N3进行误充电，使得与第三节点N3处电压 被异常上拉，与第三节点N3相连的第四晶体管M4和第一输出控制电压出现工作异常，从而影响移位寄存器的正常工作；随着产品使用时间的增长，第二晶体管M2的阈值电压产生漂移，第二晶体管M2误导通的风险更大。
在本公开实施例中，为克服上述技术问题，通过在第二节点N2与第三节点N3之间设置阻抗晶体管M_R，阻抗晶体管M_R的控制极与第一电源端相连处于常导通状态，处于导通状态的阻抗晶体管M_R可在第二节点N2与第三节点N3之间存在电流时对电流产生一定的阻碍，即阻抗晶体管M_R可产生阻抗作用，以减小在第二晶体管M2误导通时第一时钟信号对第三节点N3处电压的上拉影响，有利于维持第三节点N3处电平状态的稳定性，使得在第二晶体管M2误导通过程中第三节点N3处始终处于低电平状态。
下面将结合具体时序来进行详细描述。图3为图2所示移位寄存器的一种工作时序图，如图3所示，在下面描述中仅对第一晶体管M1～第五晶体管M5的工作状态进行详细描述，而对于第一输出控制电路1的具体工作过程将在后面结合具体示例进行描述，该移位寄存器的工作过程包括如下阶段：
第一阶段t1，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，信号输入端INPUT提供的信号处于高电平状态。
具体地，第一时钟信号处于低电平状态，第一晶体管M1和第三晶体管M3均导通；第二时钟信号处于高电平状态，第四晶体管M4截止。
信号输入端INPUT提供处于高电平状态的信号通过第一晶体管M1写入至第一节点N1，第一节点N1处于高电平状态，第二晶体管M2处于截止状态；与此同时，第二节点N2通过第三晶体管M3进行放电，第二节点N2处于低电平状态(电压略高于VGL)；阻抗晶体管M_R的栅源电压为负值，阻抗晶体管M_R处于导通状态，第三节点N3通过第二节点N2进行放电，第三节点N3处于低电平状态(电压略高于第二节点N2处电压)；由于第三节点N3处于低电平状态，因 此第五晶体管M5导通。
第一阶段t1结束时，第一节点N1处于高电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于高电平状态。
第二阶段t2，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，信号输入端INPUT提供的信号处于高电平状态。
具体地，第一时钟信号处于高电平状态，第一晶体管M1和第三晶体管M3均截止；第二时钟信号处于低电平状态，第四晶体管M4导通。
在不考虑第一输出控制电路1对第三节点N3处电压影响的情况下，由于第三晶体管M3截止，因此第三节点N3处于浮接状态以维持第一阶段t1时的低电平状态。
需要说明的是，在第二阶段t2的初始时刻，第二时钟信号由高电平切换为低电平，在第一电容C1的自举作用下，第四节点N4和第一节点N1处的电压被下拉，此时第二晶体管M2存在误导通风险。在本申请中，即便第二晶体管M2出现了短暂的误导通，由于在第二节点N2和第三节点N3之间设置有阻抗晶体管M_R，因此处于高电平状态的第一时钟信号对第三节点N3处电压影响极小，第三节点N3处电平可始终维持于低电平状态，第五晶体管M5维持导通。
由于第四晶体管M4和第五晶体管M5均导通，因此第四节点N4处的电压会被高电平电压VGH会通过第五晶体管M5和第四晶体管M4来对第一节点N1和第四节点N4进行充电，以使得第一节点N1和第四节点N4处于高电平状态，处于误导通状态的第二晶体管M2也会立即切换至截止状态。
第二阶段t2结束时，第一节点N1处于高电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于高电平状态。
第三阶段t3，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态， 信号输入端INPUT提供的信号处于高电平状态。
第一晶体管M1～第五晶体管M5在第三阶段t3的工作过程与在第一阶段t1中的工作过程一致，具体可参见前面对第一阶段t1的相应描述。
第四阶段t4，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，信号输入端INPUT提供的信号处于低电平状态。
第一晶体管M1～第五晶体管M5在第四阶段t4的工作过程与在第二阶段t2中的工作过程一致，具体可参见前面对第二阶段t2的相应描述。
第五阶段t5，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，信号输入端INPUT提供的信号处于低电平状态。
具体地，第一时钟信号处于低电平状态，第一晶体管M1和第三晶体管M3均导通；第二时钟信号处于高电平状态，第四晶体管M4截止。
信号输入端INPUT提供处于低电平状态的信号通过第一晶体管M1写入至第一节点N1，第一节点N1处于低电平状态，第二晶体管M2处于导通状态，第二节点N2通过第二晶体管M2和第三晶体管M3进行放电，第二节点N2处于低电平状态；阻抗晶体管M_R的栅源电压为负值，阻抗晶体管M_R处于导通状态，第三节点N3通过第二节点N2进行放电，第三节点N3处于低电平状态；由于第三节点N3处于低电平状态，因此第五晶体管M5导通。
第五阶段t5结束时，第一节点N1处于低电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于低电平状态。
第六阶段t6，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，信号输入端INPUT提供的信号处于低电平状态。
具体地，第一时钟信号处于高电平状态，第一晶体管M1和第三 晶体管M3均截止；第二时钟信号处于低电平状态，第四晶体管M4导通。
在第二时钟信号由高电平切换为低电平，在第一电容C1的自举作用下，第四节点N4处电压由近似等于VGL被下拉至近似等于2VGL，第一节点N1和第四节点N4均处于低电平状态。第二晶体管M2处于导通状态(第二晶体管M2正常导通)，处于高电平状态的第一时钟信号通过第二晶体管M2向第二节点N2进行充电，第二节点N2和第三节点N3处于高电平状态，第五晶体管M5截至。
第六阶段t6结束时，第一节点N1处于低电平状态，第二节点N2处于高电平状态，第三节点N3处于高电平状态，第四节点N4处于低电平状态。
在此后过程中，移位寄存器交替执行上述第五阶段t5和第六阶段t6，直至下一周期开始。
基于上述内容可见，本公开的技术方案可使得在第二阶段t2和第四阶段t4过程中避免因第二晶体管M2误开启而使得第三节点N3被异常上拉至高电平状态的问题，从而能保证第三节点N3在第二阶段t2和第四阶段t4过程中始终处于低电平状态，进而保证了移位寄存器的正常工作。
图4为本公开实施例提供的另一种移位寄存器的电路结构示意图，如图4所示，图4所示移位寄存器为基于图2所示移位寄存器的一种具体可选实施方案；其中，第一输出控制电路1包括：第九晶体管M9和第三电容C3。
其中，第九晶体管M9的控制极与第五节点N5耦接，第九晶体管M9的第一极与第二电源端耦接，第九晶体管M9的第二极与第一信号输出端OUT1耦接；第三电容C3的第一极与第五节点N5耦接，第三电容C3的第二极与第二电源端耦接。
在一些实施例中，第一输出控制电路1还包括：第六晶体管M6、第七晶体管M7、第八晶体管M8、第十晶体管M10和第二电容C2。
其中，第六晶体管M6的控制极与第三节点N3耦接，第六晶体管M6的第一极与第二时钟信号线CKB耦接以接收第二时钟信号，第 六晶体管M6的第二极与第六节点N6耦接；第七晶体管M7的控制极与第二时钟信号线CKB耦接以接收第二时钟信号，第七晶体管M7的第一极与第六节点N6耦接，第七晶体管M7的第二极与第五节点N5耦接；第八晶体管M8的控制极与第一节点N1耦接，第八晶体管M8的第一极与第五节点N5耦接，第八晶体管M8的第二极与第二电源端耦接；第十晶体管M10的控制极与第四节点N4耦接，第十晶体管M10的第一极与第一信号输出端OUT1耦接，第十晶体管M10的第二极与第一电源端耦接，第一节点N1与第四节点N4耦接；第二电容C2的第一极与第三节点N3耦接，第二电容C2的第二极与第六节点N6耦接。
图5为图4所示移位寄存器的一种工作时序图，如图5所示，第一时钟信号线CK提供的第一时钟信号、第二时钟信号线CKB提供的第二时钟信号和信号输入端INPUT提供的信号在各阶段中的电平状态，以及第一晶体管M1～第五晶体管M5在各阶段状态的工作状态，可参见对图2和图3的相应描述此处不再赘述，下面仅对第一输出控制电路1的具体工作过程进行详细描述。
第一阶段t1，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，第一节点N1处于高电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于高电平状态。
具体地，第二时钟信号处于高电平状态，第七晶体管M7截止。由于第三节点N3处于低电平状态，因此第六晶体管M6导通，处于高电平状态的第二时钟信号通过第六晶体管M6写入至第六节点N6，第六节点N6处于高电平状态。与此同时，由于第一节点N1和第四节点N4均处于高电平状态，因此第八晶体管M8和第十晶体管M10均截止。
由于第七晶体管M7和第八晶体管M8均截止，因此第五节点N5处于浮接状态，第五节点N5维持前一阶段(前一周期的最后一个阶段)的高电平状态，第九晶体管M9截止。
由于第九晶体管M9和第十晶体管M10均截止，因此第一信号输出端OUT1处于浮接状态，第一信号输出端OUT1维持前一阶段(前一 周期的最后一个阶段)的低电平状态，即第一信号输出端OUT1输出低电平信号。
第二阶段t2，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，第一节点N1处于高电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于高电平状态。
具体地，第二时钟信号处于低电平状态，第七晶体管M7导通。由于第三节点N3处于低电平状态，因此第六晶体管M6导通，处于低电平状态的第二时钟信号通过第六晶体管M6写入至第六节点N6，第六节点N6处于低电平状态。由于第六节点N6处电压由高电平状态切换为低电平状态，在第二电容C2的自举作用下，第三节点N3处的电压被下拉至更低水平。需要说明的是，即便此时第二晶体管M2发生了误导通而使得处于高电平状态的第一时钟信号对第二节点N2和第三节点N3进行上拉，但由于阻抗晶体管M_R的存在，第二电容C2对第三节点N3的下拉影响起到的主导作用，因此第三节点N3处的电压整体呈现被下拉的趋势，以进一步保证在第二阶段t2过程中第三节点N3始终处于低电平状态，在第二电容C2对第三节点N3处电压进行下拉过程中，第三节点N3处电压由近似等于VGL被下拉至近似等于2VGL，此时阻抗晶体管M_R的栅源电压会大于阻抗晶体管M_R的阈值电压，阻抗晶体管M_R由导通状态切换至截止状态。
由于第六晶体管M6和第七晶体管M7导通，因此处于低电平状态的第二时钟信号通过第六晶体管M6和第七晶体管M7写入至第五节点N5，第五节点N5处于低电平状态。与此同时，由于第一节点N1和第四节点N4均处于高电平状态，因此第八晶体管M8和第十晶体管M10均截止。
由于第九晶体管M9处于导通状态且第十晶体管M10处于截止状态，因此高电平电压VGH通过第九晶体管M9写入至第一信号输出端OUT1，第一信号输出端OUT1输出高电平信号。
第三阶段t3，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态， 第一节点N1处于高电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于高电平状态。
具体地，第二时钟信号处于高电平状态，第七晶体管M7截止。由于第三节点N3处于低电平状态，因此第六晶体管M6导通，处于高电平状态的第二时钟信号通过第六晶体管M6写入至第六节点N6，第六节点N6处于高电平状态。由于第三晶体管M3导通，低电平电压VGL通过第三晶体管M3、阻抗晶体管M_R写入至第三节点N3，第三节点N3仍处于低电平状态且电压近似等于VGL。与此同时，由于第一节点N1和第四节点N4均处于高电平状态，因此第八晶体管M8和第十晶体管M10均截止。
由于第七晶体管M7和第八晶体管M8均截止，因此第五节点N5处于浮接状态，第五节点N5维持前一阶段(第二阶段t2)的低电平状态，第九晶体管M9维持导通截止。
由于第九晶体管M9和第十晶体管M10均截止，因此第一信号输出端OUT1处于浮接状态，第一信号输出端OUT1维持前一阶段(前一周期的最后一个阶段)的的高电平状态，即第一信号输出端OUT1输出高电平信号。
由于第九晶体管M9处于导通状态且第十晶体管M10处于截止状态，因此高电平电压VGH通过第九晶体管M9写入至第一信号输出端OUT1，第一信号输出端OUT1维持输出高电平信号。
第四阶段t4，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，第一节点N1处于高电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于高电平状态。
具体地，第二时钟信号处于低电平状态，第七晶体管M7导通。由于第三节点N3处于低电平状态，因此第六晶体管M6导通，处于低电平状态的第二时钟信号通过第六晶体管M6写入至第六节点N6，第六节点N6处于低电平状态。由于第六节点N6处电压由高电平状态切换为低电平状态，在第二电容C2的自举作用下，第三节点N3处的电压被下拉至更低水平。需要说明的是，即便此时第二晶体管M2发生 了误导通而使得处于高电平状态的第一时钟信号对第三节点N3进行上拉，但由于阻抗晶体管M_R的存在，第二电容C2对第三节点N3的影响起到的主导作用，因此第三节点N3处的电压整体呈现被下拉的趋势，以进一步保证在第二阶段t2过程中第三节点N3始终处于低电平状态，在第二电容C2对第三节点N3处电压进行下拉过程中，第三节点N3处电压由近似等于VGL被下拉至近似等于2VGL。
由于第六晶体管M6和第七晶体管M7导通，因此处于低电平状态的第二时钟信号通过第六晶体管M6和第七晶体管M7写入至第五节点N5，第五节点N5处于低电平状态。与此同时，由于第一节点N1和第四节点N4均处于高电平状态，因此第八晶体管M8和第十晶体管M10均截止。
由于第九晶体管M9处于导通状态且第十晶体管M10处于截止状态，因此高电平电压VGH通过第九晶体管M9写入至第一信号输出端OUT1，第一信号输出端OUT1输出高电平信号。
第五阶段t5，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，第一节点N1处于低电平状态，第二节点N2处于低电平状态，第三节点N3处于低电平状态，第四节点N4处于低电平状态。
具体地，第二时钟信号处于高电平状态，第七晶体管M7截止。由于第三节点N3处于低电平状态，因此第六晶体管M6导通，处于高电平状态的第二时钟信号通过第六晶体管M6写入至第六节点N6，第六节点N6处于高电平状态。由于第三晶体管M3导通，低电平电压VGL通过第三晶体管M3、阻抗晶体管M_R写入至第三节点N3，第三节点N3仍处于低电平状态且电压近似等于VGL。
由于第一节点N1处于低电平状态，因此第八晶体管M8导通，高电平电压VGH通过第八晶体管M8写入至第五节点N5，第五节点N5处于高电平状态，第九晶体管M9截止。与此同时，第四节点N4处于低电平状态且电压近似等于VGL，第十晶体管M10导通，第一信号输出端OUT1通过第十晶体管M10放电，当第一信号输出端OUT1电压下降至VN4-Vth_M10时(即第十晶体管M10的栅源电源等于Vth_M10 时，其中VN4为第四节点N4处电压且近似等于VGL，Vth_M10为第十晶体管M10的阈值电压且为负值)，第十晶体管M10切换至截止状态，第一信号输出端OUT1输出低电平信号且电压近似等于VGL-Vth_M10。
需要说明的是，在第五阶段t5过程中，当第一信号输出端OUT1的电压发生上升漂移时，第十晶体管M10的栅源电压会小于第十晶体管M10的阈值电压，此时第十晶体管M10会再次导通使得第一信号输出端OUT1的电压下降，直至第十晶体管M10的栅源电压等于第十晶体管M10的阈值电压时，第十晶体管M10再次截止。
第六阶段t6，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，第一节点N1处于低电平状态，第二节点N2处于高电平状态，第三节点N3处于高电平状态，第四节点N4处于低电平状态。
具体地，第二时钟信号处于低电平状态，第七晶体管M7导通。由于第三节点N3处于高电平状态，因此第六晶体管M6截止。由于第一节点N1处于低电平状态，第八晶体管M8导通，高电平电压VGH通过第八晶体管M8写入至第五节点N5，第五节点N5处于高电平状态，第九晶体管M9截止；与此同时，由于第七晶体管M7导通，因此高电平电压VGH可通过第八晶体管M8和第七晶体管M7对第六节点N6进行充电，第六节点N6处于高电平状态。
对于第四节点N4，由于第二时钟信号由高电平状态切换为低电平状态，第一电容C1的自举作用下，第四节点N4处电压由近似等于VGL被下拉至近似等于2VGL，第十晶体管M10再次导通，第一信号输出端OUT1通过第十晶体管M10放电；在不考虑第十晶体管M10阻抗的情况下，第一信号输出端OUT1处的电压可下降至VGL，第十晶体管M10的栅源电压始终小于第十晶体管M10的阈值电压，第十晶体管M10持续导通，第一信号输出端OUT1输出低电平信号且电压近似等于VGL。
需要说明的是，在移位寄存器交替执行第五阶段t5和第六阶段t6的过程中，虽然第四节点N4处的电压由近似等于VGL与近似等于2VGL之间进行切换，但第一信号输出端OUT1处电压始终维持于近似 等于VGL。
需要说明的是，在本公开实施例中第一输出控制电路1还可以采用其他结构，例如，第一输出控制电路1仅包括上述第九晶体管M9和第十晶体管M10，或者在包括上述第九晶体管M9和第十晶体管M10的基础上根据实际需要来增设一些其他晶体管。另外，移位寄存器的驱动时序也不限于图4中所示。
图6为本公开实施例提供的又一种移位寄存器的电路结构示意图，如图6所示，与图2和图4所示移位寄存器不同的是，在图6所示移位寄存器中还包括限压晶体管M_V，其中第一节点N1通过限压晶体管M_V与所述第四节点N4耦接。具体地，限压晶体管M_V的控制极与第一电源端耦接，限压晶体管M_V的第一极与第一节点N1耦接，限压晶体管M_V的第二极与第四节点N4耦接。
图7为图6所示移位寄存器的一种工作时序图，如图7所示，与图3和图5中所示第一节点N1与第四节点N4处电压同步变化不同的是，在图7所示时序中，在第六阶段t6内，当第四节点N4处电压被第一电容C1由近似等于VGL被下拉至近似等于2VGL时，限压晶体管M_V的栅源电压大于限压晶体管M_V的阈值电压，此时限压晶体管M_V由导通状态切换至截止状态，可防止第四节点N4处过低的电压(近似等于VGL)写入至第一节点N1，从而能避免第一晶体管M1、第二晶体管M2处于高压状态，进而能提升第一晶体管M1、第二晶体管M2的使用寿命。
图8为图6所示移位寄存器中存在阻抗晶体管与不存在阻抗晶体管时第一节点、第二节点以及第三节点电压变化对比示意图，参见图8所示，以第一时钟信号和第二时钟信号处于高电平状态时的电压为+7V、处于低电平状态时的电压为-7V为例进行仿真测试。
当未设置阻抗晶体管时，在第二阶段t2中，第二节点N2处的电压为-4.551V，第三节点N3处电压为-14.16V；当设置有本公开中的阻抗晶体管M_R时，在第二阶段t2中，第二节点N2处的电压为-5.245V，第三节点N3处电压为-16.4V。由此可见，通过设置上述阻抗晶体管M_R可使得第二节点N2和第三节点N3在第二阶段t2中被 下拉至更低水平，有利于保证第五晶体管M5控制极电压的稳定性。
图9A为本公开实施例提供的再一种移位寄存器的电路结构示意图，如图9A所示，与前面实施例中所示移位寄存器不同的是，图9A所示移位寄存器中还包括：第二输出控制电路2。
其中，第二输出控制电路2至少与第一信号输出端OUT1和第二信号输出端OUT2耦接，第二输出控制电路2配置为根据第一信号输出端OUT1所输出的第一驱动信号向第二信号输出端OUT2输出与第一驱动信号的相位相反的第二驱动信号。
第二输出控制电路2具体可以为具有反相处理功能的反相处理电路，第一信号输出端OUT1作为反相处理电路的一个信号输入端，第二信号输出端OUT2作为反相处理电路的一个信号输出端。
在本实施例中，一个移位寄存器具有两个信号输出端，该两个信号输出端可输出不同的驱动信号，因此可为不同的驱动信号线提供驱动信号，有利于减少非像素区域内所布置的驱动电路数量，有利于产品窄边框的实现。
作为一个具体示例，移位寄存器的第一信号输出端OUT1与像素电路所配置的发光控制信号线相连，移位寄存器的第二信号输出端OUT2与像素电路所配置的重置信号线相连，第一信号输出端OUT1所输出的第一驱动信号为发光控制信号，第二信号输出端OUT2所输出的第二驱动信号为重置信号。
图9B为本公开实施例提供的再一种移位寄存器的电路结构示意图，如图9B所示，图9B所示移位寄存器为基于图9A所示移位寄存器的一种具体可选实施方案，图9B中所示第一输出控制电路1采用图4和图6中所示，对于第一输出控制电路1的具体结构此处不再赘述。
在一些实施例中，第二输出控制电路2包括：第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15和第四电容C4。
其中，第十一晶体管M11的控制极与第五节点N5耦接，第十一晶体管M11的第一极与第一电源端耦接，第十一晶体管M11的第二极 与第七节点N7耦接；第十二晶体管M12的控制极与第一信号输出端OUT1耦接，第十二晶体管M12的第一极与第七节点N7耦接，第十二晶体管M12的第二极与第二电源端耦接；第十三晶体管M13的控制极与第七节点N7耦接，第十三晶体管M13的第一极与第一时钟信号线CK，第十三晶体管M13的第二极与第四电容C4的第一极耦接；第十四晶体管M14，第十四晶体管M14的控制极与第七节点N7耦接，第十四晶体管M14的第一极与第一电源端耦接，第十四晶体管M14的第二极与第二信号输出端OUT2耦接；第十五晶体管M15，第十五晶体管M15的控制极与第一信号输出端OUT1耦接，第十五晶体管M15的第一极与第二信号输出端OUT2耦接，第十五晶体管M15的第二极与第二电源端耦接；第四电容C4的第二极与第七节点N7耦接。
图10为图9B所示移位寄存器的一种工作时序图，如图10所示，第一晶体管M1～第十晶体管M10在各阶段状态的工作状态，可参见前面实施例中相应描述此处不再赘述，下面仅对第二输出控制电路2的具体工作过程进行详细描述。
第一阶段t1，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，第五节点N5处于高电平状态，第一信号输出端OUT1处于低电平状态。
由于第五节点N5处于高电平状态，第一信号输出端OUT1处于低电平状态，因此第十一晶体管M11截止，第十二晶体管M12和第十五晶体管M15导通，高电平电压VGH通过第十二晶体管M12写入至第七节点N7，第七节点N7处于高电平状态，第十四晶体管M14截止。
由于第十四晶体管M14处于截止状态且第十五晶体管M15处于导通状态，因此高电平电压VGH通过第十五晶体管M15写入至第二信号输出端OUT2，第二信号输出端OUT2输出高电平信号。
第二阶段t2，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，第五节点N5处于低电平状态，第一信号输出端OUT1处于高电平状态。
由于第五节点N5处于低电平状态，第一信号输出端OUT1处于高电平状态，因此第十一晶体管M11导通，第十二晶体管M12和第十 五晶体管M15截止，低电平电压VGL通过第十二晶体管M12写入至第七节点N7，第七节点N7处于低电平状态且电压近似等于VGL，第十三晶体管M13和第十四晶体管M14导通，第二信号输出端OUT2通过第十四晶体管M14放电，当第十四晶体管M14的电压下降至VGL-Vth_M14时(即第十四晶体管M14的栅源电源等于Vth_M14时，其中VN7为第七节点N7处电压且近似等于VGL，Vth_M14为第十四晶体管M14的阈值电压且为负值)，第十四晶体管M14切换至截止状态，第二信号输出端OUT2输出低电平信号且电压近似等于VGL-Vth_M14。
需要说明的是，在第二阶段t2过程中，当第二信号输出端OUT2的电压发生上升漂移时，第十四晶体管M14的栅源电压会小于第十四晶体管M14的阈值电压，此时第十四晶体管M14会再次导通使得第二信号输出端OUT2的电压下降，直至第十四晶体管M14的栅源电压等于第十四晶体管M14的阈值电压时，第十四晶体管M14再次截止。
第三阶段t3，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，第五节点N5处于低电平状态，第一信号输出端OUT1处于高电平状态。
在第三阶段t3初始时刻，由于第五节点N5处于高低电平状态，第一信号输出端OUT1处于高电平状态，因此第十一晶体管M11导通，第十二晶体管M12和第十五晶体管M15截止，低电平电压VGL通过第十二晶体管M12写入至第七节点N7，第七节点N7处于低电平状态，第十三晶体管M13和第十四晶体管M14导通。
当第一时钟信号由高电平状态切换至低电平状态时，在第四电容C4的自举作用下，第七节点N7处的电压由近似等于VGL被下拉至近似等于2VGL，第十四晶体管M14再次导通，第二信号输出端OUT2通过第十四晶体管M14放电；在不考虑第十四晶体管M14阻抗的情况下，第二信号输出端OUT2处的电压可下降至VGL，第十四晶体管M14的栅源电压始终小于第十四晶体管M14的阈值电压，第十四晶体管M14持续导通，第二信号输出端OUT2输出低电平信号且电压近似等于VGL。
第四阶段t4，第一时钟信号线CK提供的第一时钟信号处于高电 平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，第五节点N5处于低电平状态，第一信号输出端OUT1处于高电平状态。
当第一时钟信号由高电平状态切换至低电平状态时，在第四电容C4的自举作用下，第七节点N7处的电压由近似等于2VGL被上拉至近似等于VGL，第十一晶体管M11导通，低电平电压VGL通过第十一晶体管M11写入至第七节点N7，第七节点N7维持低电平状态且电压近似等于VGL，第十四晶体管M14的栅源电压近似等于0，低十四晶体管截止；由于第一信号输出端OUT1输出高电平信号，因此第十二晶体管M12和第十五晶体管M15均截止。第二信号输出端OUT2处于浮接状态以维持前一阶段(第三阶段t3)的低电平状态，第二信号输出端OUT2输出低电平信号且电压近似等于VGL。
第五阶段t5，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，第五节点N5处于高电平状态，第一信号输出端OUT1处于低电平状态。
由于第五节点N5处于高电平状态，第一信号输出端OUT1处于低电平状态，因此第十一晶体管M11截止，第十二晶体管M12和第十五晶体管M15导通，高电平电压VGH通过第十二晶体管M12写入至第七节点N7，第七节点N7处于高电平状态，第十四晶体管M14截止。
由于第十四晶体管M14处于截止状态且第十五晶体管M15处于导通状态，因此高电平电压VGH通过第十五晶体管M15写入至第二信号输出端OUT2，第二信号输出端OUT2输出高电平信号。
第六阶段t6，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，第五节点N5处于高电平状态，第一信号输出端OUT1处于低电平状态。
第二输出控制电路2在第六阶段t6的工作过程与在第五阶段t5的工作过程一致，一致，具体可参见前面对第六阶段t6的相应描述。
图11为本公开实施例提供的再一种移位寄存器的电路结构示意图，如图11所示，与图9B所示移位寄存器内第二输出控制电路2不同的是，图11所示移位寄存器内第二输出控制电路2仅包括第十一晶体管M11、第十二晶体管M12、第十四晶体管M14、第十五晶体 管M15和第四电容C4而不包括第十三晶体管M13，且第四电容C4的第一极与第一时钟信号线CK耦接。图11所述移位寄存器的工作时序可采用图10中所示，具体过程此处不再赘述。
图12为本公开实施例提供的再一种移位寄存器的电路结构示意图，如图12所示，与图9B所示移位寄存器内第二输出控制电路2不同的是，图12所示移位寄存器内第十三晶体管M13的第一极与第二时钟信号线CKB耦接。
图13为图12所示移位寄存器的一种工作时序图，如图13所示，第一晶体管M1～第十晶体管M10在各阶段状态的工作状态，可参见前面实施例中相应描述此处不再赘述，下面仅对第二输出控制电路2的具体工作过程进行详细描述。
对于图12所示移位寄存器内第二控制电路在第一阶段t1和第二阶段t2的工作过程，与图9B所示移位寄存器内第二控制电路在第一阶段t1和第二阶段t2的工作过程一致，此处不再赘述。
第三阶段t3，第一时钟信号线CK提供的第一时钟信号处于低电平状态，第二时钟信号线CKB提供的第二时钟信号处于高电平状态，第五节点N5处于低电平状态，第一信号输出端OUT1处于高电平状态。
由于第五节点N5处于低电平状态，第一信号输出端OUT1处于高电平状态，因此第十一晶体管M11导通，第十二晶体管M12和第十五晶体管M15截止，低电平电压VGL通过第十一晶体管M11写入至第七节点N7，第七节点N7处于低电平状态且电压近似等于VGL，第十四晶体管M14维持前一阶段(第二阶段t2)的截止状态，第二信号输出端OUT2输出低电平信号且电压近似等于VGL。
第四阶段t4，第一时钟信号线CK提供的第一时钟信号处于高电平状态，第二时钟信号线CKB提供的第二时钟信号处于低电平状态，第五节点N5处于低电平状态，第一信号输出端OUT1处于高电平状态。
当第二时钟信号由高电平状态切换至低电平状态时，在第四电容C4的自举作用下，第七节点N7处的电压由近似等于VGL被下拉至近似等于2VGL，第十四晶体管M14再次导通，第二信号输出端OUT2通过第十四晶体管M14放电；在不考虑第十四晶体管M14阻抗的情况 下，第二信号输出端OUT2处的电压可下降至VGL，第十四晶体管M14的栅源电压始终小于第十四晶体管M14的阈值电压，第十四晶体管M14持续导通，第二信号输出端OUT2输出低电平信号且电压近似等于VGL。
对于图12所示移位寄存器内第二控制电路在第五阶段t5和第六阶段t6的工作过程，与图9B所示移位寄存器内第二控制电路在第五阶段t5和第六阶段t6的工作过程一致，此处不再赘述。
图14为本公开实施例提供的再一种移位寄存器的电路结构示意图，如图14所示，与图12所示移位寄存器内第二输出控制电路2不同的是，图14所示移位寄存器内第二输出控制电路2仅包括第十一晶体管M11、第十二晶体管M12、第十四晶体管M14、第十五晶体管M15和第四电容C4而不包括第十三晶体管M13，且第四电容C4的第一极与第二时钟信号线CKB耦接。图14所述移位寄存器的工作时序可采用图13中所示，具体过程此处不再赘述。
需要说明的是，在本公开实施例中，移位寄存器内的第二输出控制电路2还可以采用其他具有反相处理功能的电路结构，此处不再一一举例。
基于同一个发明构思，本公开实施例还提供了一种驱动电路。图15为本公开实施例中位于周边区域中的一个驱动电路的一种电路结构示意图，如图15所示，驱动电路包括级级联设置的多个移位寄存器SR1/SR2.../SRm，其中移位寄存器SR1/SR2.../SRm可采用前面任一实施例所提供的移位寄存器。
具体地，位于第一级的移位寄存器SR1的信号输入端INPUT与帧起始信号端STV耦接，除位于第一级的移位寄存器SR1外，位于其他级的移位寄存器/SR2.../SRm的信号输入端与前一级的移位寄存器的第一信号输出端OUT1相连。
位于奇数级的移位寄存器SR1/SR3...的第一时钟信号端CK与第一时钟信号线CLK耦接，位于奇数级的移位寄存器SR1/SR3...的第二时钟信号端CKB与第二时钟信号线CLKB耦接；位于偶数级的移位寄存器SR2/SR4...的第一时钟信号端CK与第二时钟信号线CLKB 耦接，位于偶数级的移位寄存器SR2/SR4...的第二时钟信号端CKB与第一时钟信号线CLK耦接。各级移位寄存器SR1/SR2.../SRm的第一电源端与第一电源电压供给线(未示出)耦接，各级移位寄存器SR1/SR2.../SRm的第二电源端与第二电源电压供给线(未示出)相连。
各级移位寄存器SR1/SR2.../SRm的第一信号输出端OUT1与显示区域内对应的发光控制信号线EM1/EM2.../EMm耦接。示例性地，位于第i级移位寄存器SRi的第一信号输出端OUT1与显示区域内位于第i行像素单元所对应的发光控制线EMi耦接，其中i为正整数且小于等于m。
图16为本公开实施例中位于周边区域中的一个驱动电路的另一种电路结构示意图，如图16所示，在显示区域内每个像素单元还配置有对应的重置信号线时，驱动电路内各级移位寄存器SR1/SR2.../SRm中还设置有第二输出控制电路(包含第二信号输出端OUT2)，例如移位寄存器采用图9A、图9B、图11、图12、图14中所示情况；此时各级移位寄存器SR1/SR2.../SRm的第一信号输出端OUT1与显示区域内对应的发光控制信号线EM1/EM2.../EMm耦接，各级移位寄存器SR1/SR2.../SRm的第二信号输出端OUT2与显示区域内对应的重置信号线RST1/RST2.../RSTm相连。
示例性地，位于第i级移位寄存器SRi的第一信号输出端OUT1与显示区域内位于第i行像素单元所对应的发光控制线EMi耦接，位于第i级移位寄存器SRi的第二信号输出端OUT2与显示区域内位于第i行像素单元所对应的重置信号线RSTi耦接，其中i为正整数且小于等于m。
继续参见图1，基于同一发明构思，本公开实施例还提供了一种显示基板，该显示基板包括：显示区域A和围绕显示区域A的周边区域B，显示区域A内设置有呈阵列排布的多个像素单元，每个像素单元配置有对应的发光控制信号线，周边区域B内设置有发光控制驱动电路，发光控制驱动电路包括级联设置的多个移位寄存器，发光控制驱动电路内的移位寄存器采用前面任一实施例提供的移位寄存器，发 光控制驱动电路内的移位寄存器的第一信号输出端OUT1与显示区域内对应的发光控制信号线耦接。对于本实施例中发光控制驱动电路和发光控制驱动电路内移位寄存器的描述可参见前面实施例中的内容，此处不再赘述。
在本公开过实施例中，像素单元内设置有像素电路和发光器件。本公开中的发光器件是指包括有机发光二极管(Organic Light Emitting Diode，简称OLED)、发光二极管(Light Emitting Diode，简称LED)等电流驱动型的发光元件，本公开实施例中将以发光器件为OLED为例进行示例性描述，其中发光器件的第一端和第二端分别是指阳极端和阴极端。
图17为本公开实施例像素单元的一种电路结构示意图，如图17所示，像素单元包括：像素电路和发光器件，像素电路包括：第一重置子电路21、第二重置子电路22、数据写入子电路23、阈值补偿子电路24、发光控制子电路25和驱动晶体管DTFT。
其中，第一重置子电路21与初始化电压端、驱动晶体管DTFT的控制极、对应的扫描控制信号线SC耦接，配置为响应于扫描控制信号线SC所提供扫描控制信号的控制将初始化电压端提供的初始化电压写入至驱动晶体管DTFT的控制极。
第二重置子电路22与初始化电压端、发光器件OLED的第一端、对应的重置信号线RST耦接，配置为响应于重置信号线RST的控制将初始化电压写入至发光器件OLED的第一端。
数据写入子电路23与驱动晶体管DTFT的第一极、对应的数据线DATA、对应的扫描信号线GATE耦接，配置为响应于扫描信号线GATE的控制将数据线DATA提供的数据电压写入至驱动晶体管DTFT的第一极。
阈值补偿子电路24与第二工作电压端、驱动晶体管DTFT的控制极、驱动晶体管DTFT的第一极、驱动晶体管DTFT的第二极耦接、对应的扫描信号线GATE耦接，配置为响应于扫描信号线GATE的控制将数据补偿电压写入至驱动晶体管DTFT的控制极，数据补充电压等于数据电压与驱动晶体管DTFT的阈值电压之和。
发光控制子电路25位于驱动晶体管DTFT的第二极和发光器件OLED的第一端之间，且与发光控制信号线EM耦接，配置为响应于发光控制信号线EM所提供发光控制信号的控制以使得驱动晶体管DTFT的第二极与发光器件OLED的第一端之间导通。
驱动晶体管DTFT配置为响应于数据补偿电压的控制输出相应的驱动电流，发光器件OLED的第二端与第一工作电压端耦接。
在一些实施例中，第一重置子电路21包括第二十一晶体管M21，第二重置子电路22包括第二十二晶体管M22，数据写入子电路23包括第二十三晶体管M23，阈值补偿子电路24包括第二十四晶体管M24、第二十五晶体管M25和存储电容CST，发光控制子电路25包括第二十六晶体管M26。
其中，第二十一晶体管M21的控制极与扫描控制信号线SC耦接，第二十一晶体管M21的第一极与初始化电压端耦接，第二十一晶体管M21的第二极与驱动晶体管DTFT的控制极耦接；第二十二晶体管M22的控制极与重置信号线RST耦接，第二十二晶体管M22的第一极与初始化电压端耦接，第二十二晶体管M22的第二极与发光器件OLED的第一端耦接；第二十三晶体管M23的控制极与扫描信号线GATE耦接，第二十三晶体管M23的第一极与数据线DATA耦接，第二十三晶体管M23的第二极与驱动晶体管DTFT的第一极耦接；第二十四晶体管M24的控制极与发光控制信号线EM耦接，第二十四晶体管M24的第一极与第二工作电压端耦接，第二十四晶体管M24的第二极与驱动晶体管DTFT的第一极耦接；第二十五晶体管M25的控制极与扫描信号线GATE耦接，第二十五晶体管M25的第一极与驱动晶体管DTFT的控制极耦接，第二十五晶体管M25的第二极与驱动晶体管DTFT的第二极耦接；存储电容CST的第一端与第二工作电压端耦接，存储电容CST的第二端与驱动晶体管DTFT的控制极耦接；第二十六晶体管M26的控制极与发光控制信号线EM耦接，第二十六晶体管M26的第一极与驱动晶体管DTFT的第二极耦接，第二十六晶体管M26的第二极与发光器件OLED的第一端耦接。
其中，初始化电压端提初始化电压VINIT，第一工作电压端提供 第一工作电压VDD，第二工作电压端提供的第二工作电压VSS。
图18为本公开实施例中一个像素单元与位于周边区域内的驱动电路的电路连接示意图，如图18所示，在一些实施例中，位于除第一行之外的其他行的任一像素单元，像素单元所耦接的扫描控制信号线，为前一行像素单元所配置的扫描信号线。此时扫描信号线可以实现复用，无需再额外设置扫描控制信号线，有利于减少布线空间。
针对图18中所示像素单元，显示基板的周边区域配置有2个驱动电路：发光控制驱动电路GOA_1和扫描驱动电路GOA_2，其中发光控制驱动电路GOA_1用于提供发光控制信号和重置信号，扫描驱动电路GOA_2用于提供扫描信号。
以图18中所示像素单元为第n行的像素单元为例，该像素单元所配置的发光控制信号线EM(n)与发光控制驱动电路GOA_1内位于第n级的移位寄存器SRn的第一信号输出端OUT1耦接，该像素单元所配置的重置信号线RST(n)与发光控制驱动电路GOA_1内位于第n级的移位寄存器SRn的第二信号输出端OUT2耦接，该像素单元所配置的扫描信号线GATE(n)与扫描驱动电路GOA_2内位于第n级的移位寄存器SR'n(具体电路结构为本领域的常规技术)的信号输出端OUT耦接，该像素单元所配置的扫描控制信号线为位于第n-1行的扫描信号线GATE(n-1)，扫描信号线GATE(n-1)与扫描驱动电路GOA_2内位于第n-1级的移位寄存器SR'n-1的信号输出端OUT耦接。
在本公开实施例中，由于重置信号和发光控制信号由同一驱动电路所输出，从而能确保重置信号与发光控制信号的同步输出；另外，发光控制信号通常采用了脉宽调制(Pulse Width Modulation，简称PWM)功能，使其在一帧显示时间内具有多个脉冲的输出，由于本公开中重置信号与发光控制信号同步输出且相位相反，因此第二重置子电路22会在一帧显示时间内多次开启以对发光器件OLED进行多次复位，从而能提高发光器件OLED的使用寿命、减少PWM下不同的发光控制信号脉冲控制发光器件发光之间的发光亮度差异等优点。
需要说明的是，图17和图18中所示像素电路包含7个晶体管和1个电容(又称为7T1C电路)的情况仅起到示例作用，其不会对 本公开的技术方案产生限制，本公开的技术方案还可以适用于其他像素电路。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (16)

  1. 一种移位寄存器，其中，包括：
    第一晶体管，所述第一晶体管的控制极与第一时钟信号线耦接以接收第一时钟信号，所述第一晶体管的第一极与信号输入端耦接，所述第一晶体管的第二极与第一节点耦接；
    第二晶体管，所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与第二节点耦接，所述第二晶体管的第二极与所述第一时钟信号线耦接以接收所述第一时钟信号；
    第三晶体管，所述第三晶体管的控制极与所述第一时钟信号线耦接以接收所述第一时钟信号，所述第三晶体管的第一极与第一电源端耦接，所述第三晶体管的第二极与所述第二节点耦接；
    第四晶体管，所述第四晶体管的控制极与第二时钟信号线耦接以接收第二时钟信号，所述第四晶体管的第一极与第五晶体管的第二极耦接，所述第四晶体管的第二极与所述第一节点耦接；
    第五晶体管，所述第五晶体管的控制极与第三节点耦接，所述第五晶体管的第一极与第二电源端耦接；
    第一电容，所述第一电容的第一极与第四节点耦接，所述第一电容的第二极与所述第二时钟信号线耦接，第一节点与所述第四节点耦接；
    阻抗晶体管，所述阻抗晶体管的控制极与所述第一电源端耦接，所述阻抗晶体管的第一极与所述第二节点耦接，所述阻抗晶体管的第二极与所述第三节点耦接；
    以及，第一输出控制电路，与所述第三节点、所述第四节点和第一信号输出端耦接，配置为响应于所述第三节点、所述第四节点处信号的控制向所述第一信号输出端输出第一驱动信号。
  2. 根据权利要求1所述的移位寄存器，其中，还包括：
    第二输出控制电路，至少与所述第一信号输出端和第二信号输出端耦接，配置为根据所述第一信号输出端所输出的第一驱动信号向 所述第二信号输出端输出与所述第一驱动信号的相位相反的第二驱动信号。
  3. 根据权利要求2所述的移位寄存器，其中，所述第一输出控制电路包括：
    第九晶体管，所述第九晶体管的控制极与第五节点耦接，所述第九晶体管的第一极与第二电源端耦接，所述第九晶体管的第二极与所述第一信号输出端耦接
    第三电容，所述第三电容的第一极与所述第五节点耦接，所述第三电容的第二极与所述第二电源端耦接。
  4. 根据权利要求3所述的移位寄存器，其中，所述第一输出控制电路还包括：
    第六晶体管，所述第六晶体管的控制极与所述第三节点耦接，所述第六晶体管的第一极与所述第二时钟信号线耦接以接收所述第二时钟信号，所述第六晶体管的第二极与第六节点耦接；
    第七晶体管，所述第七晶体管的控制极与所述第二时钟信号线耦接以接收所述第二时钟信号，所述第七晶体管的第一极与所述第六节点耦接，所述第七晶体管的第二极与第五节点耦接；
    第八晶体管，所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管的第一极与所述第五节点耦接，所述第八晶体管的第二极与所述第二电源端耦接；
    第十晶体管，所述第十晶体管的控制极与第四节点耦接，所述第十晶体管的第一极与所述第一信号输出端耦接，所述第十晶体管的第二极与所述第一电源端耦接，所述第一节点与所述第四节点耦接；
    第二电容，所述第二电容的第一极与所述第三节点耦接，所述第二电容的第二极与所述第六节点耦接。
  5. 根据权利要求3或4所述的移位寄存器，其中，所述第二输出控制电路包括：
    第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一晶体管的第二极与第七节点耦接；
    第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第十二晶体管的第二极与所述第二电源端耦接；
    第十三晶体管，所述第十三晶体管的控制极与所述第七节点耦接，所述第十三晶体管的第一极与所述第一时钟信号线耦接，所述第十三晶体管的第二极与第四电容的第一极耦接；
    第四电容，所述第四电容的第二极与所述第七节点耦接；
    第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
    第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
  6. 根据权利要求3或4所述的移位寄存器，其中，所述第二输出控制电路包括：
    第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一晶体管的第二极与第七节点耦接；
    第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第十二晶体管的第二极与所述第二电源端耦接；
    第十三晶体管，所述第十三晶体管的控制极与所述第七节点耦接，所述第十三晶体管的第一极与所述第二时钟信号线耦接，所述第十三晶体管的第二极与第四电容的第一极耦接；
    第四电容，所述第四电容的第二极与所述第七节点耦接；
    第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦 接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
    第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
  7. 根据权利要求3或4所述的移位寄存器，其中，所述第二输出控制电路包括：
    第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一晶体管的第二极与第七节点耦接；
    第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第十二晶体管的第二极与所述第二电源端耦接；
    第四电容，所述第四电容的第一极与所述第一时钟信号线耦接，所述第四电容的第二极与所述第七节点耦接；
    第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
    第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
  8. 根据权利要求3或4所述的移位寄存器，其中，所述第二输出控制电路包括：
    第十一晶体管，所述第十一晶体管的控制极与所述第五节点耦接，所述第十一晶体管的第一极与所述第一电源端耦接，所述第十一晶体管的第二极与第七节点耦接；
    第十二晶体管，所述第十二晶体管的控制极与所述第一信号输出端耦接，所述第十二晶体管的第一极与所述第七节点耦接，所述第 十二晶体管的第二极与所述第二电源端耦接；
    第四电容，所述第四电容的第一极与所述第二时钟信号线耦接，所述第四电容的第二极与所述第七节点耦接；
    第十四晶体管，所述第十四晶体管的控制极与所述第七节点耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
    第十五晶体管，所述第十五晶体管的控制极与所述第一信号输出端耦接，所述第十五晶体管的第一极与所述第二信号输出端耦接，所述第十五晶体管的第二极与所述第二电源端耦接。
  9. 根据权利要求1至8中任一所述的移位寄存器，其中，还包括：
    限压晶体管，所述第一节点通过所述限压晶体管与所述第四节点耦接；
    所述限压晶体管的控制极与所述第一电源端耦接，所述限压晶体管的第一极与所述第一节点耦接，所述限压晶体管的第二极与所述第四节点耦接。
  10. 一种驱动电路，其中，包括：级联设置的多个移位寄存器，所述移位寄存器采用上述权利要求1至9中任一所述的移位寄存器；
    位于第一级的移位寄存器的信号输入端与帧起始信号端耦接；
    除位于第一级的移位寄存器外，位于其他级的移位寄存器的信号输入端与前一级移位寄存器的第一信号输出端耦接。
  11. 一种显示基板，其中，包括显示区域和围绕所述显示区域的周边区域，所述显示区域内设置有多个像素单元，每个像素单元配置有对应的发光控制信号线，所述周边区域内设置有发光控制驱动电路，所述发光控制驱动电路采用上述权利要求10中所述驱动电路，所述发光控制驱动电路内各级所述移位寄存器的第一信号输出端与所述显示区域内对应的发光控制信号线耦接。
  12. 根据权利要求11所述的显示基板，其中，每个像素单元还配置有对应的重置信号线；
    所述发光控制驱动电路内的所述移位寄存器采用上述权利要求2至8中任一所述的移位寄存器，所述发光控制驱动电路内的所述移位寄存器的第二信号输出端与所述显示区域内对应的重置信号线耦接。
  13. 根据权利要求11或12所述的显示基板，其中，所述像素单元包括：像素电路和发光器件，所述像素电路包括：第一重置子电路、第二重置子电路、数据写入子电路、阈值补偿子电路、发光控制子电路和驱动晶体管；
    所述第一重置子电路，与初始化电压端、所述驱动晶体管的控制极、对应的扫描控制信号线耦接，配置为响应于所述扫描控制信号线所提供扫描控制信号的控制将初始化电压端提供的初始化电压写入至所述驱动晶体管的控制极；
    所述第二重置子电路，与所述初始化电压端、所述发光器件的第一端、对应的所述重置信号线耦接，配置为响应于所述重置信号线的控制将所述初始化电压写入至所述发光器件的第一端；
    所述数据写入子电路，与所述驱动晶体管的第一极、对应的数据线、对应的扫描信号线耦接，配置为响应于所述扫描信号线的控制将所述数据线提供的数据电压写入至所述驱动晶体管的第一极；
    所述阈值补偿子电路，与第二工作电压端、所述驱动晶体管的控制极、所述驱动晶体管的第一极、所述驱动晶体管的第二极耦接、对应的所述扫描信号线耦接，配置为响应于所述扫描信号线的控制将数据补偿电压写入至所述驱动晶体管的控制极，所述数据补充电压等于所述数据电压与所述驱动晶体管的阈值电压之和；
    所述发光控制子电路，位于所述驱动晶体管的第二极和所述发光器件的第一端之间，且与发光控制信号线耦接，配置为响应于所述发光控制信号线所提供发光控制信号的控制以使得所述驱动晶体管 的第二极与所述发光器件的第一端之间导通；
    所述驱动晶体管配置为响应于所述数据补偿电压的控制输出相应的驱动电流；
    所述发光器件的第二端与第一工作电压端耦接。
  14. 根据权利要求13所述的显示基板，其中，所述第一重置子电路包括第二十一晶体管，所述第二重置子电路包括第二十二晶体管，所述数据写入子电路包括第二十三晶体管，所述阈值补偿子电路包括第二十四晶体管、第二十五晶体管和存储电容，所述发光控制子电路包括第二十六晶体管；
    所述第二十一晶体管的控制极与所述扫描控制信号线耦接，所述第二十一晶体管的第一极与所述初始化电压端耦接，所述第二十一晶体管的第二极与所述驱动晶体管的控制极耦接；
    所述第二十二晶体管的控制极与所述重置信号线耦接，所述第二十二晶体管的第一极与所述初始化电压端耦接，所述第二十二晶体管的第二极与所述发光器件的第一端耦接；
    所述第二十三晶体管的控制极与所述扫描信号线耦接，所述第二十三晶体管的第一极与所述数据线耦接，所述第二十三晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第二十四晶体管的控制极与所述发光控制信号线耦接，所述第二十四晶体管的第一极与所述第二工作电压端耦接，所述第二十四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第二十五晶体管的控制极与所述扫描信号线耦接，所述第二十五晶体管的第一极与所述驱动晶体管的控制极耦接，所述第二十五晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述存储电容的第一端与所述第二工作电压端耦接，所述存储电容的第二端与所述驱动晶体管的控制极耦接；
    所述第二十六晶体管的控制极与所述发光控制信号线耦接，所述第二十六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第二十六晶体管的第二极与所述发光器件的第一端耦接。
  15. 根据权利要求13或14所述的显示基板，其中，位于除第一行之外的其他行的任一所述像素单元，所述像素单元所耦接的所述扫描控制信号线，为前一行像素单元所配置的所述扫描信号线。
  16. 根据权利要求11至15中任一所述的显示基板，其中，每个像素单元配置有对应的扫描信号线，所述周边区域内设置有扫描驱动电路；
    所述发光控制驱动电路内各级所述移位寄存器的信号输出端与所述显示区域内对应的扫描信号线耦接。
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