WO2022183842A1 - 一种时钟校准方法、装置和设备 - Google Patents

一种时钟校准方法、装置和设备 Download PDF

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WO2022183842A1
WO2022183842A1 PCT/CN2022/070168 CN2022070168W WO2022183842A1 WO 2022183842 A1 WO2022183842 A1 WO 2022183842A1 CN 2022070168 W CN2022070168 W CN 2022070168W WO 2022183842 A1 WO2022183842 A1 WO 2022183842A1
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signal
current
channel
module
digital signal
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PCT/CN2022/070168
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English (en)
French (fr)
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王毅
王喜瑜
张万春
张哲�
翟瑞鑫
张作锋
袁静
李登全
郝维政
赵磊
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中兴通讯股份有限公司
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Publication of WO2022183842A1 publication Critical patent/WO2022183842A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • the present application relates to the technical field of digital signal processing and communication, and in particular, to a clock calibration method, apparatus and device.
  • RF sampling receivers can directly digitize the received signal and then process it in the digital domain. Since no mixer is used, the signal processing function is completed in the digital domain, which has the advantages of low cost, low power consumption and good performance.
  • the time interleaving analog-to-digital converter uses M single-channel ADCs for alternate sampling, and the sampling rate of the entire interleaving ADC is M times the single-pass sampling rate, so that multiple low-speed and high-precision ADCs form a high-speed High precision interleaved ADC.
  • Time interleaving technology is less restricted by process and circuit design, and RF sampling ADCs mostly use time interleaving structures.
  • the mismatch between channels brings three main errors of time-interleaved ADC, namely offset error, gain error and time phase error, among them, time error is the most difficult to calibrate.
  • the existing methods for eliminating the sampling time error of the time-interleaving ADC mainly include: 1) Using the first-order Taylor expansion of the signal, obtain the time error of each sub-ADC sampling signal in the digital domain, and use the derivative of the signal and the extracted time error. value to compensate. 2) Estimate in the digital domain, judge the direction and size of the delay, and then feed it back to the analog domain to adjust the analog delay line to eliminate the time error. 3) By adding a reference channel, the time error of the analog delay line is calibrated by using the relative value rise and fall of the reference channel and the time-interleaved ADC output to control the analog delay line.
  • the above-mentioned time error elimination method has slow convergence speed and high requirements for analog design, which affects the dynamic range of ADC.
  • the present application provides a clock calibration method, apparatus, and device.
  • an embodiment of the present application provides a clock calibration method, including: for each channel in an interleaved analog-to-digital converter ADC module, determining a current digital signal type corresponding to the channel based on a current analog signal, and the interleaved ADC
  • the module includes a plurality of single-channel ADCs, and the digital signal corresponding to the channel is the signal obtained after the current analog signal passes through the corresponding single-channel ADC; the compensation value corresponding to the current digital signal of this type is determined; The compensation value performs clock calibration on the single-channel ADC corresponding to the channel.
  • an embodiment of the present application provides a clock calibration device, the clock calibration device includes: an interleaving analog-to-digital converter ADC module, a deviation detection module and a data deviation compensation module, wherein the interleaving ADC module includes a plurality of single channel ADC; each of the single-channel ADCs is configured to convert the current analog signal into a current digital signal; the deviation detection module is configured to determine, for each channel, the current digital signal corresponding to the channel based on the current analog signal type, determine the compensation value corresponding to the current digital signal of this type, and determine the current analog delay line based on the compensation value corresponding to the current digital signal; the data deviation compensation module is set to be based on the current analog delay line.
  • the clock calibration is performed on the single-channel ADC corresponding to the above-mentioned channel.
  • an embodiment of the present application provides a clock calibration device, where the device includes the clock calibration apparatus according to any one of the foregoing second aspects.
  • FIG. 1 is a flowchart of a clock calibration method provided by an embodiment of the present application.
  • FIG. 2 is a structural diagram of a clock calibration apparatus provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a time-domain interleaving analog-to-digital converter provided by an embodiment of the present application.
  • FIG. 4 is a structural diagram of a window detector provided by an embodiment of the present application.
  • FIG. 5 is a timing diagram of a window detector provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the composition of a delay module provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the composition of a delay line circuit module provided by an embodiment of the present application.
  • FIG. 8 is a flowchart of a clock calibration method provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a clock bias provided by an embodiment of the present application.
  • FIG. 10 is a schematic schematic diagram of a clock calibration algorithm provided by an embodiment of the present application.
  • FIG. 1 is a flowchart of a clock calibration method provided by an embodiment of the present application. This embodiment can be applied to the case of calibrating the time phase error in a time-interleaved ADC.
  • the method can be performed by a clock calibration device, and the device can It is implemented by means of software and/or hardware.
  • the clock calibration method provided by the embodiment of the present application mainly includes steps S11 , S12 and S13 .
  • the interleaving analog-to-digital converter ADC module For each channel in the interleaving analog-to-digital converter ADC module, determine the current digital signal type corresponding to the channel based on the current analog signal; the interleaving ADC module includes a plurality of single-channel ADCs, and the digital signal corresponding to the current channel The signal is the signal obtained after the current analog signal passes through the corresponding single-channel ADC.
  • the interleaving ADC module is composed of M identical single-channel ADC111 interleaving samples
  • the current digital signal type corresponding to the channel is determined based on the current analog signal, including:
  • the type corresponding to the data flag bit is determined as the current digital signal type corresponding to the channel.
  • the data flag refers to a flag that identifies the size of the current analog signal, which is obtained by comparing the voltage value of the current analog signal with each voltage window.
  • the window detector generates three voltage windows V w1 , V w2 , V w3 , judges whether the current analog signal is within the voltage window, obtains the comparison result, and outputs the data identification bits f1, f2, f3 according to the comparison result.
  • the three voltage windows V w1 , V w2 , and V w3 increase sequentially, that is, V w1 ⁇ V w2 ⁇ V w3 .
  • the current analog signal is input to the window detector, and when the voltage value of the current analog signal is small, f1 is a high level, f2 is a high level, and f3 is a high level.
  • f1 is a high level
  • f2 is a high level
  • f3 is a low level
  • the voltage value of the current analog signal and the analog signal continue to increase
  • f1 is a high level
  • f2 is a low level
  • f3 is a low level.
  • the voltage value of the current analog signal and the analog signal increase to the threshold value, at this time, f1 is a low level, f2 is a low level, and f3 is a low level.
  • the comparison result is that the voltage value of the current analog signal is located between the voltage windows V w1 and V w2 , that is, the voltage value of the current analog signal is greater than the voltage window V w1 and less than the window voltage V w2
  • the output data indicates that f1 is a high voltage Flat
  • f2 is a high level
  • the above-mentioned data flag bits can be represented by three binary bits, for example, the data flag bits are f1, f2, and f3. Use the high and low levels of f1, f2, and f3 to represent different data identifiers.
  • the data flag bit can be f1 is high level, f2 is high level, f3 is high level, or f1 is high level, f2 is low level, f3 is low level. It should be noted that the above-mentioned representations of the data flag bits are merely illustrative, rather than limiting.
  • the correspondence between the data identification bits and the digital signal type is pre-stored, and the above correspondence may be stored in the form of a list or in the form of a database, which is not limited in this embodiment.
  • query is performed in the above correspondence based on the determined data flag bit, and the digital signal type corresponding to the queried data flag bit is determined as the current digital signal type.
  • the current digital signal type when the data flag bits f1, f2, and f3 are all high, the current digital signal type is (i, 1); when f1, f2 are high, and f3 is low, the current digital signal type is is (i,2); when f1 is high level, f2, f3 are low level, the current digital signal type is (i,3).
  • determining the corresponding data flag bit based on the current analog signal includes: generating a preset number of voltage windows; determining the data flag corresponding to the current analog signal based on a comparison result between the current analog signal and the voltage window bit.
  • the preset number of voltage windows is not limited, and the number of voltage windows may be set according to actual conditions.
  • the number of voltage windows is three.
  • the voltage window is generated by a window detector, and the data flag bit is output by the window detector after a preset operation.
  • the window detector generates three voltage windows V w1 , V w2 , V w3 , judges whether the current analog signal is within the voltage window, obtains the comparison result, and outputs the data identification bits f1, f2, f3 according to the comparison result.
  • the three voltage windows V w1 , V w2 , and V w3 increase sequentially, that is, V w1 ⁇ V w2 ⁇ V w3 .
  • the current analog signal is input to the window detector, and when the voltage value of the current analog signal is small, f1 is a high level, f2 is a high level, and f3 is a high level.
  • f1 is a high level
  • f2 is a high level
  • f3 is a low level
  • the voltage value of the current analog signal and the analog signal continue to increase
  • f1 is a high level
  • f2 is a low level
  • f3 is a low level.
  • the voltage value of the current analog signal and the analog signal increase to the threshold value
  • f1 is low level
  • f2 is low level
  • f3 low level.
  • the comparison result is that the voltage value of the current analog signal is located between the voltage windows V w1 and V w2 , that is, the voltage value of the current analog signal is greater than the voltage window V w1 and less than the window voltage V w2
  • the output data indicates that f1 is a high voltage Flat
  • f2 is a high level
  • clock calibration is performed on the ADC corresponding to the channel based on the compensation value corresponding to the current digital signal, including:
  • the compensation value corresponding to the digital signal When the compensation value corresponding to the digital signal is greater than or equal to the calibration threshold, adjust the time delay corresponding to the channel based on the compensation value corresponding to the current digital signal, determine the newly input analog signal as the current analog signal, and return to execute An operation of determining the current digital signal type corresponding to the channel based on the current analog signal, until the compensation value corresponding to the current digital signal is smaller than the calibration threshold.
  • the compensation value corresponding to the digital signal when the compensation value corresponding to the digital signal is greater than or equal to the calibration threshold, it indicates that the current compensation value cannot compensate for the time error, and the time delay corresponding to the channel needs to be adjusted according to the compensation value, and the above-mentioned steps are repeated. In the process, the compensation value is determined again, and the time error compensation is performed. Until the compensation value of each group of data reaches the preset calibration threshold or the iteration reaches the preset number of iterations, it indicates that the time error calibration is completed at this time.
  • adjusting the time delay corresponding to the channel based on the compensation value corresponding to the current digital signal includes:
  • the time delay corresponding to the channel is adjusted based on the updated digital symbols of the current analog delay line.
  • the variance within the group is calculated respectively, for example, the variance within the group is calculated respectively for group (i, 1), group (i, 2), and group (i, 3).
  • D m,i ⁇ 2 (i,j).
  • D' m,i is obtained through D m,i of the current iteration and the previous iteration, so that the direction and step size of the digital symbol iteration can be determined:
  • D' m,i [n] represents the direction and step size of the digital symbol iteration of the m-th single-channel ADC at the current moment
  • D m,i [n] represents the variance of the m-th single-channel ADC at the current moment
  • D m,i [n-1] represents the variance of the mth single-channel ADC at the previous moment.
  • the direction of digital symbol iteration is determined by the difference between the variance D m,i [n-1] of the m-th single-channel ADC at the previous moment and the variance D m, i [n] of the m-th single-channel ADC at the current moment.
  • the step size of the digital symbol iteration is the variance D m,i [n] of the mth single-channel ADC at the current moment.
  • the digital code of the analog delay line is updated to adjust the time delay of the mth ADC.
  • the method further includes:
  • the clock calibration is triggered.
  • the on-chip sensor detects that the chip temperature change value is greater than the temperature change threshold or that the time error between the interleaved ADC module and the reference ADC is greater than the error threshold, and initiates clock calibration.
  • the temperature change can be selected to initiate calibration, which requires the participation of on-chip sensors; or the time error between the interleaved ADC module and the reference ADC can be selected to be greater than the error threshold, and the calibration can be initiated, and the reference ADC and the deviation detection module need to be running all the time .
  • the calibration initiation conditions can be selected according to actual needs. It is not limited in this embodiment.
  • FIG. 2 is a structural diagram of a clock calibration apparatus provided by an embodiment of the present application. This embodiment is applicable to the case of calibrating the time phase error in a time-interleaved ADC.
  • the method may be performed by a clock calibration apparatus, and the apparatus may It is implemented by means of software and/or hardware.
  • the clock calibration apparatus mainly includes an interleaving analog-to-digital converter ADC module 21 , a deviation detection module 22 and a data deviation compensation module 23 , wherein the interleaving ADC module 21 includes a plurality of single channel ADC;
  • Each of the single-channel ADCs is configured to convert the current analog signal into a current digital signal
  • the deviation detection module 22 is set to determine, for each channel, the current digital signal type corresponding to the channel based on the current analog signal, determine the compensation value corresponding to the current digital signal of this type, and based on the current digital signal corresponding to the current digital signal.
  • the compensation value of determines the current analog delay line
  • the data offset compensation module 23 is configured to perform clock calibration on the ADC corresponding to the channel based on the current analog delay line.
  • the data offset compensation module 23 is composed of M identical analog delay lines (VDL).
  • the current analog signal is input to the interleaving ADC module and the window detector through the analog line
  • the interleaving ADC module is composed of M identical single-channel ADC units interleaving samples
  • the digital output of the interleaving ADC module is sent to the
  • the data flag bits f1, f2 and f3 of the output data of the window detector are also sent to the error detection module.
  • the error detection module adjusts the calibration time error of the data deviation compensation module according to the compensation value corresponding to the current digital signal.
  • the deviation detection module includes a window detector and a deviation detection module, wherein,
  • the window detector is set to determine the corresponding data flag bit based on the current analog signal
  • the deviation detection module is configured to determine the type corresponding to the data flag bit as the current digital signal type corresponding to the channel.
  • the window detector includes: a comparator module, a delay module, a flip-flop module, an exclusive OR gate and an output unit, wherein,
  • the comparator module After the comparator module receives the trigger signal ⁇ ref , the preset signals are compared to obtain a comparison result, and the comparison result includes a first signal and a second signal; the first signal and the second signal are subjected to the exclusive OR After the gate, a third signal is obtained and input to the trigger module; the trigger signal is input to the trigger module after passing through the delay module, as the clock signal of the trigger module; the trigger module is based on the The clock signal performs time delay processing on the third signal to obtain a fourth signal, which is input to the output unit; the output unit performs reverse processing on the fourth signal to obtain a data flag corresponding to the current analog signal.
  • the trigger signal ⁇ ref may be the current analog signal input to the window detector.
  • the preset signal refers to a signal input to the comparator module 200 .
  • the comparison result refers to the comparison result of two preset signals in the window detector.
  • the comparison result refers to comparing whether the current analog signals input to the comparator module are the same.
  • the first signal and the second signal are signals with opposite phases.
  • the first signal refers to the output signal Op of the comparator module 200 shown in FIG. 4
  • the second signal refers to the output signal O m of the comparator module 200 shown in FIG. 4 .
  • the third signal refers to the signal ⁇ XOR obtained after the first signal Op and the second signal O m pass through the exclusive OR gate 240 .
  • the fourth signal refers to obtaining fourth signals ( ⁇ 1, ⁇ 2, ⁇ 3) after performing different time delay processing on the third signal ⁇ XOR .
  • the fourth signals ( ⁇ 1 , ⁇ 2 , ⁇ 3 ) are respectively reverse processed to obtain data flag bits ( f1 , f2 , f3 ).
  • the current analog signal ⁇ ref outputs the comparison result through the comparator module 200, that is, the first signal Op and the second signal Om , the first signal Op and the second signal Om
  • the third signal ⁇ XOR obtained after passing through the exclusive OR gate 240 is input to the D flip-flop module 220 , and the D flip-flop module 220 consists of three identical D flip-flops 221 , D flip-flops 222 , D flip-flop 223 is formed.
  • the comparator module 200 performs the comparison for a long time.
  • the fourth signal ( ⁇ 3, ⁇ 2, ⁇ 3) output by the D flip-flop is all low level, and the fourth signal is ( ⁇ 1, ⁇ 2, ⁇ 3)
  • the data flag bit is obtained that f1 is a high level, f2 is a high level, and f3 is a high level.
  • the comparator module 200 shortens the comparison time, and the D flip-flop 221 and the D flip-flop 222 have already reached the third signal ⁇ XOR before the third signal ⁇ XOR reaches the threshold. are triggered by the clock signals ⁇ Delay1 and ⁇ Delay2 respectively. At this time, since the D flip-flop 221 and the D flip-flop 222 are triggered, the default is low level when there is no input signal. Therefore, the D flip-flop 221 and the D flip-flop 222 output The fourth signal ⁇ 1 is low level , and ⁇ 2 is low level.
  • the D flip-flop 223 Since the third signal ⁇ XOR has reached the D flip-flop 223 when the D flip-flop 223 is triggered, the D flip-flop 223 outputs the fourth signal ⁇ 3 at a high level, and the fourth signal ( ⁇ 1, ⁇ 2, ⁇ 3) is reversed To the device, the obtained data flag bit is that f1 is high level, f2 is high level, and f3 is low level.
  • the comparator module 200 shortens the comparison time again, and the D flip-flop 221 has been triggered by the clock signal ⁇ Delay1 before the third signal ⁇ XOR reaches. , at this time, since the D flip-flop 221 is triggered, it is a low level by default when there is no input signal, so the fourth signal ⁇ 1 output by the D flip-flop 221 is a low level.
  • the fourth signal ⁇ 2 output by the D flip-flop 222 is high level, and the D flip-flop 222 outputs a high level.
  • 223 outputs the fourth signal ⁇ 3 is high level, passes the fourth signal ( ⁇ 1 , ⁇ 2, ⁇ 3) through the inverter to obtain the data flag bit is f1 is high level, f2 is low level, f3 is low level.
  • the comparator module 200 shortens the comparison time again, the third signal ⁇ XOR reaches the front D flip-flop 221, and the D flip-flop Neither the D flip-flop 222 nor the D flip-flop 223 is triggered by the clock signal. Since the D flip-flop 221, the D flip-flop 222 and the D flip-flop 223 are triggered, the third signal ⁇ XOR has reached the D flip-flop 221, the D flip-flop 222 and the D flip-flop 223.
  • the D flip-flop 222 outputs the fourth The signal ⁇ 1 is high level, the fourth signal ⁇ 2 output by D flip-flop 222 is high level, the fourth signal ⁇ 3 output by D flip-flop 223 is high level, and the fourth signal ( ⁇ 1 , ⁇ 2, ⁇ 3) is passed through the inverter , the data flag bit is f1 is low level, f2 is low level, f3 is low level.
  • the delay module includes a current source, 2N inverters and N+1 NMOS transistors; wherein the 2N inverters are connected in sequence, and the current source is connected to the first NMOS transistor , the n+1th NMOS transistor is connected to the 2n-1th inverter, where n is any integer between 1 and N.
  • the data offset compensation module includes a plurality of identical analog delay line units.
  • the analog extension line unit includes a coarse delay circuit and a fine delay circuit, wherein the fine delay circuit includes a first amplifier, an Nc group of capacitors and Nc switches, and the coarse extension circuit includes The second amplifier, the third amplifier, 2 groups of capacitors and 2 switches;
  • the first amplifier, the second amplifier and the third amplifier are connected in sequence, the series circuit of Nc capacitors and switches is connected in parallel between the first amplifier and the second amplifier, and the two capacitors are connected to A series circuit of switches is connected in parallel between the second amplifier and the third amplifier.
  • the analog extension line unit is composed of three amplifiers, (2+N c ) switches and (2+N c ) sets of capacitors.
  • the analog extension line unit adopts a segmented structure and is divided into two parts: a coarse delay circuit and a fine delay circuit, and the delay size is controlled by the digital code generated by the digital deviation detection circuit.
  • the circuit adopts binary weights: the two-bit coarse adjustment circuit uses a larger capacitor C 2 to quickly determine the delay range, and the Nc -bit fine adjustment circuit uses a smaller capacitor C 1 to obtain an accurate phase delay.
  • an embodiment of the present application further provides a clock calibration device, where the device includes the clock calibration apparatus described in any one of the foregoing embodiments.
  • Clock calibration equipment includes, but is not limited to, superheterodyne receivers, low-IF receivers, zero-IF receivers, and the like.
  • FIG. 3 is a schematic structural diagram of a time-domain interleaving analog-to-digital converter provided by an embodiment of the present application.
  • the current analog signal is input to the interleaving ADC module 110 and the window detector 115 through the analog line 100
  • the interleaving ADC module is composed of M identical single-channel ADC units 111 interleaving samples
  • the digital output of the interleaving ADC module is sent to the error detection module 125 through the multiplexer 120
  • the window detector 115 outputs the data flag bits f1, f2, f3 is also fed to the error detection module 125 .
  • the error detection module 125 adjusts the data deviation compensation module 105 to calibrate the time error according to the flag value corresponding to the current digital signal, wherein the data deviation compensation module is composed of M identical analog delay lines (VDL).
  • VDL analog delay lines
  • FIG. 4 is a structural diagram of a window detector provided by an embodiment of the present application.
  • the current analog signal is input to the window detector 105 through the line 100, and the current analog signal ⁇ ref is output through the comparator module 200.
  • the comparator module 200 When the voltage difference between the two preset signals is small, the comparator module 200 performs the comparison for a long time, and before the third signal ⁇ XOR reaches the D flip-flop, all the D flip-flops have been clocked by the clock signals ( ⁇ Delay1 , ⁇ Delay2 , ⁇ Delay3 ). ) trigger, at this time, since the D flip-flop is triggered, there is no input signal, the default is low level, therefore, the fourth signal ( ⁇ 3, ⁇ 2, ⁇ 3) output by the D flip-flop is all low level, the fourth The signal ( ⁇ 1, ⁇ 2, ⁇ 3) passes through the inverter, and the data flag bit is obtained that f1 is high level, f2 is high level, and f3 is high level.
  • the comparator module 200 shortens the comparison time, and the D flip-flop 221 and the D flip-flop 222 have already reached the third signal ⁇ XOR before the third signal ⁇ XOR reaches the threshold. are triggered by the clock signals ⁇ Delay1 and ⁇ Delay2 respectively. At this time, since the D flip-flop 221 and the D flip-flop 222 are triggered, the default is low level when there is no input signal. Therefore, the D flip-flop 221 and the D flip-flop 222 output The fourth signal ⁇ 1 is low level , and ⁇ 2 is low level.
  • the D flip-flop 223 Since the third signal ⁇ XOR has reached the D flip-flop 223 when the D flip-flop 223 is triggered, the D flip-flop 223 outputs the fourth signal ⁇ 3 at a high level, and the fourth signal ( ⁇ 1, ⁇ 2, ⁇ 3) is reversed To the device, the obtained data flag bit is that f1 is high level, f2 is high level, and f3 is low level.
  • the comparator module 200 shortens the comparison time again, and the D flip-flop 221 has been triggered by the clock signal ⁇ Delay1 before the third signal ⁇ XOR reaches. , at this time, since the D flip-flop 221 is triggered, it is a low level by default when there is no input signal, so the fourth signal ⁇ 1 output by the D flip-flop 221 is a low level.
  • the fourth signal ⁇ 2 output by the D flip-flop 222 is high level, and the D flip-flop 222 outputs a high level.
  • 223 outputs the fourth signal ⁇ 3 is high level, passes the fourth signal ( ⁇ 1 , ⁇ 2, ⁇ 3) through the inverter to obtain the data flag bit is f1 is high level, f2 is low level, f3 is low level.
  • the comparator module 200 shortens the comparison time again, the third signal ⁇ XOR reaches the front D flip-flop 221, and the D flip-flop Neither the D flip-flop 222 nor the D flip-flop 223 is triggered by the clock signal. Since the D flip-flop 221, the D flip-flop 222 and the D flip-flop 223 are triggered, the third signal ⁇ XOR has reached the D flip-flop 221, the D flip-flop 222 and the D flip-flop 223.
  • the D flip-flop 222 outputs the fourth The signal ⁇ 1 is high level, the fourth signal ⁇ 2 output by D flip-flop 222 is high level, the fourth signal ⁇ 3 output by D flip-flop 223 is high level, and the fourth signal ( ⁇ 1, ⁇ 2, ⁇ 3) is passed through the inverter , the data flag bit is f1 is low level, f2 is low level, f3 is low level.
  • the sampled values output by the interleaving ADC module are grouped, that is, the type of the current digital signal output by the single-channel ADC unit is determined.
  • the output digital signal is divided into different groups according to the generation channel and the voltage window to which it belongs.
  • group (i, 1) that is, the type of the current digital signal is (i, 1); when f1, f2 are high level, and f3 is low level,
  • the sampled value enters group (i, 2), that is, the type of the current digital signal is (i, 2); when f1 is high, f2, f3 are low, the sampled value enters group (i, 3), that is, the current The type of digital signal is (i, 3).
  • the deviation detection module does not receive the current digital signal.
  • the intra-group variance ⁇ 2 (i, j) is calculated respectively and the compensation value is generated (the compensation value is initially 0).
  • ⁇ ref is the external control clock, that is, the current analog signal.
  • the comparator works. At this time, the comparator module outputs the output before generating the comparison result.
  • Both O p and O m are at a high level, and the smaller the difference between the voltage differences between the two preset signals, the longer the comparison time.
  • Input O p and O m to XOR gate to get ⁇ XOR as D flip-flop input.
  • the data flag bits f1, f2, and f3 output by the D flip-flop can be obtained when the difference between the input signals is within the thresholds T 1 , T 2 , and T 3 .
  • FIG. 6 is a schematic diagram of the composition of a delay module provided by an embodiment of the present application.
  • the delay module includes: a current source, 2N inverter groups 410, and N+1 NMOS modules 420, which output delayed clocks ⁇ Delay1, ⁇ Delay2, and ⁇ Delay3.
  • FIG. 7 is a schematic diagram of the composition of a delay line circuit module provided by an embodiment of the present application.
  • the circuit is composed of three amplifiers, (2+Nc) switches and (2+Nc) capacitors.
  • the circuit adopts a segmented structure and is divided into two parts: a coarse delay circuit 500 and a fine delay circuit 510, and the delay size is controlled by the digital code generated by the digital deviation detection circuit.
  • the circuit uses binary weights: the two-bit coarse adjustment circuit uses a larger capacitor C2 to quickly determine the delay range, and the Nc-bit fine adjustment circuit uses a smaller capacitor C1 to obtain an accurate phase delay.
  • a method of clock calibration is provided. It mainly includes: grouping the output of the interleaved ADC module according to the window detector output. The delay value can be adjusted according to the variance.
  • FIG. 8 is a flowchart of a clock calibration method provided by an embodiment of the present application. As shown in FIG. 8 , the steps of the clock calibration method provided by an embodiment of the present application are as follows:
  • Step 600 The system detects that the chip temperature change value is greater than the temperature change threshold or detects that the time error between the interleaved ADC module and the reference ADC is greater than the error threshold;
  • Step 610 Trigger clock calibration
  • Step 620 Associate and group the digital signal output by the single-channel ADC unit to be calibrated and the data identification bits output by the window detector.
  • Step 630 Obtain the data variance D m,i in each group.
  • Step 640 Taking the i-th group of data as a reference, obtain D' m,i through the D m,i of the current iteration and the previous iteration, so that the direction and step size of the digital symbol iteration can be determined:
  • the digital code of the analog delay line is updated to adjust the time delay of the mth ADC.
  • T m,n and T m,n-1 respectively represent the digital control code of the analog delay line of the mth ADC at the current moment and the previous moment
  • u 2 is the step value
  • Step 650 Determine whether the calibration completion condition is met. If not, repeat the above process until the variance of each group of data reaches the preset calibration threshold or the iteration reaches the preset number of iterations, indicating that the time error calibration is completed at this time.
  • FIG. 9 is a schematic diagram of a clock deviation provided by an embodiment of the present application
  • FIG. 10 is a schematic schematic diagram of a clock calibration algorithm provided by an embodiment of the present application.
  • the actual sampling time lags behind the ideal sampling time
  • ⁇ i is the time error lag time
  • ⁇ x error is generated for the sampling value of the signal at this time.
  • the digital code output by the ADC will have a large variance, and when the clock deviation is small, the ADC output will be concentrated in several adjacent numbers. code, the variance is small at this time.
  • the traditional method requires a long statistical time.
  • the present application adopts a window detector, which can estimate the magnitude and direction of the time error by using less data.
  • the design method of the window detector is simple and the power consumption is low.
  • the current analog signal does not need to pass through the zero point frequently; the application can run in the foreground or in the background, so that the influence of PVT changes on the time error can be tracked.
  • the clock calibration apparatus provided in this embodiment can execute the clock calibration method provided by any embodiment of the present application, and has corresponding functional modules and beneficial effects for executing the method.
  • the clock calibration apparatus provided in this embodiment, can execute the clock calibration method provided by any embodiment of the present application, and has corresponding functional modules and beneficial effects for executing the method.
  • the units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized;
  • the specific names of the functional units are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application.
  • the clock calibration method, device and device provided by the above embodiments include: for each channel in the interleaved analog-to-digital converter ADC module, determining the current digital signal type corresponding to the channel based on the current analog signal;
  • the digital signal is the signal obtained after the current analog signal passes through the ADC corresponding to the channel; the compensation value corresponding to the current digital signal of this type is determined; the ADC corresponding to the channel is clocked based on the compensation value corresponding to the current digital signal.
  • the technical solution of the embodiment of the present application determines the type of the digital signal, determines the compensation value of the type of digital signal, uses the compensation value to perform clock calibration, and realizes the estimation of the size and direction of the time error by using less data.
  • the method is simple, Low power consumption.

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Abstract

一种时钟校准方法、装置和设备，所述时钟校准方法包括：针对交织模数转换器ADC模块中的每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型，所述当前通道对应的数字信号是当前模拟信号经过该通道对应的ADC后得到的信号(S11)；确定该类型的当前数字信号对应的方差(S12)；基于所述当前数字信号对应的方差对所述通道对应的单通道ADC进行时钟校准(S13)。

Description

一种时钟校准方法、装置和设备
相关申请的交叉引用
本申请基于申请号为202110247205.X、申请日为2021年03月05日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及数字信号处理和通信技术领域，具体涉及一种时钟校准方法、装置和设备。
背景技术
在现代通信领域中，传统接收机，对混频器设计要求高，容易产生相位误差和杂散频率。射频采样接收机可以对接收信号直接数字化，然后在数字域进行处理。由于不使用混频器，在数字域完成信号处理功能，具有成本低、功耗小、性能好的优点。
时间交织模数转换器(Analog-to-DigitalConverter，ADC)使用M个单通道ADC进行交替采样，整个交织ADC的采样率为单通采样率的M倍，从而多个低速高精度ADC构成一个高速高精度的交织ADC。时间交织技术受到工艺和电路设计限制较小，射频采样ADC大多采用时间交织结构。但是，通道之间的失配带来了时间交织ADC的三种主要误差，即失调误差、增益误差和时间相位误差，其中，时间误差的校准难度最高。上述误差严重降低了整个ADC的信噪比(Signal to Noise Ratio，SNR)和无杂散动态范围(Spurious Free Dynamic Range，SFDR)。因此，如何解决时间交织ADC由于子ADC不匹配产生的杂散和非线性，提高ADC的精度和性能成为亟待解决的技术问题。
现有的消除时间交织ADC采样时间误差的方法主要有：1)利用信号的一阶泰勒展开式，在数字域求取每个子ADC采样信号的时间误差，并利用信号的导数和提取的时间误差值进行补偿。2)在数字域进行估计，判断时延的方向和大小，然后反馈回模拟域调节模拟延时线消除时间误差。3)通过增加参考通道，利用参考通道和时间交织ADC输出的相关值升降控制模拟延时线校准时间误差。
上述时间误差消除方法，收敛速度慢，模拟设计要求较高，影响ADC的动态范围。
发明内容
本申请提供了一种时钟校准方法、装置、设备。
第一方面，本申请实施例提供一种时钟校准方法，包括：针对交织模数转换器ADC模块中的每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型，所述交织ADC模块包括多个单通道ADC，所述通道对应的数字信号是当前模拟信号经过对应的单通道ADC后得到的信号；确定该类型的当前数字信号对应的补偿值；基于所述当前数字信号对应的补偿值对所述通道对应的单通道ADC进行时钟校准。
第二方面，本申请实施例提供一种时钟校准装置，所述时钟校准装置包括：交织模数转换器ADC模块，偏差检测模块和数据偏差补偿模块，其中，所述交织ADC模块包括多个单通道ADC；各个所述单通道ADC，被设置为将当前模拟信号转换为当前数字信号；所述偏差检测模块，被设置为针对每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型，确定该类型的当前数字信号对应的补偿值，并基于所述当前数字信号对应的补偿值确定当前模拟延时线；数据偏差补偿模块，被设置为基于所述当前模拟延时线对所述通道对应的单通道ADC进行时钟校准。
第三方面，本申请实施例提供一种时钟校准设备，所述设备包括如上述第二方面中任一项所述的时钟校准装置。
关于本申请的以上实施例和其他方面以及其实现方式，在附图说明、具体实施方式和权利要求中提供更多说明。
附图说明
图1是本申请实施例提供的一种时钟校准方法的流程图；
图2是本申请实施例提供的一种时钟校准装置的结构图；
图3是本申请实施例提供的时域交织模数转换器的结构示意图。
图4是本申请实施例提供的窗口检测器结构图；
图5是本申请实施例提供的窗口检测器时序图；
图6是本申请实施例提供的延时模块组成示意图；
图7是本申请实施例提供的延时线电路模块组成示意图；
图8是本申请实施例提供的时钟校准方法的流程图；
图9是本申请实施例提供的时钟偏差的示意图；
图10是本申请实施例提供的时钟校准算法的原理示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施 例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
图1是本申请实施例提供的一种时钟校准方法的流程图，本实施例可适用于校准时间交织ADC中的时间相位误差的情况，该方法可以由时钟校准装置来执行，所述装置可以通过软件和/或硬件的方式来实现。
如图1所示，本申请实施例提供的时钟校准方法的主要包括步骤S11、S12和S13。
S11、针对交织模数转换器ADC模块中的每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型；所述交织ADC模块包括多个单通道ADC，所述当前通道对应的数字信号是当前模拟信号经过对应的单通道ADC后得到的信号。
S12、确定该类型的当前数字信号对应的补偿值。
S13、基于所述当前数字信号对应的补偿值对所述通道对应的单通道ADC进行时钟校准。
在本实施例中，交织ADC模块由M个相同的单通道ADC111交织采样构成
在一个实施方式中，基于当前模拟信号确定该通道对应的当前数字信号类型，包括：
基于当前模拟信号确定对应的数据标志位；
将所述数据标志位对应的类型确定为该通道对应的当前数字信号类型。
在本实施例中，所述数据标志位是指标识当前模拟信号大小的一个标识，其根据当前模拟信号的电压值与各个电压窗口进行比较得到。
窗口检测器产生三个电压窗口V w1，V w2，V w3，判断当前模拟信号是否处于电压窗口之内，得到比较结果，根据比较结果输出数据标识位f1，f2，f3。其中，三个电压窗口V w1，V w2，V w3依次增大，即V w1<V w2<V w3。
一种实施方式中，当前模拟信号输入到窗口检测器，当当前模拟信号的电压值较小时，f1为高电平，f2为高电平，f3为高电平。当当前模拟信号的电压值增大到一定程度时，此时f1为高电平，f2为高电平，f3为低电平。当当前模拟信号的电压值模拟信号继续增大，f1为高电平，f2为低电平，f3为低电平。当当前模拟信号的电压值模拟信号增大到门限值时，此时f1为低电平，f2为低电平，f3为低电平。
在所述比较结果是当前模拟信号的电压值小于电压窗口V w1，输出数据标识为f1为高电平，f2为高电平，f3为高电平，可以用(f1，f2，f3)＝(1，1，1)来表示。在所述比较结果是当前模拟信号的电压值位于电压窗口V w1与V w2之间，即当前模拟信号的电压值大于电压 窗口V w1且小于窗口电压V w2，输出数据标识为f1为高电平，f2为高电平，f3为低电平，可以用(f1，f2，f3)＝(1，1，0)来表示。在所述比较结果是当前模拟信号的电压值位于电压窗口V w2与V w3之间，即当前模拟信号的电压值大于电压窗口V w2且小于窗口电压V w3，输出数据标识为f1为高电平，f2为低电平，f3为低电平，可以用(f1，f2，f3)＝(1，0，0)来表示。在所述比较结果是当前模拟信号的电压值大于电压窗口V w3，输出数据标识为f1为低电平，f2为低电平，f3为低电平，可以用(f1，f2，f3)＝(0，0，0)来表示。
在一个实施方式中，上述数据标志位可以用三位二进制来表示，例如：数据标志位是f1，f2，f3。利用f1，f2，f3的高低电平来表示不同的数据标识。如：数据标志位可以是f1为高电平，f2为高电平，f3为高电平，还可以是f1为高电平，f2为低电平，f3为低电平。需要说明的是，上述数据标志位的表示方式仅仅是进行示例性说明，而非限定。
在一实施方式中，预先存储数据标识位与数字信号类型的对应关系，上述对应关系可以以列表的形式存储，也可以以数据库的形式存储，本实施例中不进行限定。
确定当前模拟信号对应的数据标志位之后，基于确定的数据标志位在上述对应关系中进行查询，将查询到的数据标志位对应的数字信号类型确定为当前数字信号类型。
在一实施方式中，数据标志位f1，f2，f3均为高电平时，当前数字信号类型为(i,1)；当f1，f2为高电平，f3为低电平时，当前数字信号类型为(i,2)；当f1为高电平，f2，f3为低电平时，当前数字信号类型为(i,3)。
在一个实施方式中，基于当前模拟信号确定对应的数据标志位，包括：生成预设数量的电压窗口；基于所述当前模拟信号与所述电压窗口的比较结果，确定当前模拟信号对应的数据标志位。
在本实施例中，不对电压窗口的预设数量进行限定，可以根据实际情况对电压窗口的数量进行设定。作为一示例，电压窗口的数量为3。
在一实施方式中，电压窗口由窗口检测器生成，数据标志位由窗口检测器经过预设的运算之后输出。
窗口检测器产生三个电压窗口V w1，V w2，V w3，判断当前模拟信号是否处于电压窗口之内，得到比较结果，根据比较结果输出数据标识位f1，f2，f3。其中，三个电压窗口V w1，V w2，V w3依次增大，即V w1<V w2<V w3。
一种实施方式中，当前模拟信号输入到窗口检测器，当当前模拟信号的电压值较小时，f1为高电平，f2为高电平，f3为高电平。当当前模拟信号的电压值增大到一定程度时，此时f1为高电平，f2为高电平，f3为低电平。当当前模拟信号的电压值模拟信号继续增大，f1为高电平，f2为低电平，f3为低电平。当当前模拟信号的电压值模拟信号增大到门限值 时，此时f1为低电平，f2为低电平，f3为低电平。
在所述比较结果是当前模拟信号的电压值小于电压窗口V w1，输出数据标识为f1为高电平，f2为高电平，f3为高电平，可以用(f1，f2，f3)＝(1，1，1)来表示。在所述比较结果是当前模拟信号的电压值位于电压窗口V w1与V w2之间，即当前模拟信号的电压值大于电压窗口V w1且小于窗口电压V w2，输出数据标识为f1为高电平，f2为高电平，f3为低电平，可以用(f1，f2，f3)＝(1，1，0)来表示。在所述比较结果是当前模拟信号的电压值位于电压窗口V w2与V w3之间，即当前模拟信号的电压值大于电压窗口V w2且小于窗口电压V w3，输出数据标识为f1为高电平，f2为低电平，f3为低电平，可以用(f1，f2，f3)＝(1，0，0)来表示。在所述比较结果是当前模拟信号的电压值大于电压窗口V w3，输出数据标识为f1为低电平，f2为低电平，f3为低电平，可以用(f1，f2，f3)＝(0，0，0)来表示。
在一个实施方式中，基于所述当前数字信号对应的补偿值对所述通道对应的ADC进行时钟校准，包括：
当所述数字信号对应的补偿值大于或等于校准阈值，则基于所述当前数字信号对应的补偿值调整所述通道对应的时间延迟，并将新输入的模拟信号确定为当前模拟信号，返回执行基于当前模拟信号确定所述通道对应的当前数字信号类型的操作，直到所述当前数字信号对应的补偿值小于所述校准阈值。
在本实施例中，当所述数字信号对应的补偿值大于或等于校准阈值时，则表明当前的补偿值不能补偿时间误差，需要根据补偿值调整所述通道对应的时间延迟后，重复执行上述过程，再一次确定补偿值，进行时间误差的补偿。直到各组数据的补偿值达到预先设定的校准阈值或者迭代达到预先设定的迭代次数，表明此时时间误差校准完成。
在一个实施方式中，基于所述当前数字信号对应的补偿值调整所述通道对应的时间延迟，包括：
基于所述当前数字信号对应的方差和上一时刻数字信号对应的方差，确定当前模拟延时线的数字码元的方向和步长；
通过代价函数和所述当前模拟延时线的数字码元的方向和步长更新当前模拟延时线的数字码元；
基于更新后的当前模拟延时线的数字码元调整所述通道对应的时间延迟。
在本实施例中，针对每个类型的当前数字信号，分别计算组内的方差，例如：对组(i,1)，组(i,2)，组(i,3)分别计算组内方差D m,i＝σ 2(i,j)。
例如：以第i组数据为参考，通过当前迭代和上一次迭代的D m,i,得到D' m,i，从而可以确 定数字码元迭代的方向和步长：
Figure PCTCN2022070168-appb-000001
其中，D' m,i[n]表示第m单通道ADC在当前时刻的数字码元迭代的方向和步长，D m,i[n]表示第m单通道ADC在当前时刻的方差，D m,i[n-1]表示第m单通道ADC在前一时刻的方差。数字码元迭代的方向由第m单通道ADC在前一时刻的方差D m,i[n-1]与第m单通道ADC在当前时刻的方差D m,i[n]的差值符号来确定。数字码元迭代的步长是第m单通道ADC在当前时刻的方差D m,i[n]。
通过代价函数，对模拟延时线的数字码进行更新，从而调节第m路ADC的时间延迟。
在一个实施方式中，针对ADC模块中的每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型之前还包括：
检测到芯片的温度变化值大于温度变化阈值，或者，检测到交织ADC模块与参考ADC之间的时间误差大于误差阈值，则触发时钟校准。
在本实施例中，片上传感器检测到芯片温度变化值大于温度变化阈值或者检测到交织ADC模块与参考ADC之间的时间误差大于误差阈值，则发起时钟校准。
在一实施方式中，可以选取温度变化，发起校准，需要有片上传感器参与；也可以选择交织ADC模块与参考ADC之间的时间误差大于误差阈值，发起校准，需要参考ADC和偏差探测模块一直运行。校准发起条件可以根据实际需求选取。本实施例中不进行限定。
图2是本申请实施例提供的一种时钟校准装置的结构图，本实施例可适用于校准时间交织ADC中的时间相位误差的情况，该方法可以由时钟校准装置来执行，所述装置可以通过软件和/或硬件的方式来实现。
如图2所示，本申请实施例提供的时钟校准装置的主要包括交织模数转换器ADC模块21，偏差检测模块22和数据偏差补偿模块23，其中，所述交织ADC模块21包括多个单通道ADC；
各个所述单通道ADC，被设置为将当前模拟信号转换为当前数字信号；
所述偏差检测模块22，被设置为针对每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型，确定该类型的当前数字信号对应的补偿值，并基于所述当前数字信号对应的补偿值确定当前模拟延时线；
数据偏差补偿模块23，被设置为基于所述当前模拟延时线对所述通道对应的ADC进行时 钟校准。
其中，数据偏差补偿模块23由M个相同的模拟延时线(VDL)构成。
在本实施例中，当前模拟信号通过模拟线路输入到交织ADC模块和窗口检测器，交织ADC模块由M个相同的单通道ADC单元交织采样构成，交织ADC模块的数字输出经过多路开关输送到误差探测模块，窗口检测器输出数据的数据标志位f1,f2,f3也输送到误差探测模块。误差探测模块根据当前数字信号对应的补偿值值调节数据偏差补偿模块校准时间误差。
在一个实施方式中，所述偏差检测模块包括窗口检测器和偏差探测模块，其中，
所述窗口检测器，被设置为基于当前模拟信号确定对应的数据标志位；
所述偏差探测模块，被设置为将所述数据标志位对应的类型确定为该通道对应的当前数字信号类型。
在一个实施方式中，所述窗口检测器包括：比较器模块，时延模块，触发器模块，异或门和输出单元，其中，
所述比较器模块接收到触发信号Φ ref后，预设信号进行比较，得到比较结果，所述比较结果包括第一信号和第二信号；所述第一信号和第二信号经过所述异或门之后得到第三信号，并输入至触发器模块；所述触发信号经过所述时延模块后输入至所述触发器模块，作为所述触发器模块的时钟信号；所述触发器模块基于所述时钟信号对所述第三信号进行时延处理后得到第四信号，并输入至输出单元；所述输出单元将所述第四信号进行反向处理后得到当前模拟信号对应的数据标志位。
其中，触发信号Φ ref后可以是输入至窗口检测器的当前模拟信号。预设信号是指输入至比较器模块200的信号。其中，所述比较结果是指窗口检测器中两个预设信号的比较结果。比较结果是指比较输入至比较器模块的当前模拟信号是否相同。其中，第一信号与第二信号是相位相反的信号。第一信号是指如图4所示的比较器模块200的输出信号O p，第二信号是指如图4所示的比较器模块200的输出信号O m。第三信号是指第一信号O p和第二信号O m经过所述异或门240之后得到的信号φ XOR。第四信号是指对所述第三信号φ XOR分别进行不同的时延处理后得到第四信号(φ1，φ2，φ3)。第四信号(φ1，φ2，φ3)分别进行反向处理后得到数据标志位(f1，f2，f3)。
如图4所示，在本实施例中，当前模拟信号Φ ref通过比较器模块200输出比较结果，即第一信号O p和第二信号O m，第一信号O p和第二信号O m经过所述异或门240之后得到的第三信号φ XOR，第三信号φ XOR输入到D触发器模块220，该D触发器模块220由3个相同的D触发器221、D触发器222、D触发器223构成。两个预设信号的电压差值较小时，比较器模块200执行比较时间较长，第三信号φ XOR达到D触发器前D触发器全部已被时钟信号(φ Delay1，φ Delay2， φ Delay3)触发，此时，由于D触发器被触发时，没有输入信号即默认为低电平，因此，D触发器输出的第四信号(φ3，φ2，φ3)均为低电平，将第四信号(φ1，φ2，φ3)通过反向器，得到数据标志位是f1为高电平，f2为高电平，f3为高电平。
在一实施方式中，当两个预设信号的电压差值增大到一定程度时，比较器模块200执行比较时间的缩短，第三信号φ XOR达到前D触发器221和D触发器222已分别被时钟信号φ Delay1，φ Delay2触发，此时，由于D触发器221和D触发器222被触发时，没有输入信号即默认为低电平，因此，D触发器221和D触发器222输出的第四信号φ1是低电平 ，φ2是低电平。由于D触发器223被触发时，第三信号φ XOR已达到D触发器223，因此，D触发器223输出第四信号φ3是高电平，将第四信号(φ1，φ2，φ3)通过反向器，得到数据标志位是f1为高电平，f2为高电平，f3为低电平。
在一实施方式中，当两个预设信号的电压差值继续增大时，比较器模块200执行比较时间的再次缩短，第三信号φ XOR达到前D触发器221已被时钟信号φ Delay1触发，此时，由于D触发器221被触发时，没有输入信号即默认为低电平，因此，D触发器221输出的第四信号φ1是低电平。由于D触发器222和D触发器223被触发时，第三信号φ XOR已达到D触发器222和D触发器223，因此，D触发器222输出第四信号φ2是高电平，D触发器223输出第四信号φ3是高电平，将第四信号(φ1 ，φ2，φ3)通过反向器，得到数据标志位是f1为高电平，f2为低电平，f3为低电平。
在一实施方式中，当两个预设信号的电压差值继续增大到门限值时，比较器模块200执行比较时间的再次缩短，第三信号φ XOR达到前D触发器221，D触发器222和D触发器223均未被时钟信号触发。由于D触发器221，D触发器222和D触发器223被触发时，第三信号φ XOR已达到D触发器221，D触发器222和D触发器223，因此，D触发器222输出第四信号φ1是高电平，D触发器222输出第四信号φ2是高电平，D触发器223输出第四信号φ3是高电平，将第四信号(φ1 ，φ2，φ3)通过反向器，得到数据标志位是f1为低电平，f2为低电平，f3为低电平。
在一个实施方式中，所述时延模块包括电流源，2N个反相器和N+1个NMOS管；其中，所述2N个反相器依次相连，所述电流源与首个NMOS管连接，第n+1个NMOS管与第2n-1个反相器连接，其中n是1至N之间的任意整数。
在一个实施方式中，所述数据偏差补偿模块包括多个相同的模拟延时线单元。
在一个实施方式中，所述模拟延长线单元包括粗延时电路和精延时电路，其中，所述精延时电路包括第一放大器，Nc组电容和Nc个开关，所述粗延电路包括第二放大器、第三放大器，2组电容和2个开关；
其中，所述第一放大器，所述第二放大器和所述第三放大器依次连接，Nc个电容与开关的串联电路并联在所述第一放大器与所述第二放大器之间，2个电容与开关的串联电路并联在所述第二放大器与所述第三放大器之间。
在本实施例中，该模拟延长线单元由三个放大器，(2+N c)个开关以及(2+N c)组电容组成。该模拟延长线单元采用分段式结构，分为粗延时电路与精延时电路两部分，通过数字偏差检测电路生成的数字码控制延时大小。电路采用二进制权重：两位粗调电路使用较大电容C 2，用于快速确定延时范围，N c位精调电路使用较小电容C 1，用于得到准确的相位延时。
在上述实施例的基础上，本申请实施例还提供一种时钟校准设备，所述设备包括如上述实施例中任一项所述的时钟校准装置。时钟校准设备包括但不限于如超外差接收机、低中频接收机、零中频接收机等。
在一个实施例中，图3是本申请实施例提供的时域交织模数转换器的结构示意图，如图3所示，当前模拟信号通过模拟线路100输入到交织ADC模块110和窗口检测器115，交织ADC模块由M个相同的单通道ADC单元111交织采样构成，交织ADC模块的数字输出经过多路开关120输送到误差探测模块125，窗口检测器115输出数据的数据标志位f1,f2,f3也输送到误差探测模块125。误差探测模块125根据当前数字信号对应的标志值调节数据偏差补偿模块105校准时间误差，其中，数据偏差补偿模块由M个相同的模拟延时线(VDL)构成。
图4是本申请实施例提供的窗口检测器结构图，如图4所示，当前模拟信号通过线路100输入到窗口检测器105，当前模拟信号Φ ref通过比较器模块200输出比较结果，即第一信号O p和第二信号O m，第一信号O p和第二信号O m经过所述异或门240之后得到的第三信号φ XOR，第三信号φ XOR输入到D触发器模块220，该D触发器模块220由3个相同的D触发器221、D触发器222、D触发器223构成。当两个预设信号的电压差值较小时，比较器模块200执行比较时间较长，第三信号φ XOR达到D触发器前D触发器全部已被时钟信号(φ Delay1，φ Delay2，φ Delay3)触发，此时，由于D触发器被触发时，没有输入信号即默认为低电平，因此，D触发器输出的第四信号(φ3，φ2，φ3)均为低电平，将第四信号(φ1，φ2，φ3)通过反向器，得到数据标志位是f1为高电平，f2为高电平，f3为高电平。
在一实施方式中，当两个预设信号的电压差值增大到一定程度时，比较器模块200执行比较时间的缩短，第三信号φ XOR达到前D触发器221和D触发器222已分别被时钟信号φ Delay1，φ Delay2触发，此时，由于D触发器221和D触发器222被触发时，没有输入信号即默认为低电平，因此，D触发器221和D触发器222输出的第四信号φ1是低电平 ，φ2是低电平。由于D触发器223被触发时，第三信号φ XOR已达到D触发器223，因此，D触发器223输出第四信号 φ3是高电平，将第四信号(φ1，φ2，φ3)通过反向器，得到数据标志位是f1为高电平，f2为高电平，f3为低电平。
在一实施方式中，当两个预设信号的电压差值继续增大时，比较器模块200执行比较时间的再次缩短，第三信号φ XOR达到前D触发器221已被时钟信号φ Delay1触发，此时，由于D触发器221被触发时，没有输入信号即默认为低电平，因此，D触发器221输出的第四信号φ1是低电平。由于D触发器222和D触发器223被触发时，第三信号φ XOR已达到D触发器222和D触发器223，因此，D触发器222输出第四信号φ2是高电平，D触发器223输出第四信号φ3是高电平，将第四信号(φ1 ，φ2，φ3)通过反向器，得到数据标志位是f1为高电平，f2为低电平，f3为低电平。
在一实施方式中，当两个预设信号的电压差值继续增大到门限值时，比较器模块200执行比较时间的再次缩短，第三信号φ XOR达到前D触发器221，D触发器222和D触发器223均未被时钟信号触发。由于D触发器221，D触发器222和D触发器223被触发时，第三信号φ XOR已达到D触发器221，D触发器222和D触发器223，因此，D触发器222输出第四信号φ1是高电平，D触发器222输出第四信号φ2是高电平，D触发器223输出第四信号φ3是高电平，将第四信号(φ1，φ2，φ3)通过反向器，得到数据标志位是f1为低电平，f2为低电平，f3为低电平。
根据偏差探测模块的输出结果，对交织ADC模块输出的采样值进行分组，即确定单通道ADC单元输出的当前数字信号所属类型。
输出数字信号根据产生通道与所属电压窗口不同分为不同组。当f1，f2，f3均为高电平时，采样值进入组(i,1)，即当前数字信号所属类型为(i,1)；当f1，f2为高电平，f3为低电平时，采样值进入组(i,2)，即当前数字信号所属类型为(i,2)；当f1为高电平，f2，f3为低电平时，采样值进入组(i,3)，即当前数字信号所属类型为(i,3)，当f1，f2，f3均为低电平时，偏差探测模块不接收当前数字信号。然后对组(i,1)，组(i,2)，组(i,3)分别计算组内方差σ 2(i,j)并产生补偿值(补偿值初始为0)。
图5是本申请实施例提供的窗口检测器时序图，φ ref为外部控制时钟，即当前模拟信号，当φ ref为高电平时比较器工作，此时比较器模块在产生比较结果之前，输出O p与O m均为高电平，两个预设信号的电压差值相差越小，比较时间越长。将O p与O m输入异或门得到φ XOR作为D触发器输入。将φref输入三个延时电路得到φDelay1，φDelay2，φDelay3作为三个D触发器的时钟信号。通过调节延时电路延时时间，最后实现令输入信号相差在门限T 1，T 2，T 3以内时，可以得到D触发器输出的数据标志位f1，f2，f3。
图6是本申请实施例提供的延时模块组成示意图。如图6所示，该延时模块包括：一个 电流源，2N个反相器组410，以及N+1个NMOS模块420，输出时延后的时钟φDelay1，φDelay2，φDelay3。
图7是本申请实施例提供的延时线电路模块组成示意图，如图7所示，该电路由三个放大器，(2+Nc)个开关以及(2+Nc)组电容组成。该电路采用分段式结构，分为粗延时电路500与精延时电路510两部分，通过数字偏差检测电路生成的数字码控制延时大小。电路采用二进制权重：两位粗调电路使用较大电容C2，用于快速确定延时范围，Nc位精调电路使用较小电容C1，用于得到准确的相位延时。
在一个实施例中，提供一种时钟校准的方法。主要包括：根据窗口检测器输出对交织ADC模块的输出进行分组。可以根据方差大小对时延值进行调整。图8是本申请实施例提供的时钟校准方法的流程图，如图8所示，本申请实施例提供的时钟校准方法步骤如下：
步骤600.系统检测到芯片温度变化值大于温度变化阈值或者检测到交织ADC模块与参考ADC之间的时间误差大于误差阈值；
步骤610.触发时钟校准；
步骤620.对待校准单通道ADC单元的输出的数字信号和窗口检测器的输出的数据标识位进行关联分组。
步骤630.求得各分组内的数据方差D m,i。
步骤640.以第i组数据为参考，通过当前迭代和上一次迭代的D m,i,得到D' m,i，从而可以确定数字码元迭代的方向和步长：
Figure PCTCN2022070168-appb-000002
通过代价函数，对模拟延时线的数字码进行更新，从而调节第m路ADC的时间延迟。
T m,n＝T m,n-1+u 2D' m,i
其中T m,n和T m,n-1分别表示第m路ADC在当前时刻和前一时刻的模拟延时线的数字控制码，u 2为步进值。
步骤650.判断是否满足校准完成条件，若不满足，重复进行上述过程，直到各组数据的方差达到预先设定的校准阈值或者迭代达到预先设定的迭代次数，表明此时时间误差校准完成。
图9是本申请实施例提供的时钟偏差的示意图；图10是本申请实施例提供的时钟校准算法的原理示意图。在图9中，标明了实际采样时刻落后于理想采样时刻的情况，τ i为时间误差落后时间，此时对信号的采样值产生了Δx误差。参照图10，当ADC单元与窗口检测器之 间存在时钟偏差时，ADC输出的数字码将会产生较大的方差，而当时钟偏差很小时，ADC的输出将会集中在几个相邻数字码中，此时方差很小。
本申请实施例提供的时钟校准方法和装置，当交织ADC与参考通道ADC存在时间误差时，传统的方法需要较长的统计时间。本申请采用窗口检测器，可以利用较少的数据估计出时间误差的大小和方向。窗口检测器的设计方法简单，功耗低。当前模拟信号无需频繁经过零点；本申请可以前台运行，也可以后台运行，从而可以跟踪PVT变化对时间误差带来的影响。
本实施例中提供的时钟校准装置可执行本申请任意实施例所提供的时钟校准方法，具备执行该方法相应的功能模块和有益效果。未在本实施例中详尽描述的技术细节，可参见本申请任意实施例所提供时钟校准方法。
值得注意的是，上述时钟校准装置的实施例中，所包括的各个单元和模块只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。
上述实施例提供的时钟校准方法、装置和设备，包括：针对交织模数转换器ADC模块中的每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型；所述当前通道对应的数字信号是当前模拟信号经过该通道对应的ADC后得到的信号；确定该类型的当前数字信号对应的补偿值；基于所述当前数字信号对应的补偿值对所述通道对应的ADC进行时钟校准。本申请实施例的技术方案确定数字信号的类型后，确定该类型数字信号的补偿值，利用该补偿值进行时钟校准，实现了利用较少的数据估计出时间误差的大小和方向，方法简单，功耗低。通过示范性和非限制性的示例，上文已提供了对本申请的示范实施例的详细描述。但结合附图和权利要求来考虑，对以上实施例的多种修改和调整对本领域技术人员来说是显而易见的，但不偏离本申请的范围。因此，本申请的恰当范围将根据权利要求确定。

Claims (13)

  1. 一种时钟校准方法，包括：
    针对交织模数转换器ADC模块中的每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型，所述交织ADC模块包括多个单通道ADC，所述通道对应的数字信号是当前模拟信号经过对应的单通道ADC后得到的信号；
    确定该类型的当前数字信号对应的补偿值；
    基于所述当前数字信号对应的补偿值对所述通道对应的单通道ADC进行时钟校准。
  2. 根据权利要求1所述的方法，其中，基于当前模拟信号确定该通道对应的当前数字信号类型，包括：
    基于当前模拟信号确定对应的数据标志位；
    将所述数据标志位对应的类型确定为该通道对应的当前数字信号类型。
  3. 根据权利要求2所述的方法，其中，基于当前模拟信号确定对应的数据标志位，包括：
    生成预设数量的电压窗口；
    基于所述当前模拟信号的电压值与所述电压窗口的比较结果，确定当前模拟信号对应的数据标志位。
  4. 根据权利要求1所述的方法，其中，基于所述当前数字信号对应的补偿值对所述通道对应的ADC进行时钟校准，包括：
    当所述数字信号对应的补偿值大于或等于校准阈值，则基于所述当前数字信号对应的补偿值调整所述通道对应的时间延迟，并将新输入的模拟信号确定为当前模拟信号，返回执行基于当前模拟信号确定所述通道对应的当前数字信号类型的操作，直到所述当前数字信号对应的补偿值小于所述校准阈值。
  5. 根据权利要求4所述的方法，其中，所述当前数字信号对应的补偿值包括所述当前数字信号对应的方差；
    基于所述当前数字信号对应的补偿值调整所述通道对应的时间延迟，包括：
    基于所述当前数字信号对应的方差和上一时刻数字信号对应的方差，确定当前模拟延时线的数字码元的方向和步长；
    通过代价函数和所述当前模拟延时线的数字码元的方向和步长更新当前模拟延时线的数字码元；
    基于更新后的当前模拟延时线的数字码元调整所述通道对应的时间延迟。
  6. 根据权利要求1所述的方法，其中，针对ADC模块中的每个通道，基于当前模拟信号 确定所述通道对应的当前数字信号类型之前还包括：
    检测到时钟芯片的温度变化值大于温度变化阈值，或者，检测到交织ADC模块与参考ADC之间的时间误差大于误差阈值，则触发时钟校准。
  7. 一种时钟校准装置，所述时钟校准装置包括：交织模数转换器ADC模块，偏差检测模块和数据偏差补偿模块，其中，所述交织ADC模块包括多个单通道ADC；
    各个所述单通道ADC，被设置为将当前模拟信号转换为当前数字信号；
    所述偏差检测模块，被设置为针对每个通道，基于当前模拟信号确定所述通道对应的当前数字信号类型，确定该类型的当前数字信号对应的补偿值，并基于所述当前数字信号对应的补偿值确定当前模拟延时线；
    数据偏差补偿模块，被设置为基于所述当前模拟延时线对所述通道对应的单通道ADC进行时钟校准。
  8. 根据权利要求7所述的装置，其中，所述偏差检测模块包括窗口检测器和偏差探测模块，其中，
    所述窗口检测器，被设置为基于当前模拟信号确定对应的数据标志位；
    所述偏差探测模块，被设置为将所述数据标志位对应的类型确定为该通道对应的当前数字信号类型。
  9. 根据权利要求8所述的装置，其中，所述窗口检测器包括：比较器模块，时延模块，触发器模块，异或门和输出单元，其中，
    所述比较器模块接收到触发信号后，将预设信号进行比较，得到比较结果，所述比较结果包括第一信号和第二信号；所述第一信号和第二信号经过所述异或门之后得到第三信号，并输入至触发器模块；
    所述触发信号经过所述时延模块后输入至所述触发器模块，作为所述触发器模块的时钟信号；
    所述触发器模块基于所述时钟信号对所述第三信号进行时延处理后得到第四信号，并输入至输出单元；
    所述输出单元将所述第四信号进行反向处理后得到当前模拟信号对应的数据标志位。
  10. 根据权利要求9所述的装置，其中，所述时延模块包括电流源，2N个反相器和N+1个NMOS管；其中，所述2N个反相器依次相连，所述电流源与首个NMOS管连接，第n+1个NMOS管与第2n-1个反相器连接，其中n是1至N之间的任意整数。
  11. 根据权利要求7所述的装置，其中，所述数据偏差补偿模块包括多个相同的模拟延时线单元。
  12. 根据权利要求11所述的装置，其中，所述模拟延长线单元包括粗延时电路和精延时电路，其中，所述精延时电路包括第一放大器，Nc组电容和Nc个开关，所述粗延电路包括第二放大器、第三放大器，2组电容和2个开关；
    其中，所述第一放大器，所述第二放大器和所述第三放大器依次连接，Nc个电容与开关的串联电路并联在所述第一放大器与所述第二放大器之间，2个电容与开关的串联电路并联在所述第二放大器与所述第三放大器之间。
  13. 一种时钟校准设备，所述设备包括如权利要求6-11中任一项所述的时钟校准装置。
PCT/CN2022/070168 2021-03-05 2022-01-04 一种时钟校准方法、装置和设备 WO2022183842A1 (zh)

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