WO2022181391A1 - Procédé de production de tranche de silicium, et tranche de silicium - Google Patents

Procédé de production de tranche de silicium, et tranche de silicium Download PDF

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Publication number
WO2022181391A1
WO2022181391A1 PCT/JP2022/005929 JP2022005929W WO2022181391A1 WO 2022181391 A1 WO2022181391 A1 WO 2022181391A1 JP 2022005929 W JP2022005929 W JP 2022005929W WO 2022181391 A1 WO2022181391 A1 WO 2022181391A1
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Prior art keywords
silicon wafer
heat treatment
thermal budget
condition
layer
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PCT/JP2022/005929
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English (en)
Japanese (ja)
Inventor
進 前田
治生 須藤
尚 松村
竜彦 青木
徹 山下
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グローバルウェーハズ・ジャパン株式会社
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Priority to KR1020237028590A priority Critical patent/KR20230132578A/ko
Publication of WO2022181391A1 publication Critical patent/WO2022181391A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation

Definitions

  • the present invention relates to a silicon wafer manufacturing method and a silicon wafer, having a defect-free layer (DZ layer) on the surface layer by rapid heating / cooling heat treatment (RTP treatment), and an intrinsic gettering layer (IG) by oxygen precipitates on the bulk layer layer) and a silicon wafer.
  • DZ layer defect-free layer
  • RTP treatment rapid heating / cooling heat treatment
  • IG intrinsic gettering layer
  • COPs Crystal Originated Particles present in the device active region of the wafer (approximately 10 ⁇ m deep from the wafer surface) can cause deterioration in the characteristics and reliability of semiconductor devices. be.
  • RTP rapid heating/cooling heat treatment
  • a silicon wafer is heat-treated at a high temperature to diffuse oxygen on the surface of the wafer outward to reduce interstitial oxygen. Defects are dissolved by the unsaturated state of oxygen to form a defect-free layer (DZ layer) free of minute defects in the device active region on the wafer surface.
  • DZ layer defect-free layer
  • BMDs Bulk Micro-Defects
  • minute SiO 2 precipitates BMDs
  • the thermal budget in RTP should be as small as possible. There was a problem.
  • An object of the present invention is to complete the heat treatment without damaging the RTP apparatus when performing a rapid heating / cooling heat treatment (RTP) on a silicon wafer, and a DZ layer without microdefects in the device active region on the surface of the heat treated silicon wafer. is formed, an IG layer with a high gettering ability is formed on the bulk layer, and the wafer surface is less contaminated with heavy metals, and a clean silicon wafer can be manufactured. aim.
  • RTP rapid heating / cooling heat treatment
  • a silicon wafer manufacturing method which has been made to solve the above problems, is a silicon wafer manufacturing method in which a silicon wafer is subjected to rapid heating / cooling heat treatment in a furnace, wherein the thermal budget of temperature and time is maximized.
  • the thermal budget condition for continuing heat treatment at a temperature of 1350° C. for a predetermined maximum time is 100%
  • the heat treatment is characterized by rapid heating/cooling heat treatment with a thermal budget of 53% or more and 65% or less.
  • the silicon wafer used for the rapid heating/cooling heat treatment is controlled so that the oxygen concentration of the substrate is 0.6 ⁇ 10 18 atoms/cm 3 or more and 1.0 ⁇ 10 18 atoms/cm 3 or less (ASTM '79). It is desirable to Further, in the step of continuing the heat treatment with a maximum temperature of 1350° C. for a predetermined maximum time, it is desirable that the predetermined maximum time is 20 seconds.
  • the thermal budget (sum of heat treatment steps) is 100%.
  • the silicon wafer is heat-treated with a thermal budget of 53% or more and 65% or less.
  • the heat treatment is completed without damaging the RTP device (lamp, etc.), and a DZ layer free of microdefects is formed in the device active region on the surface of the heat-treated silicon wafer, and the IG with high gettering ability is formed in the bulk layer.
  • a layer is formed and a clean silicon wafer can be produced with less heavy metal contamination on the wafer surface.
  • a silicon wafer according to the present invention which has been made to solve the above problems, has a surface layer with a LSTD count of 0.3 pcs/cm 2 or less, and a bulk layer with a BMD density of 5 ⁇ 10 10 cm ⁇ It is characterized by being 3 or more.
  • the oxygen concentration of the substrate is preferably 0.6 ⁇ 10 18 atoms/cm 3 or more and 1.0 ⁇ 10 18 atoms/cm 3 or less (ASTM'79).
  • the heat treatment when performing rapid heating/cooling heat treatment (RTP) on a silicon wafer, the heat treatment is completed without damaging the RTP apparatus, and the device active region on the surface of the heat-treated silicon wafer has no microdefects in the DZ layer. is formed, an IG layer with a high gettering ability is formed on the bulk layer, and a clean silicon wafer can be produced with less heavy metal contamination on the wafer surface.
  • RTP rapid heating/cooling heat treatment
  • FIG. 1 is a cross-sectional view showing one form of a rapid heating/cooling heat treatment apparatus (RTP apparatus) to which the method for manufacturing a silicon wafer of the present invention is applied.
  • FIG. 2 is a graph showing an example of thermal history of a silicon wafer applied in the rapid heating/cooling thermal processing apparatus (RTP apparatus) of FIG.
  • FIG. 3 shows conditions No. of the embodiment. 1 is a graph showing the thermal history of No. 1;
  • FIG. 4 shows conditions No. of the embodiment. 2 is a graph showing the thermal history of No. 2;
  • FIG. 5 shows conditions No. of the embodiment. 3 is a graph showing the thermal history of No. 3;
  • FIG. 6 shows conditions No. of the embodiment. 4 is a graph showing the thermal history of No. 4;
  • FIG. 7 shows conditions No. of the embodiment. 5 is a graph showing the thermal history of No. 5;
  • FIG. 8 shows conditions No. of the embodiment. 6 is a graph showing the thermal history of No. 6;
  • FIG. 9 shows conditions No. of the embodiment. 7 is a graph showing the thermal history of No. 7;
  • FIG. 10 shows conditions No. of the embodiment. 8 is a graph showing the thermal history of No. 8;
  • FIG. 11 shows conditions No. of the embodiment. 9 is a graph showing the thermal history of No. 9;
  • FIG. 14 shows conditions No. of the embodiment.
  • FIG. 12 is a graph showing the thermal histories of No. 12;
  • FIG. 15 is a graph showing the results of Experiments 1 and 2 of the example.
  • FIG. 16 is a graph showing the results of Experiment 3 of the example.
  • FIG. 17 is a graph showing the results of Experiments 4 and 5 of Examples.
  • FIG. 1 is a cross-sectional view showing one form of a rapid heating/cooling heat treatment apparatus (RTP apparatus) to which the method for manufacturing a silicon wafer of the present invention is applied.
  • the RTP apparatus 1 includes a chamber (reaction tube) 20 having an atmospheric gas inlet 20a and an atmospheric gas outlet 20b, a plurality of lamps 30 spaced apart above the chamber 20, A substrate supporter 40 for supporting the silicon wafer W in the reaction space 25 inside the chamber 20 is provided. Further, although not shown, there is provided rotating means for rotating the silicon wafer W around its central axis at a predetermined speed.
  • the substrate support section 40 includes a ring 10 that supports the outer peripheral portion of the silicon wafer W, and a stage 40a that supports the ring 10 .
  • the chamber 20 is made of quartz, for example.
  • the lamp 30 is composed of, for example, a halogen lamp.
  • the stage 40a is made of quartz, for example.
  • the RTP apparatus 1 can uniformly heat and process the entire silicon wafer W at a temperature gradient of 10 to 300° C./sec. The thermal budget will be detailed later.
  • a plurality of radiation thermometers embedded in the stage 40a of the substrate support section 40 detect multiple points (for example, nine points) within the substrate surface in the substrate radial direction below the silicon wafer W.
  • the reaction space Temperature control within 25 is performed.
  • the silicon wafer W is mounted on the ring 10 and fixed.
  • This ring 10 is fixed above a stage 40a installed in a reaction space 25 under an oxidizing atmosphere so that the upper surface of the silicon wafer W is substantially parallel.
  • the process gas is introduced from the atmosphere gas inlet 20a and the gas in the reaction space 25 is exhausted from the atmosphere gas outlet 20b to form a predetermined air flow on the silicon wafer W.
  • the halogen lamps 30 arranged at equal intervals are individually controlled based on feedback from a plurality of radiation thermometers embedded in the stage 40a, that is, based on the temperature under the silicon wafer W.
  • the inside of the reaction space 25 is rapidly heated while controlling the temperature of the silicon wafer W, and the silicon wafer W is heat-treated.
  • the thermal budget (sum of heat treatment steps) is 100%.
  • a rapid heating/cooling heat treatment is performed with a thermal budget of 53% or more and 65% or less.
  • the wafer surface temperature is heated to 1300° C. within 10 seconds after the start of heating.
  • the wafer surface temperature is heated to 1350° C. within 27 to 32 seconds after the start of heating, and this state is continued for 0 to 6 seconds.
  • the inside of the furnace is rapidly cooled to complete the rapid heating/cooling heat treatment.
  • the silicon wafer used in this rapid heating/cooling heat treatment step should have an oxygen concentration of 0.6 ⁇ 10 18 atoms/cm 3 or more and 1.0 ⁇ 10 18 atoms/cm 3 or less (ASTM '79). Control.
  • the Fe—B concentration by the SPV (Surface Photovoltage) method can be lowered (less than 1 ⁇ 10 9 cm ⁇ 3 ), and the silicon wafer can be cleaned. If the heating time at 1350° C. is too long and the thermal budget is too large, Fe contamination (heavy metal contamination) becomes noticeable, and the thermal load on the RTP device 1 increases, which may lead to damage to the lamp, etc., which is preferable. do not have.
  • the thermal budget (heat treatment process) is 100% when the heating time at the maximum heating temperature of 1350 ° C. is 20 seconds. ), the silicon wafer is heat-treated with a thermal budget of 53% or more and 65% or less.
  • the heat treatment is completed without damaging the RTP apparatus, a DZ layer free of minute defects is formed in the device active region on the surface of the heat-treated silicon wafer, and an IG layer with high gettering ability is formed in the bulk layer.
  • a clean silicon wafer can be produced with less heavy metal contamination on the wafer surface.
  • the maximum temperature of 1350° C. is maintained for several seconds to adjust the preferred ratio of the thermal budget, but the present invention is not limited to this form. Even if the maximum temperature of 1350° C. does not last for a duration, the thermal budget ratio may be adjusted to 53% or more and 65% or less by cooling gradually.
  • the duration at the maximum temperature was set to 20 seconds in the rapid heating/cooling heat treatment, but the present invention is not limited to this, and the maximum duration may be longer than 20 seconds. .
  • Example 1 In Experiment 1, the number of LSTDs (small defects such as COPs detected by scattered laser light) was measured by changing the conditions of the rapid heating/cooling heat treatment for silicon wafers.
  • the oxygen concentration of the substrate of the silicon wafer used in this rapid heating/cooling heat treatment step is approximately 1.0 ⁇ 10 18 atoms/cm 3 (ASTM'79).
  • Condition no. In 3 the heat history was set as shown in FIG. 5, the maximum temperature was set to 1350° C., and the maximum temperature duration was set to 13 seconds. Also, the thermal budget under these conditions was set at 85.1%.
  • Condition no. In 4 the heat history was as shown in FIG. 6, the maximum temperature was 1350° C., and the maximum temperature duration was 10 sec. Also, the thermal budget under these conditions was set at 75.2%.
  • Condition no. In 5 the heat history was set as shown in FIG. 7, the maximum temperature was set to 1350° C., and the maximum temperature duration was set to 8 seconds. Also, the thermal budget under these conditions was set at 65.4%.
  • Condition no. In 6 the heat history was set as shown in FIG. 8, the maximum temperature was set to 1350° C., and the maximum temperature duration was set to 2 seconds. Also, the thermal budget under these conditions was set at 59.4%.
  • Condition no. In 7 the heat history was set as shown in FIG. 9, the maximum temperature was set to 1350° C., and the maximum temperature duration was set to 0.1 sec. Also, the thermal budget under these conditions was set at 52.8%.
  • Condition no. In No. 8 the heat history was set as shown in FIG. 10, the maximum temperature was set to 1340° C., and the maximum temperature duration was set to 0.1 sec. Also, the thermal budget under these conditions was set at 42.3%.
  • Condition no. In 9 the heat history was set as shown in FIG. 11, the maximum temperature was set to 1330° C., and the maximum temperature duration was set to 0.1 sec. Also, the thermal budget under these conditions was set at 31.7%.
  • Condition no. In No. 10 the heat history was set as shown in FIG. 12, the maximum temperature was set to 1320° C., and the maximum temperature duration was set to 0.1 sec. Also, the thermal budget under these conditions was set at 21.1%.
  • Graph condition No. in FIG. 1-12 results are shown.
  • the vertical axis (left side) of the graph in FIG. 15 is predicted LSTD (co/cm 2 ), and the horizontal axis is condition No.
  • LSTD is condition no. 1 to No. increased with decreasing thermal budget, up to 12.
  • Condition no. After 8, the number of LSTD exceeded 0.3/cm 2 and the value became worse. Therefore, as the heat treatment conditions for erasing the COPs on the wafer surface layer, Condition No. 1 to No. 7 has been found to be preferred.
  • Example 2 In Experiment 2, the BMD density of the bulk layer was measured under the same rapid heating/cooling heat treatment conditions as in Experiment 1. Condition No. is shown in the graph of FIG. 1-12 results are shown. The vertical axis (right side) of the graph in FIG. 15 is the BMD density (cm ⁇ 3 ) of the bulk layer, and the horizontal axis is the condition No. As shown in this graph, condition no. 1 to No. 7, the BMD density of the bulk layer was substantially constant and a sufficiently high value (5 ⁇ 10 10 cm ⁇ 3 or more) was obtained. However, condition no. 8 and later, the BMD density of the bulk layer decreased as the thermal budget decreased. This is because the vacancy concentration introduced by the rapid heating/cooling heat treatment decreases with the thermal budget. Therefore, as a heat treatment condition for sufficient gettering performance of the bulk layer, Condition No. 1 to No. 7 has been found to be preferred.
  • Experiment 4 In Experiment 4, the conditions of rapid heating/cooling heat treatment for silicon wafers were changed in the same manner as in Experiment 1, and the number of LSTDs (small defects such as COPs detected by scattering laser light) was measured. Experiment 4 differs from Experiment 1 only in the oxygen concentration of the silicon wafer substrate used in the rapid heating/cooling heat treatment process, which is about 0.6 ⁇ 10 18 atoms/cm 3 (ASTM'79). Condition No. is shown in the graph of FIG. 1-12 results are shown. The vertical axis (left side) of the graph in FIG. 17 is predicted LSTD (co/cm 2 ), and the horizontal axis is condition No. As shown in this graph, the number of LSTDs varies depending on condition no. 1 to No. 12, the target value was 0.3 co/cm 2 or less.
  • the oxygen concentration of the substrate is preferably 0.6 ⁇ 10 18 atoms/cm 3 or more and about 1.0 ⁇ 10 18 atoms/cm 3 or less (ASTM'79).
  • the silicon wafer manufacturing method according to the present invention is useful for silicon wafers that require high quality, and is particularly suitable for performing rapid heating/cooling heat treatment (RTP) on silicon wafers.
  • RTP rapid heating/cooling heat treatment

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Selon la présente invention, une tranche de silicium propre est produite qui présente moins de contamination par métaux lourds sur la surface de la tranche, tout en étant pourvue d'une couche DZ dans une région active de dispositif dans la surface de la tranche de silicium qui a été soumise à un traitement thermique, la couche DZ étant exempte de micro-défauts, et en étant également pourvue d'une couche IG qui a une capacité d'absorption de gaz élevée dans une couche en profondeur.　L'invention concerne également un procédé de production d'une tranche de silicium, dans lequel une tranche de silicium est soumise à un traitement thermique d'élévation/abaissement rapide de température dans un four. En ce qui concerne un budget thermique de la température et le temps, si le budget thermique avec lequel un traitement thermique ayant une température maximale de 1350 °C est maintenu pendant une période de temps maximale prédéterminée est pris comme 100 %, le traitement thermique d'élévation/abaissement rapide de température est effectué avec un budget thermique de 53 % à 65 %.
PCT/JP2022/005929 2021-02-25 2022-02-15 Procédé de production de tranche de silicium, et tranche de silicium WO2022181391A1 (fr)

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JP2021-028234 2021-02-25

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001055485A1 (fr) * 2000-01-25 2001-08-02 Shin-Etsu Handotai Co., Ltd. Plaquette de silicium, procede de determination de la condition dans laquelle est produit un monocristal de silicium et procede de production d'une plaquette de silicium
JP2001284362A (ja) * 2000-03-31 2001-10-12 Toshiba Ceramics Co Ltd シリコンウェーハの製造方法
JP2008294112A (ja) * 2007-05-23 2008-12-04 Sumco Corp シリコン単結晶ウェーハ及びその製造方法
JP2011222842A (ja) * 2010-04-13 2011-11-04 Shin Etsu Handotai Co Ltd エピタキシャルウェーハの製造方法、エピタキシャルウェーハ及び撮像用デバイスの製造方法
JP2011233556A (ja) * 2010-04-23 2011-11-17 Covalent Materials Corp シリコンウェーハの熱処理方法
JP2012175023A (ja) * 2011-02-24 2012-09-10 Shin Etsu Handotai Co Ltd シリコン基板の製造方法及びシリコン基板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003273049A (ja) 2002-03-18 2003-09-26 Toshiba Ceramics Co Ltd ウエハの真空貼付装置
JP5984448B2 (ja) * 2012-03-26 2016-09-06 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハ

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001055485A1 (fr) * 2000-01-25 2001-08-02 Shin-Etsu Handotai Co., Ltd. Plaquette de silicium, procede de determination de la condition dans laquelle est produit un monocristal de silicium et procede de production d'une plaquette de silicium
JP2001284362A (ja) * 2000-03-31 2001-10-12 Toshiba Ceramics Co Ltd シリコンウェーハの製造方法
JP2008294112A (ja) * 2007-05-23 2008-12-04 Sumco Corp シリコン単結晶ウェーハ及びその製造方法
JP2011222842A (ja) * 2010-04-13 2011-11-04 Shin Etsu Handotai Co Ltd エピタキシャルウェーハの製造方法、エピタキシャルウェーハ及び撮像用デバイスの製造方法
JP2011233556A (ja) * 2010-04-23 2011-11-17 Covalent Materials Corp シリコンウェーハの熱処理方法
JP2012175023A (ja) * 2011-02-24 2012-09-10 Shin Etsu Handotai Co Ltd シリコン基板の製造方法及びシリコン基板

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TWI805242B (zh) 2023-06-11
TW202240034A (zh) 2022-10-16
KR20230132578A (ko) 2023-09-15

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