WO2022179195A1 - 一种偏置电路及放大器 - Google Patents

一种偏置电路及放大器 Download PDF

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Publication number
WO2022179195A1
WO2022179195A1 PCT/CN2021/130749 CN2021130749W WO2022179195A1 WO 2022179195 A1 WO2022179195 A1 WO 2022179195A1 CN 2021130749 W CN2021130749 W CN 2021130749W WO 2022179195 A1 WO2022179195 A1 WO 2022179195A1
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Prior art keywords
transistor
voltage
current source
mirror current
supply voltage
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PCT/CN2021/130749
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English (en)
French (fr)
Inventor
刘炽锋
苏强
徐啸
李咏乐
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广州慧智微电子股份有限公司
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Publication of WO2022179195A1 publication Critical patent/WO2022179195A1/zh
Priority to US17/929,705 priority Critical patent/US20220413538A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/61—Indexing scheme relating to amplifiers the cascode amplifier has more than one common gate stage

Definitions

  • the present application relates to the field of circuit technology, and in particular, to a bias circuit and an amplifier.
  • the gain of the amplifier needs to be kept as constant as possible as the input power continues to increase.
  • the output power will change linearly with the increase or decrease of the input power, so the amplifier has a high linearity.
  • a bias circuit can be used to provide a bias voltage to the transistors in the amplifier, so that under the power supply voltage, the output power linearity of the amplifier has better performance.
  • 3GPP Third Generation Partnership Project
  • the amplifier also needs to work under the condition that the power supply voltage is low voltage 3V and high voltage 4.6V, so the bias circuit provides The bias voltage cannot meet the requirements of the bias performance of the transistors in the amplifier, so that the accuracy of the provided bias voltage is reduced.
  • the embodiments of the present application expect to provide a bias circuit and an amplifier, which improve the accuracy of the provided bias voltage.
  • An embodiment of the present application provides a bias circuit, and the bias circuit includes:
  • the first end of the mirror current source is connected to the power supply voltage end
  • the second end of the mirror current source is connected to the reference voltage end
  • the third end of the mirror current source is connected to the current-voltage converter
  • the mirror current source is configured to obtain the power supply voltage transmitted by the supply voltage terminal through the first terminal, obtain the reference voltage transmitted by the reference voltage terminal through the second terminal, and use the reference voltage and the preset voltage. Setting parameters to adjust the power supply voltage to obtain a mirror current corresponding to the power supply voltage; the preset parameter is parameter information of the mirror current source;
  • the current-to-voltage converter is configured to convert the mirror current to a voltage to provide a bias voltage based on the voltage.
  • An embodiment of the present application provides an amplifier, and the amplifier includes:
  • a bias current fixer a first amplifying transistor, a second amplifying transistor, and a bias circuit as described above;
  • the output end and the signal input end of the bias current fixer are respectively connected with the first end of the first amplifying transistor
  • the output end of the bias circuit is connected to the first end of the second amplifying transistor
  • the second end of the first amplifying transistor is connected to the second end of the second amplifying transistor
  • the third end of the second amplifying transistor is respectively connected to the power supply voltage end and the signal output end;
  • the bias current fixer configured to fix the current in the first amplifying transistor
  • the bias circuit configured to provide a bias voltage to the second amplifying transistor
  • the first amplifying transistor is configured to amplify the input signal obtained from the signal input end to obtain an amplified signal, and transmit the amplified signal to the second end of the second amplifying transistor;
  • the second amplifying transistor is configured to amplify the amplified signal to obtain the output signal, and output the output signal through the signal output terminal.
  • An embodiment of the present application provides a bias circuit and an amplifier
  • the bias circuit includes: a mirror current source and a current-voltage converter; a first end of the mirror current source is connected to a power supply voltage end; a second end of the mirror current source is connected to the reference voltage terminal is connected; the third terminal of the mirror current source is connected to the current-voltage converter;
  • the mirror current source is configured to obtain the power supply voltage transmitted by the power supply voltage terminal through the first terminal, and obtain the reference voltage transmitted by the reference voltage terminal through the second terminal , and use the reference voltage and preset parameters to adjust the power supply voltage to obtain the mirror current corresponding to the power supply voltage;
  • the preset parameter is the parameter information of the mirror current source;
  • the current-to-voltage converter is configured to convert the mirror current into a voltage, so as to The bias voltage is provided based on the voltage.
  • the mirror current source is used to connect the power supply voltage terminal, the reference voltage terminal and the current-voltage converter respectively, so as to adjust the power supply voltage according to the reference voltage and preset parameters, and obtain the corresponding power supply voltage.
  • the mirror current is converted into a voltage by a current-to-voltage converter, so that the bias circuit can provide a bias voltage based on the voltage. Since the reference voltage and the preset parameters are both fixed values, the provided bias voltage can vary with the voltage. The increase of the power supply voltage can be decreased with the decrease of the power supply voltage, which improves the accuracy of the provided bias voltage.
  • FIG. 1 is a schematic diagram of an amplifier in the prior art provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of an exemplary output 1dB compression point corresponding to a general power amplifier under different supply voltages provided by an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of the composition of a bias circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the composition and structure of an exemplary bias circuit provided by an embodiment of the present application.
  • FIG. 5( a ) is a schematic diagram of an exemplary relationship between the second mirror current and the power supply voltage provided by the embodiment of the application;
  • FIG. 5(b) is a schematic diagram of the relationship between the voltage output by the voltage output terminal and the power supply voltage, according to an exemplary embodiment of the present application;
  • FIG. 6 is a schematic diagram of the composition and structure of an exemplary amplifier provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the composition and structure of an amplifier provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an exemplary relationship between a power supply voltage, a reference voltage, and a voltage according to an embodiment of the present application
  • FIG. 9 is a schematic structural diagram of an exemplary amplifier provided by an embodiment of the present application.
  • the power gain of the amplifier needs to be kept as constant as possible when the input power gradually increases, so that the gain is a constant value.
  • the gain of the amplifier cannot always be a constant value.
  • the gain of the amplifier will gradually decrease.
  • the change of the gain of the amplifier is small, the output power will decrease.
  • the amplifier has a high linearity.
  • a Cascode structure is generally used due to the requirement of withstand voltage.
  • FIG. 1 The structure is shown in Figure 1, generally consisting of transistors M1 and M2, feedback capacitor C1, RF inductor L2, bias circuit (VG1), bias circuit (VG2), low-pass filter, input terminal RF_input and output terminal RF_OUTPUT COMPOSITION.
  • the amplifier has a linear dynamic range within which the output power of the amplifier increases linearly with the input power. As the input power continues to increase, the amplifier enters the nonlinear region, and its output power no longer increases linearly with the input power, that is, its output power is lower than expected for small-signal gain.
  • the output power value when the gain drops to 1dB lower than the linear gain is defined as the 1dB compression point of the output power, which is expressed by P1dB, that is, the 1dB compression output power (P1dB).
  • linearity of the power amplifier mainly refers to the gain linearity, that is, when the output power of the power amplifier reaches the 1dB compression point, the corresponding output power (P1dB) of the power amplifier.
  • the bias circuit VG1 when the supply voltage VDD is given, the bias circuit VG1 can have a fixed bias voltage to the gate of the transistor M1, and the bias circuit VG2 can apply a fixed bias voltage to the gate of the transistor M2 a fixed bias voltage. Therefore, under the VDD voltage, the output power linearity of the power amplifier has relatively good performance.
  • the power amplifier according to the 3GPP protocol, in addition to the conventional voltage supply voltage VDD of 3.5V, the power amplifier also needs to work under the condition that the supply voltage VDD is low-voltage 3V and high-voltage 4.6V.
  • the normal voltage is 3.5V
  • the high voltage is 4.6V
  • the low voltage is 3V
  • the output power of the corresponding 1dB compression point is shown in Figure 2.
  • the 1dB compression The output power of the point is the power at the B position; when the supply voltage is 3V, the output power of the 1dB compression point is the power at the A position, which is less than the power at the B position; when the power supply voltage is 4.6V, The output power at the 1dB compression point is the power at the C position, which is greater than the power at the B position.
  • the bias circuit 1 includes:
  • the first end of the mirror current source 11 is connected to the power supply voltage end;
  • the second end of the mirror current source 11 is connected to the reference voltage end
  • the third end of the mirror current source 11 is connected to the current-voltage converter 12;
  • the mirror current source 11 is configured to obtain the supply voltage transmitted by the supply voltage terminal through the first terminal, obtain the reference voltage transmitted by the reference voltage terminal through the second terminal, and use the reference voltage and
  • the power supply voltage is adjusted by a preset parameter to obtain a mirror current corresponding to the power supply voltage; the preset parameter is parameter information of the mirror current source;
  • the current-to-voltage converter 12 is configured to convert the mirror current into a voltage to provide a bias voltage based on the voltage.
  • the bias circuit provided in the embodiment of the present application is suitable for a scenario where a bias voltage is generated.
  • the power supply voltage terminal is configured to provide a power supply voltage for the bias circuit.
  • the power supply voltage may be 3.5V, 3V, or 4.6V. The specific value can be determined according to the actual situation. The embodiment does not limit this.
  • the reference voltage terminal is configured to provide a reference voltage for the bias circuit, and the reference voltage may be 3.5V or other values, and the specific value can be determined according to the actual situation, which is not made in the embodiment of the present application. limited.
  • the current-to-voltage converter may specifically be a digital to analog converter (Digital to analog converter, DAC), or may be other converters that convert current into voltage, and the specific one can be determined according to the actual situation, This embodiment of the present application does not limit this.
  • Digital to analog converter Digital to analog converter, DAC
  • DAC Digital to analog converter
  • the preset parameter is parameter information of the mirror current source.
  • the mirror current source may be a current source constructed by transistors, a current source constructed by triodes, or a current source constructed by other devices, and the details can be determined according to the actual situation. The embodiment does not limit this.
  • the transistor is a metal-oxide semiconductor field effect transistor (MOSFET), and the specific transistor may be a C-MOS transistor or a P-MOS transistor, which can be determined according to the actual situation. This is not limited.
  • MOSFET metal-oxide semiconductor field effect transistor
  • the power supply voltage terminal in the bias circuit and the power supply voltage terminal in the amplifier are the same power supply voltage terminal.
  • the mirror current source 11 includes a first mirror current source 111 and a second mirror current source 112;
  • the first input terminal of the first mirror current source 111 is connected to the power supply voltage terminal;
  • the second input terminal of the first mirror current source 111 is connected to the reference voltage terminal;
  • the output end of the first mirror current source 111 is connected to the input end of the second mirror current source 112;
  • the output end of the second mirror current source 112 is connected to the current-voltage converter 12;
  • the first mirror current source 111 is configured to use the reference voltage and a first parameter to adjust the supply voltage to generate a first mirror current;
  • the first parameter is parameter information of the first mirror current source , which are some parameters in the preset parameters;
  • the second mirror current source 112 is configured to obtain a second mirror current positively correlated with the first mirror current according to the first mirror current and the positive correlation coefficient; the positive correlation coefficient is based on the second mirror current The coefficient obtained from the parameter of the current source; the parameter of the second mirror current source is the parameter other than the first parameter in the preset parameters.
  • the current i1 in FIG. 4 is the first mirror current.
  • the positive correlation current (the current i2 in FIG. 4 ) can be obtained first according to the first mirror current (i1) and the positive correlation coefficient, and then according to the positive correlation current and the current in the third fixed current source 133,
  • the second mirror current (current I output in Figure 4) can be obtained.
  • the first mirror current source 111 includes a first transistor 1111
  • the second mirror current source 112 includes a second transistor 1121 ;
  • the first drain of the first transistor 1111 is connected to the second drain of the second transistor 1121;
  • the second transistor 1121 is configured to obtain the first mirror current from the first drain.
  • the first mirror current source 111 of the bias circuit 1 further includes a third transistor 1112;
  • the gate of the first transistor 1111 is connected to the gate of the third transistor 1112;
  • the source of the first transistor 1111 is connected to the reference voltage terminal through a first pull-up resistor 1113;
  • the source stage of the third transistor 1112 is connected to the power supply voltage terminal through a second pull-up resistor 1114;
  • the drain of the third transistor 1112 is connected to the gate of the third transistor 1112;
  • the source of the first transistor 1111 is configured to obtain the supply voltage from the supply voltage terminal through the first pull-up resistor 1113;
  • the source stage of the third transistor 1112 is configured to obtain a reference voltage from the reference voltage terminal through the second pull-up resistor 1114;
  • the first mirror current source 111 is configured to use the reference voltage, the first parameter, the first pull-up resistor 1113 and the second pull-up resistor 1114 to adjust the supply voltage to obtain the the first mirror current.
  • the second mirror current source 112 further includes a fourth transistor 1122;
  • the gate of the second transistor 1121 is connected to the gate of the fourth transistor 1122;
  • the gate of the second transistor 1121 is connected to the second drain of the second transistor 1121;
  • the source of the second transistor 1121 is connected to the source of the fourth transistor 1122;
  • the second mirror current source 112 is configured to use the positive correlation coefficient to adjust the first mirror current to obtain the second mirror current.
  • the positive correlation current (i2) can be obtained according to the product between the first mirror current and the positive correlation coefficient, and then the difference between the positive correlation current and the current in the third fixed current source 133 can be obtained. value, the second mirror current (I output ) can be obtained.
  • the bias circuit 1 further includes a fixed current source 13 ;
  • the fixed current source 13 includes a first fixed current source 131 , a second fixed current source 132 and a third fixed current source 133 ;
  • the drain of the third transistor 1112 is connected to the source of the second transistor 1121 through the first fixed current source 131;
  • the source of the fourth transistor 1122 is connected to the second terminal of the current-voltage converter 12 through the second fixed current source 132;
  • the supply voltage terminal is connected to the first terminal of the current-to-voltage converter 12 and the drain of the fourth transistor 1122 through the third fixed current source 133 , respectively.
  • the first transistor 1111 is the same transistor as the third transistor 1112 ; the second transistor 1121 is the same transistor as the fourth transistor 1122 .
  • the first transistor and the third transistor may both be C-MOS transistors, or both may be P-MOS transistors, which may be determined according to actual conditions, which are not limited in the embodiments of the present application.
  • both the second transistor and the fourth transistor may be C-MOS transistors, or both may be P-MOS transistors, which may be determined according to actual conditions, which are not limited in the embodiments of the present application.
  • the current-to-voltage converter 12 includes a digital-to-analog converter.
  • digital-to-analog converter is specifically a DAC converter.
  • FIG. 4 is a simplified diagram of the bias circuit.
  • the reference voltage in FIG. 4 is 3.5V.
  • the voltage output terminal can output an accurate bias voltage.
  • the supply voltage increases, the current i1 increases, and the current flowing through the transistor 1121 increases, so the gate-source voltage VGS of the transistor 1121 increases, and because the gate-source voltages of the transistors 1121 and 1122 are the same, the voltage flowing through the transistor 1122 increases.
  • the current i2 increases.
  • the current i2 is formed by the addition of the I output and the fixed current 133, the I output will increase, and the increased I output will be converted from the current (I) to the voltage (V) through the current-voltage converter, so the voltage output terminal voltage increases.
  • i1 will decrease, so i2 flowing through transistor 1122 will also decrease, and since the fixed current 133 will remain unchanged, the I output will decrease, converted by a current-to-voltage converter and output through the output voltage decreases.
  • FIG. 5 the changing trend of the second mirror current (I output ) and the voltage output by the voltage output terminal (VG2) with the change of the power supply voltage (VDD) is shown in FIG. 5 : in FIG. 5(a) , there is a linear relationship between VDD and I output , when VDD decreases, I output also decreases, and when VDD increases, I output also increases, and when VDD is the same as the reference voltage (Vref) I output is 0. In Fig. 5(b), there is also a linear relationship between VDD and VG2, and VG2 also decreases when VDD decreases, and VG2 also increases when VDD increases.
  • the positive correlation current (i2) is equal to the sum of the current in the third fixed current source 133 and the second mirror current (I output ). Since the current in the third fixed current source 133 is a constant value, this If the current remains unchanged, the variation of the positive correlation current (i2) is equal to the variation of the second mirror current (I output ).
  • the first mirror current (i1) is the same as the positive correlation current (i2), then the change amount of the first mirror current (i1) is the same as the change amount of the positive correlation current (i2), and the first mirror current (i2) is the same.
  • the variation of (i1) is about the difference between the supply voltage and the reference voltage divided by the resistance of the resistor at 1113, then the variation of the second mirror current (I output ) and the variation of the positive correlation current (i2) are also It is the difference between the supply voltage and the reference voltage divided by the resistance value of the resistor at 1113, that is, there is a linear relationship between the I output and VDD.
  • the current-to-voltage converter can convert the second mirror current into a voltage according to the conversion coefficient, and the conversion coefficient is constant, so there is also a linear relationship between VDD and VG2.
  • the mirror current source is used to connect the power supply voltage terminal, the reference voltage terminal and the current-voltage converter respectively, so as to adjust the power supply voltage according to the reference voltage and preset parameters, and obtain the mirror current corresponding to the power supply voltage, and
  • the mirror current is converted into a voltage by a current-to-voltage converter, so that the bias circuit can provide a bias voltage based on the voltage. Since the reference voltage and the preset parameters are both fixed values, the provided bias voltage can increase with the increase of the supply voltage. High and rise, can be reduced as the supply voltage is reduced, improving the accuracy of the supplied bias voltage.
  • the amplifier 2 includes:
  • the bias current fixer 21 the first amplifying transistor 22, the second amplifying transistor 23, and the bias circuit 1 described in the first embodiment of the present application;
  • the output end and the signal input end of the bias current fixer 21 are respectively connected to the first end of the first amplifying transistor 22;
  • the output end of the bias circuit 1 is connected to the first end of the second amplifying transistor 23;
  • the second end of the first amplifying transistor 22 is connected to the second end of the second amplifying transistor 23;
  • the third end of the second amplifying transistor 23 is respectively connected to the power supply voltage end and the signal output end;
  • the bias current fixer 21 is configured to fix the current in the first amplifier transistor 22;
  • the bias circuit 1 is configured to provide a bias voltage to the second amplifying transistor 23;
  • the first amplifying transistor 22 is configured to amplify the input signal obtained from the signal input terminal to obtain an amplified signal, and transmit the amplified signal to the second end of the second amplifying transistor 23;
  • the second amplifying transistor 23 is configured to amplify the amplified signal to obtain the output signal, and output the output signal through the signal output terminal.
  • the amplifier provided by the embodiment of the present application is suitable for a scenario where a bias circuit is used to provide a bias voltage.
  • the amplifier further includes a low-pass filter, an inductor, a capacitor, and the like, which may be determined according to the actual situation, which is not limited in the embodiment of the present application.
  • the number of the first amplifying transistor and the second amplifying transistor in the amplifier may be determined according to the actual situation, which is not limited in the embodiment of the present application.
  • the number of low-pass filters in the amplifier is the same as the total number of first amplifying transistors and second amplifying transistors.
  • VDD provides the power supply voltage for the amplifier through the inductor L2
  • M1 and M2 are transistors
  • the RF_input is the input terminal of the amplifier. After the amplifier amplifies the input signal, it is transmitted to the RF through the capacitor C.
  • the output terminal is output, the bias voltage output by the bias current fixer (VG1 bias circuit) is filtered by the low-pass filter and then transmitted to the M1 transistor (the first amplifier transistor) to provide the bias voltage for the M1 transistor;
  • the bias voltage output by the bias circuit (VG2 bias circuit) is filtered by the low-pass filter and transmitted to the M2 transistor (the second amplifier transistor) after being filtered by the low-pass filter and capacitor C1 to provide the bias voltage for the M2 transistor;
  • the bias voltage can be varied with VDD to provide an appropriate bias voltage for the cascaded transistors when VDD is varied.
  • the amplifier 2 includes a cascode amplifier and/or an amplifier with a cascade structure of multi-stage transistors.
  • the amplifier may be a cascode amplifier, the amplifier may also be an amplifier with a cascade structure of multi-stage transistors, and the amplifier may also be an amplifier circuit built with triodes, which can be determined according to the actual situation.
  • the linearity of the amplifier is obviously improved, and the 1dB compression point of the output power is improved.
  • the output power of the amplifier including the bias circuit is 1dB compression point compared to the prior art.
  • the power increases; when the power supply voltage VDD of the amplifier is 4.6V, the output power of the amplifier including the bias circuit is also increased compared with the prior art, and the power at the 1dB compression point is also increased, and when the VDD is 4.6V
  • the increase range is greater than the increase range when VDD is 3V, so the output power of the amplifier is improved compared to the prior art, and the power at the 1dB compression point of the amplifier in the present application is improved.
  • the circuit structure diagram of the amplifier is shown in FIG. 9 , VDD provides the power supply voltage for the amplifier through the inductor L2, and M1, M2, . . . Mn is the stage
  • the RF_ input is the input terminal of the amplifier. After the amplifier amplifies the input signal, it is transmitted to the RF_ output terminal through the capacitor C for output.
  • the bias voltage output by the bias current fixer passes through After filtering by the low-pass filter, it is transmitted to the M1 transistor to provide the bias voltage for the M1 transistor; the bias voltage output by the VG2 bias circuit is filtered by the low-pass filter and transmitted to the M2 transistor after the capacitor C1, which is the M2 transistor.
  • the bias circuit is the bias circuit provided in Embodiment 1 of the application, and the bias voltage provided by the bias circuit can be changed with the change of VDD, so as to provide appropriate bias for the cascaded transistors when the VDD changes Voltage.
  • the amplifier in the present application compared with the circuit structure of the fixed VG2 bias in the prior art, the amplifier in the present application not only ensures the linearity of the output power under the normal supply voltage (3.5V), but also effectively improves the The output power linearity of a power amplifier as the supply voltage increases or decreases.
  • the bias circuit can be used not only in the cascode structure power amplifier, but also in the power amplifier of the multi-stage transistor Stack structure (the amplifier shown in Figure 9). The bias circuit can effectively improve the output of the power amplifier. Linearity.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.
  • An embodiment of the present application provides a bias circuit and an amplifier
  • the bias circuit includes: a mirror current source and a current-voltage converter; a first end of the mirror current source is connected to a power supply voltage end; a second end of the mirror current source is connected to the reference voltage terminal is connected; the third terminal of the mirror current source is connected to the current-voltage converter;
  • the mirror current source is configured to obtain the power supply voltage transmitted by the power supply voltage terminal through the first terminal, and obtain the reference voltage transmitted by the reference voltage terminal through the second terminal , and use the reference voltage and preset parameters to adjust the power supply voltage to obtain the mirror current corresponding to the power supply voltage;
  • the preset parameter is the parameter information of the mirror current source;
  • the current-to-voltage converter is configured to convert the mirror current into a voltage, so as to The bias voltage is provided based on the voltage.
  • the mirror current source is used to connect the power supply voltage terminal, the reference voltage terminal and the current-voltage converter respectively, so as to adjust the power supply voltage according to the reference voltage and preset parameters, and obtain the corresponding power supply voltage.
  • the mirror current is converted into a voltage by a current-to-voltage converter, so that the bias circuit can provide a bias voltage based on the voltage. Since the reference voltage and the preset parameters are both fixed values, the provided bias voltage can vary with the voltage. The increase of the power supply voltage can be decreased with the decrease of the power supply voltage, which improves the accuracy of the provided bias voltage.

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Abstract

本申请实施例公开了一种偏置电路及放大器，该偏置电路包括：镜像电流源和电流电压转换器；镜像电流源的第一端与供电电压端连接；镜像电流源的第二端与参考电压端连接；镜像电流源的第三端与电流电压转换器连接；镜像电流源，配置于通过第一端获取供电电压端传输的供电电压，通过第二端获取参考电压端传输的参考电压，并利用参考电压和预设参数对供电电压进行调整，得到与供电电压对应的镜像电流；预设参数为镜像电流源的参数信息；电流电压转化器，配置于将镜像电流转化为电压，以基于电压提供偏置电压。

Description

一种偏置电路及放大器
相关申请的交叉引用
本申请要求在2021年02月26日提交中国专利局、申请号为202110219250.4、申请名称为“一种偏置电路及放大器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，尤其涉及一种偏置电路及放大器。
背景技术
在放大器工作在高线性模式(4G长期演进(Long Term Evolution，LTE)/5G新空口(New Radio，NR))的情况下，放大器的增益需要随着输入功率不断增大尽量保持不变。在放大器增益变化较小的情况下，输出功率会随着输入功率的增加或者减少呈线性变化，因此放大器有着较高的线性度。
相关技术中，在放大器的供电电压给定的情况下，可以利用偏置电路向放大器中的晶体管提供一个偏置电压，使得在该供电电压下，该放大器的输出功率线性度有着比较好的性能。但根据第三代合作伙伴计划(Third Generation Partnership Project，3GPP)协议，除了常规供电电压为3.5V，该放大器还需要工作在供电电压为低压3V，高压4.6V的情况下，如此偏置电路提供的偏置电压无法满足放大器中的晶体管偏置性能的需求，使得提供的偏置电压的准确性降低。
发明内容
为解决上述技术问题，本申请实施例期望提供一种偏置电路及放大器，提高了提供的偏置电压的准确性。
本申请的技术方案是这样实现的：
本申请实施例提供一种偏置电路，所述偏置电路包括：
镜像电流源和电流电压转换器；
所述镜像电流源的第一端与供电电压端连接；
所述镜像电流源的第二端与参考电压端连接；
所述镜像电流源的第三端与所述电流电压转换器连接；
所述镜像电流源，配置于通过所述第一端获取所述供电电压端传输的供电电压，通过所述第二端获取所述参考电压端传输的参考电压，并利用所述参考电压和预设参数对所述供电电压进行调整，得到与所述供电电压对应的镜像电流；所述预设参数为所述镜像电流源的参数信息；
所述电流电压转化器，配置于将所述镜像电流转化为电压，以基于所述电压提供偏置电压。
本申请实施例提供一种放大器，所述放大器包括：
偏置电流固定器、第一放大晶体管、第二放大晶体管和如上述所述的偏置电路；
所述偏置电流固定器的输出端和信号输入端分别与所述第一放大晶体管的第一端连接；
所述偏置电路的输出端与所述第二放大晶体管的第一端连接；
所述第一放大晶体管的第二端与所述第二放大晶体管的第二端连接；
所述第二放大晶体管的第三端分别与供电电压端和信号输出端连接；
所述偏置电流固定器，配置于固定所述第一放大晶体管中的电流；
所述偏置电路，配置于向所述第二放大晶体管提供偏置电压；
所述第一放大晶体管，配置于对从信号输入端获取到的输入信号进行放大处理，得到放大信号，并将所述放大信号传输至所述第二放大晶体管的第二端；
所述第二放大晶体管，配置于对所述放大信号进行放大处理，得到所 述输出信号，并通过所述信号输出端输出所述输出信号。
本申请实施例提供了一种偏置电路及放大器，该偏置电路包括：镜像电流源和电流电压转换器；镜像电流源的第一端与供电电压端连接；镜像电流源的第二端与参考电压端连接；镜像电流源的第三端与电流电压转换器连接；镜像电流源，配置于通过第一端获取供电电压端传输的供电电压，通过第二端获取参考电压端传输的参考电压，并利用参考电压和预设参数对供电电压进行调整，得到与供电电压对应的镜像电流；预设参数为镜像电流源的参数信息；电流电压转化器，配置于将镜像电流转化为电压，以基于电压提供偏置电压。采用上述偏置电路的实现方案，利用镜像电流源分别与供电电压端、参考电压端和电流电压转化器连接，以根据利用参考电压和预设参数对供电电压进行调整，得到与供电电压对应的镜像电流，并利用电流电压转化器将该镜像电流转化为电压，使得偏置电路可以基于该电压来提供偏置电压，由于参考电压和预设参数均为定值，提供的偏置电压可随供电电压的升高而升高，可随供电电压的降低而降低，提高了提供的偏置电压的准确性。
附图说明
图1为本申请实施例提供的一种现有技术中的放大器的示意图；
图2为本申请实施例提供的一种示例性的不同供电电压下一般功率放大器对应的输出1dB压缩点示意图；
图3为本申请实施例提供的一种偏置电路组成结构示意图；
图4为本申请实施例提供的一种示例性的偏置电路组成结构示意图；
图5(a)为本申请实施例提供的一种示例性的第二镜像电流与供电电压之间的关系示意图；
图5(b)为本申请实施例提供的一种示例性的电压输出端输出的电压与供电电压之间的关系示意图；
图6为本申请实施例提供的一种示例性的放大器的组成结构示意图；
图7为本申请实施例提供的一种放大器的组成结构示意图；
图8为本申请实施例提供的一种示例性的供电电压、参考电压和电压之间的关系示意图；
图9为本申请实施例提供的一种示例性的放大器结构示意图。
具体实施方式
为了能够更加详尽地了解本申请实施例的特点与技术内容，下面结合附图对本申请实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本申请实施例。
在功率放大器工作在高线性模式(4G LTE/5G NR)的情况下，放大器的功率增益需要在输入功率逐渐增大的情况下尽量保持不变，使得该增益为一个定值。但在实际操作中，放大器的增益不可能一直为一个定值，在放大器的输入功率不断增大的情况下，放大器的增益将逐渐减小，在放大器增益变化较小的情况下，输出功率会随着输入功率的增减线性变化，因此放大器有着较高的线性度。在金属-氧化物半导体场效应晶体管(MOSFET)制作的功率放大器电路中，由于耐压的需求，一般都会使用共源共栅(Cascode)结构。该结构如图1所示，一般由晶体管M1和M2、反馈电容C1、射频电感L2、偏置电路(VG1)、偏置电路(VG2)、低通滤波器、输入端RF_输入和输出端RF_输出组成。
需要说明的是，放大器有一个线性动态范围，在这个范围内，放大器的输出功率随输入功率进行线性增加。随着输入功率的继续增加，放大器进入非线性区，其输出功率不再随输入功率的增加而线性增加，也就是说，其输出功率低于小信号增益所预计的值。通常把增益下降到比线性增益低1dB时的输出功率值定义为输出功率的1dB压缩点，用P1dB表示，即1分贝压缩输出功率(P1dB)。
需要说明的是，功率放大器的线性度主要是指增益线性度，即在功率放大器输出功率达到1dB压缩点的情况下，所对应的功率放大器的输出功率(P1dB)。
还需要说明的是，其他指标不变的情况下，P1dB越高越好。
目前，在现有的Cascode结构功率放大器中，在供电电压VDD给定的情况下，偏置电路VG1可以向晶体管M1的栅极一个固定偏置电压，偏置电路VG2可以向晶体管M2的栅极一个固定偏置电压。使得在该VDD电压下，该功率放大器的输出功率线性度有着比较好的性能。但根据3GPP协议，除了常规电压供电电压VDD为3.5V，该功率放大器还需要工作在供电电压VDD为低压3V，高压4.6V的情况下。
在供电电压VDD为低压的情况下，由于VG1和VG2不变，因此放大器的偏置电流几乎不变，使得晶体管M2的栅源电压VGS变化很小，因此M2的源漏电压VDS降低的电压约等于VDD减小的电压，因此在输入信号变大的情况下晶体管M2会提前进入三极管区，导致输出功率提前进入1dB压缩点，使得增益线性度下降。
在供电电压VDD为高压的情况下，由于VG1和VG2不变，因此放大器的偏置电流几乎不变，使得晶体管M1的源漏电压VDS几乎不变，因此晶体管M1的交流摆幅不变，由于VDD较高，放大器的输入信号RF_输入也会变大，因此，晶体管M1会较早饱和，导致输出功率的1dB压缩点提升有限。
对于固定VG1和VG2的一般功率放大器来说，常压3.5V，高压4.6V，低压3V，对应的1dB压缩点的输出功率如图2所示，在供电电压为3.5V的情况下，1dB压缩点的输出功率为B位置处的功率；在供电电压为3V的情况下，1dB压缩点的输出功率为A位置处的功率，小于B位置处的功率；在供电电压为4.6V的情况下，1dB压缩点的输出功率为C位置处的功率，大于B位置处的功率。
对于现有技术中存在的问题，具体可通过以下实施例进行解决。
实施例一
本申请的一种实施例提供一种偏置电路1，如图3所示，该偏置电路1包括：
镜像电流源11和电流电压转换器12；
所述镜像电流源11的第一端与供电电压端连接；
所述镜像电流源11的第二端与参考电压端连接；
所述镜像电流源11的第三端与所述电流电压转换器12连接；
所述镜像电流源11，配置于通过所述第一端获取所述供电电压端传输的供电电压，通过所述第二端获取所述参考电压端传输的参考电压，并利用所述参考电压和预设参数对所述供电电压进行调整，得到与所述供电电压对应的镜像电流；所述预设参数为所述镜像电流源的参数信息；
所述电流电压转化器12，配置于将所述镜像电流转化为电压，以基于所述电压提供偏置电压。
本申请实施例提供的一种偏置电路适用于产生偏置电压的场景下。
在本申请实施例中，供电电压端，配置于为偏置电路提供供电电压，该供电电压可以为3.5V，也可以为3V，还可以4.6V，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
在本申请实施例中，参考电压端配置于给偏置电路提供参考电压，该参考电压可以为3.5V，还可以为其他数值，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
在本申请实施例中，电流电压转化器具体可以为数字模拟转换器(Digital to analog converter，DAC)，也可以为其他的将电流转换为电压的转换器，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
需要说明的是，预设参数为所述镜像电流源的参数信息。
在本申请实施例中，镜像电流源可以为利用晶体管搭建的电流源，也 可以为利用三极管搭建的电流源，还可以为其他器件搭建的电流源，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
需要说明的是，晶体管为金属-氧化物半导体场效应晶体管(MOSFET)，具体的晶体管可以为C-MOS晶体管，也可以为P-MOS晶体管，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
在本申请实施例中，在偏置电路应用于放大器中，为放大器中的晶体管提供偏置电压的情况下，偏置电路中的供电电压端与放大器中的供电电压端为同一供电电压端。
可选的，如图4所示，镜像电流源11包括第一镜像电流源111和第二镜像电流源112；
所述第一镜像电流源111的第一输入端与所述供电电压端连接；
所述第一镜像电流源111的第二输入端与所述参考电压端连接；
所述第一镜像电流源111的输出端与所述第二镜像电流源112的输入端连接；
所述第二镜像电流源112的输出端与所述电流电压转换器12连接；
所述第一镜像电流源111，配置于利用所述参考电压和第一参数对所述供电电压进行调整，产生第一镜像电流；所述第一参数为所述第一镜像电流源的参数信息，为所述预设参数中的部分参数；
所述第二镜像电流源112，配置于根据所述第一镜像电流和正相关系数，得到与所述第一镜像电流正相关的第二镜像电流；所述正相关系数为根据所述第二镜像电流源的参数得到的系数；所述第二镜像电流源的参数为所述预设参数中除所述第一参数外的参数。
需要说明的是，图4中的电流i1即为第一镜像电流。
在本申请实施例中，根据第一镜像电流(i1)和正相关系数可以先得到正相关电流(图4中的电流i2)，之后再根据正相关电流和第三固定电流 源133中的电流，就可以得到第二镜像电流(图4中的电流I 输出)。
可选的，如图4所示，所述第一镜像电流源111包括第一晶体管1111，所述第二镜像电流源112包括第二晶体管1121；
所述第一晶体管1111的第一漏极与所述第二晶体管1121的第二漏极连接；
所述第二晶体管1121，配置于从所述第一漏极处获取所述第一镜像电流。
可选的，如图4所示，所述偏置电路1的第一镜像电流源111还包括第三晶体管1112；
所述第一晶体管1111的栅极与所述第三晶体管1112的栅极连接；
所述第一晶体管1111的源极通过第一上拉电阻1113与所述参考电压端连接；
所述第三晶体管1112的源级通过第二上拉电阻1114与所述供电电压端连接；
所述第三晶体管1112的漏极与所述第三晶体管1112的栅极连接；
所述第一晶体管1111的源极，配置于通过所述第一上拉电阻1113从所述供电电压端获取供电电压；
所述第三晶体管1112的源级，配置于通过所述第二上拉电阻1114从所述参考电压端获取参考电压；
所述第一镜像电流源111，配置于利用所述参考电压、所述第一参数、所述第一上拉电阻1113和所述第二上拉电阻1114对所述供电电压进行调整，得到所述第一镜像电流。
可选的，如图4所示，所述第二镜像电流源112还包括第四晶体管1122；
所述第二晶体管1121的栅极与所述第四晶体管1122的栅极连接；
所述第二晶体管1121的栅极与所述第二晶体管1121的第二漏极连接；
所述第二晶体管1121的源极与所述第四晶体管1122的源极连接；
所述第二镜像电流源112，配置于利用所述正相关系数对所述第一镜像电流进行调整，得到所述第二镜像电流。
在本申请实施例中，可以根据第一镜像电流与正相关系数之间的乘积，得到正相关电流(i2)，之后再根据正相关电流和第三固定电流源133中的电流之间的差值，就可以得到第二镜像电流(I 输出)。
可选的，如图4所示，所述偏置电路1还包括固定电流源13；所述固定电流源13包括第一固定电流源131、第二固定电流源132和第三固定电流源133；
所述第三晶体管1112的漏极通过所述第一固定电流源131与所述第二晶体管1121的源极连接；
第四晶体管1122的源极通过所述第二固定电流源132与所述电流电压转换器12的第二端连接；
所述供电电压端通过所述第三固定电流源133分别与所述电流电压转化器12的第一端和所述第四晶体管1122的漏极连接。
可选的，如图4所示，所述第一晶体管1111为与第三晶体管1112相同的晶体管；所述第二晶体管1121为与第四晶体管1122相同的晶体管。
在本申请实施例中，第一晶体管和第三晶体管可以都为C-MOS晶体管，也可以都为P-MOS晶体管，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
在本申请实施例中，第二晶体管和第四晶体管可以都为C-MOS晶体管，也可以都为P-MOS晶体管，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
可选的，所述电流电压转换器12包括数模转换器。
需要说明的是，数模转换器具体为DAC转换器。
在本申请实施例中，图4为偏置电路的简化图，在图4中的参考电压为3.5V，在供电电压为3.5V的情况下，电压输出端可以输出准确的偏置电压，在供电电压升高的情况下，电流i1升高，流经晶体管1121的电流增加，因此晶体管1121的栅源电压VGS升高，又因为晶体管1121和1122的栅源电压相同，因此流经晶体管1122的电流i2增大。因为电流i2是由I 输出和固定电流133相加而成，因此I 输出会增大，增大的I 输出会经过电流电压转换器进行电流(I)到电压(V)的转换，因此电压输出端的电压增大。在供电电压降低的情况下，i1会减小，因此流过晶体管1122的i2也会减小，由于固定电流133不变，因此I 输出会减小，通过电流电压转换器转换并通过输出端输出的电压就减小。
在本申请实施例中，第二镜像电流(I 输出)和电压输出端输出的电压(VG2)随着供电电压(VDD)的变化而变化的趋势如图5所示：在图5(a)中，VDD与I 输出之间呈线性关系，在VDD减小的情况下I 输出也减小，在VDD增大的情况下I 输出也增大，在VDD与参考电压(Vref)相同的情况下I 输出为0。在图5(b)中，VDD与VG2之间也呈线性关系，在VDD减小的情况下VG2也减小，在VDD增加的情况下VG2也增加。
在本申请实施例中，正相关电流(i2)等于第三固定电流源133中的电流与第二镜像电流(I 输出)的和，由于第三固定电流源133中的电流为定值，该电流不变，则正相关电流(i2)的变化量就等于第二镜像电流(I 输出)的变化量。
在本申请实施例中，第一镜像电流(i1)与正相关电流(i2)相同，则第一镜像电流(i1)的变化量与正相关电流(i2)的变化量相同，第一镜像电流(i1)的变化量约为供电电压与参考电压之间的差值除以1113处的电阻的阻值，则第二镜像电流(I 输出)的变化量和正相关电流(i2)的变化量 也为供电电压与参考电压之间的差值除以1113处的电阻的阻值，即I 输出与VDD之间呈线性关系。
在本申请实施例中，电流电压转换器可以根据转换系数将第二镜像电流转化为电压，而转换系数为常数，故VDD与VG2之间也呈线性关系。
可以理解的是，利用镜像电流源分别与供电电压端、参考电压端和电流电压转化器连接，以根据利用参考电压和预设参数对供电电压进行调整，得到与供电电压对应的镜像电流，并利用电流电压转化器将该镜像电流转化为电压，使得偏置电路可以基于该电压来提供偏置电压，由于参考电压和预设参数均为定值，提供的偏置电压可随供电电压的升高而升高，可随供电电压的降低而降低，提高了提供的偏置电压的准确性。
实施例二
本申请的另一种实施例提供一种放大器，如图6所示，该放大器2包括：
偏置电流固定器21、第一放大晶体管22、第二放大晶体管23和本申请实施例一所述的偏置电路1；
所述偏置电流固定器21的输出端和信号输入端分别与所述第一放大晶体管22的第一端连接；
所述偏置电路1的输出端与所述第二放大晶体管23的第一端连接；
所述第一放大晶体管22的第二端与所述第二放大晶体管23的第二端连接；
所述第二放大晶体管23的第三端分别与供电电压端和信号输出端连接；
所述偏置电流固定器21，配置于固定所述第一放大晶体管22中的电流；
所述偏置电路1，配置于向所述第二放大晶体管23提供偏置电压；
所述第一放大晶体管22，配置于对从信号输入端获取到的输入信号进行放大处理，得到放大信号，并将所述放大信号传输至所述第二放大晶体 管23的第二端；
所述第二放大晶体管23，配置于对所述放大信号进行放大处理，得到所述输出信号，并通过所述信号输出端输出所述输出信号。
本申请实施例提供的一种放大器适用于利用偏置电路提供偏置电压的场景下。
在本申请实施例中，放大器还包括低通滤波器、电感和电容等，具体的可根据实际情况进行确定，本申请实施例对此不作限定。
在本申请实施例中，放大器中的第一放大晶体管和第二放大晶体管的数量可根据实际情况进行确定，本申请实施例对此不作限定。
在本申请实施例中，放大器中的低通滤波器的数量与第一放大晶体管和第二放大晶体管的总数量相同。
示例性的，放大器如图7所示，VDD通过电感L2为放大器提供供电电压，M1和M2为晶体管，RF_输入为放大器的输入端，放大器对输入的信号放大后，通过电容C传输至RF_输出端进行输出，偏置电流固定器(VG1偏置电路)输出的偏置电压通过低通滤波器进行滤波后传输至M1晶体管(第一放大晶体管)中，为M1晶体管提供偏置电压；偏置电路(VG2偏置电路)输出的偏置电压通过低通滤波器进行滤波及电容C1后传输至M2晶体管(第二放大晶体管)中，为M2晶体管提供偏置电压；偏置电路提供的偏置电压可随VDD的改变而改变，以在VDD改变的情况下，为级联的晶体管提供合适的偏置电压。
可选的，所述放大器2包括共源共栅放大器和/或多级晶体管级联结构的放大器。
在本申请实施例中，放大器可以为共源共栅放大器，放大器也可以为多级晶体管级联结构的放大器，放大器还可以为利用三极管搭建的放大电路，具体的可根据实际情况进行确定。
示例性的，通过多次试验，放大器中使用了实施例一中的偏置电路之 后，放大器的线性度有了明显提升，输出功率的1dB压缩点有了提高。如图8中虚线所示，使用了上述偏置电路后，在放大器的供电电压VDD为3V的情况下，包含偏置电路的放大器的输出功率相较于现有的技术中，1dB压缩点的功率增加；在放大器的供电电压VDD为4.6V的情况下，包含偏置电路的放大器的输出功率相较于现有的技术中，1dB压缩点的功率也增加了，并且VDD为4.6V时的增加幅度大于VDD为3V时的增加幅度，故放大器的输出功率相比于现有技术，本申请中的放大器1dB压缩点的功率均有所提升。
在本申请实施例中，若放大器为多级晶体管级联结构的放大器，则放大器的电路结构图如图9所示，VDD通过电感L2为放大器提供供电电压，M1、M2、….Mn为级联的晶体管，RF_输入为放大器的输入端，放大器对输入的信号放大后，通过电容C传输至RF_输出端进行输出，偏置电流固定器(VG1偏置电路)输出的偏置电压通过低通滤波器进行滤波后传输至M1晶体管中，为M1晶体管提供偏置电压；VG2偏置电路输出的偏置电压通过低通滤波器进行滤波及电容C1后传输至M2晶体管中，为M2晶体管提供偏置电压；….；VGn偏置电路输出的偏置电压通过低通滤波器进行滤波及电容Cn后传输至Mn晶体管中，为Mn晶体管提供偏置电压，其中VG2偏置电路、…VGn偏置电路为本申请实施例1提供的偏置电路，该偏置电路提供的偏置电压可随VDD的改变而改变，以在VDD改变的情况下，为级联的晶体管提供合适的偏置电压。
在本申请实施例中，相对于现有技术中的固定VG2偏置的电路结构来说，本申请中的放大器不但保证了正常供电电压(3.5V)下的输出功率线性度，还能有效提高供电电压升高或者降低时的功率放大器的输出功率线性度。且该偏置电路不仅可以用在cascode结构功率放大器中，还可以用在多级晶体管Stack结构的功率放大器中(如图9所示的放大器中)，该偏置电路可以有效提高功率放大器的输出线性度。
可以理解的是，通过将偏置电路的输出端与第二放大晶体管的第一端连接，第二放大晶体管的第三端与供电电压端连接，使得在供电电压改变的情况下，偏置电路可以根据改变后的供电电压为第二放大晶体管提供准确的偏置电压，从而提高了放大器的线性度。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。
工业实用性
本申请实施例提供了一种偏置电路及放大器，该偏置电路包括：镜像电流源和电流电压转换器；镜像电流源的第一端与供电电压端连接；镜像电流源的第二端与参考电压端连接；镜像电流源的第三端与电流电压转换器连接；镜像电流源，配置于通过第一端获取供电电压端传输的供电电压，通过第二端获取参考电压端传输的参考电压，并利用参考电压和预设参数对供电电压进行调整，得到与供电电压对应的镜像电流；预设参数为镜像电流源的参数信息；电流电压转化器，配置于将镜像电流转化为电压，以基于电压提供偏置电压。采用上述偏置电路的实现方案，利用镜像电流源分别与供电电压端、参考电压端和电流电压转化器连接，以根据利用参考电压和预设参数对供电电压进行调整，得到与供电电压对应的镜像电流，并利用电流电压转化器将该镜像电流转化为电压，使得偏置电路可以基于该电压来提供偏置电压，由于参考电压和预设参数均为定值，提供的偏置电压可随供电电压的升高而升高，可随供电电压的降低而降低，提高了提供的偏置电压的准确性。

Claims (10)

  1. 一种偏置电路，所述偏置电路包括：
    镜像电流源和电流电压转换器；
    所述镜像电流源的第一端与供电电压端连接；
    所述镜像电流源的第二端与参考电压端连接；
    所述镜像电流源的第三端与所述电流电压转换器连接；
    所述镜像电流源，配置于通过所述第一端获取所述供电电压端传输的供电电压，通过所述第二端获取所述参考电压端传输的参考电压，并利用所述参考电压和预设参数对所述供电电压进行调整，得到与所述供电电压对应的镜像电流；所述预设参数为所述镜像电流源的参数信息；
    所述电流电压转化器，配置于将所述镜像电流转化为电压，以基于所述电压提供偏置电压。
  2. 根据权利要求1所述的偏置电路，其中，所述镜像电流源包括第一镜像电流源和第二镜像电流源；
    所述第一镜像电流源的第一输入端与所述供电电压端连接；
    所述第一镜像电流源的第二输入端与所述参考电压端连接；
    所述第一镜像电流源的输出端与所述第二镜像电流源的输入端连接；
    所述第二镜像电流源的输出端与所述电流电压转换器连接；
    所述第一镜像电流源，配置于利用所述参考电压和第一参数对所述供电电压进行调整，产生第一镜像电流；所述第一参数为所述第一镜像电流源的参数信息，为所述预设参数中的部分参数；
    所述第二镜像电流源，配置于根据所述第一镜像电流和正相关系数，得到与所述第一镜像电流正相关的第二镜像电流；所述正相关系数为根据所述第二镜像电流源的参数得到的系数；所述第二镜像电流源的参数为所述预设参数中除所述第一参数外的参数。
  3. 根据权利要求2所述的偏置电路，其中，所述第一镜像电流源包括第一晶体管，所述第二镜像电流源包括第二晶体管；
    所述第一晶体管的第一漏极与所述第二晶体管的第二漏极连接；
    所述第二晶体管，配置于从所述第一漏极处获取所述第一镜像电流。
  4. 根据权利要求3所述的偏置电路，其中，所述第一镜像电流源还包括第三晶体管；
    所述第一晶体管的栅极与所述第三晶体管的栅极连接；
    所述第一晶体管的源极通过第一上拉电阻与所述参考电压端连接；
    所述第三晶体管的源级通过第二上拉电阻与所述供电电压端连接；
    所述第三晶体管的漏极与所述第三晶体管的栅极连接；
    所述第一晶体管的源极，配置于通过所述第一上拉电阻从所述供电电压端获取供电电压；
    所述第三晶体管的源级，配置于通过所述第二上拉电阻从所述参考电压端获取参考电压；
    所述第一镜像电流源，配置于利用所述参考电压、所述第一参数、所述第一上拉电阻和所述第二上拉电阻对所述供电电压进行调整，得到所述第一镜像电流。
  5. 根据权利要求3所述的偏置电路，其中，所述第二镜像电流源还包括第四晶体管；
    所述第二晶体管的栅极与所述第四晶体管的栅极连接；
    所述第二晶体管的栅极与所述第二晶体管的第二漏极连接；
    所述第二晶体管的源极与所述第四晶体管的源极连接；
    所述第二镜像电流源，配置于利用所述正相关系数对所述第一镜像电流进行调整，得到所述第二镜像电流。
  6. 根据权利要求4所述的偏置电路，其中，所述偏置电路还包括固定电流源；所述固定电流源包括第一固定电流源、第二固定电流源和第三固 定电流源；
    所述第三晶体管的漏极通过所述第一固定电流源与所述第二晶体管的源极连接；
    第四晶体管的源极通过所述第二固定电流源与所述电流电压转换器的第二端连接；
    所述供电电压端通过所述第三固定电流源分别与所述电流电压转化器的第一端和所述第四晶体管的漏极连接。
  7. 根据权利要求3所述的偏置电路，其中，所述第一晶体管为与第三晶体管相同的晶体管；所述第二晶体管为与第四晶体管相同的晶体管。
  8. 根据权利要求1所述的偏置电路，其中，所述电流电压转换器包括数模转换器。
  9. 一种放大器，所述放大器包括：
    偏置电流固定器、第一放大晶体管、第二放大晶体管和如权利要求1至8任一项所述的偏置电路；
    所述偏置电流固定器的输出端和信号输入端分别与所述第一放大晶体管的第一端连接；
    所述偏置电路的输出端与所述第二放大晶体管的第一端连接；
    所述第一放大晶体管的第二端与所述第二放大晶体管的第二端连接；
    所述第二放大晶体管的第三端分别与供电电压端和信号输出端连接；
    所述偏置电流固定器，配置于固定所述第一放大晶体管中的电流；
    所述偏置电路，配置于向所述第二放大晶体管提供偏置电压；
    所述第一放大晶体管，配置于对从信号输入端获取到的输入信号进行放大处理，得到放大信号，并将所述放大信号传输至所述第二放大晶体管的第二端；
    所述第二放大晶体管，配置于对所述放大信号进行放大处理，得到所述输出信号，并通过所述信号输出端输出所述输出信号。
  10. 根据权利要求9所述的放大器，其中，所述放大器包括共源共栅放大器和/或多级晶体管级联结构的放大器。
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Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
CN113037222B (zh) * 2021-02-26 2023-09-15 广州慧智微电子股份有限公司 一种偏置电路及放大器
CN113411054B (zh) * 2021-08-19 2021-11-19 深圳飞骧科技股份有限公司 射频放大器及其输出1dB压缩点动态调整电路
CN113411055B (zh) * 2021-08-19 2021-12-28 深圳飞骧科技股份有限公司 偏置电流控制装置、射频放大器、电子设备及芯片
CN114020087B (zh) * 2021-09-17 2023-05-05 深圳市芯波微电子有限公司 抑制电源干扰的偏置电压产生电路
CN114094962B (zh) * 2021-11-23 2023-08-29 广州慧智微电子股份有限公司 一种电压电流转换电路、射频功率放大器和电子系统

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060006947A1 (en) * 2004-07-09 2006-01-12 Xindium Technologies, Inc. Current mirror biasing circuit with power control for HBT power amplifiers
CN106817093A (zh) * 2017-01-23 2017-06-09 宜确半导体（苏州）有限公司 射频功率放大器
CN109716648A (zh) * 2016-09-16 2019-05-03 派赛公司 共源共栅放大器偏置电路
CN110442180A (zh) * 2018-05-02 2019-11-12 亚德诺半导体无限责任公司 功率-循环电压参考
CN110719077A (zh) * 2019-10-23 2020-01-21 广州慧智微电子有限公司 一种功率放大器及电子设备
CN111614327A (zh) * 2019-02-22 2020-09-01 瑞昱半导体股份有限公司 具有适应性供电的射频放大器
CN113037222A (zh) * 2021-02-26 2021-06-25 广州慧智微电子有限公司 一种偏置电路及放大器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568093A (en) * 1995-05-18 1996-10-22 National Semiconductor Corporation Efficient, high frequency, class A-B amplifier for translating low voltage clock signal levels to CMOS logic levels
JP4322095B2 (ja) * 2003-11-12 2009-08-26 株式会社ルネサステクノロジ 高周波電力増幅器モジュール
CN202794314U (zh) * 2012-07-19 2013-03-13 快捷半导体(苏州)有限公司 一种功率开关管的过流检测电路
CN109150115B (zh) * 2018-08-01 2022-07-12 北京昂瑞微电子技术股份有限公司 一种射频功率放大器偏置电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060006947A1 (en) * 2004-07-09 2006-01-12 Xindium Technologies, Inc. Current mirror biasing circuit with power control for HBT power amplifiers
CN109716648A (zh) * 2016-09-16 2019-05-03 派赛公司 共源共栅放大器偏置电路
CN106817093A (zh) * 2017-01-23 2017-06-09 宜确半导体（苏州）有限公司 射频功率放大器
CN110442180A (zh) * 2018-05-02 2019-11-12 亚德诺半导体无限责任公司 功率-循环电压参考
CN111614327A (zh) * 2019-02-22 2020-09-01 瑞昱半导体股份有限公司 具有适应性供电的射频放大器
CN110719077A (zh) * 2019-10-23 2020-01-21 广州慧智微电子有限公司 一种功率放大器及电子设备
CN113037222A (zh) * 2021-02-26 2021-06-25 广州慧智微电子有限公司 一种偏置电路及放大器

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