WO2021164257A1 - 一种功率控制电路 - Google Patents

一种功率控制电路 Download PDF

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Publication number
WO2021164257A1
WO2021164257A1 PCT/CN2020/118564 CN2020118564W WO2021164257A1 WO 2021164257 A1 WO2021164257 A1 WO 2021164257A1 CN 2020118564 W CN2020118564 W CN 2020118564W WO 2021164257 A1 WO2021164257 A1 WO 2021164257A1
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Prior art keywords
tube
source
nmos tube
gate
drain
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PCT/CN2020/118564
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English (en)
French (fr)
Inventor
刘炽锋
苏强
王启明
奕江涛
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广州慧智微电子有限公司
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Priority to US17/139,928 priority Critical patent/US11881820B2/en
Publication of WO2021164257A1 publication Critical patent/WO2021164257A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • This application relates to the field of electronic technology, and in particular to a power control circuit.
  • Radio frequency power amplifier can also be abbreviated as power amplifier.
  • a power control circuit is needed to control the output power of the power amplifier.
  • the so-called power control generally has two methods, namely current control and voltage control. Among them, the current control method is to control the bias current of the power amplifier by controlling the gate bias voltage of the amplifier tube.
  • Fig. 1 is a schematic diagram of the first group structure of an existing power control circuit.
  • the drain of the MN3 tube is connected to the current source IB, and the drain of the MN3 tube is short-circuited with the gate;
  • the drain of the MN1 tube is connected to the source of the MN2 tube, and the gate of the MN1 tube serves as the radio frequency signal Input terminal;
  • the gate of the MN3 tube is connected to the gate of the MN1 tube, and a resistor R1 is connected in series, the source of the MN3 tube and the source of the MN1 tube are both connected to the ground terminal;
  • the gate of the MN2 tube is connected to the voltage source VG ,
  • a resistor R2 is connected in series in the middle, the drain of the MN2 tube is connected to the voltage source VCC, and an inductor L is connected in series in the middle, which also serves as the output end of the radio frequency signal.
  • Fig. 2 is a schematic diagram of the second composition structure of the existing power control circuit.
  • a differential amplifier is added on the basis of Figure 1. Specifically, the forward input end of the differential amplifier is connected to the drain of the MN3 tube, and the reverse input end of the differential amplifier is connected to the drain of the MN1 tube. Connected, the output end of the differential amplifier is connected to the gate of the MN3 tube, and is connected to one end of the resistor R1.
  • the connection method of other parts is the same as that described in Figure 1. Among them, MN1 tube, MN3 tube and differential amplifier form a feedback loop.
  • the drain voltages of the MN1 and MN3 tubes are equalized, thereby eliminating the influence of the channel length modulation effect and improving the current control accuracy.
  • the radio frequency power amplifier tube MN1 is in the feedback loop, a part of the radio frequency signal path will pass through the analog signal, and the analog signal will interfere with the radio frequency signal, which reduces the performance of the radio frequency power amplifier.
  • an embodiment of the present application provides a power control circuit.
  • An embodiment of the application provides a power control circuit, the circuit includes: a radio frequency signal path and a negative feedback loop;
  • the radio frequency signal path includes: a first NMOS tube and a second NMOS tube;
  • the gate of the first NMOS tube is used as the input terminal of the radio frequency signal, the drain of the first NMOS tube is connected to the source of the second NMOS tube, and the source of the first NMOS tube is connected to ground. Terminal connected; the drain of the second NMOS tube is used as the output terminal of the radio frequency signal, and is connected to the first voltage source at the same time;
  • the negative feedback loop includes: a third NMOS tube, a fourth NMOS tube, and a differential amplifier;
  • the gate of the third NMOS tube is connected to the output terminal of the differential amplifier, the source of the third NMOS tube is connected to the ground terminal, and the drain of the third NMOS tube is connected to the fourth NMOS tube.
  • the source of the fourth NMOS tube is connected; the gate of the fourth NMOS tube is connected to the inverting input terminal of the differential amplifier and at the same time connected to the second voltage source.
  • the drain of the fourth NMOS tube is connected to the The positive input terminal is connected, and at the same time, it is connected to the first bias current source;
  • the gate of the first NMOS tube is connected to the output terminal of the differential amplifier; the gate of the second NMOS tube is connected to the second voltage source;
  • the second NMOS tube and the fourth NMOS tube work in a saturation region to realize power control of the first NMOS tube.
  • the ratio of the aspect ratio of the third NMOS tube to the first NMOS tube is equal to the ratio of the aspect ratio of the fourth NMOS tube to the second NMOS tube.
  • the power control circuit further includes: a first resistor; the gate of the first NMOS tube is connected to the output terminal of the differential amplifier through the first resistor.
  • the power control circuit further includes: a second resistor; the gate of the second NMOS transistor is connected to the second voltage source through the second resistor.
  • the power control circuit further includes an inductor; the drain of the second NMOS transistor is connected to the first voltage source through the inductor.
  • the fourth NMOS transistor when the drain voltage of the fourth NMOS transistor is equal to the gate voltage, the fourth NMOS transistor operates in the saturation region.
  • the power control circuit further includes: a fifth NMOS tube; the gate of the fourth NMOS tube is connected to the inverting input terminal of the differential amplifier through the fifth NMOS tube; the fifth NMOS tube The gate and drain of the tube are short-circuited; the source of the fifth NMOS tube is connected to the first terminal of the second bias current source; the second terminal of the second bias current source is connected to the ground terminal .
  • the threshold voltage of the fifth NMOS transistor is equal to the threshold voltage of the fourth NMOS transistor; the fifth NMOS transistor works in a weak inversion region.
  • the fourth NMOS transistor works in the saturation region.
  • the gate of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is connected to the inverting input terminal of the differential amplifier.
  • the power control circuit includes: a radio frequency signal path and a negative feedback loop;
  • the radio frequency signal path includes: a first NMOS transistor gate as a radio frequency signal input terminal, a drain electrode of which is connected to a second NMOS transistor
  • the source of the tube is connected, and the source is connected to the ground terminal;
  • the drain of the second NMOS tube is used as the radio frequency signal output terminal and is connected to the first voltage source;
  • the negative feedback loop includes: the gate of the third NMOS tube and the output terminal of the differential amplifier
  • the source is connected to the ground terminal, and the drain is connected to the source of the fourth NMOS tube;
  • the gate of the fourth NMOS tube is connected to the reverse input terminal of the differential amplifier and is connected to the second voltage source, and the drain is connected to the differential
  • the positive input terminal of the amplifier is connected to the first bias current source;
  • the gate of the first NMOS tube is connected to the output terminal of the differential amplifier;
  • the gate of the second NMOS tube is connected
  • FIG. 1 is a schematic diagram of the first composition structure of an existing power control circuit
  • FIG. 2 is a schematic diagram of the second composition structure of the existing power control circuit
  • FIG. 3 is a schematic diagram of the first composition structure of a power control circuit in an embodiment of the application.
  • FIG. 4 is a schematic diagram of a second composition structure of a power control circuit in an embodiment of the application.
  • FIG. 5 is a schematic diagram of a first application circuit of a power control circuit in an embodiment of the application
  • FIG. 6 is a schematic diagram of the third composition structure of the power control circuit in an embodiment of the application.
  • FIG. 7 is a schematic diagram of a second application circuit of the power control circuit in an embodiment of the application.
  • a power control circuit When the radio frequency power amplifier is in a saturated state, a power control circuit is needed to control the output power of the radio frequency power amplifier.
  • power control There are generally two ways of power control, namely current control and voltage control.
  • the method of current control is to control the bias current of the power amplifier by controlling the gate bias voltage of the amplifier tube.
  • an embodiment of the present application provides a power control circuit.
  • the circuit structure diagram solves the above two problems.
  • the circuit specifically includes: a radio frequency signal path and a negative feedback loop;
  • the radio frequency signal path includes: a first NMOS tube MN1 and a second NMOS tube MN2;
  • the gate of the MN1 tube is used as the input terminal of the radio frequency signal, the drain of the MN1 tube is connected to the source of the MN2 tube, and the source of the MN1 tube is connected to the ground terminal; A voltage source VCC is connected;
  • the negative feedback loop includes: a third NMOS tube MN3, a fourth NMOS tube MN4, and a differential amplifier;
  • the gate of the MN3 tube is connected to the output terminal of the differential amplifier, the source of the MN3 tube is connected to the ground terminal, the drain of the MN3 tube is connected to the source of the MN4 tube; the gate of the MN4 tube is connected to the inverting input terminal of the differential amplifier , Is connected to the second voltage source VG at the same time, the drain of the MN4 tube is connected to the forward input terminal of the differential amplifier, and at the same time is connected to the first bias current source IB;
  • the grid of the MN1 tube is connected to the grid of the MN3 tube; the grid of the MN2 tube is connected to the second voltage source VG;
  • the MN2 tube and MN4 tube work in the saturation zone to realize the power control of the MN1 tube.
  • the ratio of the width to length ratio of the MN3 tube to the MN1 tube is equal to the ratio of the width to length ratio of the MN4 tube to the MN2 tube.
  • the drain voltage of the MN3 tube needs to be equal to the drain terminal voltage of the MN1 tube. Therefore, based on the above-mentioned purpose, the MN4 tube is added to the existing power control circuit in FIG.
  • the MN4 tube when the drain voltage of the MN4 tube is equal to the gate voltage, the MN4 tube works in the saturation region.
  • the gate of the MN4 tube is connected to the reverse input terminal of the differential amplifier, and the drain of the MN4 tube is connected to the forward input terminal of the differential amplifier, and the gate voltage of the MN4 tube is equal to the drain voltage. Further, the gate-source voltage of the MN4 tube is equal to the drain-source voltage of the MN4 tube. Based on the condition that the MN4 tube works in the saturation region, the gate-source voltage minus the threshold voltage is less than the drain-source voltage, so the MN4 tube works in the saturation region.
  • the MN2 tube works in the saturation region, and the MN4 tube also works in the saturation region; the gate of the MN2 tube and the gate of the MN4 tube are both connected to the second voltage source VG; the width-to-length ratio of the MN3 tube and the MN1 tube The ratio of is equal to the ratio of the width-to-length ratio of the MN4 tube to the MN2 tube; based on the above three conditions, the source voltage of the MN2 tube is equal to the source voltage of the MN4 tube.
  • the source of the MN4 tube is connected to the drain of the MN3 tube, and the drain of the MN1 tube is connected to the source of the MN2 tube. Then the source voltage of the MN4 tube is equal to the drain voltage of the MN3 tube, and the source voltage of the MN2 tube is the same as MN1.
  • the drain voltages of the tubes are equal. Furthermore, if the drain voltage of the MN3 tube is equal to the drain voltage of the MN1 tube, there is no large deviation when the first bias current source IB of the MN3 tube is mirrored to the MN1 tube, thereby increasing the bias current of the MN1 tube. control precision.
  • FIG. 4 is a schematic diagram of the second structural structure of the power control circuit in an embodiment of the application.
  • the radio frequency signal path includes: MN1 tube and MN2 tube; Connected to the ground terminal; the drain of the MN2 tube is used as the output terminal of the radio frequency signal and is connected to the voltage source VCC at the same time; the negative feedback loop includes: MN3 tube, MN4 tube and differential amplifier; the gate of MN3 tube and the output of the differential amplifier
  • the source of the MN3 tube is connected to the ground terminal, the drain of the MN3 tube is connected to the source of the MN4 tube; the gate of the MN4 tube is connected to the inverting input terminal of the differential amplifier, and it is connected to the voltage source VG at the same time, the MN4 tube
  • the drain is connected to the positive input terminal of the differential amplifier and is connected to the bias current source IB; the gate of the MN1 tube is connected to the gate of the MN3 tube; the gate of the MN2 tube is connected to the voltage source VG; the MN2 tube is connected to the MN4
  • the tube works in the saturation zone
  • the radio frequency signal path does not pass through an analog signal, that is, the analog signal will not interfere with the radio frequency signal, nor will it reduce the performance of the radio frequency power amplifier.
  • the ratio of the width to length ratio of the MN3 tube to the MN1 tube is equal to the ratio of the width to length ratio of the MN4 tube to the MN2 tube.
  • the first end of the resistor R1 is connected to the output end of the differential amplifier, and the second end of the resistor R1 is connected to the gate of the MN1 tube.
  • the first end of the resistor R2 is connected to the voltage source VG, and is also connected to the reverse input end of the differential amplifier, and the second end of the resistor R2 is connected to the gate of the MN2 tube.
  • One end of the inductor L is connected to the drain of the MN2 tube, and the other end of the inductor L is connected to the voltage source VCC.
  • the gate of the MN4 tube is connected to the reverse input terminal of the differential amplifier, and the drain of the MN4 tube is connected to the forward input terminal of the differential amplifier, so the gate voltage of the MN4 tube is equal to the drain voltage. Further, the gate-source voltage of the MN4 tube is equal to the drain-source voltage of the MN4 tube. Based on the condition that the MN4 tube works in the saturation region, the gate-source voltage minus the threshold voltage is less than the drain-source voltage, so the MN4 tube works in the saturation region.
  • the MN2 tube works in the saturation region
  • the MN4 tube also works in the saturation region
  • the grid of the MN2 tube and the grid of the MN4 tube are both connected to the voltage source VG
  • the ratio of the width-to-length ratio of the MN3 tube to the MN1 tube It is equal to the ratio of the width to length ratio of the MN4 tube and the MN2 tube
  • the source voltage of the MN2 tube is equal to the source voltage of the MN4 tube.
  • the source of the MN4 tube is connected to the drain of the MN3 tube, and the drain of the MN1 tube is connected to the source of the MN2 tube. Then the source voltage of the MN4 tube is equal to the drain voltage of the MN3 tube, and the source voltage of the MN2 tube is the same as MN1.
  • the drain voltages of the tubes are equal. Furthermore, the drain voltage of the MN3 tube is equal to the drain voltage of the MN1 tube, there is no large deviation when the bias current source IB1 of the MN3 tube is mirrored to the MN1 tube, thereby improving the control accuracy of the bias current through the MN1 tube .
  • the power control circuit includes: a radio frequency signal path and a negative feedback loop;
  • the radio frequency signal path includes: a first NMOS transistor gate as a radio frequency signal input terminal, a drain electrode of which is connected to a second NMOS transistor
  • the source of the tube is connected, and the source is connected to the ground terminal;
  • the drain of the second NMOS tube is used as the radio frequency signal output terminal and is connected to the first voltage source;
  • the negative feedback loop includes: the gate of the third NMOS tube and the output terminal of the differential amplifier
  • the source is connected to the ground terminal, and the drain is connected to the source of the fourth NMOS tube;
  • the gate of the fourth NMOS tube is connected to the reverse input terminal of the differential amplifier and is connected to the second voltage source, and the drain is connected to the differential
  • the positive input terminal of the amplifier is connected to the first bias current source;
  • the gate of the first NMOS tube is connected to the output terminal of the differential amplifier;
  • the gate of the second NMOS tube is connected
  • FIG. 5 is a schematic diagram of the first application circuit of the power control circuit in an embodiment of the application.
  • the differential amplifier circuit in the dashed frame on the left is a specific circuit diagram of the differential amplifier in the power control circuit in Fig. 4.
  • the differential amplifier circuit includes: bias current source IB3, MN8 tube, MN7 tube, MN6 tube, MP1 tube and MP2 tube; the drain of the MN8 tube is shorted to the gate, and the drain terminal is connected to the bias current IB3; MN7 The drain of the tube is connected to the drain of the MP1 tube; the drain of the MN6 tube is connected to the drain of the MP2 tube; the sources of the MN8, MN7, and MN6 tubes are all connected to the ground terminal, and the gate of the MN8 tube is connected to the MN7 tube
  • the grid of the MN7 tube is connected to the grid of the MN6 tube; the drain of the MP1 tube is short-circuited with the grid, and the grid of the MP1 tube is connected to the grid of the MP2 tube.
  • the ratio of the width to length ratio of the MN7 tube to the MN6 tube is equal to the ratio of the width to length ratio of the MP1 tube to the MP2 tube. Furthermore, it can be concluded that the gate-source voltage of the MP1 tube is equal to the gate-source voltage of the MP2 tube.
  • the rest of the power control circuit includes: bias current source IB1, voltage source VG, voltage source VCC, MN4 tube, MN3 tube, MN2 tube, MN1 tube, resistance R1, resistance R2, inductance L, radio frequency signal input terminal RFIN and radio frequency signal The output terminal RFOUT; where the gate of the MN4 tube is connected to the voltage source VG, the drain of the MN4 tube is connected to the bias current source IB1, the source of the MN4 tube is connected to the drain of the MN3 tube; the source of the MN3 tube is connected to the ground The gate of the MN1 tube is connected to the RF signal input terminal RFIN, the source of the MN1 tube is connected to the ground terminal, the drain of the MN1 tube is connected to the source of the MN2 tube; the drain of the MN2 tube is connected to the RF signal output terminal RFOUT
  • the RF signal output terminal RFOUT is connected to one end of the inductor L, and the other end of the inductor L is connected to
  • the source of the MP2 tube is connected to the drain of the MN4 tube, the source of the MP1 tube is connected to the voltage source VG, and the grids of the MN3 tube are both connected to the grids of the MN6 tube and the MP2 tube.
  • the MP2 tube of the operational amplifier circuit, the MN3 tube and the MN4 tube of the power amplifier circuit form a negative feedback loop.
  • the gate voltage of the MP2 tube is equal to the voltage source VG minus the gate-source voltage of the MP1 tube, That is, the source voltage of the MP2 tube is equal to VG, that is, the drain voltage of the MN4 tube is equal to VG, and the MN4 tube works in the saturation region.
  • the MN2 tube also works in the saturation region, and the gate of the MN4 tube and the gate of the MN2 tube are both connected to the voltage source VG, then the source voltage of the MN2 tube is equal to the source voltage of the MN4 tube; based on the source of the MN4 tube and The drain of the MN3 tube is connected, and the drain of the MN1 tube is connected to the source of the MN2 tube. Then the drain voltage of the MN3 tube is equal to the drain voltage of the MN1 tube. There is a large deviation, thereby improving the control accuracy of the bias current of the MN1 tube.
  • FIG. 6 is a schematic diagram of the third structural structure of the power control circuit in an embodiment of the application. That is, on the basis of Figure 3, the MN5 tube and the bias current source IB2 are added. Specifically, the circuit connection mode of FIG. 6 is described as follows:
  • the power control circuit includes: a radio frequency signal path and a negative feedback loop;
  • the radio frequency signal path includes: MN1 tube, MN2 tube and voltage source VCC;
  • the source of the tube is connected, the source of the MN1 tube is connected to the ground;
  • the drain of the MN2 tube is used as the output terminal of the radio frequency signal, and is connected to the voltage source VCC;
  • the negative feedback loop includes: MN3 tube, MN4 tube, differential Amplifier; the gate of the MN3 tube is connected to the output terminal of the differential amplifier, the source of the MN3 tube is connected to the ground terminal, the drain of the MN3 tube is connected to the source of the MN4 tube; the drain of the MN4 tube is connected to the positive input of the differential amplifier
  • the gate of the MN4 tube is connected to the voltage source VG;
  • the power control circuit also includes: the MN5 tube and the bias current source IB2; the gate of the MN4 tube is connected to the differential amplifier through the M
  • the radio frequency signal path does not pass through an analog signal, that is, the analog signal will not interfere with the radio frequency signal, nor will it reduce the performance of the radio frequency power amplifier.
  • the ratio of the aspect ratio of the third NMOS tube to the first NMOS tube is equal to the ratio of the aspect ratio of the fourth NMOS tube to the second NMOS tube.
  • the power control circuit further includes: a first resistor; the gate of the first NMOS tube is connected to the output terminal of the differential amplifier through the first resistor.
  • one end of the resistor R1 is connected to the output end of the differential amplifier, and the other end of the resistor R1 is connected to the gate of the MN1 tube.
  • the power control circuit further includes: a second resistor; the gate of the second NMOS tube is connected to the second voltage source through the second resistor.
  • one end of the resistor R2 is connected to the voltage source VG, and is also connected to the inverting input end of the differential amplifier, and the other end of the resistor R2 is connected to the gate of the MN2 tube.
  • the power control circuit further includes an inductor; the drain of the second NMOS transistor is connected to the first voltage source through the inductor.
  • one end of the inductor L is connected to the drain of the MN2 tube, and the other end of the inductor L is connected to the voltage source VCC.
  • the threshold voltage of the fifth NMOS transistor is equal to the threshold voltage of the fourth NMOS transistor; the fifth NMOS transistor works in a weak inversion region.
  • the gate-source voltage of the MN5 tube is equal to the threshold voltage; among them, the condition for the NMOS tube to work in the weak inversion region is that the gate-source voltage is equal to the threshold voltage; based on the gate and the threshold voltage of the MN5 tube
  • the gate of the MN4 tube is connected, and the gate of the MN4 tube is connected to the voltage source VG, so the source voltage of the MN5 tube is equal to the voltage source VG minus the threshold voltage of the MN5 tube.
  • the drain voltage of the MN4 tube is equal to the source voltage of the MN5 tube.
  • MN4 The drain-source voltage of the tube is equal to the gate-source voltage of the MN4 tube minus the threshold voltage, and the MN4 tube works in the saturation region.
  • the MN2 tube works in the saturation region
  • the MN4 tube also works in the saturation region
  • the gate of the MN2 tube and the gate of the MN4 tube are both connected to the voltage source VG; based on the above two conditions, the MN2 tube is obtained
  • the source voltage of is equal to the source voltage of the MN4 tube.
  • the source of the MN4 tube is connected to the drain of the MN3 tube, and the drain of the MN1 tube is connected to the source of the MN2 tube. Then the source voltage of the MN4 tube is equal to the drain voltage of the MN3 tube, and the source voltage of the MN2 tube is the same as MN1.
  • the drain voltages of the tubes are equal. Furthermore, the drain voltage of the MN3 tube is equal to the drain voltage of the MN1 tube, there is no large deviation when the bias current source IB1 of the MN3 tube is mirrored to the MN1 tube, thereby improving the control accuracy of the bias current through the MN1 tube .
  • the present application discloses a power control circuit.
  • the power control circuit includes: a radio frequency signal path and a negative feedback loop;
  • the radio frequency signal path includes: a first NMOS transistor gate as a radio frequency signal input terminal, and a drain and a second NMOS
  • the source of the tube is connected, and the source is connected to the ground terminal;
  • the drain of the second NMOS tube is used as the radio frequency signal output terminal and is connected to the first voltage source;
  • the negative feedback loop includes: the gate of the third NMOS tube and the output terminal of the differential amplifier
  • the source is connected to the ground terminal, and the drain is connected to the source of the fourth NMOS tube;
  • the gate of the fourth NMOS tube is connected to the reverse input terminal of the differential amplifier and is connected to the second voltage source, and the drain is connected to the differential
  • the positive input terminal of the amplifier is connected to the first bias current source;
  • the gate of the first NMOS tube is connected to the output terminal of the differential amplifier;
  • FIG. 7 is a schematic diagram of a second application circuit of the power control circuit in an embodiment of the application.
  • the differential amplifier circuit in the dashed frame on the left is a specific circuit diagram of the differential amplifier in the power control circuit in FIG. Among them, the source of the MN5 tube is connected to the source of the MP1 tube, so that the bias current source IB2 in FIG. 6 can be saved.
  • the differential amplifier circuit includes: bias current source IB3, MN8 tube, MN7 tube, MN6 tube, MN5 tube, MP1 tube and MP2 tube; the drain of the MN8 tube is shorted to the gate, and the drain terminal is connected to the bias current IB3 Connected; the drain of the MN7 tube is connected to the drain of the MP1 tube; the drain of the MN6 tube is connected to the drain of the MP2 tube; the sources of the MN8 tube, MN7 tube, and MN6 tube are all connected to the ground terminal, and the gate of the MN8 tube Connected to the gate of the MN7 tube, the gate of the MN7 tube is connected to the gate of the MN6 tube; the gate of the MN5 tube is shorted to the drain, the source of the MN5 tube is connected to the source of the MP1 tube; the drain of the MP1 tube Short to the grid, the grid of the MP1 tube is connected to the grid of the MP2 tube.
  • the ratio of the width-to-length ratio of the MN7 tube to the MN6 tube is equal to the ratio of the width-to-length ratio of the MP1 tube to the MP2 tube. Furthermore, it can be concluded that the gate-source voltage of the MP1 tube is equal to the gate-source voltage of the MP2 tube; the MN5 tube works at In the weak inversion area, the gate-source voltage of the MN5 tube is equal to the threshold voltage.
  • the rest of the power control circuit includes: bias current source IB1, voltage source VG, voltage source VCC, MN4 tube, MN3 tube, MN2 tube, MN1 tube, resistance R1, resistance R2, inductance L, radio frequency signal input terminal RFIN and radio frequency signal The output terminal RFOUT; where the gate of the MN4 tube is connected to the voltage source VG, the drain of the MN4 tube is connected to the bias current source IB1, the source of the MN4 tube is connected to the drain of the MN3 tube; the source of the MN3 tube is connected to the ground The gate of the MN1 tube is connected to the RF signal input terminal RFIN, the source of the MN1 tube is connected to the ground terminal, the drain of the MN1 tube is connected to the source of the MN2 tube; the drain of the MN2 tube is connected to the RF signal output terminal RFOUT
  • the RF signal output terminal RFOUT is connected to one end of the inductor L, and the other end of the inductor L is connected to
  • the source of the MP2 tube is connected to the drain of the MN4 tube, the source of the MN5 tube is connected to the voltage source VG, and the gates of the MN3 tube are both connected to the gates of the MN6 tube and the MP2 tube.
  • the gate of the MP1 tube is connected to the gate of the MP2 tube
  • the source of the MP1 tube is connected to the source of the MP5 tube
  • the source of the MP2 tube is connected to the source of the MN4 tube.
  • the drain is connected, and the threshold voltage of the MN5 tube is equal to the threshold voltage of the MN4 tube, the drain voltage of the MN4 tube is equal to VG minus the threshold voltage, that is, the MN4 tube works in the saturation region.
  • the MN2 tube also works in the saturation region, and the gate of the MN4 tube and the gate of the MN2 tube are both connected to the voltage source VG, then the source voltage of the MN2 tube is equal to the source voltage of the MN4 tube; based on the source of the MN4 tube and The drain of the MN3 tube is connected, and the drain of the MN1 tube is connected to the source of the MN2 tube. Then the drain voltage of the MN3 tube is equal to the drain voltage of the MN1 tube. There is a large deviation, thereby improving the control accuracy of the bias current of the MN1 tube.
  • the power control circuit includes: a radio frequency signal path and a negative feedback loop;
  • the radio frequency signal path includes: a first NMOS transistor gate as a radio frequency signal input terminal, a drain electrode of which is connected to a second NMOS transistor
  • the source of the tube is connected, and the source is connected to the ground terminal;
  • the drain of the second NMOS tube is used as the radio frequency signal output terminal and is connected to the first voltage source;
  • the negative feedback loop includes: the gate of the third NMOS tube and the output terminal of the differential amplifier
  • the source is connected to the ground terminal, and the drain is connected to the source of the fourth NMOS tube;
  • the gate of the fourth NMOS tube is connected to the reverse input terminal of the differential amplifier and is connected to the second voltage source, and the drain is connected to the differential
  • the positive input terminal of the amplifier is connected to the first bias current source;
  • the gate of the first NMOS tube is connected to the output terminal of the differential amplifier;
  • the gate of the second NMOS tube is connected

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Abstract

一种功率控制电路，包括：射频信号通路包括：第一NMOS管（MN1）栅极作为射频信号输入端，其漏极与第二NMOS管（MN2）源极相连，其源极与接地端相连；第二NMOS管（MN2）漏极作为射频信号输出端，并与第一电压源（VCC）相连；负反馈环路包括：第三NMOS管（MN3）栅极与差分放大器输出端相连，其源极与接地端相连，其漏极与第四NMOS管（MN4）源极相连；第四NMOS管（MN4）栅极与差分放大器反向输入端相连，并与第二电压源（VG）相连，其漏极与差分放大器正向输入端相连，并与第一偏置电流源（IB）相连；第一NMOS管（MN1）栅极与差分放大器输出端相连；第二NMOS管（MN2）栅极与第二电压源（VG）相连；第二NMOS管（MN2）与第四NMOS管（MN4）工作在饱和区。如此，射频信号通路不经过模拟信号，不影响第一NMOS管（MN1）性能，同时提高输出功率的控制精度。

Description

一种功率控制电路
本申请基于申请号为202010099884.6，申请日为2020年02月18日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及电子技术领域，尤其涉及一种功率控制电路。
背景技术
射频功率放大器，也可简称功放。当功放处于饱和状态时，则需功率控制电路来控制功放的输出功率。所谓功率控制一般有两种方式，分别是电流控制和电压控制。其中，电流控制的方法是通过控制功放中放大管的栅极偏置电压进而控制其偏置电流。如图1为现有的功率控制电路的第一组结构示意图。如图1所示，MN3管的漏极与电流源IB相连，MN3管的漏极与栅极短接；MN1管的漏极与MN2管的源极相连，MN1管的栅极作为射频信号的输入端；MN3管的栅极与MN1管的栅极相连，且中间串联一电阻R1，MN3管的源极与MN1管的源极均与接地端相连；MN2管的栅极与电压源VG相连，且中间串联一电阻R2，MN2管的漏极与电压源VCC相连，且中间串联一电感L，同时作为射频信号的输出端。基于上述电路连接方式导致客观存在沟道调制效应，使得经过MN3的偏置电流IB镜像到MN1时会引入较大的偏差，进而使饱和功率偏差较大。
如图2为现有的功率控制电路的第二组成结构示意图。如图2所示，即在图1的基础上添加了一个差分放大器，具体地，差分放大器的正向输入端与MN3管的漏极相连，差分放大器的反向输入端与MN1管的漏极相连，差分放大器的输出端与MN3管的栅极相连，且与电阻R1的一端相连。其他部分连接方式与如图1中描述相同。其中，MN1管、MN3管和差分放大器构成一反馈 环路。通过引入一个差分运放，使MN1和MN3管的漏端电压相等，从而消除了沟道长度调制效应的影响，提高了电流控制精度。但是由于射频功率放大管MN1在反馈环路中，使得一部分射频信号通路会走过模拟信号，模拟信号会对射频信号产生干扰，降低了射频功率放大器的性能。
发明内容
使用功率控制电路控制射频功率放大器的输出功率的同时，存在沟道长度调制效应的影响或降低射频放大器性能的问题，为解决上述问题，本申请实施例提供一种功率控制电路。
本申请的技术方案是这样实现的：
本申请实施例提供一种功率控制电路，所述电路包括：射频信号通路和负反馈环路；
所述射频信号通路包括：第一NMOS管和第二NMOS管；
所述第一NMOS管的栅极作为所述射频信号的输入端，所述第一NMOS管的漏极与所述第二NMOS管的源极相连，所述第一NMOS管的源极与接地端相连；所述第二NMOS管的漏极作为所述射频信号的输出端，同时与第一电压源相连；
所述负反馈环路包括：第三NMOS管、第四NMOS管和差分放大器；
所述第三NMOS管的栅极与所述差分放大器的输出端相连，所述第三NMOS管的源极与所述接地端相连，所述第三NMOS管的漏极与所述第四NMOS管的源极相连；所述第四NMOS管的栅极与所述差分放大器的反向输入端相连，同时与第二电压源相连，所述第四NMOS管的漏极与所述差分放大器的正向输入端相连，同时与第一偏置电流源相连；
所述第一NMOS管的栅极与所述差分放大器的输出端相连；所述第二NMOS管的栅极与所述第二电压源相连；
所述第二NMOS管与所述第四NMOS管工作在饱和区，实现对所述第一NMOS管实现了功率控制。
上述方案中，所述第三NMOS管与所述第一NMOS管的宽长比的比值和所述第四NMOS管与所述第二NMOS管的宽长比的比值相等。
上述方案中，所述功率控制电路还包括：第一电阻；所述第一NMOS管的栅极通过所述第一电阻与所述差分放大器的输出端相连。
上述方案中，所述功率控制电路还包括：第二电阻；所述第二NMOS管的栅极通过所述第二电阻与所述第二电压源相连。
上述方案中，所述功率控制电路还包括：电感；所述第二NMOS管的漏极通过所述电感与所述第一电压源相连。
上述方案中，当所述第四NMOS管的漏极电压等于栅极电压，则所述第四NMOS管工作在饱和区。
上述方案中，所述功率控制电路还包括：第五NMOS管；所述第四NMOS管的栅极通过所述第五NMOS管与所述差分放大器的反向输入端相连；所述第五NMOS管的栅极和漏极短接；所述第五NMOS管的源极与第二偏置电流源的第一端相连；所述第二偏置电流源的第二端与所述接地端相连。
上述方案中，所述第五NMOS管的阈值电压与所述第四NMOS管的阈值电压相等；所述第五NMOS管工作在弱反型区。
上述方案中，当所述第四NMOS管的漏极电压等于栅极电压减去阈值电压，则所述第四NMOS管工作在饱和区。
上述方案中，所述第四NMOS管的栅极与所述第五NMOS管的漏极相连；所述第五NMOS管的源极与所述差分放大器的反向输入端相连。
本申请公开了一种功率控制电路，所述功率控制电路包括：射频信号通路和负反馈环路；射频信号通路包括：第一NMOS管栅极作为射频信号输入端，其漏极与第二NMOS管源极相连，其源极与接地端相连；第二NMOS管漏极作为射频信号输出端，并与第一电压源相连；负反馈环路包括：第三NMOS管栅极与差分放大器输出端相连，其源极与接地端相连，其漏极与第四NMOS管源极相连；第四NMOS管栅极与差分放大器反向输入端相连，并与第二电压源相连，其漏极与差分放大器正向输入端相连，并与第一偏置电流源相连；第一 NMOS管栅极与差分放大器输出端相连；第二NMOS管栅极与第二电压源相连；第二NMOS管与第四NMOS管工作在饱和区。如此，射频信号通路不经过模拟信号，不影响第一NMOS管性能，同时提高输出功率的控制精度。
附图说明
图1为现有的功率控制电路的第一组成结构示意图；
图2为现有的功率控制电路的第二组成结构示意图；
图3为本申请实施例中功率控制电路的第一组成结构示意图；
图4为本申请实施例中功率控制电路的第二组成结构示意图；
图5为本申请实施例中功率控制电路的第一应用电路示意图；
图6为本申请实施例中功率控制电路的第三组成结构示意图；
图7为本申请实施例中功率控制电路的第二应用电路示意图。
具体实施方式
为了能够更加详尽地了解本申请实施例的特点与技术内容，下面结合附图对本申请实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本申请实施例。
当射频功率放大器处于饱和状态时，需要功率控制电路来控制射频功率放大器的输出功率。功率控制一般有两种方式，分别是电流控制和电压控制。其中电流控制的方法是通过控制功率放大器中放大管的栅极偏置电压进而控制其偏置电流。
基于现有的功率控制电路中存在沟道长度调制效应的影响和降低射频放大器性能的问题，本申请实施例提供了一种功率控制电路，图3为本申请实施例中一种功率控制电路的电路结构图，解决了上述存在的两个问题。如图3所示，该电路具体包括：射频信号通路和负反馈环路；
所述射频信号通路包括：第一NMOS管MN1和第二NMOS管MN2；
MN1管的栅极作为射频信号的输入端，MN1管的漏极与MN2管的源极相 连，MN1管的源极与接地端相连；MN2管的漏极作为射频信号的输出端，同时与第一电压源VCC相连；
所述负反馈环路包括：第三NMOS管MN3、第四NMOS管MN4和差分放大器；
MN3管的栅极与差分放大器的输出端相连，MN3管的源极与接地端相连，MN3管的漏极与MN4管的源极相连；MN4管的栅极与差分放大器的反向输入端相连，同时与第二电压源VG相连，MN4管的漏极与差分放大器的正向输入端相连，同时与第一偏置电流源IB相连；
MN1管的栅极与所述MN3管的栅极相连；MN2管的栅极与第二电压源VG相连；
MN2管与MN4管工作在饱和区，实现对MN1管的功率控制。
在一些实施例中，所述MN3管与所述MN1管的宽长比的比值和所述MN4管与所述MN2管的宽长比的比值相等。
具体地，为了使经过MN3管的第一偏置电流镜像到MN1管时不存在较大偏差，那么，MN3管的漏极电压需要与MN1管的漏端电压相等。所以，基于上述目的，在图1现有的功率控制电路中增添MN4管，并且，MN3管与MN1管的宽长比的比值和MN4管与MN2管的宽长比的比值相等。
在一些实施例中，当所述MN4管的漏极电压等于栅极电压，则所述MN4管工作在饱和区。
具体地，MN4管的栅极与差分放大器的反向输入端相连，MN4管的漏极与差分放大器的正向输入端相连，则MN4管的栅极电压与漏极电压相等。进一步地，MN4管的栅源电压与MN4管的漏源电压相等，基于MN4管工作在饱和区的条件是：栅源电压减去阈值电压小于漏源电压，所以，MN4管工作在饱和区。
进一步地，已知MN2管工作在饱和区，又MN4管也工作在饱和区；MN2管的栅极和MN4管的栅极均与第二电压源VG相连；MN3管与MN1管的宽长比的比值和MN4管与MN2管的宽长比的比值相等；基于上述三个条件，得出 MN2管的源极电压和MN4管的源极电压相等。
MN4管的源极与MN3管的漏极相连，MN1管的漏极与MN2管的源极相连，则MN4管的源极电压与MN3管的漏极电压相等，MN2管的源极电压与MN1管的漏极电压相等。进而，MN3管的漏极电压与MN1管的漏极电压相等，则经过MN3管的第一偏置电流源IB镜像到MN1管时不存在较大偏差，从而提高经过MN1管的偏置电流的控制精度。
针对图3功率控制电路的第一组成结构示意图，本申请给出了一种具体的电路图，图4为本申请实施例中功率控制电路的第二组成结构示意图。
如图4所示，所述射频信号通路包括：MN1管和MN2管；MN1管的栅极作为射频信号的输入端，MN1管的漏极与MN2管的源极相连，MN1管的源极与接地端相连；MN2管的漏极作为射频信号的输出端，同时与电压源VCC相连；所述负反馈环路包括：MN3管、MN4管和差分放大器；MN3管的栅极与差分放大器的输出端相连，MN3管的源极与接地端相连，MN3管的漏极与MN4管的源极相连；MN4管的栅极与差分放大器的反向输入端相连，同时与电压源VG相连，MN4管的漏极与差分放大器的正向输入端相连，同时与偏置电流源IB相连；MN1管的栅极与MN3管的栅极相连；MN2管的栅极与电压源VG相连；MN2管与MN4管工作在饱和区，实现对MN1管的功率控制。
上述技术方案中，射频信号通路不经过模拟信号，即模拟信号不会对射频信号产生干扰，也不会降低射频功率放大器的性能。
其中，MN3管与MN1管的宽长比的比值和MN4管与MN2管的宽长比的比值相等。
电阻R1的第一端与差分放大器的输出端相连，电阻R1的第二端与MN1管的栅极相连。
电阻R2的第一端与电压源VG相连，同时也与差分放大器的反向输入端相连，电阻R2的第二端与MN2管的栅极相连。
电感L的一端与MN2管的漏极相连，电感L的另一端与电压源VCC相连。
MN4管的栅极与差分放大器的反向输入端相连，MN4管的漏极与差分放 大器的正向输入端相连，则MN4管的栅极电压与漏极电压相等。进一步地，MN4管的栅源电压与MN4管的漏源电压相等，基于MN4管工作在饱和区的条件是：栅源电压减去阈值电压小于漏源电压，所以，MN4管工作在饱和区。
进一步地，已知MN2管工作在饱和区，又MN4管也工作在饱和区；MN2管的栅极和MN4管的栅极均与电压源VG相连；MN3管与MN1管的宽长比的比值和MN4管与MN2管的宽长比的比值相等；基于上述三个条件，得出MN2管的源极电压和MN4管的源极电压相等。
MN4管的源极与MN3管的漏极相连，MN1管的漏极与MN2管的源极相连，则MN4管的源极电压与MN3管的漏极电压相等，MN2管的源极电压与MN1管的漏极电压相等。进而，MN3管的漏极电压与MN1管的漏极电压相等，则经过MN3管的偏置电流源IB1镜像到MN1管时不存在较大偏差，从而提高经过MN1管的偏置电流的控制精度。
本申请公开了一种功率控制电路，所述功率控制电路包括：射频信号通路和负反馈环路；射频信号通路包括：第一NMOS管栅极作为射频信号输入端，其漏极与第二NMOS管源极相连，其源极与接地端相连；第二NMOS管漏极作为射频信号输出端，并与第一电压源相连；负反馈环路包括：第三NMOS管栅极与差分放大器输出端相连，其源极与接地端相连，其漏极与第四NMOS管源极相连；第四NMOS管栅极与差分放大器反向输入端相连，并与第二电压源相连，其漏极与差分放大器正向输入端相连，并与第一偏置电流源相连；第一NMOS管栅极与差分放大器输出端相连；第二NMOS管栅极与第二电压源相连；第二NMOS管与第四NMOS管工作在饱和区。如此，射频信号通路不经过模拟信号，不影响第一NMOS管性能，同时提高输出功率的控制精度。
图5为本申请实施例中功率控制电路的第一应用电路示意图。如图5所示，左侧虚线框中的差分放大器电路为图4中功率控制电路中差分放大器的具体电路图。
其中，差分放大器电路包括：偏置电流源IB3、MN8管、MN7管、MN6管、MP1管和MP2管；MN8管的漏极与栅极短接，且漏极端与偏置电流IB3 相连；MN7管的漏极与MP1管的漏极相连；MN6管的漏极与MP2管的漏极相连；MN8管、MN7管、MN6管的源极均与接地端相连，MN8管的栅极与MN7管的栅极相连，MN7管的栅极与MN6管的栅极相连；MP1管的漏极与栅极短接，MP1管的栅极与MP2管的栅极相连。其中，MN7管与MN6管的宽长比的比值和MP1管与MP2管的宽长比的比值相等。进而，能够得出MP1管的栅源电压等于MP2管的栅源电压。
功率控制电路其余部分包括：偏置电流源IB1、电压源VG、电压源VCC、MN4管、MN3管、MN2管、MN1管、电阻R1、电阻R2、电感L、射频信号输入端RFIN和射频信号输出端RFOUT；其中，MN4管的栅极与电压源VG相连，MN4管的漏极与偏置电流源IB1相连，MN4管的源极与MN3管的漏极相连；MN3管的源极与接地端相连；MN1管的栅极与射频信号输入端RFIN相连，MN1管的源极与接地端相连，MN1管的漏极与MN2管的源极相连；MN2管的漏极与射频信号输出端RFOUT相连，射频信号输出端RFOUT与电感L的一端相连，电感L的另一端与电压源VCC相连；MN2管的栅极通过电阻R2与MN4管的栅极相连；MN1管的栅极通过电阻R1与MN3管的栅极相连。
MP2管的源极与MN4管的漏极相连，MP1管的源极与电压源VG相连，MN3管的栅极均与MN6管和MP2管的栅极相连。运放放大器电路的MP2管、功率放大器电路的MN3管和MN4管构成负反馈回路。
基于MP1管的栅源电压等于MP2管的栅源电压，且MP1管的栅极与MP2管的栅极相连，所以，MP2管的栅极电压等于电压源VG减去MP1管的栅源电压，即MP2管的源极电压等于VG，也就是MN4管的漏极电压等于VG，MN4管工作在饱和区。
又MN2管也工作在饱和区，且MN4管的栅极和MN2管的栅极均与电压源VG相连，则MN2管的源极电压等于MN4管的源极电压；基于MN4管的源极与MN3管的漏极相连，MN1管的漏极与MN2管的源极相连，则MN3管的漏极电压与MN1管的漏极电压相等，经过MN3管偏置电流源IB1镜像到MN1管时不存在较大偏差，从而提高MN1管偏置电流的控制精度。
针对图3功率控制电路的第一组成结构示意图，本申请给出了另一种具体的电路图，如图6为本申请实施例中功率控制电路的第三组成结构示意图。即在图3的基础上添加了MN5管、偏置电流源IB2。具体地，图6的电路连接方式描述如下：
功率控制电路包括：射频信号通路和负反馈环路；所述射频信号通路包括：MN1管、MN2管和电压源VCC；MN1管的栅极作为射频信号的输入端，MN1管的漏极与MN2管的源极相连，MN1管的源极与接地端相连；MN2管的漏极作为射频信号的输出端，同时与电压源VCC相连；所述负反馈环路包括：MN3管、MN4管、差分放大器；MN3管的栅极与差分放大器的输出端相连，MN3管的源极与接地端相连，MN3管的漏极与MN4管的源极相连；MN4管的漏极与差分放大器的正向输入端相连，同时与偏置电流源IB1相连；MN4管的栅极与电压源VG相连；功率控制电路还包括：MN5管和偏置电流源IB2；MN4管的栅极通过MN5管与差分放大器的反向输入端相连，具体地，MN4管的栅极与MN5管的漏极相连；MN5管的源极与差分放大器的反向输入端相连；MN5管的栅极与漏极短接，MN5管的源极与偏置电流源IB2的一端相连；偏置电流源IB2的另一端与接地端相连；MN1管的栅极与MN3管的栅极相连；MN2管的栅极与电压源VG相连；MN2管与MN4管工作在饱和区，实现对MN1管的功率控制。
上述技术方案中，射频信号通路不经过模拟信号，即模拟信号不会对射频信号产生干扰，也不会降低射频功率放大器的性能。
在一些实施例中，所述第三NMOS管与所述第一NMOS管的宽长比的比值和所述第四NMOS管与所述第二NMOS管的宽长比的比值相等。
在一些实施例中，所述功率控制电路还包括：第一电阻；所述第一NMOS管的栅极通过所述第一电阻与所述差分放大器的输出端相连。
具体地，所述电阻R1的一端与差分放大器的输出端相连，电阻R1的另一端与MN1管的栅极相连。
在一些实施例中，所述功率控制电路还包括：第二电阻；所述第二NMOS 管的栅极通过所述第二电阻与所述第二电压源相连。
具体地，电阻R2的一端与电压源VG相连，同时也与差分放大器的反向输入端相连，电阻R2的另一端与MN2管的栅极相连。
在一些实施例中，所述功率控制电路还包括：电感；所述第二NMOS管的漏极通过所述电感与所述第一电压源相连。
具体地，所述电感L的一端与MN2管的漏极相连，所述电感L的另一端与电压源VCC相连。
在一些实施例中，所述第五NMOS管的阈值电压与所述第四NMOS管的阈值电压相等；所述第五NMOS管工作在弱反型区。
具体地，MN5管工作在弱反型区，则MN5管的栅源电压等于阈值电压；其中，NMOS管工作在弱反型区的条件是栅源电压等于阈值电压；基于MN5管的栅极与MN4管的栅极相连，且MN4管的栅极与电压源VG相连，所以，MN5管的源极电压等于电压源VG减去MN5管的阈值电压。
基于MN4管的漏极与差分放大器的正向输入端相连，MN5管的源极与差分放大器的反向输入端相连，则MN4管的漏极电压等于MN5管的源极电压，进一步地，MN4管的漏源电压等于MN4管的栅源电压减去阈值电压，MN4管工作在饱和区。
进一步地，已知MN2管工作在饱和区，又MN4管也工作在饱和区，且MN2管的栅极和MN4管的栅极均与电压源VG相连；基于上述两个条件，得出MN2管的源极电压和MN4管的源极电压相等。
MN4管的源极与MN3管的漏极相连，MN1管的漏极与MN2管的源极相连，则MN4管的源极电压与MN3管的漏极电压相等，MN2管的源极电压与MN1管的漏极电压相等。进而，MN3管的漏极电压与MN1管的漏极电压相等，则经过MN3管的偏置电流源IB1镜像到MN1管时不存在较大偏差，从而提高经过MN1管的偏置电流的控制精度。
本申请公开了一种功率控制电路，所述功率控制电路包括：射频信号通路和负反馈环路；射频信号通路包括：第一NMOS管栅极作为射频信号输入端， 其漏极与第二NMOS管源极相连，其源极与接地端相连；第二NMOS管漏极作为射频信号输出端，并与第一电压源相连；负反馈环路包括：第三NMOS管栅极与差分放大器输出端相连，其源极与接地端相连，其漏极与第四NMOS管源极相连；第四NMOS管栅极与差分放大器反向输入端相连，并与第二电压源相连，其漏极与差分放大器正向输入端相连，并与第一偏置电流源相连；第一NMOS管栅极与差分放大器输出端相连；第二NMOS管栅极与第二电压源相连；第二NMOS管与第四NMOS管工作在饱和区。如此，射频信号通路不经过模拟信号，不影响第一NMOS管性能，同时提高输出功率的控制精度。
图7为本申请实施例中功率控制电路的第二应用电路示意图。如图7所示，左侧虚线框中的差分放大器电路为图6中功率控制电路中差分放大器的具体电路图。其中，将MN5管的源极接到MP1管的源极，从而可以节省图6中偏置电流源IB2。
其中，差分放大器电路包括：偏置电流源IB3、MN8管、MN7管、MN6管、MN5管、MP1管和MP2管；MN8管的漏极与栅极短接，且漏极端与偏置电流IB3相连；MN7管的漏极与MP1管的漏极相连；MN6管的漏极与MP2管的漏极相连；MN8管、MN7管、MN6管的源极均与接地端相连，MN8管的栅极与MN7管的栅极相连，MN7管的栅极与MN6管的栅极相连；MN5管的栅极与漏极短接，MN5管的源极与MP1管的源极相连；MP1管的漏极与栅极短接，MP1管的栅极与MP2管的栅极相连。其中，MN7管与MN6管的宽长比的比值和MP1管与MP2管的宽长比的比值相等，进而，能够得出MP1管的栅源电压等于MP2管的栅源电压；MN5管工作在弱反型区，则MN5管的栅源电压等于阈值电压。
功率控制电路其余部分包括：偏置电流源IB1、电压源VG、电压源VCC、MN4管、MN3管、MN2管、MN1管、电阻R1、电阻R2、电感L、射频信号输入端RFIN和射频信号输出端RFOUT；其中，MN4管的栅极与电压源VG相连，MN4管的漏极与偏置电流源IB1相连，MN4管的源极与MN3管的漏极相连；MN3管的源极与接地端相连；MN1管的栅极与射频信号输入端RFIN相 连，MN1管的源极与接地端相连，MN1管的漏极与MN2管的源极相连；MN2管的漏极与射频信号输出端RFOUT相连，射频信号输出端RFOUT与电感L的一端相连，电感L的另一端与电压源VCC相连；MN2管的栅极通过电阻R2与MN4管的栅极相连；MN1管的栅极通过电阻R1与MN3管的栅极相连。
MP2管的源极与MN4管的漏极相连，MN5管的源极与电压源VG相连，MN3管的栅极均与MN6管和MP2管的栅极相连。
基于MP1管的栅源电压等于MP2管的栅源电压，MP1管的栅极与MP2管的栅极相连，MP1管的源极与MP5管的源极相连，MP2管的源极与MN4管的漏极相连，及MN5管的阈值电压与MN4管的阈值电压相等，则MN4管的漏极电压等于VG减去阈值电压，即MN4管工作在饱和区。
又MN2管也工作在饱和区，且MN4管的栅极和MN2管的栅极均与电压源VG相连，则MN2管的源极电压等于MN4管的源极电压；基于MN4管的源极与MN3管的漏极相连，MN1管的漏极与MN2管的源极相连，则MN3管的漏极电压与MN1管的漏极电压相等，经过MN3管偏置电流源IB1镜像到MN1管时不存在较大偏差，从而提高MN1管偏置电流的控制精度。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请公开了一种功率控制电路，所述功率控制电路包括：射频信号通路和负反馈环路；射频信号通路包括：第一NMOS管栅极作为射频信号输入端，其漏极与第二NMOS管源极相连，其源极与接地端相连；第二NMOS管漏极作为射频信号输出端，并与第一电压源相连；负反馈环路包括：第三NMOS管栅极与差分放大器输出端相连，其源极与接地端相连，其漏极与第四NMOS管源极相连；第四NMOS管栅极与差分放大器反向输入端相连，并与第二电压源相连，其漏极与差分放大器正向输入端相连，并与第一偏置电流源相连；第一NMOS管栅极与差分放大器输出端相连；第二NMOS管栅极与第二电压源相连；第二NMOS管与第四NMOS管工作在饱和区。如此，射频信号通路不经过模拟信号，不影响第一NMOS管性能，同时提高输出功率的控制精度。

Claims (9)

  1. 一种功率控制电路，其中，所述功率控制电路包括：射频信号通路和负反馈环路；
    所述射频信号通路包括：第一NMOS管和第二NMOS管；
    所述第一NMOS管的栅极作为所述射频信号的输入端，所述第一NMOS管的漏极与所述第二NMOS管的源极相连，所述第一NMOS管的源极与接地端相连；所述第二NMOS管的漏极作为所述射频信号的输出端，同时与第一电压源相连；
    所述负反馈环路包括：第三NMOS管、第四NMOS管和差分放大器；
    所述第三NMOS管的栅极与所述差分放大器的输出端相连，所述第三NMOS管的源极与所述接地端相连，所述第三NMOS管的漏极与所述第四NMOS管的源极相连；所述第四NMOS管的栅极与所述差分放大器的反向输入端相连，同时与第二电压源相连，所述第四NMOS管的漏极与所述差分放大器的正向输入端相连，同时与第一偏置电流源相连；
    所述第一NMOS管的栅极与所述差分放大器的输出端相连；所述第二NMOS管的栅极与所述第二电压源相连；
    所述第二NMOS管与所述第四NMOS管工作在饱和区，实现对所述第一NMOS管的功率控制。
  2. 根据权利要求1所述的功率控制电路，其中，
    所述第三NMOS管与所述第一NMOS管的宽长比的比值和所述第四NMOS管与所述第二NMOS管的宽长比的比值相等。
  3. 根据权利要求1所述的功率控制电路，其中，
    所述功率控制电路还包括：第一电阻；
    所述第一NMOS管的栅极通过所述第一电阻与所述差分放大器的输出端相连。
  4. 根据权利要求3所述的功率控制电路，其中，
    所述功率控制电路还包括：第二电阻；
    所述第二NMOS管的栅极通过所述第二电阻与所述第二电压源相连。
  5. 根据权利要求4所述的功率控制电路，其中，
    所述功率控制电路还包括：电感；
    所述第二NMOS管的漏极通过所述电感与所述第一电压源相连。
  6. 根据权利要求1所述的功率控制电路，其中，
    当所述第四NMOS管的漏极电压等于栅极电压，则所述第四NMOS管工作在饱和区。
  7. 根据权利要求1-5任一项所述的功率控制电路，其中，
    所述功率控制电路还包括：第五NMOS管；
    所述第四NMOS管的栅极通过所述第五NMOS管与所述差分放大器的反向输入端相连；
    所述第四NMOS管的栅极与所述第五NMOS管的漏极相连；所述第五NMOS管的源极与所述差分放大器的反向输入端相连；所述第五NMOS管的栅极和漏极短接；
    所述第五NMOS管的源极与第二偏置电流源的第一端相连；所述第二偏置电流源的第二端与所述接地端相连。
  8. 根据权利要求7所述的功率控制电路，其中，
    所述第五NMOS管的阈值电压与所述第四NMOS管的阈值电压相等；
    所述第五NMOS管工作在弱反型区。
  9. 根据权利要求7所述的功率控制电路，其中，
    当所述第四NMOS管的漏极电压等于栅极电压减去阈值电压，则所述第四NMOS管工作在饱和区。
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CN114337619A (zh) * 2022-01-12 2022-04-12 电子科技大学 一种消除误翻转的反流比较器
CN116073656A (zh) * 2023-02-17 2023-05-05 无锡麟聚半导体科技有限公司 一种电流调节电路及芯片
CN116073656B (zh) * 2023-02-17 2024-04-09 无锡麟聚半导体科技有限公司 一种电流调节电路及芯片
CN117097310A (zh) * 2023-10-11 2023-11-21 芯睿微电子(昆山)有限公司 具有下电快速稳定电路的器件及下电快速稳定电路
CN117097310B (zh) * 2023-10-11 2024-03-15 芯睿微电子(昆山)有限公司 具有下电快速稳定电路的器件及下电快速稳定电路

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