WO2022179174A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2022179174A1
WO2022179174A1 PCT/CN2021/129190 CN2021129190W WO2022179174A1 WO 2022179174 A1 WO2022179174 A1 WO 2022179174A1 CN 2021129190 W CN2021129190 W CN 2021129190W WO 2022179174 A1 WO2022179174 A1 WO 2022179174A1
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Prior art keywords
connection
segment
array substrate
signal lines
pixel circuit
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PCT/CN2021/129190
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English (en)
French (fr)
Inventor
冯宏庆
李洪瑞
曾祥韬
秦韶阳
赵成雨
王守坤
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合肥维信诺科技有限公司
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Application filed by 合肥维信诺科技有限公司 filed Critical 合肥维信诺科技有限公司
Priority to KR1020237021154A priority Critical patent/KR20230104986A/ko
Publication of WO2022179174A1 publication Critical patent/WO2022179174A1/zh
Priority to US18/337,601 priority patent/US20230337492A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.
  • a notch or hole can be formed on the display screen, and external light can enter the photosensitive component located below the screen through the notch or hole on the screen. Since the signal lines around the slot or opening need to be connected one by one, it is necessary to set a larger wiring space around the slot or opening, which affects the screen ratio of the display screen.
  • Embodiments of the present application provide an array substrate, a display panel, and a display device, which can increase the screen ratio of the display area and improve the display effect.
  • an embodiment of the present application provides an array substrate having a hole area and a display area, the display area includes a wire-wound display area and a main display area, the wire-wound display area is located between the hole area and the main display area, and the wire-wound display area is located between the hole area and the main display area.
  • the display area surrounds the hole area;
  • the array substrate includes: a first pixel circuit, a plurality of first pixel circuit arrays are distributed in the winding display area; a second pixel circuit, a plurality of second pixel circuit arrays are distributed in the main display area; a signal line, each first signal line is electrically connected to the first pixel circuit and the second pixel circuit and extends along the first direction, the plurality of first signal lines includes a plurality of first type signal lines and a plurality of second type signal lines , each second type of signal line includes a first section and a second section separated by a hole area; a plurality of first connection signal lines, at least part of the plurality of first connection signal lines is located in the winding display area, the first connection signal line
  • the wire includes a first connection segment, a second connection segment and a third connection segment that are connected to each other, the first connection segment is electrically connected to the first segment, the third connection segment is electrically connected to the second segment, and the second connection segment is connected to the
  • connection segment and the third connection segment both extend along the second direction, and the second connection segment extends along the first direction; wherein, the positive direction of the first pixel circuit on the plane where the array substrate is located.
  • the projected area is smaller than the orthographic projection area of the second pixel circuit on the plane of the array substrate, and the orthographic projection of the first connection signal line on the plane of the array substrate does not overlap with the orthographic projection of the first pixel circuit on the plane of the array substrate .
  • an embodiment of the present application provides a display panel, including the array substrate according to any embodiment of the first aspect.
  • an embodiment of the present application provides a display device, including the display panel described in the second aspect.
  • the array substrate, the display panel, and the display device provided by the embodiments of the present application, on the one hand, since at least part of the first connection signal lines are also arranged in the winding display area, the number of first connection signal lines arranged in the frame of the hole area can be reduced. Even if the first connection signal line is not arranged on the frame of the hole area, the frame area of the hole area can be reduced and the screen ratio of the array substrate can be improved.
  • the orthographic projection of the first connection signal line on the plane where the array substrate is located does not overlap with the orthographic projection of the first pixel circuit on the plane where the array substrate is located, thereby reducing the number of first pixel circuits.
  • the possibility of forming a parasitic capacitance between the connecting signal line and the first pixel circuit can reduce the coupling effect between the first connecting signal line and the first pixel circuit, and improve the display effect.
  • FIG. 1 shows a schematic top view of an array substrate provided by an embodiment of the present application
  • Fig. 2 shows a kind of enlarged schematic diagram of Q1 area in Fig. 1;
  • FIG. 3 shows a schematic structural diagram of a first pixel circuit and a first pixel circuit provided by an embodiment of the present application
  • Fig. 4 shows a kind of sectional schematic diagram of AA in Fig. 2;
  • Fig. 5 shows another schematic cross-sectional view along A-A in Fig. 2;
  • FIG. 6 shows another schematic top view of the array substrate provided by the embodiment of the present application.
  • Fig. 7 shows a kind of enlarged schematic diagram of Q2 area in Fig. 6;
  • Fig. 8 shows another enlarged schematic diagram of the Q1 region in Fig. 1;
  • Fig. 9 shows a schematic sectional view of the direction B-B in Fig. 8.
  • FIG. 10 shows a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 shows a schematic top view of an array substrate provided by an embodiment of the present application.
  • FIG. 2 shows an enlarged schematic view of the Q region in FIG. 1 .
  • an embodiment of the present application provides an array substrate 100 having a hole area Hole and a display area AA surrounding the hole area Hole.
  • the display area AA includes a winding display area A1 and a main display area A2, the winding display area A1 is located between the hole area Hole and the main display area A2, and the winding display area A1 surrounds the hole area Hole.
  • the hole area may also be referred to as an opening area, a slot area, a blind hole area, a through hole area, etc., which is not limited in this application.
  • Hole area can be used to place photosensitive components.
  • the photosensitive component may be an image acquisition device for acquiring external image information.
  • the photosensitive component is a camera and the like.
  • the photosensitive component may not be limited to an image acquisition device.
  • the photosensitive component may also be an infrared sensor, a proximity sensor, an infrared lens, a flood light sensing element, an ambient light sensor, and a light sensor such as a dot matrix projector.
  • the hole area can be a rectangular area, a circular area, an oval area, or a square area, etc.
  • the shape of the hole area can be set according to actual requirements, which is not limited in this application.
  • the winding display area A1 is used to place windings, such as the windings of data signal lines, scanning signal lines, light-emitting control signal lines, and the like.
  • the hole area Hole is a non-display area.
  • the winding display area A1 is a display area.
  • the array substrate 100 includes a first pixel circuit PU1 , a second pixel circuit PU2 , a first signal line 10 and a first connection signal line 20 .
  • a plurality of first pixel circuits PU1 arrays are distributed in the winding display area A1.
  • a plurality of second pixel circuits PU2 are arrayed in the main display area A2.
  • the first pixel circuit PU1 and the second pixel circuit PU2 are used to drive the light-emitting element to emit light.
  • the orthographic projection area of the first pixel circuit PU1 on the plane where the array substrate 100 is located is smaller than the orthographic projection area of the second pixel circuit PU2 on the plane where the array substrate 100 is located. That is, with respect to the second pixel circuit PU2, the area of the first pixel circuit PU1 is compressed.
  • the density of the pixel circuits on the array substrate 100 is also relatively high.
  • the pixel circuits on the entire array substrate are arranged next to each other, that is, there is not enough space between adjacent pixel circuits to place signal lines. .
  • each of the second pixel circuits PU2 is disposed next to each other, and there is not enough space between adjacent second pixel circuits PU2 to place signal lines.
  • the orthographic projection area of the first pixel circuit PU1 on the plane where the array substrate 100 is located is smaller than the orthographic projection area of the second pixel circuit PU2 on the plane where the array substrate 100 is located, at least part of the first pixel circuit PU1 They are not arranged in close proximity, that is to say, the gap between at least a part of the first pixel circuits PU1 is increased, and the increased gap can be used to set the signal wiring.
  • Each of the first signal lines 10 is electrically connected to both the first pixel circuit PU1 and the second pixel circuit PU2 and extends along the first direction X. It can be understood that the plurality of first signal lines 10 are all located in the display area AA.
  • the plurality of first signal lines 10 include a plurality of first type signal lines 11 and a plurality of second type signal lines 12 .
  • Each of the first type of signal lines 11 extends along the first direction X.
  • Each of the second type signal lines 12 includes a first segment 121 and a second segment 122 which are separated by the hole region Hole and extend along the first direction X. As shown in FIG.
  • the orthographic projection of the first signal line 10 on the plane of the array substrate may overlap with the orthographic projection of the first pixel circuit PU1 and the second pixel circuit PU2 on the plane of the array substrate.
  • each of the first type of signal lines 11 is a continuous trace, and each of the first type of signal lines 11 is not separated by the hole area.
  • the first connection signal line 20 may be used to connect the separated first segment 121 and the second segment 122 .
  • Each first connection signal line 20 includes a first connection segment 21 , a second connection segment 22 and a third connection segment 23 connected to each other, and the second connection segment 22 is connected between the first connection segment 21 and the third connection segment 23 ,
  • the first connecting segment 21 is electrically connected to the first segment 121 (the black dots in the figure indicate that the first connecting segment 21 is connected to the first segment 121 )
  • the third connecting segment 23 is electrically connected to the second segment 122 (the black dots in the figure indicate that the first connecting segment 21 is connected to the second segment 122 ).
  • the dots indicate that the third connection segment 23 is connected to the second segment 122 ), and both the first connection segment 21 and the third connection segment 23 extend along the second direction Y.
  • the second connecting segment 22 extends along the first direction X.
  • the second connection segment 22 is represented by a dotted line in the figure.
  • the orthographic projection of the first connection signal line 20 on the plane where the array substrate 100 is located does not overlap with the orthographic projection of the first pixel circuit PU1 on the plane where the array substrate 100 is located.
  • the orthographic projection area of the first pixel circuit PU1 on the plane where the array substrate 100 is located to be smaller than the orthographic projection area of the second pixel circuit PU2 on the plane where the array substrate 100 is located, at least part of the first pixel
  • the circuits PU1 are not arranged next to each other, that is to say, the gaps between at least part of the first pixel circuits PU1 are increased, so that the first connection signal lines 20 are arranged in the increased gaps.
  • the number of the first connection signal lines 20 arranged on the border of the hole area can be reduced, and even the number of first connection signal lines 20 can be reduced.
  • the first connection signal line 20 is not disposed on the frame of the hole area, so the frame area of the hole area can be reduced, and the screen ratio of the array substrate can be increased.
  • the orthographic projection of the first connection signal line 20 on the plane of the array substrate 100 and the orthographic projection of the first pixel circuit PU1 on the plane of the array substrate 100 do not overlap , reducing the possibility of parasitic capacitance formed between the first connection signal line 20 and the first pixel circuit PU1 , which can weaken the coupling effect between the first connection signal line 20 and the first pixel circuit PU1 and improve the display effect.
  • the first direction X and the second direction Y intersect.
  • the first direction X and the second direction Y may be perpendicular.
  • the first direction X may be a column direction
  • the second direction Y may be a row direction
  • the first signal line 10 may be a data signal line.
  • the first direction X may be the row direction
  • the second direction Y may be the column direction
  • the first signal line 10 may be a scan signal line, a light-emitting control signal line, or a reference voltage signal line. This application does not limit this.
  • the circuit structure of the first pixel circuit PU1 is the same as the circuit structure of the second pixel circuit PU2, and both the first pixel circuit PU1 and the second pixel circuit PU2 include transistors.
  • the size of at least one of the transistors is smaller than the size of the transistors at the same connection position in the second pixel circuit PU2.
  • the circuit structures of the first pixel circuit PU1 and the second pixel circuit PU2 are both the circuit structures of 7T1C as shown in FIG. 3 .
  • the circuit structures of the first pixel circuit PU1 and the second pixel circuit PU2 may also be 2T1C, 4T1C, 6T1C, 6T2C, 7T2C, etc., which are not limited in this application.
  • T means transistor
  • C means capacitor
  • 7T1C means having 7 transistors and 1 capacitor, and so on.
  • the first pixel circuit PU1 and the second pixel circuit PU2 each include a first light-emitting control transistor M1, a data writing transistor M2, a driving transistor M3, a compensation transistor M4, a first initialization transistor M5, and a second light-emitting control transistor M1.
  • the connection relationship of each element is shown in FIG. 3 , which will not be repeated here.
  • PVDD and PVEE represent power signal lines. Exemplarily, the voltage on the PVDD signal line is greater than the voltage on the PVEE signal line.
  • VDATA represents a data signal line
  • SCAN1, SCAN2 and SCAN3 represent a scan signal line
  • EM represents a light emission control signal line
  • D represents a light emitting element.
  • any one of the first pixel circuits PU1 can be The size of the transistors is set to be smaller than the size of the transistors in the same connection position in the second pixel circuit PU2, and the sizes of the remaining transistors in the first pixel circuit PU1 and the second pixel circuit PU2 may be equal.
  • the size of the first light emission control transistor M1 in the first pixel circuit PU1 may be set smaller than the size of the first light emission control transistor M1 in the second pixel circuit PU2.
  • the size of the transistors in the first pixel circuit PU1 can also be set to be smaller than the size of the transistors at the same connection position in the second pixel circuit PU2, or the size of all the transistors in the first pixel circuit PU1 and the size of the storage capacitor can be set It is set to be smaller than the size of the transistor at the same connection position and the storage capacitor at the same connection position in the second pixel circuit PU2.
  • the application does not limit the selection of specific transistors in the first pixel circuit PU1, as long as the orthographic projection area of the first pixel circuit PU1 on the plane where the array substrate 100 is located is smaller than that of the second pixel circuit PU2 on the plane where the array substrate 100 is located Orthographic projection area.
  • the first pixel circuit PU1 by setting the transistors in the first pixel circuit PU1 as small-sized transistors, the first pixel circuit PU1 with a small orthographic projection area can be simply and conveniently implemented, so that there is a space between adjacent first pixel circuits PU1. Enough space to set up signal traces.
  • the line width of the first signal lines 10 in the line display area A1 is smaller than the line width of the first signal lines 10 in the main display area A2, and the line spacing of the adjacent first signal lines 10 in the winding display area A1 is smaller than that of the main display area A1.
  • the first signal line 10 can be multiplexed as the gate electrode or the source/drain electrode of the transistors in the first pixel circuit PU1 and the second pixel circuit PU2. Still taking the circuit structure of the first pixel circuit PU1 and the second pixel circuit PU2 as 7T1C shown in FIG. 3 as an example, the first electrode of the data writing transistor M2 is electrically connected to the data signal line VDATA, and the first signal line 10 is used as an example.
  • the part of the first signal line 10 connected to the semiconductor layer of the data writing transistor M2 is multiplexed as the first pole of the data writing transistor M2, and the first pole of the data writing transistor M2 is source/drain .
  • the first signal line 10 is the scan signal line SCAN1, and the overlapping portion of the first signal line 10 and the semiconductor layer of the first initialization transistor M5 is multiplexed as the gate of the first initialization transistor M5.
  • the first signal line 10 is the light-emitting control signal line EM
  • the overlapping portion of the first signal line 10 and the semiconductor layers of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 is multiplexed into the first light-emitting control transistor M1 and the gate of the second light-emitting control transistor M6. Therefore, reducing the line width and line spacing of the first signal lines 10 in the winding display area A1 is equivalent to reducing the size of the transistors in the first pixel circuit PU1.
  • the size of the transistors in the first pixel circuit PU1 can be reduced simply and conveniently, so that adjacent first pixels There is enough space between circuits PU1 to set up signal traces.
  • the hole area Hole has a center line L in the second direction Y, and the vertical distance between the second type signal line 12 and the center line L in the second direction Y is smaller.
  • the smaller the vertical distance between the second connection segment 22 electrically connected to the second type signal line 12 and the center line L in the second direction, and the vertical distance between the second type signal line 12 and the center line L in the second direction Y The smaller the distance is, the smaller the vertical distance in the second direction Y between the first connection segment 21 and the third connection segment 23 electrically connected to the second type of signal line 12 and the center line L is.
  • the innermost second type signal line 12 and the outermost second type signal line 12 among the plurality of second type signal lines 12 facing the hole area Take the innermost second type signal line 12 and the outermost second type signal line 12 among the plurality of second type signal lines 12 facing the hole area as an example, wherein the plurality of second type signal lines 12 facing the hole area Hole are Among the two types of signal lines 12, the innermost second type signal line 12 has the smallest vertical distance from the center line L in the second direction Y, and the outermost one of the plurality of second type signal lines 12 facing the hole area is the smallest. The vertical distance between the second type of signal line 12 and the center line L in the second direction Y is the largest.
  • the second connection segment 22 corresponding to the innermost second type signal line 12 is disposed at the innermost side, and the first connection segment 21 and the third connection segment 23 corresponding to the innermost second type signal line 12 are arranged at the outermost side.
  • the second connection segment 22 corresponding to the outermost second type signal line 12 is arranged at the outermost side, and the first connection segment 21 and the third connection segment 23 corresponding to the outermost second type signal line 12 are arranged at the innermost side.
  • first connection segment 21 and the third connection segment 23 of the same first connection signal line 20 are the same.
  • the above arrangement can make the length of the second connection segment 22 corresponding to the innermost second type signal line 12 greater than the length of the second connection segment 22 corresponding to the outermost second type signal line 12, and the innermost second type signal line 12.
  • the lengths of the first connection segment 21 and the third connection segment 23 corresponding to the signal line 12 are smaller than the lengths of the first connection segment 21 and the third connection segment 23 corresponding to the outermost second type signal line 12, so that the innermost
  • the total lengths of the second type signal lines 12 and the first connecting signal lines 20 corresponding to the outermost second type signal lines 12 tend to be the same, so that the resistances of the first connecting signal lines 20 tend to be the same.
  • the voltage drop of the connecting signal lines 20 tends to be consistent, which is beneficial to display uniformity.
  • the first connection signal lines 20 may be uniformly distributed in the winding display area A1.
  • the line spacings between the second connection segments 22 are the same.
  • the line spacings between the first connecting segments 21 are the same, and the line spacings between the third connecting segments 23 are the same.
  • the plurality of second connecting segments 22 may be evenly distributed on both sides of the hole area in the second direction Y. As shown in FIG.
  • the number of the first pixel circuits PU1 arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is equal, so that the first pixel circuit PU1 is equal in number.
  • the line spacings of the two connecting segments 22 in the second direction Y are the same.
  • the number of the first pixel circuits PU1 arranged along the first direction X in the interval between adjacent first connection segments 21 is equal, so that the line spacings of the first connection segments 21 in the first direction X are the same.
  • the number of the first pixel circuits PU1 arranged along the first direction X in the interval between adjacent third connection segments 23 is equal, so that the line spacings of the third connection segments 23 in the first direction X are the same.
  • the number of first pixel circuits PU1 arranged along the first direction X in the interval between adjacent first connection segments 21 and the arrangement along the first direction X in the interval between adjacent third connection segments 23 The number of the first pixel circuits PU1 is equal, so that the line spacing of the first connection segment 21 in the first direction X is the same as the line spacing of the third connection segment 23 in the first direction X.
  • the number of the first pixel circuits PU1 arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is equal to the number of the first pixel circuits PU1 between the adjacent first connection segments 21 .
  • the number of the first pixel circuits PU1 arranged along the first direction X within the interval is twice the number.
  • first pixel circuits PU1 arranged along the first direction X in the interval between adjacent first connection segments 21 and the arrangement along the first direction X in the interval between adjacent third connection segments 23 The number of the first pixel circuits PU1 is equal, therefore, the number of the first pixel circuits PU1 arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is also equal to The number of the first pixel circuits PU1 arranged along the first direction X in the interval between the adjacent third connection segments 23 is twice the number.
  • the number of the first pixel circuits PU1 arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is two, and the number of adjacent first pixel circuits PU1 is two.
  • the number of the first pixel circuits PU1 arranged along the first direction X in the interval between one connection segment 21 is one, and the number of the first pixel circuits PU1 arranged along the first direction X in the interval between adjacent third connection segments 23 is one.
  • the number of one pixel circuit PU1 is one.
  • the length of the second connection segment 22 closer to the center line L than the distance from the center line L is approximately two longer than the length of the first pixel circuit PU1 , and the length of the first connecting segment 21 that is closer to the center line L is longer than that of the first connecting segment 21 that is farther from the center line L
  • the length of the first pixel circuit PU1 is approximately one less than the length of the first pixel circuit PU1
  • the length of the third connection segment 23 closer to the center line L is approximately one shorter than the length of the third connection segment 23 farther from the center line L.
  • the length of the first pixel circuit PU1 Therefore, it is further ensured that the total lengths of the two first connection signal lines 20 corresponding to two adjacent second type signal lines 12 located on the same side of the hole center line L are equal.
  • the number of the first pixel circuits PU1 arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is only an example, and they are located on the same side of the hole area.
  • the number of the first pixel circuits PU1 arranged along the second direction Y in the interval between the adjacent second connection segments 22 may be four, six, eight, etc., which is not limited in this application. It can be understood that the number of the first pixel circuits PU1 arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is an even number.
  • a plurality of first pixel circuits PU1 arranged along the second direction Y within the interval between adjacent second connection segments 22 may be arranged next to each other. In this way, when the size of the first pixel circuits PU1 is fixed, the gap between the adjacent first pixel circuits PU1 can be increased; when the line width of the first connection signal line 20 is fixed, it is not necessary to In the case where the size of a pixel circuit PU1 is set too small, it can also be ensured that the first connection signal line 20 can be placed in the gap between the adjacent first pixel circuits PU1.
  • the second connection segment 22 and the first signal line 10 may be disposed in the same layer and material, and the first connection segment 21 and the third connection segment 23 and the first signal line 10 are located in different films Floor. In this way, the second connection segment 22 and the first signal line 10 can be simultaneously formed in the same process step, while the extension directions of the first connection segment 21 and the third connection segment 23 and the first signal line 10 intersect, and the first connection The segment 21 and the third connection segment 23 are disposed in a different film layer from the first signal line 10 , which can avoid signal interference between the first connection signal line 20 and the first signal line 10 .
  • the first signal line 10 is a data signal line.
  • the array substrate 100 may include a substrate 01 and a first conductive layer 02 , a second conductive layer 03 , a third conductive layer 04 and a fourth conductive layer 05 disposed on one side of the substrate 01 and stacked.
  • An insulating layer is disposed between adjacent conductive layers.
  • the first pixel circuit PU1 includes a transistor T and a storage capacitor Cst.
  • the transistor T includes a semiconductor b, a gate g, a source s and a drain d.
  • the storage capacitor Cst includes a first electrode plate c1 and a second electrode plate c2.
  • the gate g and the first electrode plate c1 may be located on the first conductive layer 02
  • the second electrode plate c2 may be located on the second conductive layer 03
  • the source electrode s, the drain electrode d the first signal line 10 and the second electrode
  • the connection segment 22 may be located in the third conductive layer 04
  • the first connection segment 21 and the third connection segment 23 may both be located in the fourth conductive layer 05 .
  • the first connection segment 21 and the third connection segment 23 can be connected to the second connection segment 22 through via holes.
  • the first connection segment 21 , the second connection segment 22 and the third connection segment 23 are all located at different film layers from the first signal line 10 , and the first connection segment 21 and the second connection segment 22 and the third connecting segment 23 are located in the same film layer. In this way, the first connection segment 21 , the second connection segment 22 and the third connection segment 23 can be simultaneously formed in the same process step, and signal interference between the first connection signal line 20 and the first signal line 10 can be avoided.
  • the first signal line 10 is a data signal line. As shown in FIG. 5 , the first signal line 10 may be located in the third conductive layer 04 , and the first connection segment 21 , the second connection segment 22 and the third connection segment 23 may all be located in the fourth conductive layer 05 . The first connection segment 21 and the third connection segment 23 may be connected to the first signal line 10 through via holes.
  • the first direction X may be a column direction
  • the second direction Y may be a row direction
  • the first signal line 10 may be a data signal line.
  • the first direction X may be a row direction
  • the second direction Y may be a column direction
  • the first signal line 10 may be a scanning signal line or a light-emitting control line Signal line or reference voltage signal line.
  • the first direction X is the column direction
  • the second direction Y is the row direction
  • the first signal line 10 is a data signal line
  • the array substrate 100 further includes a plurality of A second signal line 30 and a plurality of second connection signal lines 40 are provided.
  • the second signal line 30 is a scan signal line, a light-emitting control signal line, or a reference voltage signal line.
  • Each of the second signal lines 30 is electrically connected to the first pixel circuit PU1 and the second pixel circuit PU2 and extends along the second direction Y. It can be understood that the plurality of second signal lines 30 are all located in the display area AA.
  • the plurality of second signal lines 30 include a plurality of third-type signal lines 31 and a plurality of fourth-type signal lines 32 , and each fourth-type signal line 32 includes a third segment 321 and a fourth segment 322 separated by a hole area.
  • the orthographic projection of the second signal line 30 on the plane where the array substrate is located may overlap with the orthographic projections of the first pixel circuit and the second pixel circuit on the plane where the array substrate is located.
  • each third type signal line 31 is a continuous wiring, and each third type signal line 31 is not separated by the hole area.
  • the separated third segment 321 and the fourth segment 322 may be connected by the second connection signal line 40 .
  • Each second connection signal line 40 includes a fourth connection segment 44, a fifth connection segment 45 and a sixth connection segment 46 that are connected to each other.
  • the fourth connection segment 44 is electrically connected to the third segment 321 (the black circles in the figure indicate the first
  • the sixth connecting segment 46 is electrically connected to the fourth segment 322 (the black circles in the figure indicate that the sixth connecting segment 46 is connected to the fourth segment 32)
  • the fifth connecting segment 45 Connected between the fourth connection segment 44 and the sixth connection segment 46 , the fourth connection segment 44 and the sixth connection segment 46 both extend along the first direction X
  • the fifth connection segment 45 extends along the second direction Y.
  • the fifth connection segment 45 is indicated by a dotted line in the figure.
  • the orthographic projection of the second connection signal line 40 on the plane of the array substrate does not overlap with the orthographic projection of the first pixel circuit PU1 on the plane of the array substrate.
  • the orthographic projection area of the first pixel circuit PU1 on the plane where the array substrate 100 is located to be smaller than the orthographic projection area of the second pixel circuit PU2 on the plane where the array substrate 100 is located, at least part of the first pixel
  • the circuits PU1 are not arranged next to each other, that is to say, the gap between at least part of the first pixel circuits PU1 is increased, so that the first connection signal line 20 and the second connection signal line 40 are arranged in the enlarged gap.
  • the orthographic projections of the first connecting signal line 20 and the second connecting signal line 40 on the plane where the array substrate 100 is located are the same as the first pixel circuit PU1 on the array substrate.
  • the orthographic projections on the plane where 100 is located do not overlap, which reduces the possibility of parasitic capacitances being formed between the first connection signal line 20 and the second connection signal line 40 and the first pixel circuit PU1, which can weaken the first connection signal line 20 and the coupling effect between the second connection signal line 40 and the first pixel circuit PU1, so as to improve the display effect.
  • the second connection signal line 40 can be set according to the setting method of the first connection signal line 20 in the above-mentioned embodiment, which will not be repeated here.
  • the array substrate 100 may further include a fifth conductive layer 06 .
  • An insulating layer is disposed between adjacent conductive layers.
  • the first signal line 10 and the second connection segment 22 may be located in the third conductive layer 04, the first connection segment 21 and the third connection segment 23 (not shown in FIG. 9) may both be located in the fourth conductive layer 05, and the second signal
  • the line 30 may be located at the first conductive layer 02 , and the fourth connection segment 44 , the fifth connection segment 45 (not shown in FIG. 9 ), and the sixth connection segment 46 may all be located at the fifth conductive layer 06 .
  • FIG. 10 shows a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 200 includes the array substrate 100 described in any of the above embodiments and a light-emitting layer 201 on the array substrate 100 .
  • the light-emitting layer 201 may be an organic light-emitting layer, that is, the display panel 200 may be an organic light-emitting diode (Organic Light Emitting Diode, OLED) display panel.
  • OLED Organic Light Emitting Diode
  • the problem-solving principle of the display panel is similar to that of the aforementioned array substrate. Therefore, the implementation of the display panel can refer to the aforementioned implementation of the array substrate, and the repetition will not be repeated here.
  • Embodiments of the present application further provide a display device, including the display panel 200 described in the foregoing embodiments.
  • the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book, or a television.

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Abstract

本申请公开了一种阵列基板、显示面板及显示装置。该阵列基板包括：第一像素电路，第二像素电路；多条第一信号线，多条第一信号线包括多条第一类信号线和多条第二类信号线，各第二类信号线包括被孔区分隔的第一段和第二段；多条第一连接信号线，多条第一连接信号线中的至少部分位于绕线显示区，第一连接段和第三连接段均沿第二方向延伸，第二连接段沿第一方向延伸；其中，第一像素电路在阵列基板所在平面上的正投影面积小于第二像素电路在阵列基板所在平面上的正投影面积，且第一连接信号线在阵列基板所在平面上的正投影与第一像素电路在阵列基板所在平面上的正投影无交叠。根据本申请实施例，能够提高显示区的屏占比，且能够改善显示效果。

Description

阵列基板、显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板、显示面板及显示装置。
相关申请的交叉引用
本申请要求享有于2021年02月24日提交的名称为“阵列基板、显示面板及显示装置”的中国专利申请第202110206169.2号的优先权，该申请的全部内容通过引用并入本文中。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，传统的电子设备如手机、平板电脑等，由于需要集成诸如前置摄像头、听筒以及红外感应元件等。现有技术中，可通过在显示屏上开槽(Notch)或开孔，外界光线可通过屏幕上的开槽或开孔进入位于屏幕下方的感光组件。由于开槽或开孔周围的信号线需要一一对应连接起来，需要在开槽或开孔周围设置较大的布线空间，影响显示屏的屏占比。
发明内容
本申请实施例提供了一种阵列基板、显示面板及显示装置，能够提高显示区的屏占比，且能够改善显示效果。
第一方面，本申请实施例提供一种阵列基板，具有孔区和显示区，显示区包括绕线显示区和主显示区，绕线显示区位于孔区和主显示区之间，且绕线显示区围绕孔区；阵列基板包括：第一像素电路，多个第一像素电路阵列分布于绕线显示区；第二像素电路，多个第二像素电路阵列分布于主显示区；多条第一信号线，各第一信号线与第一像素电路及第二像素电 路电连接且沿第一方向延伸，多条第一信号线包括多条第一类信号线和多条第二类信号线，各第二类信号线包括被孔区分隔的第一段和第二段；多条第一连接信号线，多条第一连接信号线中的至少部分位于绕线显示区，第一连接信号线包括相互连接的第一连接段、第二连接段和第三连接段，第一连接段与第一段电连接，第三连接段与第二段电连接，第二连接段连接在第一连接段与第三连接段之间，第一连接段和第三连接段均沿第二方向延伸，第二连接段沿第一方向延伸；其中，第一像素电路在阵列基板所在平面上的正投影面积小于第二像素电路在阵列基板所在平面上的正投影面积，且第一连接信号线在阵列基板所在平面上的正投影与第一像素电路在阵列基板所在平面上的正投影无交叠。
第二方面，本申请实施例提供一种显示面板，包括如第一方面任一实施例所述的阵列基板。
第三方面，本申请实施例提供一种显示装置，包括如第二方面所述的显示面板。
根据本申请实施例提供的阵列基板、显示面板及显示装置，一方面，由于将至少部分第一连接信号线也设置于绕线显示区，可以减少在孔区的边框设置的第一连接信号线的条数，甚至可以不在孔区的边框设置第一连接信号线，因此可以减小孔区的边框面积，提高阵列基板的屏占比。另一方面，通过压缩第一像素电路的面积，使第一连接信号线在阵列基板所在平面上的正投影与第一像素电路在阵列基板所在平面上的正投影无交叠，减小了第一连接信号线与第一像素电路之间形成寄生电容的可能性，能够减弱第一连接信号线与第一像素电路之间的耦合效应，改善显示效果。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1示出本申请实施例提供的阵列基板的一种俯视示意图；
图2示出图1中Q1区域的一种放大示意图；
图3示出本申请实施例提供的第一像素电路和第一像素电路的一种结构示意图；
图4示出图2中AA向的一种剖面示意图；
图5示出图2中A-A向的另一种剖面示意图；
图6示出本申请实施例提供的阵列基板的另一种俯视示意图；
图7示出图6中Q2区域的一种放大示意图；
图8示出图1中Q1区域的另一种放大示意图；
图9示出图8中B-B向的一种剖面示意图；
图10示出本申请实施例提供的显示面板的一种结构示意图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
图1示出本申请实施例提供的一种阵列基板的俯视示意图。图2示出图1中Q区域的一种放大示意图。如图1及图2所示，本申请实施例提供一种阵列基板100，具有孔区Hole及围绕孔区Hole的显示区AA。显示区AA包括绕线显示区A1和主显示区A2，绕线显示区A1位于孔区Hole和主显示区A2之间，且绕线显示区A1围绕孔区Hole。
示例性的，孔区Hole也可以称为开孔区、开槽区、盲孔区、通孔区等，本申请对此不作限定。孔区Hole可以用于放置感光组件。感光组件可以是图像采集装置，用于采集外部图像信息。例如感光组件为摄像头等。感光组件可以不限于是图像采集装置，例如在一些实施例中，感光组件也可以是红外传感器、接近传感器、红外镜头、泛光感应元件、环境光传感器以及点阵投影器等光传感器。
孔区Hole可以为矩形区域、圆形区域、椭圆形区域或者方形区域等， 可以根据实际需求设置孔Hole的形状，本申请对此不作限定。
绕线显示区A1用于放置绕线，如数据信号线、扫描信号线、发光控制信号线等的绕线。
可以理解的是，孔区Hole为非显示区。绕线显示区A1为显示区。
如图1和图2所示，阵列基板100包括第一像素电路PU1、第二像素电路PU2、第一信号线10及第一连接信号线20。
多个第一像素电路PU1阵列分布于绕线显示区A1。多个第二像素电路PU2阵列分布于主显示区A2。示例性的，第一像素电路PU1及第二像素电路PU2用于驱动发光元件发光。
第一像素电路PU1在阵列基板100所在平面上的正投影面积小于第二像素电路PU2在阵列基板100所在平面上的正投影面积。也就是说，相对于第二像素电路PU2，压缩了第一像素电路PU1的面积。为了提高显示面板的像素密度，阵列基板100上像素电路的密度也比较高，通常整个阵列基板上的各像素电路都是紧邻设置的，即相邻像素电路之间没有足够的空间放置信号走线。示例性的，各第二像素电路PU2均紧邻设置，相邻第二像素电路PU2之间没有足够的空间放置信号走线。而本申请实施例中，由于第一像素电路PU1在阵列基板100所在平面上的正投影面积小于第二像素电路PU2在阵列基板100所在平面上的正投影面积，因此至少部分第一像素电路PU1之间不是紧邻设置的，也就是说至少部分第一像素电路PU1之间的空隙增大，该增大的空隙可以用来设置信号走线。
各第一信号线10与第一像素电路PU1及第二像素电路PU2均电连接且沿第一方向X延伸。可以理解的是，多条第一信号线10均位于显示区AA。多条第一信号线10包括多条第一类信号线11和多条第二类信号线12。各第一类信号线11均沿第一方向X延伸。各第二类信号线12包括被孔区Hole分隔的且沿第一方向X延伸的第一段121和第二段122。
示例性的，第一信号线10在阵列基板所在平面上的正投影可以与第一像素电路PU1及第二像素电路PU2在阵列基板所在平面上的正投影交叠。
可以理解的是，各第一类信号线11为连续性走线，各第一类信号线11未被孔区Hole分隔开。
为了能够为同一条第二类信号线12所电连接的像素驱动电路提供信号，可以利用第一连接信号线20将分隔开的第一段121和第二段122连接起来。
多条第一连接信号线20中的至少部分位于绕线显示区A1。各第一连接信号线20包括相互连接的第一连接段21、第二连接段22和第三连接段23，第二连接段22连接在第一连接段21与第三连接段23之间，第一连接段21与第一段121电连接(图中以黑色圆点示意第一连接段21与第一段121连接)，第三连接段23与第二段122电连接(图中以黑色圆点示意第三连接段23与第二段122连接)，第一连接段21和第三连接段23均沿第二方向Y延伸。第二连接段22沿第一方向X延伸。为了清楚的区分出第一信号线10与第二连接段22，图中以虚线示意第二连接段22。
第一连接信号线20在阵列基板100所在平面上的正投影与第一像素电路PU1在阵列基板100所在平面上的正投影无交叠。本申请实施例中，通过将第一像素电路PU1在阵列基板100所在平面上的正投影面积设置为小于第二像素电路PU2在阵列基板100所在平面上的正投影面积，使得至少部分第一像素电路PU1之间不是紧邻设置的，也就是说使得至少部分第一像素电路PU1之间的空隙增大，从而在增大的空隙内设置第一连接信号线20。
本申请实施例中，一方面，由于将至少部分第一连接信号线20也设置于绕线显示区AA，可以减少在孔区Hole的边框设置的第一连接信号线20的条数，甚至可以不在孔区Hole的边框设置第一连接信号线20，因此可以减小孔区Hole的边框面积，提高阵列基板的屏占比。另一方面，通过压缩第一像素电路PU1的面积，使第一连接信号线20在阵列基板100所在平面上的正投影与第一像素电路PU1在阵列基板100所在平面上的正投影无交叠，减小了第一连接信号线20与第一像素电路PU1之间形成寄生电容的可能性，能够减弱第一连接信号线20与第一像素电路PU1之间的耦合效应，改善显示效果。
示例性的，第一方向X和第二方向Y相交。第一方向X和第二方向Y可以垂直。例如，第一方向X可以是列方向，第二方向Y是行方向，第一信号线10可以是数据信号线。又例如，第一方向X可以是行方向，第二方 向Y是列方向，第一信号线10可以是扫描信号线或发光控制信号线或参考电压信号线。本申请对此不作限定。
在一些可选的实施例中，第一像素电路PU1的电路结构与第二像素电路PU2的电路结构相同，且第一像素电路PU1及第二像素电路PU2均包括晶体管，第一像素电路PU1中至少一个晶体管的尺寸小于第二像素电路PU2中相同连接位置的晶体管的尺寸。
示例性的，第一像素电路PU1及第二像素电路PU2的电路结构均是如图3所示的7T1C的电路结构。当然，第一像素电路PU1及第二像素电路PU2的电路结构也可以都是2T1C、4T1C、6T1C、6T2C、7T2C等，本申请对此不作限定。其中，“T”表示晶体管，“C”表示电容，“7T1C”表示具有7个晶体管和1个电容，其他以此类推。
如图3所示，第一像素电路PU1及第二像素电路PU2均包括第一发光控制晶体管M1、数据写入晶体管M2、驱动晶体管M3、补偿晶体管M4、第一初始化晶体管M5、第二发光控制晶体管M6、第二初始化晶体管M7及存储电容Cst。各元件的连接关系如图3所示，在此不再赘述。图3中，PVDD及PVEE表示电源信号线，示例性的，PVDD信号线上的电压大于PVEE信号线上的电压。VDATA表示数据信号线，SCAN1、SCAN2及SCAN3表示扫描信号线，EM表示发光控制信号线，D表示发光元件。
为了使第一像素电路PU1在阵列基板100所在平面上的正投影面积小于第二像素电路PU2在阵列基板100所在平面上的正投影面积，示例性的，可以将第一像素电路PU1中任意一个晶体管的尺寸设置为小于第二像素电路PU2中相同连接位置的晶体管的尺寸，第一像素电路PU1和第二像素电路PU2中其余晶体管的尺寸可以相等。例如，可以将第一像素电路PU1中第一发光控制晶体管M1的尺寸设置为小于第二像素电路PU2中第一发光控制晶体管M1的尺寸。当然，也可以将第一像素电路PU1中多个晶体管的尺寸设置为小于第二像素电路PU2中相同连接位置的晶体管的尺寸，或者将第一像素电路PU1中所有晶体管的尺寸以及存储电容的尺寸设置为小于第二像素电路PU2中相同连接位置的晶体管及相同连接位置的存储电容的尺寸。本申请对第一像素电路PU1中具体晶体管的选择上不作限定，只 要能够使第一像素电路PU1在阵列基板100所在平面上的正投影面积小于第二像素电路PU2在阵列基板100所在平面上的正投影面积即可。
根据本申请实施例，通过将第一像素电路PU1中的晶体管设置为小尺寸晶体管，能够简单方便的实现具有小正投影面积的第一像素电路PU1，使得相邻第一像素电路PU1之间有足够的空间设置信号走线。
在另一些可选的实施例中，为了使第一像素电路PU1在阵列基板100所在平面上的正投影面积小于第二像素电路PU2在阵列基板100所在平面上的正投影面积，也可以将绕线显示区A1内的第一信号线10的线宽小于主显示区A2内的第一信号线10的线宽，绕线显示区A1内的相邻第一信号线10的线间距小于主显示区内A1的相邻第一信号线10的线间距。
在制备第一像素电路PU1和第二像素电路PU2的过程中，第一信号线10可以复用为第一像素电路PU1和第二像素电路PU2中晶体管的栅极或者源极/漏极。仍以第一像素电路PU1和第二像素电路PU2的电路结构为图3所示的7T1C为例，数据写入晶体管M2的第一极与数据信号线VDATA电连接，以第一信号线10为数据信号线为例，第一信号线10与数据写入晶体管M2的半导体层连接的部分复用为数据写入晶体管M2的第一极，数据写入晶体管M2的第一极为源极/漏极。又例如，第一信号线10为扫描信号线SCAN1，第一信号线10与第一初始化晶体管M5的半导体层交叠的部分复用为第一初始化晶体管M5的栅极。又例如，第一信号线10为发光控制信号线EM，第一信号线10与第一发光控制晶体管M1及第二发光控制晶体管M6的半导体层交叠的部分复用为第一发光控制晶体管M1及第二发光控制晶体管M6的栅极。因此，减小绕线显示区A1内的第一信号线10的线宽及线距，相当于减小了第一像素电路PU1中晶体管的尺寸。
本申请实施例中，通过压缩绕线显示区A1内的第一信号线10的线宽及线距，可以简单方便的实现减小第一像素电路PU1中晶体管的尺寸，使得相邻第一像素电路PU1之间有足够的空间设置信号走线。
在一些可选的实施例中，如图2所示，孔区Hole在第二方向Y上具有中心线L，第二类信号线12与中心线L在第二方向Y上的垂直距离越小，与第二类信号线12电连接的第二连接段22与中心线L在第二方向上的垂 直距离越小，且第二类信号线12与中心线L在第二方向Y上的垂直距离越小，与第二类信号线12电连接的第一连接段21及第三连接段23与中心线L在第二方向Y上的垂直距离越小。
以孔区Hole正对的多条第二类信号线12中的最内侧的第二类信号线12和最外侧的第二类信号线12为例，其中，孔区Hole正对的多条第二类信号线12中的最内侧的第二类信号线12与中心线L在第二方向Y上的垂直距离最小，孔区Hole正对的多条第二类信号线12中的最外侧的第二类信号线12与中心线L在第二方向Y上的垂直距离最大。
最内侧的第二类信号线12对应的第二连接段22设置在最内侧，且最内侧的第二类信号线12对应的第一连接段21及第三连接段23在最外侧。最外侧的第二类信号线12对应的第二连接段22设置在最外侧，且最外侧的第二类信号线12对应的第一连接段21及第三连接段23设置在最内侧。
可以理解的是，同一条第一连接信号线20的第一连接段21和第三连接段23的长度相等。
上述设置方式可以使最内侧的第二类信号线12对应的第二连接段22的长度大于最外侧的第二类信号线12对应的第二连接段22的长度，且最内侧的第二类信号线12对应的第一连接段21及第三连接段23的长度小于最外侧的第二类信号线12对应的第一连接段21及第三连接段23的长度，从而使最内侧的第二类信号线12及最外侧的第二类信号线12对应的第一连接信号线20的总长度趋于一致，使各第一连接信号线20的电阻趋于一致，也就是使各第一连接信号线20的压降趋于一致，有利于显示均一性。
在一些可选的实施例中，第一连接信号线20可以均匀的分布在绕线显示区A1内。例如，在第二方向Y上，第二连接段22之间的线间距相同。在第一方向X上，第一连接段21之间的线间距相同，且第三连接段23之间的线间距相同。
在一些可选的实施例中，多个第二连接段22可以均匀分布在孔区Hole在第二方向Y上的两侧。
示例性的，如图2所示，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的第一像素电路PU1的数量相等，从而 使第二连接段22在第二方向Y上的线间距相同。相邻第一连接段21之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量相等，从而使第一连接段21在第一方向X上的线间距相同。相邻第三连接段23之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量相等，从而使第三连接段23在第一方向X上的线间距相同。并且相邻第一连接段21之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量与相邻第三连接段23之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量相等，使第一连接段21在第一方向X上的线间距与第三连接段23在第一方向X上的线间距相同。
进一步的，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的第一像素电路PU1的数量，等于相邻第一连接段21之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量的两倍。由于相邻第一连接段21之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量与相邻第三连接段23之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量相等，因此，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的第一像素电路PU1的数量，也等于相邻第三连接段23之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量的两倍。
例如，如图2所示，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的第一像素电路PU1的数量为两个，相邻第一连接段21之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量为一个，相邻第三连接段23之间的间隔内的沿第一方向X排布的第一像素电路PU1的数量为一个。以孔区Hole中心线L同一侧相邻两条第二类信号线12对应的两条第一连接信号线20为例，距离中心线L较近的第二连接段22的长度比距离中心线L较远的第二连接段22的长度大致多两个第一像素电路PU1的长度，距离中心线L较近的第一连接段21的长度比距离中心线L较远的第一连接段21的长度大致少一个第一像素电路PU1的长度，距离中心线L较近的第三连接段23的长度比距离中心线L较远的第三连接段23的长度大致少一个第一像素电路PU1的长度，因此，进一步 保证位于孔区Hole中心线L同一侧的相邻两条第二类信号线12对应的两条第一连接信号线20的总长度相等。
位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的第一像素电路PU1的数量为两个仅是一种示例，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的第一像素电路PU1的数量可以为四个、六个、八个等，本申请对此不作限定。可以理解的是，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的第一像素电路PU1的数量为偶数。
在一些可选的实施例中，相邻第二连接段22之间的间隔内的沿第二方向Y排布的多个第一像素电路PU1可以紧邻设置。如此，在第一像素电路PU1的尺寸一定的情况下，可以增大相邻第一像素电路PU1之间的空隙；在第一连接信号线20的线宽一定的情况下，可以在不必将第一像素电路PU1的尺寸设置的过小的情况下，也能保证相邻第一像素电路PU1之间的空隙能够放置下第一连接信号线20。
在一些可选的实施例中，第二连接段22可以与第一信号线10设置为同层且同材质，且第一连接段21及第三连接段23与第一信号线10位于不同膜层。如此可以在同一工艺步骤中同时形成第二连接段22与第一信号线10，而第一连接段21及第三连接段23与第一信号线10的延伸方向是相交的，将第一连接段21及第三连接段23设置为与第一信号线10位于不同膜层，可以避免第一连接信号线20与第一信号线10发生信号干扰。
作为一个示例，以第一信号线10为数据信号线为例。如图4所示，阵列基板100可以包括衬底01及设置于衬底01一侧且层叠设置的第一导电层02、第二导电层03、第三导电层04及第四导电层05。相邻的导电层之间均设置有绝缘层。示例性的，第一像素电路PU1包括晶体管T及存储电容Cst。晶体管T包括半导体b、栅极g、源极s及漏极d。存储电容Cst包括第一极板c1和第二极板c2。作为一个示例，栅极g及第一极板c1可以位于第一导电层02，第二极板c2可以位于第二导电层03，源极s、漏极d、第一信号线10及第二连接段22可以位于第三导电层04，第一连接段21及第三连接段23可以均位于第四导电层05。第一连接段21及第三连接段23 可以通过过孔与第二连接段22连接。
在另一些可选的实施例中，第一连接段21、第二连接段22及第三连接段23均与第一信号线10位于不同膜层，且第一连接段21、第二连接段22及第三连接段23位于同一膜层。如此可以在同一工艺步骤中同时形成第一连接段21、第二连接段22及第三连接段23，并避免第一连接信号线20与第一信号线10发生信号干扰。
作为一个示例，仍以第一信号线10为数据信号线为例。如图5所示，第一信号线10可以位于第三导电层04，第一连接段21、第二连接段22及第三连接段23可以均位于第四导电层05。第一连接段21及第三连接段23可以通过过孔与第一信号线10连接。
在一些可选的实施例中，如图1和图2所示，第一方向X可以为列方向，第二方向Y可以为行方向，第一信号线10可以为数据信号线。
在另一些可选的实施例中，如图6和图7所示，第一方向X可以为行方向，第二方向Y可以为列方向，第一信号线10可以为扫描信号线或发光控制信号线或参考电压信号线。
在一些可选的实施例中，如图1和图8所示，第一方向X为列方向，第二方向Y为行方向，第一信号线10为数据信号线，阵列基板100还包括多条第二信号线30及多条第二连接信号线40。
第二信号线30为扫描信号线或发光控制信号线或参考电压信号线。各第二信号线30与第一像素电路PU1及第二像素电路PU2电连接且沿第二方向Y延伸。可以理解的是，多条第二信号线30均位于显示区AA。多条第二信号线30包括多条第三类信号线31和多条第四类信号线32，各第四类信号线32包括被孔区Hole分隔的第三段321和第四段322。
示例性的，第二信号线30在阵列基板所在平面上的正投影可以与第一像素电路及第二像素电路在阵列基板所在平面上的正投影交叠。
可以理解的是，各第三类信号线31为连续性走线，各第三类信号线31未被孔区Hole分隔开。
为了能够为同一条第四类信号线32所电连接的像素驱动电路提供信号，可以利用第二连接信号线40将分隔开的第三段321和第四段322连接起来。
多条第二连接信号线40中的至少部分位于绕线显示区A1。各第二连接信号线40包括相互连接的第四连接段44、第五连接段45和第六连接段46，第四连接段44与第三段321电连接(图中以黑色圆点示意第四连接段44与第三段321连接)，第六连接段46与第四段322电连接(图中以黑色圆点示意第六连接段46与第四段32连接)，第五连接段45连接在第四连接段44与第六连接段46之间，第四连接段44和第六连接段46均沿第一方向X延伸，第五连接段45沿第二方向Y延伸。为了清楚的区分出第二信号线20与第五连接段45，图中以虚线示意第五连接段45。
第二连接信号线40在阵列基板所在平面上的正投影与第一像素电路PU1在阵列基板所在平面上的正投影无交叠。本申请实施例中，通过将第一像素电路PU1在阵列基板100所在平面上的正投影面积设置为小于第二像素电路PU2在阵列基板100所在平面上的正投影面积，使得至少部分第一像素电路PU1之间不是紧邻设置的，也就是说使得至少部分第一像素电路PU1之间的空隙增大，从而在增大的空隙内设置第一连接信号线20及第二连接信号线40。
本申请实施例中，通过压缩第一像素电路PU1的面积，使第一连接信号线20及第二连接信号线40在阵列基板100所在平面上的正投影均与第一像素电路PU1在阵列基板100所在平面上的正投影无交叠，减小了第一连接信号线20及第二连接信号线40与第一像素电路PU1之间形成寄生电容的可能性，能够减弱第一连接信号线20及第二连接信号线40与第一像素电路PU1之间的耦合效应，改善显示效果。
可以按照上述实施例中第一连接信号线20的设置方式设置第二连接信号线40，在此不再赘述。
作为一个示例，如图9所示，阵列基板100还可以包括第五导电层06。相邻的导电层之间均设置有绝缘层。第一信号线10及第二连接段22可以位于第三导电层04，第一连接段21及第三连接段23(图9中未示出)可以均位于第四导电层05，第二信号线30可以位于第一导电层02，第四连接段44、第五连接段45(图9中未示出)及第六连接段46可以均位于第五导电层06。
本申请实施例提供还一种显示面板，包括如上述任一实施例所述的阵列基板。图10示出本申请一种实施例提供的显示面板的结构示意图。如图10所示，该显示面板200包括上述任一实施例所述的阵列基板100及位于阵列基板100上的发光层201。示例性的，发光层201可以是有机发光层，即该显示面板200可以是有机发光二极管(Organic Light Emitting Diode，OLED)显示面板。
该显示面板解决问题的原理与前述阵列基板相似，因此该显示面板的实施可以参见前述阵列基板的实施，重复之处在此不再赘述。
本申请实施例还提供一种显示装置，包括如上述实施例所述的显示面板200。该显示装置可以是例如手机、平板计算机、笔记本电脑、电纸书或电视机等任何具有显示功能的电子设备。
依照本申请如上文所述的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该申请仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (15)

  1. 一种阵列基板，具有孔区和显示区，所述显示区包括绕线显示区和主显示区，所述绕线显示区位于所述孔区和所述主显示区之间，且所述绕线显示区围绕所述孔区；
    所述阵列基板包括：
    第一像素电路，多个所述第一像素电路阵列分布于所述绕线显示区；
    第二像素电路，多个所述第二像素电路阵列分布于所述主显示区；
    多条第一信号线，各所述第一信号线与所述第一像素电路及所述第二像素电路电连接且沿第一方向延伸，多条所述第一信号线包括多条第一类信号线和多条第二类信号线，各所述第二类信号线包括被所述孔区分隔的第一段和第二段；
    多条第一连接信号线，多条所述第一连接信号线中的至少部分位于所述绕线显示区，所述第一连接信号线包括相互连接的第一连接段、第二连接段和第三连接段，所述第一连接段与所述第一段电连接，所述第三连接段与所述第二段电连接，所述第二连接段连接在所述第一连接段与所述第三连接段之间，所述第一连接段和所述第三连接段均沿第二方向延伸，所述第二连接段沿所述第一方向延伸；
    其中，所述第一像素电路在所述阵列基板所在平面上的正投影面积小于所述第二像素电路在所述阵列基板所在平面上的正投影面积，且所述第一连接信号线在所述阵列基板所在平面上的正投影与所述第一像素电路在所述阵列基板所在平面上的正投影无交叠。
  2. 根据权利要求1所述的阵列基板，其中，所述第一像素电路的电路结构与所述第二像素电路的电路结构相同，且所述第一像素电路及所述第二像素电路均包括至少一个晶体管，所述第一像素电路中的至少一个晶体管的尺寸小于所述第二像素电路中相同连接位置的所述至少一个晶体管的尺寸。
  3. 根据权利要求2所述的阵列基板，其中，所述绕线显示区内的所述第一信号线的线宽小于所述主显示区内的所述第一信号线的线宽，所述绕线显示区内的相邻所述第一信号线的线间距小于所述主显示区内的相邻所 述第一信号线的线间距。
  4. 根据权利要求1所述的阵列基板，其中，所述孔区在所述第二方向上具有中心线，所述第二类信号线与所述中心线在所述第二方向上的垂直距离越小，与所述第二类信号线电连接的所述第二连接段与所述中心线在所述第二方向上的垂直距离越小，且所述第二类信号线与所述中心线在所述第二方向上的垂直距离越小，与所述第二类信号线电连接的所述第一连接段及所述第三连接段与所述中心线在所述第二方向上的垂直距离越小。
  5. 根据权利要求4所述的阵列基板，其中，位于所述孔区同一侧的相邻所述第二连接段之间的间隔内的沿所述第二方向排布的所述第一像素电路的数量相等，且相邻所述第一连接段之间的间隔内的沿所述第一方向排布的所述第一像素电路的数量与相邻所述第三连接段之间的间隔内的沿所述第一方向排布的所述第一像素电路的数量相等；
    位于所述孔区同一侧的相邻所述第二连接段之间的间隔内的沿所述第二方向排布的所述第一像素电路的数量，等于相邻所述第一连接段之间的间隔内的沿所述第一方向排布的所述第一像素电路的数量的两倍。
  6. 根据权利要求5所述的阵列基板，其中，相邻所述第二连接段之间的间隔内的沿所述第二方向排布的多个所述第一像素电路紧邻设置。
  7. 根据权利要求1所述的阵列基板，其中，所述第二连接段与所述第一信号线设置为同层且同材质，且所述第一连接段及所述第三连接段与所述第一信号线位于不同膜层。
  8. 根据权利要求1所述的阵列基板，其中，所述第一连接段、所述第二连接段及所述第三连接段均与所述第一信号线位于不同膜层，且所述第一连接段、所述第二连接段及所述第三连接段位于同一膜层。
  9. 根据权利要求1至8任一项所述的阵列基板，其中，所述第一方向为列方向，所述第二方向为行方向，所述第一信号线为数据信号线。
  10. 根据权利要求1至8任一项所述的阵列基板，其中，所述第一方向为行方向，所述第二方向为列方向，所述第一信号线为扫描信号线或发光控制信号线或参考电压信号线。
  11. 根据权利要求1至8任一项所述的阵列基板，其中，所述第一方 向为列方向，所述第二方向为行方向，所述第一信号线为数据信号线，所述阵列基板还包括：
    多条第二信号线，各所述第二信号线与所述第一像素电路及所述第二像素电路电连接且沿所述第二方向延伸，多条所述第二信号线包括多条第三类信号线和多条第四类信号线，各所述第四类信号线包括被所述孔区分隔的第三段和第四段；
    多条第二连接信号线，多条所述第二连接信号线中的至少部分位于所述绕线显示区，所述第二连接信号线包括相互连接的第四连接段、第五连接段和第六连接段，所述第四连接段与所述第三段电连接，所述第六连接段与所述第四段电连接，所述第五连接段连接在所述第四连接段与所述第六连接段之间，所述第四连接段和所述第六连接段均沿所述第一方向延伸，所述第五连接段沿所述第二方向延伸；
    其中，所述第二连接信号线在所述阵列基板所在平面上的正投影与所述第一像素电路在所述阵列基板所在平面上的正投影无交叠。
  12. 根据权利要求11所述的阵列基板，其中，所述第二信号线为扫描信号线或发光控制信号线或参考电压信号线。
  13. 根据权利要求11所述的阵列基板，其中，所述第一方向为列方向，所述第二方向为行方向，所述第一信号线为数据信号线。
  14. 一种显示面板，包括如权利要求1至13任一项所述的阵列基板。
  15. 一种显示装置，包括如权利要求14所述的显示面板。
PCT/CN2021/129190 2021-02-24 2021-11-08 阵列基板、显示面板及显示装置 WO2022179174A1 (zh)

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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113160742B (zh) * 2021-02-24 2022-10-04 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置
CN113823642B (zh) * 2021-09-15 2024-01-19 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置
EP4339925A4 (en) * 2021-10-22 2024-08-14 Boe Technology Group Co Ltd DISPLAY SUBSTRATE AND ELECTRONIC DEVICE
CN114360378B (zh) * 2021-12-31 2023-11-21 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN114419996B (zh) * 2022-01-21 2023-07-25 武汉华星光电技术有限公司 显示面板
CN114464658B (zh) * 2022-01-29 2023-05-02 昆山国显光电有限公司 显示面板及显示装置
CN114899213B (zh) * 2022-06-21 2024-07-26 厦门天马显示科技有限公司 显示面板和显示装置
CN115148776B (zh) * 2022-06-30 2024-10-29 厦门天马显示科技有限公司 一种显示面板及显示装置
CN115224097A (zh) * 2022-07-28 2022-10-21 京东方科技集团股份有限公司 显示基板以及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109541867A (zh) * 2018-12-28 2019-03-29 厦门天马微电子有限公司 一种显示面板和显示装置
CN109686243A (zh) * 2019-01-31 2019-04-26 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN111128079A (zh) * 2020-01-02 2020-05-08 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板和显示装置
CN111833738A (zh) * 2020-05-27 2020-10-27 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置
CN111834375A (zh) * 2019-05-23 2020-10-27 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN111916486A (zh) * 2020-08-27 2020-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN113160742A (zh) * 2021-02-24 2021-07-23 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004177891A (ja) * 2002-11-29 2004-06-24 Mitsubishi Electric Corp 表示パネルおよびこれを用いた大型表示装置
JP4507611B2 (ja) * 2004-01-29 2010-07-21 セイコーエプソン株式会社 有機エレクトロルミネッセンス装置、及び電子機器
JP2007232795A (ja) * 2006-02-27 2007-09-13 Hitachi Displays Ltd 有機ｅｌ表示装置
JP5834733B2 (ja) * 2011-10-03 2015-12-24 セイコーエプソン株式会社 電気光学装置、電子機器
CN107633807B (zh) * 2017-09-08 2019-10-15 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN107680995B (zh) * 2017-11-02 2023-08-08 武汉天马微电子有限公司 一种显示面板及显示装置
CN108010947B (zh) * 2017-11-29 2021-01-08 上海天马有机发光显示技术有限公司 一种有机发光显示面板和有机发光显示装置
CN108417605B (zh) * 2018-02-27 2020-08-25 上海天马微电子有限公司 显示面板和显示装置
CN108682372A (zh) * 2018-04-03 2018-10-19 京东方科技集团股份有限公司 阵列基板及其驱动方法、显示装置
CN109637372B (zh) * 2019-01-28 2021-07-30 武汉天马微电子有限公司 显示面板及显示装置
CN109713024B (zh) * 2019-01-31 2021-01-08 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
KR20200097371A (ko) * 2019-02-07 2020-08-19 삼성디스플레이 주식회사 표시 장치
CN110288943B (zh) * 2019-07-08 2020-10-16 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN111834377A (zh) * 2020-02-19 2020-10-27 昆山国显光电有限公司 阵列基板、显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109541867A (zh) * 2018-12-28 2019-03-29 厦门天马微电子有限公司 一种显示面板和显示装置
CN109686243A (zh) * 2019-01-31 2019-04-26 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN111834375A (zh) * 2019-05-23 2020-10-27 昆山国显光电有限公司 显示基板、显示面板及显示装置
CN111128079A (zh) * 2020-01-02 2020-05-08 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板和显示装置
CN111833738A (zh) * 2020-05-27 2020-10-27 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置
CN111916486A (zh) * 2020-08-27 2020-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN113160742A (zh) * 2021-02-24 2021-07-23 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置

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