WO2022179175A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2022179175A1
WO2022179175A1 PCT/CN2021/129200 CN2021129200W WO2022179175A1 WO 2022179175 A1 WO2022179175 A1 WO 2022179175A1 CN 2021129200 W CN2021129200 W CN 2021129200W WO 2022179175 A1 WO2022179175 A1 WO 2022179175A1
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Prior art keywords
signal lines
connection
type
line
signal line
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PCT/CN2021/129200
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English (en)
French (fr)
Inventor
冯宏庆
李洪瑞
曾祥韬
秦韶阳
赵成雨
王守坤
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合肥维信诺科技有限公司
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Priority to KR1020237021705A priority Critical patent/KR20230107379A/ko
Publication of WO2022179175A1 publication Critical patent/WO2022179175A1/zh
Priority to US18/341,064 priority patent/US20230345785A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.
  • a notch or hole can be formed on the display screen, and external light can enter the photosensitive component located below the screen through the notch or hole on the screen. Since the signal lines around the slot or opening need to be connected one by one, it is necessary to set a larger wiring space around the slot or opening, which affects the screen ratio of the display screen.
  • Embodiments of the present application provide an array substrate, a display panel, and a display device, which can increase the screen ratio of the display area and improve the display effect.
  • an embodiment of the present application provides an array substrate having a hole area and a display area surrounding the hole area; the array substrate includes: a pixel circuit, a plurality of pixel circuit arrays are distributed in the display area; a plurality of first signal lines, each The first signal lines are electrically connected to the pixel circuit and extend along the first direction.
  • the plurality of first signal lines include a plurality of first-type signal lines and a plurality of second-type signal lines, and each second-type signal line includes a plurality of signal lines separated by holes.
  • a first-type compensation signal line and a plurality of second-type compensation signal lines the first-type compensation signal line extends along the first direction, and the second-type compensation signal line extends along the second direction; wherein, the first connection signal line is in the array
  • the orthographic projection on the plane where the substrate is located does not overlap with the orthographic projection of the pixel circuit on the plane where the array substrate is located, and the orthographic projection of the first compensation signal line on the plane where the array substrate is located and the orthographic projection of the pixel circuit on the plane where the array substrate is located There is no overlap.
  • the first type of compensation signal line is used to compensate for the uneven density of the first connection signal line located in the display area in the first direction
  • the second type of compensation signal line is used to compensate for the first connection located in the display area.
  • the density of the signal lines in the second direction is uneven.
  • an embodiment of the present application provides a display panel, including the array substrate according to any embodiment of the first aspect.
  • an embodiment of the present application provides a display device, including the display panel described in the second aspect.
  • the array substrate since at least part of the first connection signal lines are also arranged in the display area, the strips of the first connection signal lines arranged in the frame of the hole area can be reduced. Even if the first connection signal line is not arranged on the frame of the hole area, the frame area of the hole area can be reduced and the screen ratio of the array substrate can be increased.
  • the array substrate further includes a first compensation signal line, the first compensation signal line is disposed in other regions of the display area except the region where the first connection signal line is located, and the extension direction of the first type of compensation signal line is the same as that of the first compensation signal line. The extension directions of the two connection segments are the same.
  • the first type of compensation signal line is used to compensate the uneven density of the first connection signal line in the display area in the first direction
  • the extension direction of the second type of compensation signal line is the same as that of the first connection.
  • the extension direction of the segment and the third connection segment are the same
  • the second type of compensation signal line is used to compensate the uneven density of the first connection signal line in the display area in the second direction, so that the wiring density of the entire display area tends to be Consistent, thereby improving the problem of uneven display (such as mura).
  • the orthographic projection of the first connection signal line and the first compensation signal line on the plane where the array substrate is located does not overlap with the orthographic projection of the pixel circuit on the plane where the array substrate is located, reducing the number of the first connection signal line and the The possibility of forming parasitic capacitance between the first compensation signal line and the pixel circuit can reduce the coupling effect between the first connection signal line and the first compensation signal line and the pixel circuit, thereby improving the display effect.
  • FIG. 1 shows a schematic top view of an array substrate provided by an embodiment of the present application
  • Fig. 2 shows a kind of enlarged schematic diagram of Q1 area in Fig. 1;
  • FIG. 3 shows an enlarged schematic view of a comparative example of the Q1 region in FIG. 1;
  • Fig. 4 shows another enlarged schematic diagram of the Q1 region in Fig. 1;
  • Fig. 5 shows the cross-sectional schematic diagram of the direction A-A in Fig. 4;
  • FIG. 6 shows another schematic top view of the array substrate provided by the embodiment of the present application.
  • Fig. 7 shows a kind of enlarged schematic diagram of Q2 area in Fig. 6;
  • Fig. 8 shows another enlarged schematic diagram of the Q1 region in Fig. 1;
  • Fig. 9 shows a kind of enlarged schematic diagram of S region in Fig. 8.
  • Figure 10 shows a schematic cross-sectional view of the direction B-B in Figure 8.
  • FIG. 11 shows a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 shows a schematic top view of an array substrate provided by an embodiment of the present application.
  • FIG. 2 shows an enlarged schematic view of the Q region in FIG. 1 .
  • an embodiment of the present application provides an array substrate 100 having a hole area Hole and a display area AA surrounding the hole area Hole.
  • the hole area may also be referred to as an opening area, a slot area, a blind hole area, a through hole area, etc., which is not limited in this application.
  • Hole area can be used to place photosensitive components.
  • the photosensitive component may be an image acquisition device for acquiring external image information.
  • the photosensitive component is a camera and the like.
  • the photosensitive component may not be limited to an image acquisition device.
  • the photosensitive component may also be an infrared sensor, a proximity sensor, an infrared lens, a flood light sensing element, an ambient light sensor, and a light sensor such as a dot matrix projector.
  • the hole area can be a rectangular area, a circular area, an oval area or a square area, etc.
  • the shape of the hole area can be set according to actual requirements, which is not limited in this application.
  • hole area Hole is a non-display area.
  • the array substrate 100 includes a pixel circuit PU, a first signal line 10 , a first connection signal line 20 and a first compensation signal line 30 .
  • a plurality of pixel circuit PU arrays are distributed in the display area AA.
  • the pixel circuit PU is used to drive the light-emitting element to emit light.
  • the density of the pixel circuits on the array substrate 100 is also relatively high.
  • the pixel circuits on the entire array substrate are arranged next to each other, that is, there is not enough space between adjacent pixel circuits to place signal lines. .
  • Each of the first signal lines 10 is electrically connected to the pixel circuit PU and extends along the first direction X. It can be understood that the plurality of first signal lines 10 are all located in the display area AA.
  • the plurality of first signal lines 10 include a plurality of first type signal lines 11 and a plurality of second type signal lines 12 .
  • Each of the first type of signal lines 11 extends along the first direction X.
  • Each of the second type signal lines 12 includes a first segment 121 and a second segment 122 which are separated by the hole region Hole and extend along the first direction X. As shown in FIG.
  • the orthographic projection of the first signal line 10 on the plane where the array substrate is located may overlap with the orthographic projection of the pixel circuit PU on the plane where the array substrate is located.
  • each of the first-type signal lines 11 is a continuous line, and each of the first-type signal lines 11 is not separated by the hole area.
  • the first connection signal line 20 may be used to connect the separated first segment 121 and the second segment 122 .
  • Each first connection signal line 20 includes a first connection segment 21 , a second connection segment 22 and a third connection segment 23 connected to each other, and the second connection segment 22 is connected between the first connection segment 21 and the third connection segment 23 ,
  • the first connecting segment 21 is electrically connected to the first segment 121 (the black dots in the figure indicate that the first connecting segment 21 is connected to the first segment 121 )
  • the third connecting segment 23 is electrically connected to the second segment 122 (the black dots in the figure indicate that the first connecting segment 21 is connected to the second segment 122 ).
  • the dots indicate that the third connection segment 23 is connected to the second segment 122 ), and both the first connection segment 21 and the third connection segment 23 extend along the second direction Y.
  • the second connecting segment 22 extends along the first direction X.
  • the second connection segment 22 is represented by a dotted line in the figure.
  • the orthographic projection of the first connection signal line 20 on the plane where the array substrate 100 is located does not overlap with the orthographic projection of the pixel circuit PU on the plane where the array substrate 100 is located.
  • by reducing the size of the pixel circuits PU at least some of the pixel circuits PU are not arranged next to each other, that is to say, the gap between at least some of the pixel circuits PU is increased, so that within the increased gap A first connection signal line 20 is provided.
  • the plurality of first compensation signal lines 30 include a plurality of first type compensation signal lines 31 and a plurality of second type compensation signal lines 32, the first type compensation signal lines 31 extend along the first direction X, and the second type compensation signal lines 32 extends in the second direction Y. And the orthographic projection of the first compensation signal line 30 on the plane where the array substrate 100 is located does not overlap with the orthographic projection of the pixel circuit PU on the plane where the array substrate 100 is located. That is to say, the first compensation signal line 30 is also disposed at the position corresponding to the gap between the adjacent pixel circuits PU.
  • the number of the first connection signal lines 20 arranged on the border of the hole area can be reduced, and even not in the hole area.
  • the frame is provided with the first connection signal line 20, so the frame area of the hole area can be reduced, and the screen ratio of the array substrate can be improved.
  • the wiring density of the display area occupied by the first connection signal lines 20 is greater than that of other connection signal lines 20
  • problems such as uneven display (such as mura) may occur when the array substrate drives the light-emitting element to display.
  • the array substrate provided by the embodiment of the present application further includes a first compensation signal line 30, the first compensation signal line 30 is disposed in other areas in the display area AA except the area where the first connection signal line 20 is located, and the first type of compensation signal line 30 is The extension direction of the signal line 31 is the same as the extension direction of the second connection section 22.
  • the first type of compensation signal line 31 is used to compensate the uneven density of the first connection signal line 20 located in the display area AA in the first direction X
  • the extension direction of the second type compensation signal line 32 is the same as the extension direction of the first connection segment 21 and the third connection segment 23
  • the second type compensation signal line 32 is used to compensate the first connection signal line 20 located in the display area AA in the
  • the uneven density in the second direction Y makes the wiring density of the entire display area AA tend to be consistent, thereby improving the problem of uneven display (eg, mura).
  • the orthographic projections of the first connection signal line 20 and the first compensation signal line 30 on the plane of the array substrate do not overlap with the orthographic projection of the pixel circuit PU on the plane of the array substrate, which reduces the number of first connection signal lines.
  • 20 and the first compensation signal line 30 and the possibility of forming a parasitic capacitance between the pixel circuit PU can reduce the coupling effect between the first connection signal line 20 and the first compensation signal line 30 and the pixel circuit PU, and improve the display effect.
  • the first direction X and the second direction Y intersect.
  • the first direction X and the second direction Y may be perpendicular.
  • the first direction X may be a column direction
  • the second direction Y may be a row direction
  • the first signal line 10 may be a data signal line.
  • the first direction X may be the row direction
  • the second direction Y may be the column direction
  • the first signal line 10 may be a scan signal line, a light-emitting control signal line, or a reference voltage signal line. This application does not limit this.
  • the line spacing between adjacent first type compensation signal lines 31 is equal to the line spacing between adjacent second connection segments 22 .
  • the line width of the first type of compensation signal line 31 is equal to that of the second connection segment 22 . That is to say, the plurality of second connection segments 22 and the plurality of first-type compensation signal lines 31 are uniformly distributed in the second direction Y. As shown in FIG. Since the first type of compensation signal line 31 and the second connection segment 22 both extend along the first direction X, the line widths are equal and are uniformly distributed, so the wiring density of the entire display area AA in the first direction X can be further improved tend to be consistent.
  • the line spacing between the immediately adjacent first-type compensation signal lines 31 and the second connection segments 22 is equal to the line spacing between adjacent first-type compensation signal lines 31, and/ Or, the line spacing between the immediately adjacent first type compensation signal lines 31 and the second connection segments 22 is equal to the line spacing between the adjacent second connection segments 22 .
  • the second connection segment 22 is on the extension line of part of the first type compensation signal line 31, or in other words, two first type compensation signal lines are provided at both ends of the second connection segment 22 in the first direction X. 31 , the extension lines of the two first type compensation signal lines 31 pass through the second connection section 22 .
  • the line spacing between adjacent second-type compensation signal lines 32 , the line spacing between adjacent first connection segments 21 , and the adjacent third connection are equal, and the line widths of the second type compensation signal lines 32 and the line widths of the first connection segment 21 and the third connection segment 22 are equal. That is to say, the plurality of second-type compensation signal lines 32 , the plurality of first connection segments 21 and the plurality of third connection segments 22 are uniformly distributed in the first direction X. As shown in FIG.
  • the second type of compensation signal line 32 , the first connection segment 21 and the third connection segment 22 all extend along the second direction Y, the line widths are equal and are uniformly distributed, so the entire display area AA can be further extended in the second direction.
  • the trace density on Y tends to be consistent.
  • the line spacing between the immediately adjacent second-type compensation signal lines 32 and the first connection segment 21 is equal to the line spacing between adjacent second-type compensation signal lines 32, and/ Or, the line spacing between the immediately adjacent second type compensation signal line 32 and the first connection segment 21 is equal to the line spacing between the adjacent first connection segments 21; in the first direction X, the adjacent second type compensation signal line
  • the line spacing between the signal line 32 and the third connection segment 23 is equal to the line spacing between the adjacent second-type compensation signal lines 32 , and/or, the second-type compensation signal line 32 and the third connection segment 23 are immediately adjacent to each other. The line spacing between them is equal to the line spacing between adjacent third connection segments 23 .
  • the first connection segment 21 and the third connection segment 23 are on the extension line of part of the second type compensation signal line 32 , or in other words, the first connection segment 21 and the third connection segment 23 are in the second direction Y.
  • Two second-type compensation signal lines 32 are disposed at both ends, and the extension lines of the two second-type compensation signal lines 32 pass through the first connection section 21 and/or the third connection section 23 .
  • first compensation signal line 30 If the first compensation signal line 30 is not connected with other signal lines, parasitic capacitance will be generated between the first compensation signal line 30 and other signal lines, which will affect signal stability and thus display stability.
  • the array substrate 100 may further include a plurality of first fixed voltage signal lines 41 and a plurality of second fixed voltage signal lines 42 .
  • a plurality of first fixed voltage signal lines 41 are electrically connected to the pixel circuit PU and extend along the first direction X.
  • the first type compensation signal line 31 is electrically connected to the second fixed voltage signal line 42
  • the second type compensation signal line 32 is electrically connected to the first fixed voltage signal line 41 .
  • the orthographic projection of the first fixed voltage signal line 41 on the plane where the array substrate is located overlaps the orthographic projection of the pixel circuit PU on the plane where the array substrate is located.
  • the plurality of second fixed voltage signal lines 42 are electrically connected to the pixel circuit PU and extend along the second direction Y.
  • the orthographic projection of the second fixed voltage signal line 42 on the plane where the array substrate is located overlaps with the orthographic projection of the pixel circuit PU on the plane where the array substrate is located.
  • the first direction X may be the column direction
  • the second direction Y may be the row direction
  • the first fixed voltage signal line 41 may be a power supply signal line (Vdd line)
  • the second fixed voltage signal line 42 may be a reference voltage signal line (Vref line).
  • the first direction X may be the row direction
  • the second direction Y may be the column direction
  • the first fixed voltage signal line 41 may be a reference voltage signal line
  • the second fixed voltage signal line 42 may be a power supply signal line. This application does not limit this.
  • the second type of compensation signal line 32 is electrically connected to the first fixed voltage signal line 41.
  • parasitic capacitance formed by the second type of compensation signal line 32 can be avoided, and display stability is improved;
  • a fixed voltage signal line 41 extends along the first direction X
  • the second type compensation signal line 32 extends along the second direction Y, which is equivalent to forming a grid-shaped first fixed voltage signal line 41, which increases the first fixed voltage
  • the routing area of the signal line 41 can reduce the resistance of the first fixed voltage signal line 41 , thereby reducing the voltage drop (IR drop) of the first fixed voltage signal line 41 .
  • the first type of compensation signal line 31 is electrically connected to the second fixed voltage signal line 42.
  • the parasitic capacitance formed by the first type of compensation signal line 31 can be avoided, and the display stability can be improved; on the other hand, the second fixed voltage The signal line 42 extends along the second direction Y, and the first type compensation signal line 31 extends along the first direction X, which is equivalent to forming a grid-shaped second fixed voltage signal line 42, and the second fixed voltage signal line 42 is enlarged Therefore, the resistance of the second fixed voltage signal line 42 can be reduced, thereby reducing the voltage drop (IR drop) of the second fixed voltage signal line 42 .
  • the first fixed voltage signal line 41 and the second fixed voltage signal line 42 are located in different film layers, and the second connection section 22 , the first type of compensation signal line 31 and the first A signal line 10 is arranged in the same layer and with the same material, and the first connection section 21 , the third connection section 23 , and the second type of compensation signal line 32 are arranged in the same layer and with the same material.
  • the second connection segment 22 the first type of compensation signal line 31 and the first signal line 10 can be simultaneously formed in the same process step, and the first connection segment 21 and the third connection are simultaneously formed in the same process step.
  • Section 23 , the second type of compensation signal line 32 are simultaneously formed in the same process step.
  • the array substrate 100 may include a substrate 01 and a first conductive layer 02 , a second conductive layer 03 , a third conductive layer 04 and a fourth conductive layer 05 which are disposed on one side of the substrate 01 and are stacked.
  • An insulating layer is provided between adjacent conductive layers.
  • the pixel circuit PU includes a transistor T and a storage capacitor Cst.
  • the transistor T includes a semiconductor b, a gate g, a source s and a drain d.
  • the storage capacitor Cst includes a first electrode plate c1 and a second electrode plate c2.
  • the gate g and the first electrode plate c1 may be located in the first conductive layer 02
  • the second electrode plate c2 and the second fixed voltage signal line 42 may be located in the second conductive layer 03
  • the first signal line 10, the second connection segment 22 and the first type of compensation signal line 31 may be located in the third conductive layer 04
  • the signal lines 32 may all be located in the fourth conductive layer 05 .
  • the first connection segment 21 and the third connection segment 23 can be connected to the second connection segment 22 through via holes.
  • the first fixed-voltage signal line 41 may include a first sub-fixed-voltage signal line 411 and a second sub-fixed-voltage signal line 412 arranged in layers, so as to further reduce the first fixed-voltage signal line 41 . pressure drop.
  • the first sub-fixed voltage signal line 411 may be located in the third conductive layer 04
  • the second sub-fixed voltage signal line 412 may be located in the fourth conductive layer 05 .
  • the hole area Hole has a center line L in the second direction Y, and the vertical distance between the second type signal line 12 and the center line L in the second direction Y is smaller.
  • the smaller the vertical distance between the second connection segment 22 electrically connected to the second type signal line 12 and the center line L in the second direction Y, and the smaller the vertical distance between the second type signal line 12 and the center line L in the second direction Y The smaller the vertical distance is, the smaller the vertical distance between the first connection segment 21 and the third connection segment 23 electrically connected to the second type of signal line 12 and the center line L in the second direction Y is.
  • the innermost second type signal line 12 and the outermost second type signal line 12 among the plurality of second type signal lines 12 facing the hole area Take the innermost second type signal line 12 and the outermost second type signal line 12 among the plurality of second type signal lines 12 facing the hole area as an example, wherein the plurality of second type signal lines 12 facing the hole area Hole are Among the two types of signal lines 12, the innermost second type signal line 12 has the smallest vertical distance from the center line L in the second direction Y, and the outermost one of the plurality of second type signal lines 12 facing the hole area is the smallest. The vertical distance between the second type of signal line 12 and the center line L in the second direction Y is the largest.
  • the second connection segment 22 corresponding to the innermost second type signal line 12 is arranged at the innermost side, and the first connection segment 21 and the third connection segment 23 corresponding to the innermost second type signal line 12 are arranged at the outermost side.
  • the second connection segment 22 corresponding to the outermost second type signal line 12 is arranged at the outermost side, and the first connection segment 21 and the third connection segment 23 corresponding to the outermost second type signal line 12 are arranged at the innermost side
  • first connection segment 21 and the third connection segment 23 of the same first connection signal line 20 are the same.
  • the above arrangement can make the length of the second connection segment 22 corresponding to the innermost second type signal line 12 greater than the length of the second connection segment 22 corresponding to the outermost second type signal line 12, and the innermost second type signal line 12.
  • the lengths of the first connection segment 21 and the third connection segment 23 corresponding to the signal line 12 are smaller than the lengths of the first connection segment 21 and the third connection segment 23 corresponding to the outermost second type signal line 12, so that the innermost
  • the total lengths of the second type signal lines 12 and the first connecting signal lines 20 corresponding to the outermost second type signal lines 12 tend to be the same, so that the resistances of the first connecting signal lines 20 tend to be the same.
  • the voltage drop of the connecting signal lines 20 tends to be consistent, which is beneficial to display uniformity.
  • the first connection signal lines 20 may be uniformly distributed in the display area AA.
  • the line spacing between adjacent second connection segments 22 is the same.
  • the line spacing between adjacent first connecting segments 21 is the same, and the line spacing between adjacent third connecting segments 23 is the same.
  • the plurality of second connecting segments 22 may be evenly distributed on both sides of the hole area in the second direction Y. As shown in FIG.
  • the number of pixel circuits PU arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is equal, so that the adjacent first The line spacings of the two connecting segments 22 in the second direction Y are the same.
  • the number of pixel circuits PU arranged along the first direction X in the interval between the adjacent first connection segments 21 on the same side of the hole area is equal, so that the adjacent first connection segments 21 are in the first direction X
  • the line spacing is the same.
  • the number of pixel circuits PU arranged along the first direction X in the interval between the adjacent third connection segments 23 on the same side of the hole area is equal, so that the adjacent third connection segments 23 are in the first direction X
  • the line spacing is the same.
  • the number of pixel circuits PU arranged along the first direction X within the interval between adjacent first connection segments 21 and the pixels arranged along the first direction X within the interval between adjacent third connection segments 23 The number of circuits PU is equal, so that the line spacing in the first direction X of the adjacent first connection segments 21 is the same as the line spacing in the first direction X of the adjacent third connection segments 23 .
  • the number of pixel circuits PU arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is equal to the number of adjacent first connections located on the same side of the hole area.
  • the number of pixel circuits PU arranged in the first direction X within the interval between the segments 21 is twice as large.
  • the number of pixel circuits PU arranged along the first direction X within the interval between the adjacent first connection segments 21 on the same side of the hole area and the adjacent third connection segments 23 on the same side of the hole area is greater than the number of pixel circuits PU arranged in the first direction X
  • the number of pixel circuits PU arranged along the first direction X in the interval between them is equal, therefore, the number of pixel circuits PU arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area Hole is equal.
  • the number of pixel circuits PU is also equal to twice the number of pixel circuits PU arranged along the first direction X within the interval between the adjacent third connection segments 23 on the same side of the hole area.
  • the number of pixel circuits PU arranged along the second direction Y in the interval between adjacent second connection segments 22 on the same side of the hole area is two, and the number of pixel circuits PU located on the same side of the hole area is two.
  • the number of pixel circuits PU arranged along the first direction X in the interval between the adjacent first connection segments 21 on the side is one, which is located in the interval between the adjacent third connection segments 23 on the same side of the hole area.
  • the number of pixel circuits PU arranged along the first direction X is one.
  • the length of the second connection segment 22 closer to the center line L than the distance from the center line L is approximately two more lengths of the pixel circuit PU, and the length of the first connection segment 21 that is closer to the center line L is longer than the length of the first connection segment 21 that is farther from the center line L
  • the length of the pixel circuit PU is approximately one less, and the length of the third connection segment 23 closer to the center line L is approximately one pixel circuit PU less than the length of the third connection segment 23 farther from the center line L. Therefore, further It is ensured that the total lengths of the two first connection signal lines 20 corresponding to the two adjacent second type signal lines 12 on the same side of the hole area Hole center line L are equal.
  • the number of pixel circuits PU arranged along the second direction Y in the interval between the adjacent second connection segments 22 on the same side of the hole area is only an example.
  • the number of pixel circuits PU arranged along the second direction Y in the interval between adjacent second connection segments 22 may be four, six, eight, etc., which is not limited in this application.
  • Exemplarily, the number of pixel circuits PU arranged along the second direction Y in the interval between adjacent second connection segments 22 on the same side of the hole region Hole may be an even number.
  • a plurality of pixel circuits PU arranged along the second direction Y within the interval between adjacent second connection segments 22 may be arranged next to each other. In this way, when the size of the pixel circuit PU is constant, the gap between adjacent pixel circuits PU can be increased; when the line width of the first connection signal line 20 is constant, the size of the pixel circuit PU does not need to be changed. If the setting is too small, it can also ensure that the first connection signal line 20 can be placed in the gap between the adjacent pixel circuits PU.
  • the first direction X may be a column direction
  • the second direction Y may be a row direction
  • the first signal line 10 may be a data signal line.
  • the first direction X may be a row direction
  • the second direction Y may be a column direction
  • the first signal line 10 may be a scanning signal line or a light-emitting control line Signal line or reference voltage signal line.
  • the first direction X is the column direction
  • the second direction Y is the row direction
  • the first signal line 10 is a data signal line
  • the array substrate 100 It also includes a plurality of second signal lines 50 , a plurality of second connection signal lines 60 and a plurality of second compensation signal lines 70 .
  • the second signal line 50 is a scan signal line, a light-emitting control signal line, or a reference voltage signal line.
  • Each of the second signal lines 50 is electrically connected to the pixel circuit PU and extends along the second direction Y. It can be understood that the plurality of second signal lines 50 are all located in the display area AA.
  • the plurality of second signal lines 50 include a plurality of third-type signal lines 51 and a plurality of fourth-type signal lines 52 , and each fourth-type signal line 52 includes a third segment 521 and a fourth segment 522 separated by a hole area.
  • the orthographic projection of the second signal line 50 on the plane where the array substrate is located may overlap with the orthographic projection of the pixel circuit PU on the plane where the array substrate is located.
  • each third type signal line 51 is a continuous wiring, and each third type signal line 51 is not separated by the hole area.
  • the second connection signal line 60 may be used to connect the separated third segment 521 and the fourth segment 522.
  • Each second connection signal line 60 includes a fourth connection segment 64, a fifth connection segment 65 and a sixth connection segment 66 that are connected to each other.
  • the fourth connection segment 64 is electrically connected to the third segment 521 (the black circles in the figure indicate the first
  • the four connecting segments 64 are connected to the third segment 521)
  • the sixth connecting segment 66 is electrically connected to the fourth segment 522 (the black dots in the figure indicate that the sixth connecting segment 66 is connected to the fourth segment 522)
  • the fifth connecting segment 65 Connected between the fourth connection segment 64 and the sixth connection segment 66 , the fourth connection segment 64 and the sixth connection segment 66 both extend along the first direction X
  • the fifth connection segment 65 extends along the second direction Y.
  • the fifth connection segment 65 is indicated by a dotted line in the figure.
  • the orthographic projection of the second connection signal line 60 on the plane of the array substrate does not overlap with the orthographic projection of the pixel circuit PU on the plane of the array substrate.
  • by reducing the size of the pixel circuits PU at least some of the pixel circuits PU are not arranged next to each other, that is to say, the gap between at least some of the pixel circuits PU is increased, so that within the increased gap A second connection signal line 60 is provided.
  • the plurality of second compensation signal lines 70 include a plurality of third type compensation signal lines 71 and a plurality of fourth type compensation signal lines 72.
  • the third type compensation signal lines 71 extend along the first direction X
  • the fourth type of compensation signal line 72 extends along the second direction Y
  • the fourth type of compensation signal line 72 is used for compensation
  • the density of the second connection signal lines 60 in the display area AA in the second direction Y is uneven.
  • the orthographic projection of the second compensation signal line 70 on the plane where the array substrate 100 is located does not overlap with the orthographic projection of the pixel circuit PU on the plane where the array substrate 100 is located. That is to say, the second compensation signal line 70 is also disposed at the position corresponding to the gap between the adjacent pixel circuits PU.
  • the number of the second connection signal lines 60 arranged on the frame of the hole area can be reduced, and even not in the hole area.
  • the frame is provided with the second connection signal line 60, so the frame area of the hole area can be reduced, and the screen ratio of the array substrate can be improved.
  • the wiring density of the display area occupied by the second connection signal lines 60 is greater than that of other display areas. Different areas have different wiring densities, which leads to problems such as uneven display (such as mura) when the array substrate drives the display of the light-emitting element.
  • the array substrate provided by the embodiment of the present application further includes a second compensation signal line 70 , and the second compensation signal line 70 is disposed in other regions of the display area AA except for the region where the second connection signal line 60 is located, and the third type of compensation signal line 70 is
  • the extension direction of the signal line 71 is the same as the extension direction of the fourth connection segment 64 and the sixth connection segment 66 .
  • the third type of compensation signal line 71 is used to compensate the second connection signal line 60 located in the display area AA in the first direction X
  • the density on the surface is uneven
  • the extension direction of the fourth type of compensation signal line 72 is the same as that of the fifth connection section 65
  • the fourth type of compensation signal line 72 is used to compensate the second connection signal line 60 in the display area AA.
  • the uneven density in the second direction Y makes the wiring density of the entire display area AA tend to be consistent, thereby improving the problem of uneven display (eg, mura).
  • the orthographic projections of the second connection signal line 60 and the second compensation signal line 70 on the plane of the array substrate do not overlap with the orthographic projection of the pixel circuit on the plane of the array substrate, which reduces the number of the second connection signal line 60
  • the possibility of forming parasitic capacitance between the second compensation signal line 70 and the pixel circuit PU can reduce the coupling effect between the second connection signal line 60 and the second compensation signal line 70 and the pixel circuit PU, thereby improving the display effect.
  • the second connection signal line 60 can be set according to the setting method of the first connecting signal line 20 in the above embodiment, and the second compensation signal line 70 can be set according to the setting method of the first compensation signal line 30 in the above embodiment, which will not be repeated here. .
  • the third type of compensation signal line 71 may be electrically connected to the second fixed voltage signal line 42 to prevent the third type of compensation signal line 71 from forming parasitic capacitance and further reduce the voltage drop of the second fixed voltage signal line 42 .
  • the fourth type of compensation signal line 72 can be electrically connected to the first fixed voltage signal line 41 to prevent the fourth type of compensation signal line 72 from forming parasitic capacitance and further reduce the voltage drop of the first fixed voltage signal line 41 .
  • the array substrate 100 may further include a fifth conductive layer 06 and a sixth conductive layer 07 .
  • An insulating layer is provided between adjacent conductive layers.
  • the second signal line 50 may be located in the first conductive layer 02, the second fixed voltage signal line 42 may be located in the second conductive layer 03, the first signal line 10, the second connection section 22 (not shown in FIG. 10) and the first
  • the class compensation signal line 31 may be located on the third conductive layer 04, and the first connection segment 21 (not shown in FIG. 10 ), the third connection segment 23 (not shown in FIG. 10 ) and the second class compensation signal line 32 may all be Located in the fourth conductive layer 05 , the fourth type of compensation signal line 72 may be located in the fifth conductive layer 06 , and the third type of compensation signal line 71 may be located in the sixth conductive layer 07 .
  • FIG. 11 shows a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 200 includes the array substrate 100 described in any of the above embodiments and a light-emitting layer 201 on the array substrate 100 .
  • the light-emitting layer 201 may be an organic light-emitting layer, that is, the display panel 200 may be an organic light-emitting diode (Organic Light Emitting Diode, OLED) display panel.
  • OLED Organic Light Emitting Diode
  • the problem-solving principle of the display panel is similar to that of the aforementioned array substrate. Therefore, the implementation of the display panel can refer to the aforementioned implementation of the array substrate, and the repetition will not be repeated here.
  • Embodiments of the present application further provide a display device, including the display panel 200 described in the foregoing embodiments.
  • the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book, or a television.

Abstract

本申请公开了一种阵列基板、显示面板及显示装置。该阵列基板包括：像素电路；多条第一信号线，多条第一信号线包括多条第一类信号线和多条第二类信号线，各第二类信号线包括被孔区分隔的第一段和第二段；多条第一连接信号线，多条第一连接信号线中的至少部分位于显示区，第一连接信号线包括相互连接的第一连接段、第二连接段和第三连接段；多条第一补偿信号线；其中，第一连接信号线在阵列基板所在平面上的正投影与像素电路在阵列基板所在平面上的正投影无交叠，且第一补偿信号线在阵列基板所在平面上的正投影与像素电路在阵列基板所在平面上的正投影无交叠。根据本申请实施例，能够提高显示区的屏占比，且能够改善显示效果。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2021年02月24日提交的名称为“阵列基板、显示面板及显示装置”的中国专利申请第202110206171.X号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板、显示面板及显示装置。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，传统的电子设备如手机、平板电脑等，由于需要集成诸如前置摄像头、听筒以及红外感应元件等。现有技术中，可通过在显示屏上开槽(Notch)或开孔，外界光线可通过屏幕上的开槽或开孔进入位于屏幕下方的感光组件。由于开槽或开孔周围的信号线需要一一对应连接起来，需要在开槽或开孔周围设置较大的布线空间，影响显示屏的屏占比。
发明内容
本申请实施例提供了一种阵列基板、显示面板及显示装置，能够提高显示区的屏占比，且能够改善显示效果。
第一方面，本申请实施例提供一种阵列基板，具有孔区和围绕孔区的显示区；阵列基板包括：像素电路，多个像素电路阵列分布于显示区；多条第一信号线，各第一信号线与像素电路电连接且沿第一方向延伸，多条第一信号线包括多条第一类信号线和多条第二类信号线，各第二类信号线包括被孔区分隔的第一段和第二段；多条第一连接信号线，多条第一连接信号线中的至少部分位于显示区，第一连接信号线包括相互连接的第一连 接段、第二连接段和第三连接段，第一连接段与第一段电连接，第三连接段与第二段电连接，第二连接段连接在第一连接段与第三连接段之间，第一连接段和第三连接段均沿第二方向延伸，第二连接段沿第一方向延伸；多条第一补偿信号线，多条第一补偿信号线位于显示区，多条第一补偿信号线包括多条第一类补偿信号线和多条第二类补偿信号线，第一类补偿信号线沿第一方向延伸，第二类补偿信号线沿第二方向延伸；其中，第一连接信号线在阵列基板所在平面上的正投影与像素电路在阵列基板所在平面上的正投影无交叠，且第一补偿信号线在阵列基板所在平面上的正投影与像素电路在阵列基板所在平面上的正投影无交叠，第一类补偿信号线用于补偿位于显示区内的第一连接信号线在第一方向上的密度不均，第二类补偿信号线用于补偿位于显示区内的第一连接信号线在第二方向上的密度不均。
第二方面，本申请实施例提供一种显示面板，包括如第一方面任一实施例所述的阵列基板。
第三方面，本申请实施例提供一种显示装置，包括如第二方面所述的显示面板。
根据本申请实施例提供的阵列基板、显示面板及显示装置，一方面，由于将至少部分第一连接信号线也设置于显示区，可以减少在孔区的边框设置的第一连接信号线的条数，甚至可以不在孔区的边框设置第一连接信号线，因此可以减小孔区的边框面积，提高阵列基板的屏占比。另一方面，阵列基板进一步包括第一补偿信号线，第一补偿信号线设置于显示区中除第一连接信号线所在区域之外的其它区域，并且第一类补偿信号线的延伸方向与第二连接段的延伸方向相同，第一类补偿信号线用于补偿位于显示区内的第一连接信号线在第一方向上的密度不均，第二类补偿信号线的延伸方向与第一连接段及第三连接段的延伸方向相同，第二类补偿信号线用于补偿位于显示区内的第一连接信号线在第二方向上的密度不均，使得整个显示区的走线密度趋于一致，从而改善显示不均(如mura)的问题。又一方面，第一连接信号线及第一补偿信号线在阵列基板所在平面上的正投影与像素电路在阵列基板所在平面上的正投影均无交叠，减小了第一连接 信号线及第一补偿信号线与像素电路之间形成寄生电容的可能性，能够减弱第一连接信号线及第一补偿信号线与像素电路之间的耦合效应，改善显示效果。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1示出本申请实施例提供的阵列基板的一种俯视示意图；
图2示出图1中Q1区域的一种放大示意图；
图3示出图1中Q1区域的一种对比示例的放大示意图；
图4示出图1中Q1区域的另一种放大示意图；
图5示出图4中A-A向的剖面示意图；
图6示出本申请实施例提供的阵列基板的另一种俯视示意图；
图7示出图6中Q2区域的一种放大示意图；
图8示出图1中Q1区域的又一种放大示意图；
图9示出图8中S区域的一种放大示意图；
图10示出图8中B-B向的剖面示意图；
图11示出本申请实施例提供的显示面板的一种结构示意图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
图1示出本申请实施例提供的一种阵列基板的俯视示意图。图2示出图1中Q区域的一种放大示意图。如图1及图2所示，本申请实施例提供 一种阵列基板100，具有孔区Hole及围绕孔区Hole的显示区AA。
示例性的，孔区Hole也可以称为开孔区、开槽区、盲孔区、通孔区等，本申请对此不作限定。孔区Hole可以用于放置感光组件。感光组件可以是图像采集装置，用于采集外部图像信息。例如感光组件为摄像头等。感光组件可以不限于是图像采集装置，例如在一些实施例中，感光组件也可以是红外传感器、接近传感器、红外镜头、泛光感应元件、环境光传感器以及点阵投影器等光传感器。
孔区Hole可以为矩形区域、圆形区域、椭圆形区域或者方形区域等，可以根据实际需求设置孔区Hole的形状，本申请对此不作限定。
可以理解的是，孔区Hole为非显示区。
如图1和图2所示，阵列基板100包括像素电路PU、第一信号线10、第一连接信号线20及第一补偿信号线30。
多个像素电路PU阵列分布于显示区AA。示例性的，像素电路PU用于驱动发光元件发光。
为了提高显示面板的像素密度，阵列基板100上的像素电路的密度也比较高，通常整个阵列基板上的各像素电路都是紧邻设置的，即相邻像素电路之间没有足够的空间放置信号线。而本申请实施例中，至少部分相邻像素电路PU之间具有空隙。可以理解为，在保持显示面板的像素密度不变的情况下，本申请实施例相当于从整体上减小了像素电路PU的尺寸，使得至少部分相邻像素电路PU之间具有空隙，从而可以在该空隙对应的位置放置信号线。
各第一信号线10与像素电路PU电连接且沿第一方向X延伸。可以理解的是，多条第一信号线10均位于显示区AA。多条第一信号线10包括多条第一类信号线11和多条第二类信号线12。各第一类信号线11均沿第一方向X延伸。各第二类信号线12包括被孔区Hole分隔的且沿第一方向X延伸的第一段121和第二段122。
示例性的，第一信号线10在阵列基板所在平面上的正投影可以与像素电路PU在阵列基板所在平面上的正投影交叠。
可以理解的是，各第一类信号线11为连续性走线，各第一类信号线11 未被孔区Hole分隔开。
为了能够为同一条第二类信号线12所电连接的像素驱动电路提供信号，可以利用第一连接信号线20将分隔开的第一段121和第二段122连接起来。
多条第一连接信号线20中的至少部分位于显示区AA。各第一连接信号线20包括相互连接的第一连接段21、第二连接段22和第三连接段23，第二连接段22连接在第一连接段21与第三连接段23之间，第一连接段21与第一段121电连接(图中以黑色圆点示意第一连接段21与第一段121连接)，第三连接段23与第二段122电连接(图中以黑色圆点示意第三连接段23与第二段122连接)，第一连接段21和第三连接段23均沿第二方向Y延伸。第二连接段22沿第一方向X延伸。为了清楚的区分出第一信号线10与第二连接段22，图中以虚线示意第二连接段22。
第一连接信号线20在阵列基板100所在平面上的正投影与像素电路PU在阵列基板100所在平面上的正投影无交叠。本申请实施例中，通过缩小像素电路PU的尺寸，使得至少部分像素电路PU之间不是紧邻设置的，也就是说使得至少部分像素电路PU之间的空隙增大，从而在增大的空隙内设置第一连接信号线20。
多条第一补偿信号线30包括多条第一类补偿信号线31和多条第二类补偿信号线32，第一类补偿信号线31沿第一方向X延伸，第二类补偿信号线32沿第二方向Y延伸。并且第一补偿信号线30在阵列基板100所在平面上的正投影与像素电路PU在阵列基板100所在平面上的正投影无交叠。也就是说，第一补偿信号线30也设置在相邻像素电路PU之间的空隙所对应的位置。
本申请实施例中，由于将至少部分第一连接信号线20也设置于显示区AA，可以减少在孔区Hole的边框设置的第一连接信号线20的条数，甚至可以不在孔区Hole的边框设置第一连接信号线20，因此可以减小孔区Hole的边框面积，提高阵列基板的屏占比。
如图3所示(图3未示意出像素电路)，由于至少部分第一连接信号线20也设置在显示区AA内，因此第一连接信号线20所占据的显示区域的走线密度大于其它显示区域的走线密度，由于显示区中不同区域的走线 密度不同，导致阵列基板驱动发光元件显示时，会出现显示不均(如mura)等问题。
而本申请实施例提供的阵列基板进一步包括第一补偿信号线30，第一补偿信号线30设置于显示区AA中除第一连接信号线20所在区域之外的其它区域，并且第一类补偿信号线31的延伸方向与第二连接段22的延伸方向相同，第一类补偿信号线31用于补偿位于显示区AA内的第一连接信号线20在第一方向X上的密度不均，第二类补偿信号线32的延伸方向与第一连接段21及第三连接段23的延伸方向相同，第二类补偿信号线32用于补偿位于显示区AA内的第一连接信号线20在第二方向Y上的密度不均，使得整个显示区AA的走线密度趋于一致，从而改善显示不均(如mura)的问题。另外，第一连接信号线20及第一补偿信号线30在阵列基板所在平面上的正投影与像素电路PU在阵列基板所在平面上的正投影均无交叠，减小了第一连接信号线20及第一补偿信号线30与像素电路PU之间形成寄生电容的可能性，能够减弱第一连接信号线20及第一补偿信号线30与像素电路PU之间的耦合效应，改善显示效果。
示例性的，第一方向X和第二方向Y相交。第一方向X和第二方向Y可以垂直。例如，第一方向X可以是列方向，第二方向Y是行方向，第一信号线10可以是数据信号线。又例如，第一方向X可以是行方向，第二方向Y是列方向，第一信号线10可以是扫描信号线或发光控制信号线或参考电压信号线。本申请对此不作限定。
在一些可选的实施例中，在第二方向Y上，相邻第一类补偿信号线31之间的线间距与相邻第二连接段22之间的线间距相等。第一类补偿信号线31的线宽与第二连接段22的线宽相等。也就是说，多条第二连接段22及多条第一类补偿信号线31在第二方向Y上都是均匀分布的。由于第一类补偿信号线31和第二连接段22均是沿第一方向X延伸，线宽相等并且均是均匀分布，因此能够进一步使得整个显示区AA在第一方向X上的走线密度趋于一致。
示例性的，在第二方向Y上，紧邻的第一类补偿信号线31与第二连接段22之间的线间距与相邻第一类补偿信号线31之间的线间距相等，和/或， 紧邻的第一类补偿信号线31与第二连接段22之间的线间距与相邻第二连接段22之间的线间距相等。
示例性的，第二连接段22在部分第一类补偿信号线31的延长线上，或者说，第二连接段22在第一方向X上的两端设置有两条第一类补偿信号线31，该两条第一类补偿信号线31的延长线经过第二连接段22。
在另一些可选的实施例中，在第一方向X上，相邻第二类补偿信号线32之间的线间距、相邻第一连接段21之间的线间距及相邻第三连接段23之间的线间距相等，且第二类补偿信号线32的线宽、第一连接段21及第三连接段22的线宽相等。也就是说，多条第二类补偿信号线32、多条第一连接段21及多条第三连接段22在第一方向X上都是均匀分布的。由于第二类补偿信号线32、第一连接段21及第三连接段22均是沿第二方向Y延伸，线宽相等并且均是均匀分布，因此能够进一步使得整个显示区AA在第二方向Y上的走线密度趋于一致。
示例性的，在第一方向X上，紧邻的第二类补偿信号线32与第一连接段21之间的线间距与相邻第二类补偿信号线32之间的线间距相等，和/或，紧邻的第二类补偿信号线32与第一连接段21之间的线间距与相邻第一连接段21之间的线间距相等；在第一方向X上，紧邻的第二类补偿信号线32与第三连接段23之间的线间距与相邻第二类补偿信号线32之间的线间距相等，和/或，紧邻的第二类补偿信号线32与第三连接段23之间的线间距与相邻第三连接段23之间的线间距相等。
示例性的，第一连接段21及第三连接段23在部分第二类补偿信号线32的延长线上，或者说，第一连接段21及第三连接段23在第二方向Y上的两端设置有两条第二类补偿信号线32，该两条第二类补偿信号线32的延长线经过第一连接段21和/或第三连接段23。
如果第一补偿信号线30与其它信号线无连接关系的话，第一补偿信号线30与其它信号线之间会产生寄生电容，影响信号稳定性，从而影响显示稳定性。
在一些可选的实施例中，如图4所示，阵列基板100还可以包括多条第一固定电压信号线41及多条第二固定电压信号线42。多条第一固定电 压信号线41与像素电路PU电连接且沿第一方向X延伸。第一类补偿信号线31与第二固定电压信号线42电连接，第二类补偿信号线32与第一固定电压信号线41电连接。
示例性的，第一固定电压信号线41在阵列基板所在平面上的正投影与像素电路PU在阵列基板所在平面上的正投影交叠。多条第二固定电压信号线42与像素电路PU电连接且沿第二方向Y延伸。
示例性的，第二固定电压信号线42在阵列基板所在平面上的正投影与像素电路PU在阵列基板所在平面上的正投影交叠。
例如，第一方向X可以是列方向，第二方向Y可以是行方向，第一固定电压信号线41可以是电源信号线(Vdd line)，第二固定电压信号线42可以是参考电压信号线(Vref line)。又例如，第一方向X可以是行方向，第二方向Y可以是列方向，第一固定电压信号线41可以是参考电压信号线，第二固定电压信号线42可以是电源信号线。本申请对此不作限定。
根据本申请实施例，第二类补偿信号线32与第一固定电压信号线41电连接，一方面，可以避免第二类补偿信号线32形成寄生电容，提高显示稳定性；另一方面，第一固定电压信号线41沿第一方向X延伸，第二类补偿信号线32沿第二方向Y延伸，相当于构成了网格状的第一固定电压信号线41，增大了第一固定电压信号线41的走线面积，从而可以降低第一固定电压信号线41的电阻，进而降低第一固定电压信号线41的压降(IR drop)。同理，第一类补偿信号线31与第二固定电压信号线42电连接，一方面，可以避免第一类补偿信号线31形成寄生电容，提高显示稳定性；另一方面，第二固定电压信号线42沿第二方向Y延伸，第一类补偿信号线31沿第一方向X延伸，相当于构成了网格状的第二固定电压信号线42，增大了第二固定电压信号线42的走线面积，从而可以降低第二固定电压信号线42的电阻，进而降低第二固定电压信号线42的压降(IR drop)。
在一些可选的实施例中，如图5所示，第一固定电压信号线41与第二固定电压信号线42位于不同膜层，第二连接段22、第一类补偿信号线31及第一信号线10设置为同层且同材质，第一连接段21、第三连接段23、第二类补偿信号线32设置为同层且同材质。如此能够避免信号干扰，且在 同一工艺步骤中同时形成第二连接段22、第一类补偿信号线31及第一信号线10，在同一工艺步骤中同时形成第一连接段21、第三连接段23、第二类补偿信号线32。
示例性的，阵列基板100可以包括衬底01及设置于衬底01一侧且层叠设置的第一导电层02、第二导电层03、第三导电层04及第四导电层05。相邻的导电层之间均设置有绝缘层。示例性的，像素电路PU包括晶体管T及存储电容Cst。晶体管T包括半导体b、栅极g、源极s及漏极d。存储电容Cst包括第一极板c1和第二极板c2。作为一个示例，栅极g及第一极板c1可以位于第一导电层02，第二极板c2及第二固定电压信号线42可以位于第二导电层03，源极s、漏极d、第一信号线10、第二连接段22及第一类补偿信号线31可以位于第三导电层04，第一连接段21、第三连接段23(图中未示出)及第二类补偿信号线32可以均位于第四导电层05。第一连接段21及第三连接段23可以通过过孔与第二连接段22连接。
示例性的，如图5所示，第一固定电压信号线41可以包括层叠设置的第一子固定电压信号线411和第二子固定电压信号线412，以进一步降低第一固定电压信号线41的压降。第一子固定电压信号线411可以位于第三导电层04，第二子固定电压信号线412可以位于第四导电层05。
图中为了清楚的示出各走线及晶体管T和存储电容Cst，并未示出第一信号线10、第一固定电压信号线41与第二固定电压信号线42与晶体管T或存储电容Cst存在交叠，这并不用于限定本申请。
在一些可选的实施例中，如图2所示，孔区Hole在第二方向Y上具有中心线L，第二类信号线12与中心线L在第二方向Y上的垂直距离越小，与第二类信号线12电连接的第二连接段22与中心线L在第二方向Y上的垂直距离越小，且第二类信号线12与中心线L在第二方向Y上的垂直距离越小，与第二类信号线12电连接的第一连接段21及第三连接段23与中心线L在第二方向Y上的垂直距离越小。
以孔区Hole正对的多条第二类信号线12中的最内侧的第二类信号线12和最外侧的第二类信号线12为例，其中，孔区Hole正对的多条第二类信号线12中的最内侧的第二类信号线12与中心线L在第二方向Y上的垂 直距离最小，孔区Hole正对的多条第二类信号线12中的最外侧的第二类信号线12与中心线L在第二方向Y上的垂直距离最大。
最内侧的第二类信号线12对应的第二连接段22设置在最内侧，且最内侧的第二类信号线12对应的第一连接段21及第三连接段23设置在最外侧。最外侧的第二类信号线12对应的第二连接段22设置在最外侧，且最外侧的第二类信号线12对应的第一连接段21及第三连接段23设置在最内侧
可以理解的是，同一条第一连接信号线20的第一连接段21和第三连接段23的长度相等。
上述设置方式可以使最内侧的第二类信号线12对应的第二连接段22的长度大于最外侧的第二类信号线12对应的第二连接段22的长度，且最内侧的第二类信号线12对应的第一连接段21及第三连接段23的长度小于最外侧的第二类信号线12对应的第一连接段21及第三连接段23的长度，从而使最内侧的第二类信号线12及最外侧的第二类信号线12对应的第一连接信号线20的总长度趋于一致，使各第一连接信号线20的电阻趋于一致，也就是使各第一连接信号线20的压降趋于一致，有利于显示均一性。
在一些可选的实施例中，第一连接信号线20可以均匀的分布在显示区AA内。例如，在第二方向Y上，相邻第二连接段22之间的线间距相同。在第一方向X上，相邻第一连接段21之间的线间距相同，且相邻第三连接段23之间的线间距相同。
在一些可选的实施例中，多个第二连接段22可以均匀分布在孔区Hole在第二方向Y上的两侧。
示例性的，如图2所示，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的像素电路PU的数量相等，从而使相邻第二连接段22在第二方向Y上的线间距相同。位于孔区Hole同一侧的相邻第一连接段21之间的间隔内的沿第一方向X排布的像素电路PU的数量相等，从而使相邻第一连接段21在第一方向X上的线间距相同。位于孔区Hole同一侧的相邻第三连接段23之间的间隔内的沿第一方向X排布的像素电路PU的数量相等，从而使相邻第三连接段23在第一方向X上的线 间距相同。并且相邻第一连接段21之间的间隔内的沿第一方向X排布的像素电路PU的数量与相邻第三连接段23之间的间隔内的沿第一方向X排布的像素电路PU的数量相等，使相邻第一连接段21在第一方向X上的线间距与相邻第三连接段23在第一方向X上的线间距相同。
进一步的，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的像素电路PU的数量，等于位于孔区Hole同一侧的相邻第一连接段21之间的间隔内的沿第一方向X排布的像素电路PU的数量的两倍。由于位于孔区Hole同一侧的相邻第一连接段21之间的间隔内的沿第一方向X排布的像素电路PU的数量与位于孔区Hole同一侧的相邻第三连接段23之间的间隔内的沿第一方向X排布的像素电路PU的数量相等，因此，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的像素电路PU的数量，也等于位于孔区Hole同一侧的相邻第三连接段23之间的间隔内的沿第一方向X排布的像素电路PU的数量的两倍。
例如，如图2所示，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的像素电路PU的数量为两个，位于孔区Hole同一侧的相邻第一连接段21之间的间隔内的沿第一方向X排布的像素电路PU的数量为一个，位于孔区Hole同一侧的相邻第三连接段23之间的间隔内的沿第一方向X排布的像素电路PU的数量为一个。以孔区Hole中心线L同一侧相邻两条第二类信号线12对应的两条第一连接信号线20为例，距离中心线L较近的第二连接段22的长度比距离中心线L较远的第二连接段22的长度大致多两个像素电路PU的长度，距离中心线L较近的第一连接段21的长度比距离中心线L较远的第一连接段21的长度大致少一个像素电路PU的长度，距离中心线L较近的第三连接段23的长度比距离中心线L较远的第三连接段23的长度大致少一个像素电路PU的长度，因此，进一步保证孔区Hole中心线L同一侧相邻两条第二类信号线12对应的两条第一连接信号线20的总长度相等。
位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的像素电路PU的数量为两个仅是一种示例，位于孔区Hole同一 侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的像素电路PU的数量可以为四个、六个、八个等，本申请对此不作限定。示例性的，位于孔区Hole同一侧的相邻第二连接段22之间的间隔内的沿第二方向Y排布的像素电路PU的数量可以为偶数。
在一些可选的实施例中，相邻第二连接段22之间的间隔内的沿第二方向Y排布的多个像素电路PU可以紧邻设置。如此，在像素电路PU的尺寸一定的情况下，可以增大相邻像素电路PU之间的空隙；在第一连接信号线20的线宽一定的情况下，可以在不必将像素电路PU的尺寸设置的过小的情况下，也能保证相邻像素电路PU之间的空隙能够放置下第一连接信号线20。
在一些可选的实施例中，如图1和图2所示，第一方向X可以为列方向，第二方向Y可以为行方向，第一信号线10可以为数据信号线。
在另一些可选的实施例中，如图6和图7所示，第一方向X可以为行方向，第二方向Y可以为列方向，第一信号线10可以为扫描信号线或发光控制信号线或参考电压信号线。
在一些可选的实施例中，如图1、图8及图9所示，第一方向X为列方向，第二方向Y为行方向，第一信号线10为数据信号线，阵列基板100还包括多条第二信号线50、多条第二连接信号线60及多条第二补偿信号线70。
第二信号线50为扫描信号线或发光控制信号线或参考电压信号线。各第二信号线50与像素电路PU电连接且沿第二方向Y延伸。可以理解的是，多条第二信号线50均位于显示区AA。多条第二信号线50包括多条第三类信号线51和多条第四类信号线52，各第四类信号线52包括被孔区Hole分隔的第三段521和第四段522。
示例性的，第二信号线50在阵列基板所在平面上的正投影可以与像素电路PU在阵列基板所在平面上的正投影交叠。
可以理解的是，各第三类信号线51为连续性走线，各第三类信号线51未被孔区Hole分隔开。
为了能够为同一条第四类信号线52所电连接的像素电路提供信号，可 以利用第二连接信号线60将分隔开的第三段521和第四段522连接起来。
多条第二连接信号线60中的至少部分位于显示区AA。各第二连接信号线60包括相互连接的第四连接段64、第五连接段65和第六连接段66，第四连接段64与第三段521电连接(图中以黑色圆点示意第四连接段64与第三段521连接)，第六连接段66与第四段522电连接(图中以黑色圆点示意第六连接段66与第四段522连接)，第五连接段65连接在第四连接段64与第六连接段66之间，第四连接段64和第六连接段66均沿第一方向X延伸，第五连接段65沿第二方向Y延伸。为了清楚的区分出第二信号线50与第五连接段65，图中以虚线示意第五连接段65。
第二连接信号线60在阵列基板所在平面上的正投影与像素电路PU在阵列基板所在平面上的正投影无交叠。本申请实施例中，通过缩小像素电路PU的尺寸，使得至少部分像素电路PU之间不是紧邻设置的，也就是说使得至少部分像素电路PU之间的空隙增大，从而在增大的空隙内设置第二连接信号线60。
多条第二补偿信号线70包括多条第三类补偿信号线71和多条第四类补偿信号线72，第三类补偿信号线71沿第一方向X延伸，第三类补偿信号线71用于补偿位于显示区AA内的第二连接信号线60在第一方向X上的密度不均，第四类补偿信号线72沿第二方向Y延伸，第四类补偿信号线72用于补偿位于显示区AA内的第二连接信号线60在第二方向Y上的密度不均。并且第二补偿信号线70在阵列基板100所在平面上的正投影与像素电路PU在阵列基板100所在平面上的正投影无交叠。也就是说，第二补偿信号线70也设置在相邻像素电路PU之间的空隙所对应的位置。
本申请实施例中，由于将至少部分第二连接信号线60也设置于显示区AA，可以减少在孔区Hole的边框设置的第二连接信号线60的条数，甚至可以不在孔区Hole的边框设置第二连接信号线60，因此可以减小孔区Hole的边框面积，提高阵列基板的屏占比。
同理，由于至少部分第二连接信号线60也设置在显示区AA内，因此第二连接信号线60所占据的显示区域的走线密度大于其它显示区域的走线密度，由于显示区中的不同区域的走线密度不同，导致阵列基板驱动发光 元件显示时，会出现显示不均(如mura)等问题。
而本申请实施例提供的阵列基板进一步包括第二补偿信号线70，第二补偿信号线70设置于显示区AA中除第二连接信号线60所在区域之外的其它区域，并且第三类补偿信号线71的延伸方向与第四连接段64及第六连接段66的延伸方向相同，第三类补偿信号线71用于补偿位于显示区AA内的第二连接信号线60在第一方向X上的密度不均，第四类补偿信号线72的延伸方向与第五连接段65的延伸方向相同，第四类补偿信号线72用于补偿位于显示区AA内的第二连接信号线60在第二方向Y上的密度不均，使得整个显示区AA的走线密度趋于一致，从而改善显示不均(如mura)的问题。另外，第二连接信号线60及第二补偿信号线70在阵列基板所在平面上的正投影与像素电路在阵列基板所在平面上的正投影均无交叠，减小了第二连接信号线60及第二补偿信号线70与像素电路PU之间形成寄生电容的可能性，能够减弱第二连接信号线60及第二补偿信号线70与像素电路PU之间的耦合效应，改善显示效果。
可以按照上述实施例中第一连接信号线20的设置方式设置第二连接信号线60，按照上述实施例中第一补偿信号线30的设置方式设置第二补偿信号线70，在此不再赘述。
示例性的，第三类补偿信号线71可以与第二固定电压信号线42电连接，避免第三类补偿信号线71形成寄生电容，且进一步降低第二固定电压信号线42的压降。第四类补偿信号线72可以与第一固定电压信号线41电连接，避免第四类补偿信号线72形成寄生电容，且进一步降低第一固定电压信号线41的压降。
作为一个示例，如图10所示，阵列基板100还可以包括第五导电层06及第六导电层07。相邻的导电层之间均设置有绝缘层。
第二信号线50可以位于第一导电层02，第二固定电压信号线42可以位于第二导电层03，第一信号线10、第二连接段22(图10中未示出)及第一类补偿信号线31可以位于第三导电层04，第一连接段21(图10中未示出)、第三连接段23(图10中未示出)及第二类补偿信号线32可以均位于第四导电层05，第四类补偿信号线72可以位于第五导电层06，第三 类补偿信号线71可以位于第六导电层07。
本申请实施例提供还一种显示面板，包括如上述任一实施例所述的阵列基板。图11示出本申请一种实施例提供的显示面板的结构示意图。如图11所示，该显示面板200包括上述任一实施例所述的阵列基板100及位于阵列基板100上的发光层201。示例性的，发光层201可以是有机发光层，即该显示面板200可以是有机发光二极管(Organic Light Emitting Diode，OLED)显示面板。
该显示面板解决问题的原理与前述阵列基板相似，因此该显示面板的实施可以参见前述阵列基板的实施，重复之处在此不再赘述。
本申请实施例还提供一种显示装置，包括如上述实施例所述的显示面板200。该显示装置可以是例如手机、平板计算机、笔记本电脑、电纸书或电视机等任何具有显示功能的电子设备。
依照本申请如上文所述的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该申请仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (17)

  1. 一种阵列基板，具有孔区和围绕所述孔区的显示区；所述阵列基板包括：
    像素电路，多个所述像素电路阵列分布于所述显示区；
    多条第一信号线，各所述第一信号线与所述像素电路电连接且沿第一方向延伸，多条所述第一信号线包括多条第一类信号线和多条第二类信号线，各所述第二类信号线包括被所述孔区分隔的第一段和第二段；
    多条第一连接信号线，多条所述第一连接信号线中的至少部分位于所述显示区，所述第一连接信号线包括相互连接的第一连接段、第二连接段和第三连接段，所述第一连接段与所述第一段电连接，所述第三连接段与所述第二段电连接，所述第二连接段连接在所述第一连接段与所述第三连接段之间，所述第一连接段和所述第三连接段均沿第二方向延伸，所述第二连接段沿所述第一方向延伸；
    多条第一补偿信号线，多条所述第一补偿信号线位于所述显示区，多条所述第一补偿信号线包括多条第一类补偿信号线和多条第二类补偿信号线，所述第一类补偿信号线沿所述第一方向延伸，所述第二类补偿信号线沿所述第二方向延伸；
    其中，所述第一连接信号线在所述阵列基板所在平面上的正投影与所述像素电路在所述阵列基板所在平面上的正投影无交叠，且所述第一补偿信号线在所述阵列基板所在平面上的正投影与所述像素电路在所述阵列基板所在平面上的正投影无交叠，所述第一类补偿信号线用于补偿位于所述显示区内的所述第一连接信号线在所述第一方向上的密度不均，所述第二类补偿信号线用于补偿位于所述显示区内的所述第一连接信号线在所述第二方向上的密度不均。
  2. 根据权利要求1所述的阵列基板，其中，在所述第二方向上，相邻所述第一类补偿信号线之间的线间距与相邻所述第二连接段之间的线间距相等，且所述第一类补偿信号线的线宽与所述第二连接段的线宽相等。
  3. 根据权利要求1所述的阵列基板，其中，在所述第一方向上，相邻所述第二类补偿信号线之间的线间距、相邻所述第一连接段之间的线间距及相邻所述第三连接段之间的线间距相等，且所述第二类补偿信号线的线宽、所述第一连接段的线宽及所述第三连接段的线宽相等。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    多条第一固定电压信号线，多条所述第一固定电压信号线与所述像素电路电连接且沿所述第一方向延伸；
    多条第二固定电压信号线，多条所述第二固定电压信号线与所述像素电路电连接且沿所述第二方向延伸；
    其中，所述第一类补偿信号线与所述第二固定电压信号线电连接，所述第二类补偿信号线与所述第一固定电压信号线电连接。
  5. 根据权利要求4所述的阵列基板，其中，所述第一固定电压信号线与所述第二固定电压信号线位于不同膜层，所述第二连接段、所述第一类补偿信号线及所述第一信号线设置为同层且同材质，所述第一连接段、所述第三连接段、所述第二类补偿信号线设置为同层且同材质。
  6. 根据权利要求1所述的阵列基板，其中，所述孔区在所述第二方向上具有中心线，所述第二类信号线与所述中心线在所述第二方向上的垂直距离越小，与所述第二类信号线电连接的所述第二连接段与所述中心线在所述第二方向上的垂直距离越小，且所述第二类信号线与所述中心线在所述第二方向上的垂直距离越小，与所述第二类信号线电连接的所述第一连接段及所述第三连接段与所述中心线在所述第二方向上的垂直距离越小。
  7. 根据权利要求6所述的阵列基板，其中，位于所述孔区同一侧的相邻所述第二连接段之间的间隔内的沿所述第二方向排布的所述像素电路的数量相等，且相邻所述第一连接段之间的间隔内的沿所述第一方向排布的所述像素电路的数量与相邻所述第三连接段之间的间隔内的沿所述第一方 向排布的所述像素电路的数量相等；
    位于所述孔区同一侧的相邻所述第二连接段之间的间隔内的沿所述第二方向排布的所述像素电路的数量，等于相邻所述第一连接段之间的间隔内的沿所述第一方向排布的所述像素电路的数量的两倍。
  8. 根据权利要求7所述的阵列基板，其中，相邻所述第二连接段之间的间隔内的沿所述第二方向排布的多个所述像素电路紧邻设置，相邻所述第一类补偿信号线之间的间隔内的沿所述第二方向排布的多个所述像素电路紧邻设置。
  9. 根据权利要求1至8任一项所述的阵列基板，其中，所述第一方向为列方向，所述第二方向为行方向，所述第一信号线为数据信号线；或者，所述第一方向为行方向，所述第二方向为列方向，所述第一信号线为扫描信号线或发光控制信号线或参考电压信号线。
  10. 根据权利要求1至8任一项所述的阵列基板，其中，所述第一方向为列方向，所述第二方向为行方向，所述第一信号线为数据信号线，所述阵列基板还包括：
    多条第二信号线，所述第二信号线为扫描信号线或发光控制信号线或参考电压信号线，各所述第二信号线与所述像素电路电连接且沿所述第二方向延伸，多条所述第二信号线包括多条第三类信号线和多条第四类信号线，各所述第四类信号线包括被所述孔区分隔的第三段和第四段；
    多条第二连接信号线，多条所述第二连接信号线中的至少部分位于所述显示区，所述第二连接信号线包括相互连接的第四连接段、第五连接段和第六连接段，所述第四连接段与所述第三段电连接，所述第六连接段与所述第四段电连接，所述第五连接段连接在所述第四连接段与所述第六连接段之间，所述第四连接段和所述第六连接段均沿所述第一方向延伸，所述第五连接段沿所述第二方向延伸；
    多条第二补偿信号线，多条所述第二补偿信号线位于所述显示区，多 条所述第二补偿信号线包括多条第三类补偿信号线和多条第四类补偿信号线，所述第三类补偿信号线沿所述第一方向延伸，所述第四类补偿信号线沿所述第二方向延伸；
    其中，所述第二连接信号线在所述阵列基板所在平面上的正投影与所述像素电路在所述阵列基板所在平面上的正投影无交叠，且所述第二补偿信号线在所述阵列基板所在平面上的正投影与所述像素电路在所述阵列基板所在平面上的正投影无交叠，所述第三类补偿信号线用于补偿位于所述显示区内的所述第二连接信号线在所述第一方向上的密度不均，所述第四类补偿信号线用于补偿位于所述显示区内的所述第二连接信号线在所述第二方向上的密度不均。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括：
    多条第一固定电压信号线，多条所述第一固定电压信号线与所述像素电路电连接且沿所述第一方向延伸；
    多条第二固定电压信号线，多条所述第二固定电压信号线与所述像素电路电连接且沿所述第二方向延伸；
    其中，所述第三类补偿信号线与所述第二固定电压信号线电连接，所述第四类补偿信号线与所述第一固定电压信号线电连接。
  12. 根据权利要求1所述的阵列基板，其中，在所述第二方向上，紧邻的所述第一类补偿信号线与所述第二连接段之间的线间距与相邻所述第一类补偿信号线之间的线间距相等，和/或，紧邻的所述第一类补偿信号线与所述第二连接段之间的线间距与相邻所述第二连接段之间的线间距相等。
  13. 根据权利要求1所述的阵列基板，其中，所述第一类补偿信号线的线宽与所述第二连接段的线宽相等。
  14. 根据权利要求1所述的阵列基板，其中，在所述第一方向上，紧邻的所述第二类补偿信号线与所述第一连接段之间的线间距与相邻所述第 二类补偿信号线之间的线间距相等，和/或，紧邻的所述第二类补偿信号线与所述第一连接段之间的线间距与相邻所述第一连接段之间的线间距相等；
    在所述第一方向上，紧邻的所述第二类补偿信号线与所述第三连接段之间的线间距与相邻所述第二类补偿信号线之间的线间距相等，和/或，紧邻的所述第二类补偿信号线与所述第三连接段之间的线间距与相邻所述第三连接段之间的线间距相等。
  15. 根据权利要求1所述的阵列基板，其中，所述第二类补偿信号线的线宽、所述第一连接段的线宽及所述第三连接段的线宽相等。
  16. 一种显示面板，包括如权利要求1至15任一项所述的阵列基板。
  17. 一种显示装置，包括如权利要求16所述的显示面板。
PCT/CN2021/129200 2021-02-24 2021-11-08 阵列基板、显示面板及显示装置 WO2022179175A1 (zh)

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CN113823642B (zh) * 2021-09-15 2024-01-19 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置
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