WO2022174543A1 - 设计规则检查方法、装置及存储介质 - Google Patents

设计规则检查方法、装置及存储介质 Download PDF

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Publication number
WO2022174543A1
WO2022174543A1 PCT/CN2021/103734 CN2021103734W WO2022174543A1 WO 2022174543 A1 WO2022174543 A1 WO 2022174543A1 CN 2021103734 W CN2021103734 W CN 2021103734W WO 2022174543 A1 WO2022174543 A1 WO 2022174543A1
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code
drc
design rule
conflict
file
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PCT/CN2021/103734
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English (en)
French (fr)
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吴彬
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长鑫存储技术有限公司
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Priority to US17/471,252 priority Critical patent/US20220269848A1/en
Publication of WO2022174543A1 publication Critical patent/WO2022174543A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • the present application relates to the field of chip verification, and in particular, to a design rule checking method, device and storage medium.
  • the general chip design adopts the sign off process, that is, when the design data is completed, the design rule check (DRC) is used to check whether the current design violates the design rules.
  • DRC design rule check
  • the DRC code file is checked by executing the design rule, the test pattern is generated, and the faulty test pattern is determined, and the designer optimizes the design rule and the DRC code based on the test pattern.
  • the design rule is generated, and the faulty test pattern is determined, and the designer optimizes the design rule and the DRC code based on the test pattern.
  • the present application provides a design rule checking method, device and storage medium, which realize error checking and localization of DRC codes.
  • an embodiment of the present application provides a design rule checking method, including:
  • a code conflict report is generated, and the code conflict report is used to indicate the code location where the code conflict exists.
  • classifying the parsed pieces of DRC codes to determine whether there is a code conflict in the pieces of DRC codes includes:
  • the design rule includes at least one design rule based on the width and area of the semiconductor structures in the chip, the distance, the inclusion relationship, and the extension relationship between the semiconductor structures.
  • the determining whether there is a code conflict in the DRC code segment of each design rule includes:
  • the method further includes:
  • the method further includes:
  • the DRC code update file including an update to the DRC codes that have code conflicts or code overlaps
  • the updated DRC code file is executed, and a test pattern corresponding to the updated DRC code file is generated, and the test pattern is used to verify whether the chip design meets the design requirements.
  • an embodiment of the present application provides a design rule checking device, including:
  • a processing module is used to parse the multi-section DRC codes in the DRC code file, classify the parsed multi-section DRC codes, and determine whether there is a code conflict in the multi-section DRC codes;
  • a code conflict report is generated, and the code conflict report is used to indicate the code location where the code conflict exists.
  • the processing module is specifically used for:
  • the design rule includes at least one design rule based on the width and area of the semiconductor structures in the chip, the distance, the inclusion relationship, and the extension relationship between the semiconductor structures.
  • the processing module is specifically used for:
  • the processing module is further configured to:
  • the apparatus further includes: a receiving module
  • a receiving module for receiving a DRC code update file, the DRC code update file including an update to the DRC codes that have code conflicts or code overlaps;
  • the processing module is also used to update the DRC code file according to the DRC code update file;
  • the updated DRC code file is executed, and a test pattern corresponding to the updated DRC code file is generated, and the test pattern is used to verify whether the chip design meets the design requirements.
  • an embodiment of the present application provides a design rule checking device, including:
  • the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the design rule checking apparatus to perform any one of the first aspects of the present application Methods.
  • an embodiment of the present application provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, the processor can be executed The method of any one of the first aspects of the present application.
  • an embodiment of the present application provides a computer program product, including a computer program, which implements the method described in any one of the first aspect of the present application when the computer program is executed by a processor.
  • the present application provides a design rule checking method, device, and storage medium, which are applied to the field of chip verification.
  • the method includes: acquiring a design rule checking DRC code file, analyzing multiple pieces of DRC code in the DRC code file, and analyzing the parsed multiple pieces of DRC code.
  • the DRC codes are classified to determine whether there is a code conflict in the multi-segment DRC codes, and if there is a code conflict, a code conflict report is generated, and the code conflict report is used to indicate the code location where the code conflict exists.
  • Fig. 1 is the schematic diagram of the existing DRC development process
  • FIG. 2 is a schematic diagram of a DRC development process provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a design rule checking method provided by an embodiment of the present application.
  • Fig. 4 is the distribution diagram 1 of the distance-based design rule in each inspection area of the chip
  • Fig. 5 is the distribution diagram 2 of the distance-based design rule in each inspection area of the chip
  • FIG. 6 is a schematic flowchart of another design rule checking method provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram 1 of a design rule checking device provided by an embodiment of the present application.
  • FIG. 8 is a second schematic structural diagram of a design rule checking device provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a hardware structure of a design rule checking apparatus provided by an embodiment of the present application.
  • switch control module switch control, SWC
  • sense amplifier sense amplify, SA
  • word line driver sub word-line driver, SWD
  • peripheral circuit
  • PERI peripheral
  • PERI includes: X-direction decoder (X-Decode, XDEC), Y-direction decoder (Y-Decode, Y-DEC), electrostatic impedance (electrostatic discharge, ESD), sealing ring Seal-Ring and so on.
  • Active area OD The area where active devices are made on the silicon wafer.
  • N-type metal-oxide-semiconductor N-Metal-Oxide-Semiconductor, NMOS.
  • the designer In the DRC development process, the designer generates a design rule check DRC code file based on the Design Rule Manual (DRM), and the DRC code file is used to verify whether the design of each check area of the chip meets the DRM requirements.
  • the DRC code file includes DRC codes corresponding to multiple design rules. There may be overlaps between DRC codes of the same design rule, such as including the same check items, and the DRC codes of the same design rule may conflict in different check areas. For example, the value ranges of the same check item are defined differently.
  • Table 1 is a design rule configuration table based on polysilicon POLY distance.
  • the design rule PO_S_01 defines the distance between runner POLYs greater than or equal to 0.2 ⁇ m
  • the design rule PO_S_05 defines the distance between POLYs greater than or equal to 0.2 ⁇ m. is equal to 0.185.
  • Design Rule ID definition Value range PO_S_01 Min-runner POLY to runner POLY spacing:SA,SWD,SWC ⁇ 0.2 PO_S_05 Min-POLY to POLY spacing ⁇ 0.185 PO_S_08 Min-POLY to POLY spacing:SA,SWD,SWC ⁇ 0.25 PO_S_28 Min-POLY to POLY spacing for NMOS in XDEC ⁇ 0.165 SL_S_01 Min-POLY to POLY spacing in seal ring 0.15 SL_S_02 Min-POLY to POLY spacing in outside seal ring ⁇ 0.35 PGRES_S_01 Min-POLY resistor to POLY resistor spacing in ESD region ⁇ 0.5
  • FIG 1 is a schematic diagram of the existing DRC development process.
  • the existing DRC development process after obtaining the above DRC code file, directly execute the DRC code file, and manually check and confirm the DRC code by generating a test graph There are possible errors. If the designer does not clearly define the design rules of DRM at the beginning of the chip design, it is easy to report errors in the verification process of the chip design. These errors may be on the order of millions. The above errors cannot occur when the chip design data is submitted. The designer needs to constantly revise the design parameters, execute the DRC code file many times, and verify the test results. The number of development iterations is huge and the development efficiency is low.
  • the present application provides a design rule checking method.
  • the inventor considers adding a design rule checking device to perform code analysis on the acquired DRC code file before generating a test image to find out conflicting DRC codes. section, generate the corresponding inspection report, so that the designer can revise the DRC code file or DRM based on the inspection report, avoid the conflict or redundancy of the DRC code in the DRC code file, improve the execution efficiency of the DRC code, and shorten it by at least 10%.
  • the development time of the DRC due to the reduction in the number of errors, also shortens the time to verify the test layout.
  • FIG. 2 is a schematic diagram of a DRC development process provided by an embodiment of the present application.
  • the design rule checking device intelligently detects the DRC code file based on the design rule checking scheme provided by the present application.
  • Code conflict or code redundancy if there is a code conflict or code redundancy in the DRC code file, a check report is generated to indicate the location of the error code or redundant code, waiting for the designer to correct the DRC code file or DRM.
  • the design rule checking device intelligently detects the DRC code file based on the design rule checking scheme provided by the present application.
  • Code conflict or code redundancy if there is a code conflict or code redundancy in the DRC code file, a check report is generated to indicate the location of the error code or redundant code, waiting for the designer to correct the DRC code file or DRM.
  • the verification process of the DRC code file enter the verification process of the DRC code file, generate a test pattern by executing the DRC code file, and verify whether the analysis test pattern meets the design
  • FIG. 3 is a schematic flowchart of a design rule checking method provided by an embodiment of the present application. As shown in FIG. 3 , the design rule checking method of the present embodiment mainly includes the following steps:
  • Step 101 Obtain a design rule check DRC code file.
  • the DRC code file of this embodiment includes multiple sections of DRC code, wherein each section of DRC code corresponds to a design rule.
  • the design rules include at least one design rule based on width, space, area, enclosure, and extend of semiconductor structures in the chip.
  • a DRC code file includes multiple pieces of DRC code based on different design rules, and there are situations where multiple DRC codes correspond to the same design rule.
  • the width-based design rule is used to define the width of the semiconductor structure, for example, to define the width of the semiconductor structure to be smaller than a predetermined width.
  • the distance-based design rule is used to define the distance between the semiconductor structures, for example, to define that the distance between the semiconductor structures is greater than a predetermined distance.
  • the area-based design rule is used to limit the area of the chip area occupied by the semiconductor structure, for example, the area of the chip area occupied by the semiconductor structure is limited to be smaller than a predetermined area value.
  • the design rule based on the inclusion relationship is used to define a positional relationship between semiconductors, for example, to define that a certain semiconductor structure also includes another semiconductor structure.
  • the extension relationship-based design rule is used to define another positional relationship between the semiconductors, for example, to limit the length of the polysilicon extending beyond the semiconductor layer to be greater than a preset length to avoid short circuits.
  • the semiconductor structure of this embodiment may be a semiconductor layer, a semiconductor module, a semiconductor device, etc., which is not limited by this embodiment of the present application.
  • each section of DRC code can be used to verify whether the semiconductor structures in a certain inspection area of the chip meet the design requirements, for example, DRC code section 1 is used to verify whether the distance between the semiconductor structures in the word line driver SWD of the chip meets the design requirements, DRC code segment 2 is used to verify whether the width of the semiconductor structure in the sense amplifier SA of the chip meets the design requirements, and DRC code segment 3 is used to verify whether the area of the chip occupied by the X-direction encoder of the chip meets the design requirements.
  • Step 102 parse multiple pieces of DRC code in the DRC code file.
  • Step 103 Classify the parsed DRC codes to determine whether there is a code conflict in the DRC codes.
  • step 104 is executed.
  • step 105 is executed.
  • Step 104 Generate a code conflict report, where the code conflict report is used to indicate a code location where a code conflict exists.
  • Step 105 Execute the DRC code file to generate a test pattern corresponding to the DRC code file.
  • the parsed multi-segment DRC codes can be classified to obtain the DRC code segment of each design rule; the DRC of each design rule is determined. Whether the code segment has code conflicts.
  • each segment of DRC code corresponds to a design rule
  • the derivative layer information of the design rule corresponding to each segment of DRC code is obtained, and the derivative layer information is used to indicate the logical operation of the DRC code. If the logical operations of the two DRC codes are the same, it can be determined that the design rules of the two DRC codes are the same design rule, and the two DRC codes can be classified into one category for subsequent code conflict analysis.
  • the check item is related to the type of design rule. If the design rule is a distance-based design rule, the check item is the distance between semiconductor structures. If the design rule is an area-based design rule, the check item is the area of the semiconductor structure. If the design rule is a width-based design rule, The check item is the width of the semiconductor structure.
  • the DRC codes whose derivation layer information indicates the distance operation are classified into one category, and the code conflict analysis is performed on the DRC code segments of this type of design rules.
  • the same check item in the DRC code segment of the distance-based design rule that is, the numerical range field of the distance between semiconductor structures is the same. If the value range fields are not identical, it is determined that there is a code conflict in the DRC code segment of this type of design rule; if the value range fields are all the same, it is determined that there is no code conflict in the DRC code segment of this type of design rule.
  • the multi-segment DRC code in the DRC code file is parsed to obtain the derived layer list of design rule PO_S_01 (see Table 2) and the derived layer list of design rule PO_S_08 (see Table 3).
  • the derived layer list defines the logical operation of the design rule.
  • PO represents polysilicon POLY
  • S represents the distance space.
  • PO_S_01_A and PO_S_08_A may indicate the reference layer of the chip in a certain inspection area
  • PO_S_01_B1 and PO_S_08_B1 may indicate the semiconductor layer of the chip in the inspection area SA
  • PO_S_01_B2 and PO_S_08_B2 may indicate that the chip is in the inspection area
  • the semiconductor layers of the SWD, PO_S_01_B3 and PO_S_08_B3 may represent the semiconductor layers of the chip in the inspection area SWC.
  • FIG. 4 is a distribution diagram 1 of the distance-based design rule in each inspection area of the chip.
  • the design rule PO_S_01 and the design rule PO_S_08 cover the three inspection areas of the chip, which are SWC, SA, SWD respectively.
  • the design rules PO_S_01 and PO_S_08 are both design rules based on the distance of the semiconductor structure in the chip.
  • the value range fields of the check items of the same design rule in different check areas or the same check area should be the same to avoid code conflicts in the DRC code segment.
  • other inspection areas of the chip may also correspond to other types of design rules, such as design rules based on area, extension relationship, etc. (not shown in FIG. 4 ), which is not limited in this embodiment of the present application.
  • the DRC codes corresponding to PO_S_01 and PO_S_08 can be classified into one category to perform code conflict analysis. It is necessary to further determine the check items (distance) in the DRC code segments corresponding to PO_S_01 and PO_S_08 are the same as the numeric range fields of .
  • Table 4 shows the limit of the numerical range of the check item (distance) between the derived layers of the design rules PO_S_01 and PO_S_08.
  • the DRC code in the DRC code file is parsed to obtain the derived layer list of the design rule PO_S_05 (see Table 5) and the derived layer list of the design rule SL_S_01 (see Table 6).
  • SL represents the sealing ring
  • pch POLY represents the polysilicon connected to the P-type MOS transistor
  • nch POLY represents the polysilicon connected to the N-type MOS transistor
  • drawing represents the connection on the chip.
  • test variables used in the logic operation of design rule PO_S_05 and design rule SL_S_01 include "POLY; SL", that is, these two design rules have the same check items, therefore, design rule PO_S_05 can be determined
  • design rule SL_S_01 is used to define the distance between semiconductor structures.
  • Table 7 shows the numerical range limitations of the check items (distances) between the derived layers of the design rules PO_S_05 and SL_S_01. Due to the thresholds of the distances, which are 0.185 ⁇ m and 0.15 ⁇ m, respectively, the threshold values are different, and the judgment conditions (i.e. judgment The symbols, such as the judgment symbol of PO_S_05 is greater than or equal to, and the judgment symbol of SL_S_01 is equal to) are also different. It can be determined that there is a code conflict between the DRC codes corresponding to the design rules PO_S_05 and SL_S_01, and a code conflict report needs to be generated.
  • the designer needs to adjust the DRC code of PO_S_05 or SL_S_01 according to the code conflict report, for example, unify the distance threshold and judgment conditions in PO_S_05 and SL_S_01; or delete the check item POLY in PO_S_05 or SL_S_01; SL is deleted, and then POLY is checked separately; SL determines the design rules.
  • the multi-segment DRC code in the DRC code file is parsed to obtain the derived layer list of design rule PO_S_05 (see Table 5) and the derived layer list of design rule PO_S_28 (see Table 8).
  • FIG. 5 is a distribution diagram of the distance-based design rule in each inspection area of the chip.
  • the inspection areas covered by the design rule PO_S_05 include: SWC, SA, SWD, and peripheral XDEC, YDEC , ESD, Seal-Ring, etc.
  • Design rule PO_S_28 covers the inspection area of the chip as the peripheral XDEC.
  • test variables used in the logic operations of design rule PO_S_05 and design rule PO_S_28 include "POLY; SL", that is, these two design rules have the same check items, therefore, design rule PO_S_05 can be determined
  • design rule PO_S_05 can be determined
  • the same design rule as design rule PO_S_28 is used to define the distance between semiconductor structures.
  • Table 9 shows the limitation of the numerical range of the check items (distances) between the derived layers of the design rules PO_S_05 and PO_S_28. Since the thresholds of the distances are 0.185 ⁇ m and 0.165 ⁇ m, respectively, and the thresholds are different, the design rules PO_S_05 and PO_S_28 can be determined. There is a code conflict in the corresponding DRC code, and a code conflict report needs to be generated. The designer needs to adjust the DRC code of PO_S_05 according to the code conflict report, such as removing NMOS in XDEC from the DRC code of PO_S_05.
  • confirming whether there is a code conflict in the DRC code segment is mainly to determine whether the value range fields with the same check items in the DRC code of the same design rule are different. If the value range fields of , are different, it can be determined that there is a code conflict in the DRC code segment of this design rule.
  • the value range field of the check item includes a value field and a relational field
  • the relational field includes greater than, equal to, less than, greater than or equal to, and less than or equal to.
  • the difference between the numerical range fields includes at least one of the numerical field and the relational field.
  • the DRC code file is checked by acquiring the design rule, the multi-segment DRC code in the DRC code file is parsed, the parsed multi-segment DRC code is classified, and it is determined whether there is a code conflict in the multi-segment DRC code , if there is a code conflict, a code conflict report is generated, and the code conflict report is used to indicate the code location where the code conflict exists.
  • the design rule checking method in addition to determining whether there is a code conflict in the multi-segment DRC codes, the design rule checking method also includes:
  • the designer can delete some DRC codes in the DRC code file according to the overlapping position indicated by the code overlap report to reduce the redundancy of the DRC code.
  • the design rule PGRES_S_01 in the DRM file is defined as Min-PO resistor to PO resistor spacing in ESD region.
  • the definition of the derivative layer PGRES_S_01_B of the design rule PGRES_S_01 is POLY and POLY;res, assuming that the derivative layer PO_S_28_B of the design rule PO_S_28 is also defined as POLY and POLY;res.
  • a code overlap report will be generated.
  • the designer can modify the derivative layer PGRES_S_01_B of PGRES_S_01 and define it as POLY and POLY; for res and ESD, modify the derivative layer PO_S_28_B of PO_S_28 and define it as POLY and POLY; res not ESD, so as to avoid code errors caused by unclear definition of the derived layer.
  • FIG. 6 is a schematic flowchart of another design rule checking method provided by an embodiment of the present application. As shown in FIG. 6 , after sending a code conflict report or a code overlap report, the design rule checking method of this embodiment further includes:
  • Step 201 Receive a DRC code update file, where the DRC code update file includes updates to DRC codes with code conflicts or code overlaps.
  • Step 202 Update the DRC code file according to the DRC code update file.
  • Step 203 Execute the updated DRC code file to generate a test pattern corresponding to the updated DRC code file, and the test pattern is used to verify whether the chip design meets the design requirements.
  • the update of the DRC code includes operations such as deletion, modification and addition of the DRC code.
  • the test pattern corresponding to the DRC code file can be understood as the layout of each area of the chip generated after the DRC code is executed. Usually, the check items of each design rule in the DRC code file are different. By updating the DRC code file, the layout of each area is continuously adjusted to verify the quality of the DRC code.
  • a DRC code file with a low error rate can be generated, and based on the optimized DRC code file, a test graph is generated to further verify the optimized DRC code, and the execution efficiency of the DRC code is improved. , while shortening the time for DRC development.
  • the design rule checking apparatus may be divided into functional modules according to the above method embodiments.
  • each functional module may be divided into each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, or can be implemented in the form of software function modules. It should be noted that, the division of modules in the embodiments of the present application is schematic, and is only a logical function division, and there may be other division manners in actual implementation. The following description will be given by using the division of each function module corresponding to each function as an example.
  • FIG. 7 is a schematic structural diagram 1 of a design rule checking apparatus provided by an embodiment of the present application.
  • the design rule checking apparatus 300 in this embodiment includes: an acquisition module 301 and a processing module 302 .
  • an obtaining module 301 configured to obtain a design rule check (DRC) code file
  • a processing module 302 configured to parse the multi-section DRC codes in the DRC code file, classify the parsed multi-section DRC codes, and determine whether there is a code conflict in the multi-section DRC codes;
  • a code conflict report is generated, and the code conflict report is used to indicate the code location where the code conflict exists.
  • processing module 302 is specifically configured to:
  • the design rule includes at least one design rule based on the width and area of the semiconductor structures in the chip, the distance, the inclusion relationship, and the extension relationship between the semiconductor structures.
  • processing module 302 is specifically configured to:
  • processing module 302 is further configured to:
  • FIG. 8 is a second schematic structural diagram of a design rule checking apparatus provided by an embodiment of the present application. Based on the device shown in FIG. 7 , as shown in FIG. 8 , the design rule checking device 300 of this embodiment further includes: a receiving module 303 ;
  • a receiving module 303 for receiving a DRC code update file, the DRC code update file including an update to the DRC code with code conflict or code overlap;
  • the processing module 302 is further configured to update the DRC code file according to the DRC code update file;
  • the updated DRC code file is executed, and a test pattern corresponding to the updated DRC code file is generated, and the test pattern is used to verify whether the chip design meets the design requirements.
  • the design rule checking device provided in the embodiment of the present application is used to execute each step of the foregoing method embodiment, and its implementation principle and technical effect are similar, and details are not described herein again.
  • FIG. 9 is a schematic diagram of a hardware structure of a design rule checking apparatus provided by an embodiment of the present application.
  • the design rule checking device 400 of this embodiment includes:
  • processor 401 (only one processor is shown in Figure 9);
  • a memory 402 in communication with the at least one processor;
  • the memory 402 stores instructions executable by the at least one processor 401, and the instructions are executed by the at least one processor 401 to enable the design rule checking apparatus 400 to perform various steps of the foregoing method embodiments .
  • the memory 402 may be independent or integrated with the processor 401 .
  • the design rule checking apparatus 400 further includes: a bus 403 for connecting the memory 402 and the processor 401 .
  • Embodiments of the present application further provide a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, each step of the foregoing method embodiments is implemented.
  • Embodiments of the present application provide a computer program product, including a computer program, which implements each step of the foregoing method embodiments when the computer program is executed by a processor.
  • Embodiments of the present application further provide a chip, including: a processing module and a communication interface, where the processing module can execute the technical solutions in the foregoing method embodiments.
  • the chip also includes a storage module (eg, memory), the storage module is used for storing instructions, the processing module is used for executing the instructions stored in the storage module, and the execution of the instructions stored in the storage module causes the processing module to execute the aforementioned method implementation.
  • a storage module eg, memory
  • the storage module is used for storing instructions
  • the processing module is used for executing the instructions stored in the storage module
  • the execution of the instructions stored in the storage module causes the processing module to execute the aforementioned method implementation.
  • processors mentioned in the embodiments of the present application may be a central processing unit (Central Processing Unit, CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application-specific integrated circuits ( Application Specific Integrated Circuit, ASIC), off-the-shelf Programmable Gate Array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically programmable read-only memory (Erasable PROM, EPROM). Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be Random Access Memory (RAM), which acts as an external cache.
  • RAM Static RAM
  • DRAM Dynamic RAM
  • SDRAM Synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDR SDRAM
  • enhanced SDRAM ESDRAM
  • synchronous link dynamic random access memory Synchlink DRAM, SLDRAM
  • Direct Rambus RAM Direct Rambus RAM
  • the bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, or the like.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the buses in the drawings of the present application are not limited to only one bus or one type of bus.
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components
  • the memory storage module
  • memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.
  • the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.

Abstract

一种设计规则检查方法、装置（300，400）及存储介质，应用于芯片验证领域，该方法包括：获取设计规则检查DRC代码文件（101），对DRC代码文件中的多段DRC代码进行解析，对解析后的多段DRC代码进行分类（102），确定多段DRC代码中是否存在代码冲突（103），若存在代码冲突，生成代码冲突报告，代码冲突报告用于指示存在代码冲突的代码位置（104）。利用上述方法，可实现对DRC代码文件中的代码错误的快速检查和定位，辅助测试人员对DRM文件以及DRC文件的修正，提升DRC代码的执行效率，同时缩短了DRC开发的时间。

Description

设计规则检查方法、装置及存储介质
本申请要求于2021年02月22日提交中国专利局、申请号为202110197091.2、申请名称为“设计规则检查方法、装置及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片验证领域，尤其涉及一种设计规则检查方法、装置及存储介质。
背景技术
一般的芯片设计都是采用签核(sign off)流程，即设计数据完成时，通过设计规则检查(design rule check，DRC)，来检查当前设计是否违反设计规则。
现有方案中，通过执行设计规则检查DRC代码文件，生成测试图形，确定存在错误的测试图形，设计人员基于测试图形进行设计规则及DRC代码的优化。通常在设计之初，可能会有百万级数量的错误，设计人员需要逐个查看错误，造成芯片设计周期的延长。
发明内容
本申请提供一种设计规则检查方法、装置及存储介质，实现对DRC代码的错误检查和定位。
第一方面，本申请实施例提供一种设计规则检查方法，包括：
获取设计规则检查(DRC)代码文件；
对所述DRC代码文件中的多段DRC代码进行解析，对解析后的所述多段DRC代码进行分类，确定所述多段DRC代码是否存在代码冲突；
若存在代码冲突，生成代码冲突报告，所述代码冲突报告用于指示存在代码冲突的代码位置。
在本申请的一个实施例中，所述对解析后的所述多段DRC代码进行分类，确定所述多段DRC代码是否存在代码冲突，包括：
根据每段DRC代码对应的设计规则的类型，对解析后的所述多段DRC代码进行分类，得到每种设计规则的DRC代码段；
确定每一种设计规则的DRC代码段是否存在代码冲突。
在本申请的一个实施例中，所述设计规则包括基于芯片中半导体结构的宽度、面积，半导体结构之间的距离、包含关系、延伸关系的至少一项设计规则。
在本申请的一个实施例中，所述确定每一种设计规则的DRC代码段是否存在代码冲突，包括：
确定每一种设计规则的DRC代码段中同一检查项的数值范围字段是否相同，若同一检查项的数值范围字段不完全相同，确定所述DRC代码段存在代码冲突。
在本申请的一个实施例中，所述方法还包括：
确定所述多段DRC代码是否存在代码重叠，若存在代码重叠，生成代码重叠报告， 所述代码重叠报告用于指示存在代码重叠的代码位置。
在本申请的一个实施例中，所述方法还包括：
接收DRC代码更新文件，所述DRC代码更新文件包括对存在代码冲突或代码重叠的DRC代码的更新；
根据所述DRC代码更新文件，更新所述DRC代码文件；
执行更新后的DRC代码文件，生成更新后的DRC代码文件对应的测试图形，所述测试图形用于验证芯片设计是否满足设计要求。
第二方面，本申请实施例提供一种设计规则检查装置，包括：
获取模块，用于获取设计规则检查(DRC)代码文件；
处理模块，用于对所述DRC代码文件中的多段DRC代码进行解析，对解析后的所述多段DRC代码进行分类，确定所述多段DRC代码是否存在代码冲突；
若存在代码冲突，生成代码冲突报告，所述代码冲突报告用于指示存在代码冲突的代码位置。
在本申请的一个实施例中，所述处理模块，具体用于：
根据每段DRC代码对应的设计规则的类型，对解析后的所述多段DRC代码进行分类，得到每种设计规则的DRC代码段；
确定每一种设计规则的DRC代码段是否存在代码冲突。
在本申请的一个实施例中，所述设计规则包括基于芯片中半导体结构的宽度、面积，半导体结构之间的距离、包含关系、延伸关系的至少一项设计规则。
在本申请的一个实施例中，所述处理模块，具体用于：
确定每一种设计规则的DRC代码段中同一检查项的数值范围字段是否相同，若同一检查项的数值范围字段不完全相同，确定所述DRC代码段存在代码冲突。
在本申请的一个实施例中，所述处理模块，还用于：
确定所述多段DRC代码是否存在代码重叠，若存在代码重叠，生成代码重叠报告，所述代码重叠报告用于指示存在代码重叠的代码位置。
在本申请的一个实施例中，所述装置还包括：接收模块；
接收模块，用于接收DRC代码更新文件，所述DRC代码更新文件包括对存在代码冲突或代码重叠的DRC代码的更新；
所述处理模块，还用于根据所述DRC代码更新文件，更新所述DRC代码文件；
执行更新后的DRC代码文件，生成更新后的DRC代码文件对应的测试图形，所述测试图形用于验证芯片设计是否满足设计要求。
第三方面，本申请实施例提供一种设计规则检查装置，包括：
至少一个处理器；以及
与所述至少一个处理器通信连接的存储器；其中，
所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述设计规则检查装置能够执行本申请第一方面中任一项所述的方法。
第四方面，本申请实施例提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当所述计算机执行指令被处理器执行时，使得所述处理 器能够执行本申请第一方面中任一项所述的方法。
第五方面，本申请实施例提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时实现本申请第一方面中任一项所述的方法。
本申请提供一种设计规则检查方法、装置及存储介质，应用于芯片验证领域，该方法包括：获取设计规则检查DRC代码文件，对DRC代码文件中的多段DRC代码进行解析，对解析后的多段DRC代码进行分类，确定多段DRC代码中是否存在代码冲突，若存在代码冲突，生成代码冲突报告，代码冲突报告用于指示存在代码冲突的代码位置。利用上述方法，可实现对DRC代码文件中的代码错误的快速检查和定位，辅助测试人员对DRM文件以及DRC文件的修正，提升DRC代码的执行效率，同时缩短了DRC开发的时间。
附图说明
图1为现有的DRC开发流程的示意图；
图2为本申请实施例提供的DRC开发流程的示意图；
图3为本申请实施例提供的一种设计规则检查方法的流程示意图；
图4为基于距离的设计规则在芯片各检查区域的分布图一；
图5为基于距离的设计规则在芯片各检查区域的分布图二；
图6为本申请实施例提供的另一种设计规则检查方法的流程示意图；
图7为本申请实施例提供的设计规则检查装置的结构示意图一；
图8为本申请实施例提供的设计规则检查装置的结构示意图二；
图9为本申请实施例提供的一种设计规则检查装置的硬件结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
首先对本申请实施例的相关术语进行简要介绍。
芯片设计中涉及如下几个检查区域：开关控制模块(switch control,SWC)、感应放大器(sense amplify,SA)字线驱动器(sub word-line driver,SWD)、外围(电路)(peripheral,PERI)。
其中PERI包括：X方向译码器(X-Decode,XDEC)、Y方向译码器(Y-Decode,Y-DEC)、静电阻抗器(electrostatic discharge,ESD)、密封圈Seal-Ring等。
有源区OD：硅片上做有源器件的区域。
N型金属-氧化物-半导体：N-Metal-Oxide-Semiconductor，NMOS。
在DRC开发流程中，设计人员基于设计规则手册(Design Rule Manual，DRM)生成设计规则检查DRC代码文件，DRC代码文件用于验证芯片各个检查区域的设计是否满足DRM的要求。DRC代码文件中包括多种设计规则对应的DRC代码，同种设计规则的DRC代码之间可能存在重叠，例如包含相同的检查项，同种设计规则的DRC代码在不同的检查区域可能存在冲突，例如同一检查项的数值范围定义不同。
示例性的，表1为基于多晶硅POLY距离的设计规则配置表，如表1所示，设计规则PO_S_01定义runner POLY之间的距离大于或等于0.2μm，设计规则PO_S_05定义POLY之间的距离大于或等于0.185。这几条设计规则可以使用相似的DRC代码实现。不过，如果在设计过程中没有清晰地区分这些设计规则，在验证版图时就报错，从而增加开发的迭代次数，延长开发时间。
表1
设计规则ID 定义 数值范围
PO_S_01 Min-runner POLY to runner POLY spacing:SA,SWD,SWC ≥0.2
PO_S_05 Min-POLY to POLY spacing ≥0.185
PO_S_08 Min-POLY to POLY spacing:SA,SWD,SWC ≥0.25
PO_S_28 Min-POLY to POLY spacing for NMOS in XDEC ≥0.165
SL_S_01 Min-POLY to POLY spacing in seal ring ＝0.15
SL_S_02 Min-POLY to POLY spacing in outside seal ring ≥0.35
PGRES_S_01 Min-POLY resistor to POLY resistor spacing in ESD region ≥0.5
图1为现有的DRC开发流程的示意图，如图1所示，现有的DRC开发流程，在获取上述DRC代码文件后，直接执行DRC代码文件，通过生成测试图形，人工查看并确认DRC代码中有可能的错误。如果设计人员在芯片设计之初，没有将DRM的设计规则定义清楚，很容易在芯片设计的验证环节报出错误，这些错误有可能是百万级数量的。芯片设计数据在提交时不能出现上述错误，设计人员需要不断修正设计参数，多次执行DRC代码文件、验证测试结果，开发的迭代次数量巨大，开发效率低。
为了解决上述问题，本申请提供一种设计规则检查方法，发明人考虑在生成测试图像之前，增加一个设计规则检查装置，用于对获取的DRC代码文件进行代码分析，查找出存在冲突的DRC代码段，生成相应的检查报告，以便设计人员基于检查报告，对DRC代码文件或DRM进行修正，避免DRC代码文件中的DRC代码存在冲突或冗余，提升DRC代码执行效率的同时，缩短至少10％的DRC开发时间，由于报错数量减少，也缩短了验证测试版图的时间。
图2为本申请实施例提供的DRC开发流程的示意图，如图2所示，设计规则检查装置在获取DRC代码文件后，基于本申请提供的设计规则检查方案，智能化检测DRC代码文件中的代码冲突或代码冗余，若DRC代码文件中存在代码冲突或代码冗余，则生成检查报告，用于指示出错代码或冗余代码的位置，等待设计人员修正DRC代码文件或者DRM。 通过上述修正，在DRC代码文件不存在代码冲突或代码冗余时，再进入DRC代码文件的验证流程，通过执行DRC代码文件生成测试图形，验证分析测试图形是否满足设计要求，若不满足设计要求，则生成分析报告，等待设计人员修正DRC代码文件或者DRM。若满足设计要求，则结束设计流程。
下面以具体地实施例对本申请提供的设计规则检查方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图3为本申请实施例提供的一种设计规则检查方法的流程示意图，如图3所示，本实施例的设计规则检查方法主要包括以下几个步骤：
步骤101、获取设计规则检查DRC代码文件。
本实施例的DRC代码文件包括多段DRC代码，其中每段DRC代码对应一种设计规则。在芯片设计领域，设计规则包括基于芯片中半导体结构的宽度(width)、距离(space)、面积(area)、包含关系(enclosure)、延伸关系(extend)的至少一项设计规则。通常情况下，DRC代码文件包括基于不同设计规则的多段DRC代码，存在多个DRC代码对应同种设计规则的情况。
基于宽度的设计规则用于限定半导体结构的宽度，例如限定半导体结构的宽度小于预设宽度。
基于距离的设计规则用于限定半导体结构之间的距离，例如限定半导体结构之间的距离大于预设距离。
基于面积的设计规则用于限定半导体结构占用芯片区域的面积，例如限定半导体结构占用芯片区域的面积小于预设面积值。
基于包含关系的设计规则用于限定半导体之间的一种位置关系，例如限定某个半导体结构内还包含另一半导体结构。
基于延伸关系的设计规则用于限定半导体之间的另一种位置关系，例如限定多晶硅延伸到半导体层之外的长度大于预设长度，避免短路。
本实施例的半导体结构可以是半导体层、半导体模块、半导体器件等，对此本申请实施例不作任何限制。
应理解，每段DRC代码可用于验证芯片的某一检查区域中半导体结构是否满足设计要求，例如DRC代码段1用于验证芯片的字线驱动器SWD中半导体结构之间的距离是否满足设计要求，DRC代码段2用于验证芯片的感应放大器SA中的半导体结构的宽度是否满足设计要求，DRC代码段3用于验证芯片的X方向编码器占用芯片的面积是否满足设计要求等。
步骤102、对DRC代码文件中的多段DRC代码进行解析。
步骤103、对解析后的多段DRC代码进行分类，确定多段DRC代码是否存在代码冲突。
若存在代码冲突，执行步骤104。
若不存在代码冲突，执行步骤105。
步骤104、生成代码冲突报告，代码冲突报告用于指示存在代码冲突的代码位置。
步骤105、执行DRC代码文件，生成DRC代码文件对应的测试图形。
在本申请的一个实施例中，可根据每段DRC代码对应的设计规则的类型，对解析后的多段DRC代码进行分类，得到每种设计规则的DRC代码段；确定每一种设计规则的DRC代码段是否存在代码冲突。
本实施例中，每段DRC代码对应一种设计规则，通过对每段DRC代码进行解析，得到每段DRC代码对应的设计规则的衍生层信息，衍生层信息用于指示DRC代码的逻辑运算。若两段DRC代码的逻辑运算相同，可以确定这两段DRC代码的设计规则为同种设计规则，可将这两段DRC代码分为一类，进行后续代码冲突分析。
具体可通过如下方式确定每一种设计规则的DRC代码段是否存在代码冲突：确定每一种设计规则的DRC代码段中同一检查项的数值范围字段是否相同。若同种设计规则的DRC代码段中的同一检查项的数值范围字段不完全相同，确定该设计规则的DRC代码段存在代码冲突；若同种设计规则的DRC代码段中的同一检查项的数值范围字段相同，确定该设计规则的DRC代码段不存在代码冲突。
本实施例中，检查项与设计规则的类型有关。若设计规则为基于距离的设计规则，其检查项为半导体结构之间的距离，若设计规则为基于面积的设计规则，其检查项为半导体结构的面积，若设计规则为基于宽度的设计规则，其检查项为半导体结构的宽度。
示例性的，以基于距离的设计规则为例，通过对多段DRC代码进行解析，将衍生层信息指示距离运算的DRC代码归为一类，这对该类设计规则的DRC代码段进行代码冲突分析，确定基于距离的设计规则的DRC代码段中同一检查项，即半导体结构之间的距离的数值范围字段是否相同。若数值范围字段不完全相同，确定该类设计规则的DRC代码段存在代码冲突；若数值范围字段均相同，确定该类设计规则的DRC代码段不存在代码冲突。
下面结合几个具体的示例，对上述实施例的技术方案进行详细说明。
作为一种示例，对DRC代码文件中的多段DRC代码进行解析，得到设计规则PO_S_01的衍生层列表(见表2)，以及设计规则PO_S_08的衍生层列表(见表3)。衍生层列表定义了设计规则的逻辑运算。其中，PO表示多晶硅POLY，S表示距离space。
表2
PO_S_01的衍生层 定义
PO_S_01_A Copy POLY
PO_S_01_B1 ((POLY not POLY；dummy)not OD)and SA
PO_S_01_B2 ((POLY not POLY；dummy)not OD)and SWD
PO_S_01_B3 ((POLY not POLY；dummy)not OD)and SWC
表3
PO_S_08的衍生层 定义
PO_S_08_A Copy POLY
PO_S_08_B1 ((POLY not POLY；dummy)not OD)and SA
PO_S_08_B2 ((POLY not POLY；dummy)not OD)and SWD
PO_S_08_B3 ((POLY not POLY；dummy)not OD)and SWC
需要说明的是，表2和表3中，PO_S_01_A以及PO_S_08_A可表示芯片在某一检查区域的基准层，PO_S_01_B1以及PO_S_08_B1可表示芯片在检查区域SA的半导体层，PO_S_01_B2以及PO_S_08_B2可表示芯片在检查区域SWD的半导体层，PO_S_01_B3以及PO_S_08_B3可表示芯片在检查区域SWC的半导体层。
对比表2和表3，设计规则PO_S_01和PO_S_08的逻辑运算相同，因此，可确定设计规则PO_S_01和PO_S_08为同种设计规则，均用于限定半导体结构之间的距离。
示例性的，图4为基于距离的设计规则在芯片各检查区域的分布图一，如图4所示，设计规则PO_S_01和设计规则PO_S_08覆盖芯片的三个检查区域，分别为SWC、SA、SWD，结合表2和表3可知，设计规则PO_S_01和PO_S_08均为基于芯片中半导体结构的距离的设计规则。同种设计规则在不同检查区域或者相同检查区域的检查项的数值范围字段应相同，以避免DRC代码段的代码冲突。应理解，芯片的其他检查区域还可以对应其他类型的设计规则，例如基于面积、延伸关系等的设计规则(图4未示出)，对此本申请实施例不作任何限制。
在本示例中，由于PO_S_01和PO_S_08的逻辑运算相同，可以将PO_S_01和PO_S_08对应的DRC代码归为一类，进行代码冲突分析，需要进一步确定PO_S_01和PO_S_08对应的DRC代码段中检查项(距离)的数值范围字段是否相同。表4示出了设计规则PO_S_01和PO_S_08的衍生层之间的检查项(距离)的数值范围限制，由于距离的阈值，分别为0.2μm和0.25μm，阈值大小不相同，可确定PO_S_01和PO_S_08对应的DRC代码段存在代码冲突，需要生成代码冲突报告。其中，导致代码冲突的原因主要有两种：一是两种设计规则对应的DRC代码有错误，二是这两种设计规则本身有错误。因此，设计人员需要根据代码冲突报告，对DRC代码或DRM进行手动修正。
表4
Figure PCTCN2021103734-appb-000001
上述示例示出了基于距离的设计规则的规则定义不同，将导致DRC代码冲突的情况，如表4所示，设计规则定义的检查区域相同时，会出现检查项的数值范围字段的阈值大小不同，设计人员需要及时修正DRC代码中的代码冲突字段。
作为另一种示例，对DRC代码文件中的多段DRC代码进行解析，得到设计规则PO_S_05的衍生层列表(见表5)，以及设计规则SL_S_01的衍生层列表(见表6)。其中，SL表示密封圈Seal ring，pch POLY表示连接P型MOS管的多晶硅，nch POLY表示连接N型MOS管的多晶硅，drawing表示芯片上的连线。
表5
PO_S_05的衍生层 定义
PO_S_05_A Copy POLY
PO_S_05_B (or POLY；pch POLY；nch POLY；SL POLY；drawing)not OD
表6
SL_S_01的衍生层 定义
SL_S_01_A Copy POLY
SL_S_01_B POLY；SL and SealRing
表5和表6中，设计规则PO_S_05和设计规则SL_S_01的逻辑运算中所用的测试变量中均包括“POLY；SL”，即这两条设计规则有相同的检查项，因此，可确定设计规则PO_S_05和设计规则SL_S_01为同种设计规则，均用于限定半导体结构之间的距离。
表7
设计规则ID 衍生层A 衍生层B 检查项 数值
PO_S_05 PO_S_05_A PO_S_05_B 距离 ≥0.185
SL_S_01 SL_S_01_A SL_S_01_B 距离 ＝0.15
表7示出了设计规则PO_S_05和SL_S_01的衍生层之间的检查项(距离)的数值范围限制，由于距离的阈值，分别为0.185μm和0.15μm，阈值大小不相同，且判断条件(即判断符号，如PO_S_05的判断符号是大于或等于，SL_S_01的判断符号是等于)也不同，可确定设计规则PO_S_05和SL_S_01对应的DRC代码存在代码冲突，需要生成代码冲突报告。设计人员需要根据代码冲突报告，调整PO_S_05或者SL_S_01的DRC代码，例如将PO_S_05和SL_S_01中的距离阈值和判断条件进行统一；或者将PO_S_05或SL_S_01中的检查项POLY；SL删除，再单独对POLY；SL确定设计规则。
上述示例示出了基于距离的设计规则的检查层次有重叠，检查项的数值范围限定不同，将导致DRC代码冲突的情况，如表7所示，两条设计规则所用的测试变量“POLY；SL”有重叠，可以通过修正其中一条设计规则的DRC代码避免代码冲突，例如修正PO_S_05的DRC代码，将POLY；SL删除，在SL_S_01单独进行距离的检查。
作为另一种示例，对DRC代码文件中的多段DRC代码进行解析，得到设计规则PO_S_05的衍生层列表(见表5)，设计规则PO_S_28的衍生层列表(见表8)。
表8
Figure PCTCN2021103734-appb-000002
示例性的，图5为基于距离的设计规则在芯片各检查区域的分布图二，如图5所示，设计规则PO_S_05覆盖芯片的检查区域有：SWC、SA、SWD、以及外围的XDEC、YDEC、ESD、Seal-Ring等。设计规则PO_S_28覆盖芯片的检查区域为外围的XDEC。
表5和表8中，设计规则PO_S_05和设计规则PO_S_28的逻辑运算中所用的测试变量中均包括“POLY；SL”，即这两条设计规则有相同的检查项，因此，可确定设计规则PO_S_05和设计规则PO_S_28为同种设计规则，均用于限定半导体结构之间的距离。
表9
Figure PCTCN2021103734-appb-000003
表9示出了设计规则PO_S_05和PO_S_28的衍生层之间的检查项(距离)的数值范围限定，由于距离的阈值，分别为0.185μm和0.165μm，阈值大小不同，可确定设计规则PO_S_05和PO_S_28对应的DRC代码存在代码冲突，需要生成代码冲突报告。设计人员需要根据代 码冲突报告，调整PO_S_05的DRC代码，例如从PO_S_05的DRC代码中删除XDEC中的NMOS。
上述示例示出了基于距离的设计规则的检查区域有重叠，检查项的数值范围限定不同，将导致DRC代码冲突的情况，可通过修正其中一条设计规则的DRC代码避免代码冲突，例如修正PO_S_05的DRC代码，将XDEC中的NMOS代码删除。
基于上述各个示例可知，确认DRC代码段是否存在代码冲突主要是确定同种设计规则的DRC代码中具有相同检查项的数值范围字段是否存在不同，若同种设计规则的两条规则中相同检查项的数值范围字段存在不同，可确定该设计规则的DRC代码段存在代码冲突。
需要指出的是，检查项的数值范围字段包括数值字段和关系字段，关系字段包括大于、等于、小于、大于等于、小于等于。数值范围字段的不同包括数值字段、关系字段的至少一项不同。
本实施例提供的设计规则检查方法，通过获取设计规则检查DRC代码文件，对DRC代码文件中的多段DRC代码进行解析，对解析后的多段DRC代码进行分类，确定多段DRC代码中是否存在代码冲突，若存在代码冲突，生成代码冲突报告，代码冲突报告用于指示存在代码冲突的代码位置。利用上述方法，可实现对DRC代码文件中的代码错误的快速检查和定位，辅助测试人员对DRM文件以及DRC文件的修正，提升DRC代码的执行效率，同时缩短了DRC开发的时间。
可选的，在上述实施例的基础上，除了确定多段DRC代码是否存在代码冲突之外，设计规则检查方法还包括：
确定多段DRC代码是否存在代码重叠，若存在代码重叠，生成代码重叠报告，代码重叠报告用于指示存在代码重叠的代码位置。设计人员可根据代码重叠报告指示的重叠位置，删除DRC代码文件中的部分DRC代码，减少DRC代码的冗余。
示例性的，如表1所示，DRM文件中设计规则PGRES_S_01的定义为Min-PO resistor to PO resistor spacing in ESD region。在解析设计规则PGRES_S_01对应的DRC代码后，得到设计规则PGRES_S_01的衍生层PGRES_S_01_B的定义为POLY and POLY；res，假设设计规则PO_S_28的衍生层PO_S_28_B定义也为POLY and POLY；res。基于上述实施例的设计规则检查方案，将生成代码重叠报告，设计人员可基于代码重叠报告，修正PGRES_S_01的衍生层PGRES_S_01_B定义为POLY and POLY；res and ESD，修正PO_S_28的衍生层PO_S_28_B定义为POLY and POLY；res not ESD，从而避免由于衍生层定义不清楚导致的代码报错。
图6为本申请实施例提供的另一种设计规则检查方法的流程示意图，如图6所示，在发送代码冲突报告或代码重叠报告之后，本实施例的设计规则检查方法还包括：
步骤201、接收DRC代码更新文件，DRC代码更新文件包括对存在代码冲突或代码重叠的DRC代码的更新。
步骤202、根据DRC代码更新文件，更新DRC代码文件。
步骤203、执行更新后的DRC代码文件，生成更新后的DRC代码文件对应的测试图形，测试图形用于验证芯片设计是否满足设计要求。
对DRC代码的更新包括：对DRC代码的删除、修改、增加等操作。
DRC代码文件对应的测试图形可以理解为执行DRC代码后生成的芯片各区域的版图。通常情况下，DRC代码文件中的每条设计规则的检查项是不同的，通过对DRC代码文件的 更新，不断调整各区域的版图，验证DRC代码的质量。
通过本实施例对DRC代码文件的优化更新，可生成报错率较低的DRC代码文件，基于优化后的DRC代码文件，生成测试图形，进一步验证优化后的DRC代码，提高了DRC代码的执行效率，同时缩短了DRC开发的时间。
本申请实施例可以根据上述方法实施例对设计规则检查装置进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以使用硬件的形式实现，也可以使用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。下面以使用对应各个功能划分各个功能模块为例进行说明。
图7为本申请实施例提供的设计规则检查装置的结构示意图一。如图7所示，本实施例的设计规则检查装置300，包括：获取模块301和处理模块302。
获取模块301，用于获取设计规则检查(DRC)代码文件；
处理模块302，用于对所述DRC代码文件中的多段DRC代码进行解析，对解析后的所述多段DRC代码进行分类，确定所述多段DRC代码是否存在代码冲突；
若存在代码冲突，生成代码冲突报告，所述代码冲突报告用于指示存在代码冲突的代码位置。
在本申请的一个实施例中，所述处理模块302，具体用于：
根据每段DRC代码对应的设计规则的类型，对解析后的所述多段DRC代码进行分类，得到每种设计规则的DRC代码段；
确定每一种设计规则的DRC代码段是否存在代码冲突。
在本申请的一个实施例中，所述设计规则包括基于芯片中半导体结构的宽度、面积，半导体结构之间的距离、包含关系、延伸关系的至少一项设计规则。
在本申请的一个实施例中，所述处理模块302，具体用于：
确定每一种设计规则的DRC代码段中同一检查项的数值范围字段是否相同，若同一检查项的数值范围字段不完全相同，确定所述DRC代码段存在代码冲突。
在本申请的一个实施例中，所述处理模块302，还用于：
确定所述多段DRC代码是否存在代码重叠，若存在代码重叠，生成代码重叠报告，所述代码重叠报告用于指示存在代码重叠的代码位置。
图8为本申请实施例提供的设计规则检查装置的结构示意图二。在图7所示装置的基础上，如图8所示，本实施例的设计规则检查装置300，还包括：接收模块303；
接收模块303，用于接收DRC代码更新文件，所述DRC代码更新文件包括对存在代码冲突或代码重叠的DRC代码的更新；
所述处理模块302，还用于根据所述DRC代码更新文件，更新所述DRC代码文件；
执行更新后的DRC代码文件，生成更新后的DRC代码文件对应的测试图形，所述测试图形用于验证芯片设计是否满足设计要求。
本申请实施例提供的设计规则检查装置，用于执行前述方法实施例的各个步骤，其实现原理和技术效果类似，在此不再赘述。
图9为本申请实施例提供的一种设计规则检查装置的硬件结构示意图。如图9所示，本 实施例的设计规则检查装置400，包括：
至少一个处理器401(图9中仅示出了一个处理器)；以及
与所述至少一个处理器通信连接的存储器402；其中，
所述存储器402存储有可被所述至少一个处理器401执行的指令，所述指令被所述至少一个处理器401执行，以使所述设计规则检查装置400能够执行前述方法实施例的各个步骤。
可选的，存储器402既可以是独立的，也可以跟处理器401集成在一起。
当存储器402是独立于处理器401之外的器件时，设计规则检查装置400还包括：总线403，用于连接存储器402和处理器401。
本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当所述计算机执行指令被处理器执行时实现前述方法实施例的各个步骤。
本申请实施例提供一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时实现前述方法实施例的各个步骤。
本申请实施例还提供了一种芯片，包括：处理模块与通信接口，该处理模块能执行前述方法实施例中的技术方案。
进一步地，该芯片还包括存储模块(如，存储器)，存储模块用于存储指令，处理模块用于执行存储模块存储的指令，并且对存储模块中存储的指令的执行使得处理模块执行前述方法实施例中的技术方案。
应理解，本申请实施例中提及的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
总线可以是工业标准体系结构(Industry Standard Architecture，ISA)总线、外部设备互连(Peripheral Component，PCI)总线或扩展工业标准体系结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，本申请附图中的总线并不限定仅有一根总线或一种类型的总线。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、 分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)集成在处理器中。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (13)

  1. 一种设计规则检查方法，包括：
    获取设计规则检查(DRC)代码文件；
    对所述DRC代码文件中的多段DRC代码进行解析，对解析后的所述多段DRC代码进行分类，确定所述多段DRC代码是否存在代码冲突；
    若存在代码冲突，生成代码冲突报告，所述代码冲突报告用于指示存在代码冲突的代码位置。
  2. 根据权利要求1所述的方法，其中，所述对解析后的所述多段DRC代码进行分类，确定所述多段DRC代码是否存在代码冲突，包括：
    根据每段DRC代码对应的设计规则的类型，对解析后的所述多段DRC代码进行分类，得到每种设计规则的DRC代码段；
    确定每一种设计规则的DRC代码段是否存在代码冲突。
  3. 根据权利要求2所述的方法，其中，所述设计规则包括基于芯片中半导体结构的宽度、面积，半导体结构之间的距离、包含关系、延伸关系的至少一项设计规则。
  4. 根据权利要求2所述的方法，其中，所述确定每一种设计规则的DRC代码段是否存在代码冲突，包括：
    确定每一种设计规则的DRC代码段中同一检查项的数值范围字段是否相同，若同一检查项的数值范围字段不完全相同，确定所述DRC代码段存在代码冲突。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：
    确定所述多段DRC代码是否存在代码重叠，若存在代码重叠，生成代码重叠报告，所述代码重叠报告用于指示存在代码重叠的代码位置。
  6. 根据权利要求1所述的方法，其中，所述方法还包括：
    接收DRC代码更新文件，所述DRC代码更新文件包括对存在代码冲突或代码重叠的DRC代码的更新；
    根据所述DRC代码更新文件，更新所述DRC代码文件；
    执行更新后的DRC代码文件，生成更新后的DRC代码文件对应的测试图形，所述测试图形用于验证芯片设计是否满足设计要求。
  7. 一种设计规则检查装置，包括：
    获取模块，用于获取设计规则检查(DRC)代码文件；
    处理模块，用于对所述DRC代码文件中的多段DRC代码进行解析，对解析后的所述多段DRC代码进行分类，确定所述多段DRC代码是否存在代码冲突；
    若存在代码冲突，生成代码冲突报告，所述代码冲突报告用于指示存在代码冲突的代码位置。
  8. 根据权利要求7所述的装置，其中，所述处理模块，具体用于：
    根据每段DRC代码对应的设计规则的类型，对解析后的所述多段DRC代码进行分类，得到每种设计规则的DRC代码段；
    确定每一种设计规则的DRC代码段是否存在代码冲突。
  9. 根据权利要求8所述的装置，其中，所述设计规则包括基于芯片中半导体结构的宽度、面积，半导体结构之间的距离、包含关系、延伸关系的至少一项设计规则。
  10. 根据权利要求8所述的装置，其中，所述处理模块，具体用于：
    确定每一种设计规则的DRC代码段中同一检查项的数值范围字段是否相同，若同一检查项的数值范围字段不完全相同，确定所述DRC代码段存在代码冲突。
  11. 根据权利要求7所述的装置，其中，所述处理模块，还用于：
    确定所述多段DRC代码是否存在代码重叠，若存在代码重叠，生成代码重叠报告，所述代码重叠报告用于指示存在代码重叠的代码位置。
  12. 根据权利要求7所述的装置，其中，所述装置还包括：接收模块；
    接收模块，用于接收DRC代码更新文件，所述DRC代码更新文件包括对存在代码冲突或代码重叠的DRC代码的更新；
    所述处理模块，还用于根据所述DRC代码更新文件，更新所述DRC代码文件；
    执行更新后的DRC代码文件，生成更新后的DRC代码文件对应的测试图形，所述测试图形用于验证芯片设计是否满足设计要求。
  13. 一种设计规则检查装置，包括：
    至少一个处理器；以及
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述设计规则检查装置能够执行权利要求1-6中任一项所述的方法。
PCT/CN2021/103734 2021-02-22 2021-06-30 设计规则检查方法、装置及存储介质 WO2022174543A1 (zh)

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