WO2022166953A1 - 晶片转移装置和晶片转移方法 - Google Patents

晶片转移装置和晶片转移方法 Download PDF

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Publication number
WO2022166953A1
WO2022166953A1 PCT/CN2022/075364 CN2022075364W WO2022166953A1 WO 2022166953 A1 WO2022166953 A1 WO 2022166953A1 CN 2022075364 W CN2022075364 W CN 2022075364W WO 2022166953 A1 WO2022166953 A1 WO 2022166953A1
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Prior art keywords
wafers
row
wafer
column
along
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PCT/CN2022/075364
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English (en)
French (fr)
Inventor
郎欣林
罗会才
闫静
周诚
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深圳市丰泰工业科技有限公司
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Priority claimed from CN202110170645.XA external-priority patent/CN113990792A/zh
Priority claimed from CN202110170599.3A external-priority patent/CN114005818A/zh
Application filed by 深圳市丰泰工业科技有限公司 filed Critical 深圳市丰泰工业科技有限公司
Publication of WO2022166953A1 publication Critical patent/WO2022166953A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65G—TRANSPORT OR STORAGE DEVICES, e.g. CONVEYORS FOR LOADING OR TIPPING, SHOP CONVEYOR SYSTEMS OR PNEUMATIC TUBE CONVEYORS
    • B65G47/00—Article or material-handling devices associated with conveyors; Methods employing such devices
    • B65G47/74—Feeding, transfer, or discharging devices of particular kinds or types
    • B65G47/90—Devices for picking-up and depositing articles or materials
    • B65G47/91—Devices for picking-up and depositing articles or materials incorporating pneumatic, e.g. suction, grippers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65G—TRANSPORT OR STORAGE DEVICES, e.g. CONVEYORS FOR LOADING OR TIPPING, SHOP CONVEYOR SYSTEMS OR PNEUMATIC TUBE CONVEYORS
    • B65G69/00—Auxiliary measures taken, or devices used, in connection with loading or unloading
    • B65G69/20—Auxiliary treatments, e.g. aerating, heating, humidifying, deaerating, cooling, de-watering or drying, during loading or unloading; Loading or unloading in a fluid medium other than air
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

Definitions

  • the present disclosure generally relates to the technical field of semiconductor equipment, and more particularly, to a wafer transfer apparatus and a wafer transfer method.
  • the wafer transfer process includes several processes of peeling, transferring, and arranging. First, the wafer is peeled off from the carrier, then the peeled wafer is transferred, and then the transferred wafer is arranged. The entire wafer transfer process requires multiple sets of equipment to work together to complete the operations of wafer stripping, transfer and arrangement respectively.
  • the performance of the wafer at the center of the wafer is relatively uniform, while the performance of the wafer at the edge of the wafer and the performance of the wafer at the center are quite different, and there may be a difference of 5 wavelengths.
  • the present disclosure relates to a wafer transfer apparatus, comprising: a suction mechanism, a driving mechanism, a first stage, and a second stage;
  • the first stage and the second stage are spaced apart;
  • the adsorption mechanism includes an operating head main body, which is a hollow main body cavity, and an operating working surface protruding from the outer wall of the operating head main body is provided on the outer wall of the operating head main body. at least one air port communicated with the main body cavity is provided on it, so as to adsorb the wafer; and
  • the driving mechanism is used for driving the adsorption mechanism to operate between the first stage and the second stage.
  • the adsorption mechanism further comprises: an operating head base and a sealing cover, wherein the operating head base is fixed on the operating body on the opposite side of the operating surface, A base cavity communicated with the main body cavity is provided in the operating head base; a cavity opening is provided on the base cavity; and
  • the sealing cover is detachably sealed and fixed on the cavity opening; the sealing cover is provided with at least one cover through hole penetrating the sealing cover and communicating with the base cavity.
  • a boss is provided on the outer wall of the main body of the operating head, and the operating working surface is located on one surface of the boss.
  • the air port includes a plurality of air hole openings, and air hole channels corresponding to the number of the air hole openings are arranged inside the outer wall of the operating head body; one end of each air hole channel is communicated with one of the air hole openings , and the other end is communicated with the main body cavity.
  • At least one of the gas ports is a bar opening
  • the inner wall of the main body of the operating head is provided with bar-shaped through grooves corresponding to the number of the bar-shaped openings; one end of each of the bar-shaped through grooves is communicated with one of the bar-shaped openings, and the other end is connected with the main body cavity connected.
  • the head base is integrally formed with the head body.
  • the wafer transfer apparatus includes a laser generator disposed below the adsorption mechanism for irradiating the wafer on the first stage.
  • the laser generator comprises an ultraviolet laser generator.
  • the present disclosure relates to a wafer transfer method comprising:
  • controlling the adsorption device to adsorb the first batch of wafers from the first stage, wherein the first batch of wafers includes at least one wafer;
  • the suction device controls the suction device to suction a second batch of wafers from the first stage, the second batch of wafers including at least one wafer;
  • the wafers of the second batch are arranged on the second stage relative to the wafers of the first batch according to a preset arrangement rule.
  • the step before the step of controlling the adsorption device to adsorb the first batch of wafers from the first stage, the step further includes:
  • the present disclosure relates to a wafer transfer method comprising:
  • first row of wafers including at least one wafer from the first row of wafers and at least one wafer from the second row of wafers;
  • the second row of wafers including at least one remaining wafer from the first row of wafers and at least one remaining wafer from the second row of wafers;
  • the second column of wafers is arranged along the second direction at predetermined second predetermined intervals relative to the first column of wafers.
  • the arranging the first row of wafers along the first direction comprises:
  • Extracting the first row of wafers from a wafer wherein the wafer includes a first row of wafers and a second row of wafers arranged at a first initial interval; on the first tray along the first direction arranging the extracted first row of wafers; and
  • the arranging of the second row of wafers relative to the first row of wafers at a predetermined first predetermined interval along the first direction includes:
  • Extracting the second row of wafers from the wafers ; arranging the extracted second row of wafers on the first tray along the first direction at a predetermined first predetermined interval relative to the first row of wafers row wafers.
  • the extracting a first row of wafers includes at least one wafer from the first row of wafers and at least one wafer from the second row of wafers, along the first row of wafers.
  • Arranging the first row of wafers in two directions includes:
  • the first column of wafers is extracted from the first tray, wherein the first tray includes a first column of wafers and a second column of wafers arranged at a second initial interval, the first column of wafers including at least one wafer in the first row of wafers and at least one wafer from the second row of wafers; arranging the extracted first column of wafers on the fourth tray along the second direction; and
  • the array of wafers arranging the second array of wafers along the second direction at preset second preset intervals includes:
  • the second row of wafers is extracted from the first tray; the second row of wafers includes at least one wafer remaining from the first row of wafers and at least one wafer remaining from the second row of wafers ; Arrange the extracted wafers in the second row on the fourth tray along the second direction at a predetermined second predetermined interval relative to the first row of wafers.
  • the arranging the first row of wafers along the first direction comprises:
  • the first row of wafers is extracted from a second tray, wherein the second tray includes a first row of wafers and a second row of wafers arranged at a first initial interval;
  • the extracted first row of wafers is arranged on a three-feed tray;
  • the arranging of the second row of wafers relative to the first row of wafers at a predetermined first predetermined interval along the first direction includes:
  • the extracting a first row of wafers includes at least one wafer from the first row of wafers and at least one wafer from the second row of wafers, along the first row of wafers.
  • Arranging the first row of wafers in two directions includes:
  • the first column of wafers is extracted from the third tray, wherein the third tray includes a first column of wafers and a second column of wafers arranged at a second initial interval; the first column of wafers includes at least one wafer in the first row of wafers and at least one wafer from the second row of wafers; arranging the extracted first column of wafers on the fifth tray along the second direction; and
  • the array of wafers arranging the second array of wafers along the second direction at preset second preset intervals includes:
  • the second row of wafers is extracted from the third tray; the second row of wafers includes at least one wafer remaining from the first row of wafers and at least one wafer remaining from the second row of wafers ; arranging the second row of wafers on the fifth tray along the second direction at a predetermined second predetermined interval relative to the first row of wafers.
  • the first initial interval is less than the first predetermined interval.
  • the second initial interval is less than the second predetermined interval.
  • the first direction and the second direction have a first predetermined angle, and the first predetermined angle is between 0° and 180°.
  • the first direction and the second direction are perpendicular to each other.
  • the wafer transfer method includes:
  • first row of wafers including a plurality of first sub-row wafers, the first sub-row wafers including a plurality of wafers;
  • a second row of wafers is arranged along the first direction relative to the first row of wafers at predetermined first predetermined intervals, the second row of wafers includes a plurality of second sub-row wafers, and the second sub-row wafers include multiple chips;
  • first column of wafers including a plurality of first sub-row wafers including at least one wafer from the first sub-row of wafers and from the second sub-row of wafers at least one of the wafers;
  • the second column of wafers is arranged along the second direction at predetermined second predetermined intervals relative to the first column of wafers.
  • the present disclosure provides a wafer transfer apparatus and a wafer transfer method
  • the wafer transfer apparatus includes a suction mechanism, a drive mechanism, a first stage, and a second stage; the first stage and the second stage are spaced apart
  • the adsorption mechanism includes an operating head main body, the operating head main body is an inner hollow main body cavity, the outer wall of the operating head main body is provided with an operating working surface protruding from the outer wall of the operating head main body, and the operating working surface is provided with a main body cavity.
  • the connected at least one air port is used for sucking the wafer; the driving mechanism is used for driving the sucking mechanism to run between the first stage and the second stage.
  • the plurality of wafers are adsorbed by the adsorption mechanism, so as to transfer the plurality of wafers from the first stage to the second stage, which can improve the efficiency of wafer transfer.
  • the wafer transfer method includes: arranging a first row of wafers along a first direction, the first row of wafers including a plurality of wafers; arranging a second row of wafers along the first direction at a preset first preset interval relative to the first row of wafers, the second row of wafers the wafer includes a plurality of wafers; extracting a first column of wafers, the first column of wafers including at least one wafer from the first row of wafers and at least one wafer from the second row of wafers; arranging the first column of wafers along the second direction; extracting A second row of wafers, the second row of wafers includes at least one wafer remaining from the first row of wafers and at least one remaining wafer from the second row of wafers; relative to the first row of wafers at preset second preset intervals along the second Orientation arranges the wafers in the second column.
  • FIG. 1 is a schematic structural diagram of a wafer transfer apparatus according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a decomposed state of an adsorption mechanism provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a combined state of an adsorption mechanism provided by an embodiment of the present disclosure
  • Fig. 4 is the partial enlarged view of A place in Fig. 3;
  • FIG. 5 is a schematic flowchart of a wafer transfer method according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of an embodiment of a wafer transfer method provided by an embodiment of the present disclosure
  • FIG. 7 is a flowchart of a wafer transfer method according to an embodiment of the present disclosure.
  • FIG. 8 is an operational schematic diagram of a wafer transfer method provided by another embodiment of the present disclosure.
  • 100 wafer transfer device; 110, adsorption mechanism; 120, drive mechanism; 130, first stage; 140, second stage; 150, laser generator;
  • the present disclosure relates to a wafer transfer apparatus 100 including: a suction mechanism 110 , a driving mechanism 120 , a first stage 130 , and a second stage 140 .
  • the first carrier 130 and the second carrier 140 are spaced apart;
  • the adsorption mechanism 110 includes an operating head body 111 , the operating head main body 111 is a hollow main body cavity, and the outer wall of the operating head main body 111 is provided with a protruding operating head main body
  • the operating surface 1111 of the outer wall of the 111 is provided with at least one air port 1112 communicated with the main body cavity on the operating surface 1111 for adsorbing wafers;
  • the driving mechanism 120 is used for driving the adsorption mechanism 110 on the first carrier 130 and the second carrier. run between the two stages 140 .
  • the adsorption mechanism 110 is used to adsorb a plurality of wafers, so as to transfer the plurality of wafers from the first stage 130 to the second stage 140, which can improve the wafer transfer efficiency. efficiency.
  • the wafer is placed on the tray, and the tray is placed on the first stage 130 .
  • a wafer carrying structure between the wafer and the tray, and the wafer carrying structure includes an adhesive layer and a carrying layer.
  • the adhesive layer is connected with the carrier layer, the side of the adhesive layer away from the carrier layer is bonded with the wafer, and the side of the carrier layer away from the adhesive layer is connected with the material tray.
  • the wafer transfer apparatus 100 includes a laser generator 150 disposed below the adsorption mechanism 110 for irradiating the wafer on the first stage 130 .
  • a laser generator 150 disposed below the adsorption mechanism 110 for irradiating the wafer on the first stage 130 .
  • the wafer can be easily adsorbed by the adsorption mechanism 110 , so that the adsorption mechanism 110 can transfer the wafer on the first stage 130 to the second stage 140 .
  • the adhesive layer includes an ultraviolet debonding agent, which loses its tack when exposed to ultraviolet light. In this way, the adhesive layer and the wafer are separated from each other by the irradiation of ultraviolet light.
  • the laser generator 150 includes an ultraviolet laser generator 150 .
  • the ultraviolet laser generator 150 may emit ultraviolet light, so that the wafer is peeled off from the adhesive layer by the ultraviolet light irradiation.
  • the adsorption mechanism 110 includes an operation head main body 111 , an operation head base 112 and a sealing cover 113 .
  • the main body 111 of the operating head as the main working part of the adsorption mechanism 110, is structured as a main body cavity with a hollow inside, and the main body cavity is surrounded by cavity walls.
  • the operating head base 112 is fixed on the operating body on the opposite side of the operating surface 1111.
  • the operating head base 112 is provided with a base cavity 1121 that communicates with the main body cavity;
  • the base cavity 1121 is provided with a base cavity 1121. cavity opening;
  • the main body 111 of the operating head may also be provided with a gas channel.
  • the function of the gas channel is to connect the inner space of the main body cavity with the outside, so as to inhale or blow air into the inner space of the main body cavity through the gas channel, thereby realizing the Adjusting the pressure inside the main body cavity, for example, sucking in the gas channel can generate a negative pressure inside the main body cavity, and blowing air into the gas channel can generate a positive pressure inside the main body cavity.
  • An operating working surface 1111 is provided on the outer wall of the operating head main body 111, and the operating working surface 1111 is used as a working surface contacting the wafer. Considering that the wafers are located on the same plane during discharge, in the embodiment of the present application, the operating working surface 1111 Can be flat.
  • the sealing cover plate 113 is detachably sealed and fixed on the cavity opening; the sealing cover plate 113 is provided with at least one cover plate through hole 1131 which penetrates the sealing cover plate 113 and communicates with the base cavity 1121.
  • the operation head base 112 is fixed to the operation head main body 111 , and the position of the operation head base 112 is opposite to the position of the operation work surface 1111 .
  • the opposite positions refer to two opposite sides on the operating head body 111 , the operating working surface 1111 is located above the operating head, and the operating head base 112 is located below the operating head body 111 .
  • the operating head base 112 and the operating working surface 1111 are arranged on two opposite sides of the operating head main body 111, the purpose is to make the operating working surface 1111 protrude and prevent the operating head base 112 from being in contact with the wafer on the operating working surface 1111.
  • interference caused by false touches is formed on the wafer.
  • a base cavity 1121 is provided inside the operation head base 112 , and the base cavity 1121 communicates with the main body cavity of the operation head main body 111 .
  • a gas channel opening is provided on the side wall of the base cavity 1121, and the function of the gas channel opening is to communicate the base cavity 1121 with the outside.
  • the operating head main body 111 and the operating head base 112 may be of separate structures, and are connected and fixed in a detachable manner. It can also be a one-piece structure, which can be cast and formed by integral molding technology, or formed by welding. In addition, the structure of the operating head main body 111 and the operating head base 112 can be obtained by processing a whole piece of material.
  • the main body cavity and the base cavity 1121 can be regarded as the same cavity without distinction.
  • the gas channel opening can communicate with the base cavity 1121 and the main body cavity, and then communicate with the air port 1112 on the operating head main body 111; when in use, the base cavity 1121 and the inside of the main body cavity can be air pressure controlled through the gas channel opening , and then the air pressure passes through at least one air port 1112 on the operating surface 1111, and operations such as adsorption or blowing can be performed.
  • the wafer when the gas port 1112 is aligned with the wafer, if a negative pressure is applied to the gas channel opening, the wafer can be adsorbed through the gas channel opening 1112, and if a positive pressure is applied to the gas channel opening, the wafer can be blown open through the gas channel opening 1112 , so that the wafers leave the gas port 1112, providing a basis for batch operation of wafers.
  • the structure of the operating head main body 111 will be described in detail below.
  • the shape of the surface of the operating surface 1111 can be any shape, the operating surface 1111 can be elongated, and because the size of the chip is very small, the size of the chip is generally in the order of tens of microns, for example: Micro
  • the chip size of the LED is defined as below 75 microns, or even below 50 microns, so the width of the operating surface 1111 is generally narrow, and within 0.05mm-0.1 mm, the length of the operating surface 1111 can be set as required, which is not required in this application. limited.
  • one or more air ports 1112 are opened on the operating surface 1111, and each air port 1112 is communicated with the inner space of the operating head body 111.
  • the air ports 1112 can be directly opened on the operating head body.
  • On the outer wall of the operating head 111 preferably on the operating working surface 1111 , it communicates with the inner space of the operating head body 111 .
  • the gas channel may be one or more, and in certain embodiments, is not limited.
  • one or more through holes may be provided on the outer wall of the operating head body 111 as gas passages.
  • the air pressure inside the main body cavity of the operating head main body 111 can be controlled through the gas channel of the operating head main body 111 , and the air pressure inside the main body cavity can be adsorbed or blown through through at least one air port 1112 . operate.
  • the air port 1112 when the air port 1112 is aligned with the wafer, if the inside of the operating head body 111 is under negative pressure, the wafer can be adsorbed through the air port 1112; The wafers are blown away so that the wafers leave the gas port 1112, and then the operation head body 111 provides a basis for batch operation of the wafers.
  • the air openings 1112 provided on the operating surface 1111 are air openings.
  • the plurality of air openings are arranged in at least one row on the operating surface 1111, and the plurality of air openings are used in the operation work.
  • the face 1111 is arranged in a row, and in some embodiments, the plurality of pore openings are arranged in a straight line.
  • the plurality of air hole openings are arranged in multiple rows on the operating working surface 1111, and are arranged in parallel between adjacent rows.
  • the spacing between adjacent air hole openings on the same row is equal.
  • the size of the air port 1112 is smaller than the width of the operating surface 1111, and considering the size of the chip, in some embodiments, the aperture of the air port 1112 ranges from 0.001 mm to 0.05 mm.
  • the aperture range of the gas port 1112 depends on 15%-80% of the width of the corresponding wafer in the direction perpendicular to the gas port 1112 in the corresponding direction. For example, if the width of the wafer is 1 mm, the aperture of the gas port 1112 ranges from 0.15 mm to 0.8 mm.
  • the aperture range of the air port 1112 needs to be designed and selected for different products according to other factors such as air pressure.
  • the air port 1112 may communicate with the inner space of the operating head body 111 directly through the outer wall of the operating working surface 1111 .
  • the air port 1112 may also communicate with the inner space of the operating head body 111 through an air hole channel.
  • the number of air hole channels corresponds to the number of air hole openings, and one end of each air hole channel is communicated with a corresponding air hole channel, and the other end is communicated with the inside of the operating head main body 111 .
  • the air port 1112 provided on the operating surface 1111 is a bar-shaped opening, and the outer wall of the operating head body 111 is provided with bar-shaped through grooves corresponding to the number of bar-shaped openings; The bar-shaped opening is communicated, and the other end is communicated with the main body cavity.
  • the strip opening is one, and in certain embodiments, the strip opening is linear.
  • a plurality of air ports 1112 may be arranged to be spaced apart.
  • the gas port 1112 may be a single circular hole, an intermittent strip-shaped hole, or a continuous linear gas port.
  • the operating working surface 1111 when the gas operating head is in contact with the chip, in order to prevent other parts of the gas operating head from touching the chip by mistake except the operating working surface 1111, the operating working surface 1111 can be made to protrude more from the outer wall of the operating head body 111, which is Therefore, a boss 1113 may be provided on the outer wall of the operating head main body 111 , and the operation working surface 1111 is located on the boss 1113 .
  • the structure of the boss 1113 is not limited.
  • the structure of the boss 1113 can make the working surface more protrude from the operating head main body 111, reduce the volume of the operating head main body 111, and further, when the gas operating head moves, The false contact between the gas operation head and the chip can be reduced, which further causes the chip to be miscontacted and dislocated.
  • the bosses 1113 may be square edges, the bosses 1113 may be wedge-shaped edges, or the bosses 1113 may be cylindrical or other arc-shaped structures.
  • the present disclosure relates to a wafer transfer method including:
  • S110 controlling the adsorption device to adsorb the first batch of wafers from the first stage 130, where the first batch of wafers includes at least one wafer;
  • S130 Controlling the adsorption device to adsorb the second batch of wafers from the first stage 130, where the second batch of wafers includes at least one wafer;
  • S140 Arrange the second batch of wafers on the second stage 140 relative to the first batch of wafers according to a preset arrangement rule.
  • a plurality of wafers are adsorbed from the first stage 130 by the adsorption device and arranged on the second stage 140, and the plurality of wafers are removed from the first stage 130 by the adsorption device Adsorbed and arranged on the second stage 140 .
  • the second batch of wafers is arranged on the second stage 140 relative to the first batch of wafers, so that the mass transfer of wafers can be realized and the second stage 140 can be arranged according to the preset arrangement rules.
  • the second batch of wafers is distributed, which not only realizes the transfer of the wafers but also realizes the arrangement of the wafers.
  • step of S110 controlling the adsorption device to adsorb the first batch of wafers from the first stage 130, it further includes:
  • S100 Control the laser light emitted by the laser generator 150 to irradiate the first batch of wafers on the first stage 130 .
  • the wafer transfer method provided according to the present disclosure includes:
  • S700 Arrange the first row of wafers along the first direction, where the first row of wafers includes a plurality of wafers;
  • S710 Arrange the wafers in the second row along the first direction at a preset first preset interval relative to the wafers in the first row, where the wafers in the second row include a plurality of wafers;
  • S720 Extracting a first row of wafers, where the first row of wafers includes at least one wafer from the first row of wafers and at least one wafer from the second row of wafers;
  • S730 Arrange the first row of wafers along the second direction
  • S740 Extracting a second row of wafers, where the second row of wafers includes at least one wafer remaining from the first row of wafers and at least one remaining wafer from the second row of wafers;
  • S750 Arrange the wafers in the second column along the second direction at a predetermined second predetermined interval relative to the wafers in the first column.
  • the wafer transfer method by arranging the first row of wafers along the first direction, and then arranging the second row of wafers relative to the first row of wafers, there is a predetermined first preset interval between the second row of wafers and the first row of wafers. Then, the wafers in the first row are extracted, the wafers in the first row are arranged in the second direction, the wafers in the second row are extracted, and the wafers in the second row are arranged relative to the wafers in the first row. There is a predetermined second predetermined interval between the second row of wafers and the first row of wafers.
  • the wafer transfer method provided by the present disclosure can not only transfer a single wafer, but also transfer a row of wafers, and can also be applied to a packaged multifunctional integrated unit.
  • the wafer transfer method provided in this embodiment can be applied to a multifunctional integrated circuit unit integrating one or more of a logic chip, a MEMS device, or a sensor.
  • a two-dimensional rectangular coordinate system is established with one of the wafers as the origin, with one side of the wafer as the x-axis, and the other side of the wafer perpendicular to the side as the y-axis.
  • the first direction is the A direction
  • the second direction is the B direction, that is, the first direction is the direction along the x-axis
  • the second direction is the direction along the y-axis.
  • the first preset interval is y1
  • the second preset interval is x1.
  • the first direction may also be the y-axis direction
  • the second direction may be the x-axis direction.
  • the wafer transfer method provided by the embodiments of the present disclosure includes:
  • S800 Arrange the first row of wafers along the first direction, where the first row of wafers includes a plurality of wafers;
  • S810 Arrange the wafers in the second row along the first direction at a preset first preset interval relative to the wafers in the first row;
  • S820 Extracting a first row of wafers, where the first row of wafers includes at least one wafer from the first row of wafers;
  • S830 Arrange the first row of wafers along the second direction
  • S840 Extracting a second row of wafers, where the second row of wafers includes at least one remaining wafer from the first row of wafers and at least one wafer from the second row of wafers;
  • S850 Arrange the wafers in the second column along the second direction at a predetermined second predetermined interval relative to the wafers in the first column.
  • the first row of wafers when extracting the first row of wafers, includes at least one wafer in the first row of wafers; when extracting the second row of wafers, the second row of wafers includes at least one wafer from the remaining wafers in the first row of wafers One wafer and at least one wafer from the second row of wafers. That is, the number of wafers in the first row is less than the number of wafers in the second row, so that the wafers can be transferred and arranged according to the number of wafers in the first row or the number of wafers in the second row, so that the plurality of wafers have a first preset interval and a second row of wafers. Two preset intervals.
  • the first row of wafers includes two wafers and the second row of wafers includes one wafer. Extracting the first row of wafers means extracting one wafer in the first row of wafers; extracting the second row of wafers means extracting the remaining one wafer in the first row of wafers and one wafer in the second row of wafers.
  • the first row of wafers may also include one wafer, and the second row of wafers may also include two wafers. In this way, extracting the first row of wafers means extracting one wafer in the first row and one wafer in the second row. Extracting the second row of wafers is to extract the remaining one wafer in the second row of wafers.
  • the wafer transfer method provided by the embodiments of the present disclosure includes:
  • S310 Arrange the first row of wafers along the first direction, where the first row of wafers includes a plurality of wafers;
  • S320 Arrange the wafers in the second row along the first direction at a preset first preset interval relative to the wafers in the first row;
  • S330 Extracting a first row of wafers, where the first row of wafers includes at least one wafer from the first row of wafers and at least one wafer from the second row of wafers;
  • S340 Arrange the first row of wafers along the second direction
  • S350 Extracting a second row of wafers, where the second row of wafers includes at least one remaining wafer from the first row of wafers;
  • S360 Arrange the wafers in the second column along the second direction at a predetermined second predetermined interval relative to the wafers in the first column.
  • the first row of wafers when extracting the first row of wafers, includes at least one wafer in the first row of wafers and at least one wafer from the second row of wafers; when extracting the second row of wafers, the second row of wafers
  • the wafers include at least one remaining wafer from the first row of wafers. That is, the number of wafers in the first row is greater than the number of wafers in the second row, so that the wafers can be transferred and arranged according to the number of wafers in the first row or the number of wafers in the second row, so that the plurality of wafers have a first preset interval and a second row of wafers. Two preset intervals.
  • the first row of wafers includes two wafers and the second row of wafers includes one wafer, and extracting the first row of wafers is one wafer in the first row and one wafer in the second row of wafers. Extracting the second row of wafers is to extract the remaining one wafer in the first row of wafers.
  • the first row of wafers may also include one wafer, and the second row of wafers includes two wafers, and extracting the first row of wafers means extracting one wafer in the first row and one wafer in the second row.
  • arranging the first row of wafers along the first direction includes:
  • Extracting a first row of wafers from a wafer wherein the wafer includes a first row of wafers and a second row of wafers arranged at a first initial interval; arranging the extracted first row of wafers on a first tray along a first direction;
  • Arranging the second row of wafers along the first direction at a predetermined first predetermined interval relative to the first row of wafers includes:
  • Extracting the second row of wafers from the wafers ; arranging the extracted second row of wafers on the first tray along a first direction at a predetermined first preset interval relative to the first row of wafers.
  • the wafers can be arranged while transferring the wafers, thereby realizing the transfer of a large amount of wafers.
  • extracting a first column of wafers, the first column of wafers includes at least one wafer from the first column of wafers and at least one wafer from the second column of wafers, and arranging the first column of wafers along the second direction includes :
  • a first row of wafers is extracted from a first tray, wherein the first tray includes first and second rows of wafers arranged at a second initial interval, the first row of wafers including at least one of the wafers from the first row a wafer and at least one wafer from the second row of wafers; arranging the extracted first row of wafers on a fourth tray along the second direction;
  • Extracting a second row of wafers includes at least one remaining wafer from the first row of wafers and at least one remaining wafer from the second row of wafers; relative to the first row of wafers at a preset second preset interval along the first
  • the second row of wafers arranged in two directions includes:
  • the second row of wafers is extracted from the first tray; the second row of wafers includes at least one wafer remaining from the first row of wafers and at least one remaining wafer from the second row of wafers; relative to the first row of wafers
  • the extracted second column of wafers are arranged on the fourth tray along the second direction at two predetermined intervals.
  • the first row of wafers on the first tray is transferred to the fourth tray, so that there are a first preset interval and a second preset interval between the plurality of wafers on the fourth tray, so that the first A two-dimensional array is formed among the multiple wafers on the four-feed tray.
  • massive transfer of wafers is realized, and the efficiency of wafer transfer is improved.
  • arranging the first row of wafers along the first direction includes:
  • a first row of wafers is extracted from a second tray, wherein the second tray includes a first row of wafers and a second row of wafers arranged at a first initial interval; the extracted first row of wafers is arranged on a third tray along a first direction a row of wafers;
  • Arranging the second row of wafers along the first direction at a predetermined first predetermined interval relative to the first row of wafers includes:
  • the wafers can be arranged while transferring the wafers, thereby realizing the transfer of a large amount of wafers.
  • extracting a first column of wafers, the first column of wafers includes at least one wafer from the first column of wafers and at least one wafer from the second column of wafers, and arranging the first column of wafers along the second direction includes :
  • a first row of wafers is withdrawn from a third tray, wherein the third tray includes a first row of wafers and a second row of wafers arranged at a second initial interval; the first row of wafers includes at least one of the wafers from the first row wafers and at least one wafer from the second row of wafers; arranging the extracted first row of wafers on a fifth tray along the second direction;
  • Extracting a second row of wafers includes at least one remaining wafer from the first row of wafers and at least one remaining wafer from the second row of wafers; relative to the first row of wafers at a preset second preset interval along the first
  • the second row of wafers arranged in two directions includes:
  • the second row of wafers is extracted from the third tray; the second row of wafers includes at least one wafer remaining from the first row of wafers and at least one remaining wafer from the second row of wafers; relative to the first row of wafers
  • a second row of wafers are arranged on the fifth tray along the second direction at two predetermined intervals.
  • the first row of wafers on the third tray is transferred to the fifth tray, so that the plurality of wafers on the fifth tray have a first preset interval and a second preset interval, so that the first A two-dimensional array is formed among the multiple wafers on the five-feed tray.
  • massive transfer of wafers is realized, and the efficiency of wafer transfer is improved.
  • the first initial interval is less than the first predetermined interval.
  • the transferred wafers can have the first preset interval.
  • the first preset interval can be set according to actual needs.
  • the multiple wafers after the wafer dicing are arranged according to the first preset interval. It is also possible to make a plurality of wafers on the first tray to be arranged at first preset intervals after being transferred to the second tray.
  • the second initial interval is less than the second predetermined interval.
  • the transferred multiple wafers can have a second preset interval, and the second preset interval can be set according to actual needs.
  • the plurality of wafers on the first tray can be arranged at a second preset interval after being transferred to the third tray. It is also possible to arrange the plurality of wafers on the third tray after being transferred to the fifth tray according to the first preset interval.
  • the first preset interval is between 0.5um and 5mm
  • the second preset interval is between 0.5um and 5mm.
  • the first predetermined interval is between 0.6um and 5mm
  • the second predetermined interval is between 0.6um and 5mm.
  • the first preset interval and the second preset interval are required intervals between a plurality of wafers on the LED display screen.
  • a high-definition LED display with a conventional resolution of 1920*1080 requires 1920*1080*3 Micro LED chips, totaling 6.2 million chips.
  • the chips on the display screen need to form a high-density two-dimensional array structure with a first preset interval and a second preset interval.
  • first preset angle between the first direction and the second direction, and the first preset angle is between 0° and 180°.
  • first preset angle between the first direction and the second direction so that the wafers to be transferred can be selected according to actual wafer arrangement requirements.
  • the first direction and the second direction are perpendicular to each other.
  • the first preset angle is 90°. In this way, the efficiency of wafer transfer can be improved and the position of the wafer arrangement can be easily adjusted.
  • a two-dimensional array structure is formed between a plurality of wafers.
  • the parameters of the wafers before arranging the first row of wafers in the first direction, further includes detecting parameters of the wafers, the parameters of the wafers including one or more of wafer type, color difference, or wavelength.
  • the types of wafers include one or more of red wafers, blue wafers, white wafers, and green wafers.
  • the wafer transfer method includes:
  • S410 Arrange the first row of wafers along the first direction, the first row of wafers includes a plurality of first sub-row wafers, and the first sub-row wafers include a plurality of wafers;
  • S420 Arrange the wafers in the second row along the first direction at a preset first preset interval relative to the wafers in the first row, where the wafers in the second row include a plurality of wafers in a second sub-row, and the wafers in the second sub-row include a plurality of wafers;
  • S430 Extract the first row of wafers, where the first row of wafers includes a plurality of first sub-row wafers, and the first sub-row wafer includes at least one wafer from the first sub-row wafer and at least one wafer from the second sub-row wafer ;
  • S440 Arrange the first row of wafers along the second direction
  • S450 Extract a second row of wafers, where the second row of wafers includes a plurality of second sub-row wafers, and the second sub-row wafers include at least one wafer remaining from the first sub-row wafer and at least one remaining wafer from the second sub-row wafer a chip;
  • S460 Arrange the wafers in the second column along the second direction at a predetermined second predetermined interval relative to the wafers in the first column.
  • the above-mentioned wafer transfer method by arranging the first row of wafers and the second row of wafers, and arranging the first row of wafers and the second row of wafers, wherein the first row of wafers includes a plurality of first sub-row wafers, and the second row of wafers includes A plurality of first sub-columns of wafers.
  • the transfer of the plurality of wafers can be realized by arranging a plurality of first sub-row wafers and a plurality of second sub-row wafers, and a plurality of first sub-row wafers and a plurality of second sub-row wafers, thereby realizing the transfer of the plurality of wafers.
  • a two-dimensional array structure is formed.

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Abstract

公开了晶片转移装置和晶片转移方法。该晶片转移装置包括：吸附机构、驱动机构、第一载台、以及第二载台；第一载台和第二载台间隔开设置；吸附机构包括操作头主体，操作头主体为内部中空的主体腔体，操作头主体的外壁上设置有凸出操作头主体外壁的操作工作面，操作工作面上设置有与主体腔体相连通的至少一个气口，以用于吸附晶片；驱动机构用于驱动吸附机构在第一载台和第二载台之间运行。

Description

晶片转移装置和晶片转移方法
相关申请的引用
本公开要求于2021年02月08日向中国人民共和国国家知识产权局提交的申请号为202110170645.X，发明名称为“晶片转移装置和晶片转移方法”的发明专利公开以及于2021年02月08日向中国人民共和国国家知识产权局提交的申请号为202110170599.3，发明名称为“晶片转移方法”的发明专利公开的全部权益，并通过引用的方式将其全部内容并入本公开。
领域
本公开大体上涉及半导体设备技术领域，更具体地涉及晶片转移装置和晶片转移方法。
背景
晶片转移过程包括剥离、转移、排片这几个过程，首先将晶片从载台上剥离，然后对剥离后的晶片进行转移，然后对转移后的晶片进行排片。整个晶片转移过程需要多套设备联合共同工作来分别完成晶片的剥离、转移和排片的操作。
对晶圆进行切割时，晶圆中心点位置的晶片性能相对均匀，而晶圆边缘位置的晶片性能与中心位置的晶片性能差距较大，可能会有5个波长的差距。
概述
公开第一方面，本公开涉及晶片转移装置，其包括：吸附机构、驱动机构、第一载台、以及第二载台；
其中：
所述第一载台和所述第二载台间隔开设置；
所述吸附机构包括操作头主体，所述操作头主体为内部中空的主体腔体，所述操作头主体的外壁上设置有凸出所述操作头主体外壁的操作工作面，所述操作工作面上设置有与所述主体腔体相连通的至少一个气口，以用于吸附晶片；以及
所述驱动机构用于驱动所述吸附机构在所述第一载台和所述第二载台之间运行。
在某些实施方案中，所述吸附机构还包括：操作头基座和密封盖板，其中，所述操作头基座固定在所述操作主体上与所述操作工作面的位置相对一侧，所述操作头基座内设置有与所述主体腔体相连通的基座腔体；所述基座腔体上设置有腔体开口；以及
所述密封盖板可拆卸密封固定在所述腔体开口上；所述密封盖板上设置有贯穿所述密封盖板、且与所述基座腔体相连通的至少一个盖 板通孔。
在某些实施方案中，所述操作头主体外壁上设置有凸台，所述操作工作面位于所述凸台上的一个面上。
在某些实施方案中，所述气口包括多个气孔开口，所述操作头主体外壁内部设置与所述气孔开口数量对应的气孔通道；每个所述气孔通道一端与一个所述气孔开口相连通，另一端与所述主体腔体相连通。
在某些实施方案中，至少一个所述气口为条形开口；以及
所述操作头主体外壁内部设置与所述条形开口数量对应的条形通槽；每个所述条形通槽的一端与一个所述条形开口相连通，另一端与所述主体腔体相连通。
在某些实施方案中，所述操作头基座与所述操作头主体一体成型。
在某些实施方案中，所述晶片转移装置包括激光发生器，所述激光发生器设置在所述吸附机构的下方以用于照射所述第一载台上的晶片。
在某些实施方案中，所述激光发生器包括紫外线激光发生器。
第二方面，本公开涉及晶片转移方法，其包括：
控制吸附装置从第一载台上吸附第一批晶片，所述第一批晶片包括至少一个晶片；
控制所述吸附装置在第二载台上布置所述第一批晶片；
控制所述吸附装置从所述第一载台上吸附第二批晶片，所述第二批晶片包括至少一个晶片；以及
按预设排布规则相对所述第一批晶片在所述第二载台上布置所述第二批晶片。
在某些实施方案中，所述控制吸附装置从第一载台上吸附第一批晶片的步骤之前还包括：
控制所述激光发生器发射的激光照射到所述第一载台上的所述第一批晶片。
第三方面，本公开涉及晶片转移方法，其包括：
沿第一方向布置第一排晶片，所述第一排晶片包括多个晶片；
相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片，所述第二排晶片包括多个晶片；
提取第一列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片；
沿第二方向布置所述第一列晶片；
提取所述第二列晶片，所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；以及
相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片。
在某些实施方案中，所述沿第一方向布置第一排晶片包括：
从晶圆上提取所述第一排晶片，其中所述晶圆包括以第一初始间隔排布的第一排晶片和第二排晶片；沿所述第一方向在所述第一料盘上布置提取的所述第一排晶片；以及
所述相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片包括：
从所述晶圆上提取所述第二排晶片；相对所述第一排晶片按预设第一预设间隔沿所述第一方向在所述第一料盘上布置提取的所述第二排晶片。
在某些实施方案中，所述提取第一列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片，沿第二方向布置所述第一列晶片包括：
从所述第一料盘上提取所述第一列晶片，其中所述第一料盘包括以第二初始间隔排布的第一列晶片和第二列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片；沿所述第二方向在所述第四料盘上布置提取的所述第一列晶片；以及
所述提取所述第二列晶片，所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片包括：
从所述第一料盘上提取所述第二列晶片；所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向在所述第四料盘上布置提取的所述第二列晶片。
在某些实施方案中，所述沿第一方向布置第一排晶片包括：
从第二料盘上提取所述第一排晶片，其中所述第二料盘包括以第一初始间隔排布的第一排晶片和第二排晶片；沿所述第一方向在所述第三料盘上布置提取的所述第一排晶片；以及
所述相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片包括：
从所述第二料盘上提取所述第二排晶片；相对所述第一排晶片按预设第一预设间隔沿所述第一方向在所述第三料盘上布置所述第二排晶片。
在某些实施方案中，所述提取第一列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片，沿第二方向布置所述第一列晶片包括：
从所述第三料盘上提取所述第一列晶片，其中所述第三料盘包括以第二初始间隔排布的第一列晶片和第二列晶片；所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片；沿所述第二方向在所述第五料盘上布置提取的所述第一列晶片；以及
所述提取所述第二列晶片，所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片包括：
从所述第三料盘上提取所述第二列晶片；所述第二列晶片包括来 自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向在所述第五料盘上布置所述第二列晶片。
在某些实施方案中，所述第一初始间隔小于所述第一预设间隔。
在某些实施方案中，所述第二初始间隔小于所述第二预设间隔。
在某些实施方案中，所述第一方向与所述第二方向之间具有第一预设角度，所述第一预设角度介于0°至180°之间。
在某些实施方案中，所述第一方向与所述第二方向互相垂直。
在某些实施方案中，所述晶片转移方法包括：
沿所述第一方向布置第一排晶片，所述第一排晶片包括多个第一子排晶片，所述第一子排晶片包括多个晶片；
相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片，所述第二排晶片包括多个第二子排晶片，所述第二子排晶片包括多个晶片；
提取第一列晶片，所述第一列晶片包括多个第一子列晶片，所述第一子列晶片包括来自所述第一子排晶片中的至少一个晶片和来自所述第二子排晶片中的至少一个晶片；
沿所述第二方向布置所述第一列晶片；
提取所述第二列晶片，所述第二列晶片包括多个第二子列晶片，所述第二子列晶片包括来自所述第一子排晶片中剩余的至少一个晶片和来自所述第二子排晶片中剩余的至少一个晶片；以及
相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片。
在某些实施方案中，本公开提供的晶片转移装置和晶片转移方法，晶片转移装置包括吸附机构、驱动机构、第一载台、以及第二载台；第一载台和第二载台间隔开设置；吸附机构包括操作头主体，操作头主体为内部中空的主体腔体，操作头主体的外壁上设置有凸出操作头主体外壁的操作工作面，操作工作面上设置有与主体腔体相连通的至少一个气口，以用于吸附晶片；驱动机构用于驱动吸附机构在第一载台和第二载台之间运行。利用本公开实施例提供的晶片转移装置，通过吸附机构对多个晶片进行吸附，从而将多个晶片从第一载台上转移至第二载台上，这样可以提高晶片转移的效率。晶片转移方法包括：沿第一方向布置第一排晶片，第一排晶片包括多个晶片；相对第一排晶片按预设第一预设间隔沿第一方向布置第二排晶片，第二排晶片包括多个晶片；提取第一列晶片，第一列晶片包括来自第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片；沿第二方向布置第一列晶片；提取第二列晶片，第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中剩余的至少一个晶片；相对第一列晶片按预设第二预设间隔沿第二方向布置第二列晶片。利用上述的晶片转移方法转移多个晶片，使得多个晶片之间形成具有一定间距的高密度二维阵列排布。
附图简要说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
为了更清楚地说明本公开的技术方案，下面将对本公开的描述中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的晶片转移装置的结构示意图；
图2为本公开一实施例提供的吸附机构的分解状态的结构示意图；
图3为本公开一实施例提供的吸附机构的组合状态的结构示意图；
图4为图3中A处的局部放大图；
图5为本公开一实施例提供的晶片转移方法的流程示意图；
图6为本公开一实施例提供的晶片转移方法的一实施方式的流程示意图；
图7为本公开一实施例提供的晶片转移方法的流程图；以及
图8为本公开另一实施例提供的晶片转移方法的操作示意图。
附图标记：
100、晶片转移装置；110、吸附机构；120、驱动机构；130、第一载台；140、第二载台；150、激光发生器；
111、操作头主体；112、操作头基座；113、密封盖板；
1111、操作工作面；1112、气口；1121、基座腔体；1113、凸台；1131、盖板通孔。
详述
为了对本公开的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本公开的具体实施方式。以下描述中，需要理解的是，“前”、“后”、“上”、“下”、“左”、“右”、“纵”、“横”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“头”、“尾”等指示的方位或位置关系为基于附图所示的方位或位置关系、以特定的方位构造和操作，仅是为了便于描述本技术方案，而不是指示所指的装置或元件必须具有特定的方位，因此不能理解为对本公开的限制。
还需要说明的是，除非另有明确的规定和限定，“安装”、“相连”、“连接”、“固定”、“设置”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。当一个元件被称为在另一元件“上”或“下”时，该元件能够“直接地”或“间接地”位于另一元件之上，或者也可能存在一个或更多个居间元件。术语“第一”、“第二”、“第三”等仅是为了便于描述本技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征 的数量，由此，限定有“第一”、“第二”、“第三”等的特征可以明示或者隐含地包括一个或者更多个该特征。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本公开实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本公开。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本公开的描述。
参考图1至图4，本公开涉及晶片转移装置100，其包括：吸附机构110、驱动机构120、第一载台130、以及第二载台140。
第一载台130和第二载台140间隔开设置；吸附机构110包括操作头主体111，操作头主体111为内部中空的主体腔体，操作头主体111的外壁上设置有凸出操作头主体111外壁的操作工作面1111，操作工作面1111上设置有与主体腔体相连通的至少一个气口1112，以用于吸附晶片；驱动机构120用于驱动吸附机构110在第一载台130和第二载台140之间运行。利用本公开实施例提供的晶片转移装置100，通过吸附机构110对多个晶片进行吸附，从而将多个晶片从第一载台130上转移至第二载台140上，这样可以提高晶片转移的效率。
晶片放置于料盘上，料盘放置于第一载台130上。晶片与料盘之间具有晶片承载结构，晶片承载结构包括粘接层和承载层。粘接层与承载层连接，粘接层远离承载层的一侧与晶片粘接，承载层远离粘接层的一侧与料盘连接。
晶片转移装置100包括激光发生器150，激光发生器150设置在吸附机构110的下方以用于照射第一载台130上的晶片。通过激光的照射，可以使得晶片便于被吸附机构110吸附起来，进而使得吸附机构110将第一载台130上的晶片转移至第二载台140上。
粘接层包括紫外线失粘剂，紫外线失粘剂在经过紫外线光照射下会失去粘性。这样，通过紫外线光的照射使得粘接层与晶片之间剥离开。激光发生器150包括紫外线激光发生器150。紫外线激光发生器150可以发射紫外线光，以使得通过紫外线光照射将晶片与粘接层剥离开。
吸附机构110包括：操作头主体111、操作头基座112以及密封盖板113。其中，操作头主体111作为吸附机构110的主要工作部分，其结构为内部中空的主体腔体，主体腔体四周为腔壁。
操作头基座112固定在操作主体上与操作工作面1111的位置相对一侧，操作头基座112内设置有与主体腔体相连通的基座腔体1121；基座腔体1121上设置有腔体开口；
在操作头主体111上还可以设置有气体通道，气体通道的作用是将主体腔体内部空间与外界相连通，以便通过气体通道对主体腔体的内部空间进行吸气或吹气，进而实现对主体腔体内部进行压力调节，例如：对气体通道吸气，可以使得主体腔体内部产生负压，对气体通道进行吹气，可以使得主体腔体内部产生正压。
在操作头主体111的外壁上设置有操作工作面1111，操作工作面1111作为与晶片接触的工作面，考虑到晶片在排放时位于同一平面上，所以在本申请实施例中，操作工作面1111可以为平面。
密封盖板113可拆卸密封固定在腔体开口上；密封盖板113上设 置有贯穿密封盖板113、且与基座腔体1121相连通的至少一个盖板通孔1131。
操作头基座112与操作头主体111相固定，操作头基座112的位置与操作工作面1111的位置相对。在某些实施方案中，位置相对是指位于操作头主体111上位置相反的两个侧面，操作工作面1111位于操作头的上方，操作头基座112位于操作头主体111的下方。
将操作头基座112与操作工作面1111设置在操作头主体111上位置相反的两个侧面，其目的是使得操作工作面1111凸出设置，避免操作头基座112在操作工作面1111与晶片进行接触时，对晶片形成误触而带来的干扰。
在操作头基座112的内部设置有基座腔体1121，基座腔体1121与操作头主体111的主体腔体相连通。在基座腔体1121的侧壁上设置有气体通道开口，气体通道开口的作用是将基座腔体1121与外部相连通。
在某些实施方案中，操作头主体111和操作头基座112可以为分体式结构，通过可拆卸方式相连接固定。也可以为一体式结构，通过一体成型技术铸造成型，或者，通过焊接的方式成型，另外，还可以通过对整块材料进行加工，得到操作头主体111和操作头基座112的结构。
在某些实施方案中，当操作头主体111为一体式结构时，主体腔体和基座腔体1121可以不用区分，作为同一个腔体。
气体通道开口，可以连通基座腔体1121以及主体腔体，进而连通操作头主体111上的气口1112；在使用时，通过气体通道开口可以对基座腔体1121以及主体腔体内部进行气压控制，进而气压通过操作工作面1111上的至少一个气口1112，可以进行吸附或吹开等操作。在具体使用时，当将气口1112对准晶片时，如果气体通道开口施加负压，就可通过气口1112对晶片进行吸附，如果气体通道开口施加正压，就可以通过气口1112对晶片进行吹开，使得晶片离开气口1112，为批量操作晶片提供了基础。
下面对操作头主体111的结构进行详细描述。
在某些实施方案中，操作工作面1111的表面的形状可以为任意形状，操作工作面1111可以为长条形，并且由于芯片的体积非常小，一般芯片尺寸在几十微米级，例如：Micro LED的晶片尺寸界定为75微米以下，甚至是50微米以下，所以操作工作面1111的宽度一般较窄，在0.05mm-0.1mm，操作工作面1111的长度可以根据需要设置，本申请中不做限定。
在某些实施方案中，在操作工作面1111上开设一个或多个气口1112，每个气口1112均与操作头主体111内部空间相连通，在具体应用中，气口1112可以直接开设在操作头主体111的外壁上，优选位于操作工作面1111上，然后与操作头主体111内部空间相连通。
在某些实施方案中，气体通道可以为一个或多个，在某些实施方案中，不做限定。在某些实施方案中，可以在操作头主体111的外壁上设置有一个或多个贯穿孔，作为气体通道。
在某些实施方案中，通过操作头主体111的气体通道，可以对操作头主体111的主体腔体内部进行气压控制，主体腔体内部的气压通过至少一个气口1112，可以进行吸附或吹开等操作。在具体使用时，当将气口1112对准晶片时，如果操作头主体111内部为负压，就可通 过气口1112对晶片进行吸附，如果操作头主体111内部为正压，就可以通过气口1112对晶片进行吹开，使得晶片离开气口1112，进而该操作头主体111，为批量操作晶片提供了基础。
在某些实施方案中，操作工作面1111上设置的气口1112为气孔开口，当气孔开口为多个时，多个气孔开口在操作工作面1111上呈至少一行排列，多个气孔开口在操作工作面1111上呈一行排列，在某些实施方案中，多个气孔开口呈直线排列。多个气孔开口在操作工作面1111上呈多行排列，并且相邻行之间平行设置。此外，考虑到芯片之间间距均匀，所以，在某些实施方案中，在某些实施方案中，同一行上相邻气孔开口之间的间距相等。
当气口1112采用气孔开口时，气口1112的尺寸小于操作工作面1111的宽度，并且考虑到芯片的尺寸，在某些实施方案中，气口1112的孔径范围在0.001mm-0.05mm。气口1112的孔径范围取决于对应晶片在对应方向上与气口1112垂直的方向的宽度的15％-80％。例如，晶片的宽度为1mm，则气口1112的孔径范围为0.15mm至0.8mm。气口1112的孔径范围需要配合气压等其他因素针对不同的产品进行设计选型。
在某些实施方案中，气口1112可以直接通过操作工作面1111的外壁与操作头主体111内部空间相连通。另外，考虑到气流的稳定性，气口1112还可以通过气孔通道与操作头主体111内部空间相连通。气孔通道的数量与气孔开口数量对应，并且每个气孔通道一端与对应的一个气孔通道相连通，另一端与操作头主体111内部相连通。
在某些实施方案中，操作工作面1111上设置的气口1112为条形开口，操作头主体111外壁内部设置与条形开口数量对应的条形通槽；每个条形通槽的一端与一个条形开口相连通，另一端与主体腔体相连通。
在某些实施方案中，条形开口为一个，在某些实施方案中，条形开口为直线形。条形开口为多个，并且相邻条形开口之间平行设置。此外，考虑到芯片之间间距均匀，可以设置多个气口1112间隔排布。气口1112可以是单独的圆孔，也可以是间断的条形孔，还可以是一条连续的线状气口。
在某些实施方案中，在气体操作头与芯片接触时，为了避免气体操作头除操作工作面1111外的其它部分误触芯片，可以使得操作工作面1111更加突出操作头主体111的外壁，为此，可以在操作头主体111外壁上设置有凸台1113，并且操作工作面1111位于凸台1113上。
在某些实施方案中，凸台1113的结构不做限定，凸台1113的结构，可以使得工作面更加凸出操作头主体111，减少操作头主体111的体积，进而在气体操作头移动时，可以减少气体操作头与芯片的误接触，进而导致芯片被误接触而错位。凸台1113为方棱、凸台1113为楔形棱、或凸台1113为圆柱形或其它弧形结构均可。
参考图5和图6，本公开涉及晶片转移方法，其包括：
S110：控制吸附装置从第一载台130上吸附第一批晶片，第一批晶片包括至少一个晶片；
S120：控制吸附装置在第二载台140上布置第一批晶片；
S130：控制吸附装置从第一载台130上吸附第二批晶片，第二批晶片包括至少一个晶片；
S140：按预设排布规则相对第一批晶片在第二载台140上布置第二批晶片。
利用本公开实施例提供的晶片转移方法，通过吸附装置将多个晶片从第一载台130上吸附并布置在第二载台140上，通过吸附装置将多个晶片从第一载台130上吸附并布置在第二载台140上。且按照预设排布规则相对第一批晶片在第二载台140上布置第二批晶片，这样能够实现晶片的巨量转移且在将第二载台140上能够按照预设排布规则排布第二批晶片，不仅实现晶片的转移还实现了晶片的排布。
在某些实施方案中，在S110：控制吸附装置从第一载台130上吸附第一批晶片的步骤之前还包括：
S100：控制激光发生器150发射的激光照射到第一载台130上的第一批晶片。
这样能够便于吸附装置将第一载台130上的晶片转移至第二载台140上，提高晶片转移的效率。
参考图7和图8，依据本公开提供的晶片转移方法，其包括：
S700：沿第一方向布置第一排晶片，第一排晶片包括多个晶片；
S710：相对第一排晶片按预设第一预设间隔沿第一方向布置第二排晶片，第二排晶片包括多个晶片；
S720：提取第一列晶片，第一列晶片包括来自第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片；
S730：沿第二方向布置第一列晶片；
S740：提取第二列晶片，第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中剩余的至少一个晶片；
S750：相对第一列晶片按预设第二预设间隔沿第二方向布置第二列晶片。
利用上述的晶片转移方法，通过沿第一方向布置第一排晶片，然后相对第一排晶片布置第二排晶片，第二排晶片与第一排晶片之间具有预设第一预设间隔。然后提取第一列晶片，按第二方向布置第一列晶片，再提取第二列晶片，然后相对第一列晶片排布第二列晶片。第二列晶片与第一列晶片之间具有预设第二预设间隔。这样，多次重复上述步骤，使得多个晶片之间具有预设第一预设间隔和预设第二预设间隔，从而能够根据实际需求对多个晶片之间的间隔进行调整，进而形成具有预设间隔的二维晶片阵列。
当然，本公开提供的晶片转移方法，不仅仅可以对单颗晶片进行转移，也可以对成排的晶片进行转移，还可以应用于封装好的多功能集成单元。由多颗RGB芯片组成的一个彩色像素单元、或者由多颗LED芯片组成的一个背光单元。本实施例提供的晶片转移方法可以应用于集成了逻辑芯片、MEMS装置、或者传感器中的一种或多种的多功能集成电路单元。
参考图8，以其中一个晶片为原点建立二维直角坐标系，以该晶片的一条边为x轴，以该晶片另一条与该条边垂直的边为y轴。图示中第一方向为A方向，第二方向为B方向，即第一方向为沿x轴方向，第二方向为沿y轴方向。第一预设间隔为y1，第二预设间隔为x1。当然，在某些实施方案中，第一方向也可以为y轴方向，第二方向可以为x轴方向。
在某些实施方案中，本公开实施例提供的晶片转移方法，其包括：
S800：沿第一方向布置第一排晶片，第一排晶片包括多个晶片；
S810：相对第一排晶片按预设第一预设间隔沿第一方向布置第二排晶片；
S820：提取第一列晶片，第一列晶片包括来自第一排晶片中的至少一个晶片；
S830：沿第二方向布置第一列晶片；
S840：提取第二列晶片，第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中的至少一个晶片；
S850：相对第一列晶片按预设第二预设间隔沿第二方向布置第二列晶片。
上述的晶片转移方法，通过提取第一列晶片时，第一列晶片包括第一排晶片中的至少一个晶片；提取第二列晶片时，第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中的至少一个晶片。即第一列晶片的数量小于第二列晶片的数量，从而可以根据第一排晶片或第二排晶片的数量对晶片进行转移及排片，使得多个晶片之间具有第一预设间隔和第二预设间隔。
在某些实施方案中，第一排晶片包括两个晶片，第二排晶片包括一个晶片。提取第一列晶片即提取第一排晶片中的一个晶片；提取第二列晶片，即提取第一排晶片中剩余的一个晶片和第二排晶片中的一个晶片。当然，第一排晶片也可以包括一个晶片，第二排晶片也可以包括两个晶片，这样，提取第一列晶片即提取第一排晶片中的一个晶片和第二排晶片中的一个晶片，提取第二列晶片即提取第二排晶片中剩余的一个晶片。
在某些实施方案中，本公开实施例提供的晶片转移方法，其包括：
S310：沿第一方向布置第一排晶片，第一排晶片包括多个晶片；
S320：相对第一排晶片按预设第一预设间隔沿第一方向布置第二排晶片；
S330：提取第一列晶片，第一列晶片包括来自第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片；
S340：沿第二方向布置第一列晶片；
S350：提取第二列晶片，第二列晶片包括来自第一排晶片中剩余的至少一个晶片；
S360：相对第一列晶片按预设第二预设间隔沿第二方向布置第二列晶片。
上述的晶片转移方法，通过提取第一列晶片时，第一列晶片包括第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片；提取第二列晶片时，第二列晶片包括来自第一排晶片中剩余的至少一个晶片。即第一列晶片的数量大于第二列晶片的数量，从而可以根据第一排晶片或第二排晶片的数量对晶片进行转移及排片，使得多个晶片之间具有第一预设间隔和第二预设间隔。
在某些实施方案中，第一排晶片包括两个晶片，第二排晶片包括一个晶片，提取第一列晶片即提取第一排晶片中的一个晶片和第二排晶片中的一个晶片。提取第二列晶片即提取第一排晶片中剩余的一个晶片。当然，第一排晶片也可以包括一个晶片，第二排晶片包括两个晶片，提取第一列晶片即提取第一排晶片中的一个晶片和第二排晶片中的一个晶片。
在某些实施方案中，沿第一方向布置第一排晶片包括：
从晶圆上提取第一排晶片，其中晶圆包括以第一初始间隔排布的第一排晶片和第二排晶片；沿第一方向在第一料盘上布置提取的第一排晶片；
相对第一排晶片按预设第一预设间隔沿第一方向布置第二排晶片包括：
从晶圆上提取第二排晶片；相对第一排晶片按预设第一预设间隔沿第一方向在第一料盘上布置提取的第二排晶片。
这样，通过将晶圆上的晶片排布在第一料盘上，不仅实现了晶片的转移，也实现了将晶片按照第一预设间隔进行排布，进而提高了晶片转移的效率。避免了将晶片从晶圆上转移到其他承载件后，再在其他承载件上对晶片进行排布，然后再将晶圆转移至目标料盘上。利用本公开实施例提供的晶片转移方法，可以在转移晶片的同时对晶片进行排布，实现了晶片的巨量转移。
在某些实施方案中，提取第一列晶片，第一列晶片包括来自第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片，沿第二方向布置第一列晶片包括：
从第一料盘上提取第一列晶片，其中第一料盘包括以第二初始间隔排布的第一列晶片和第二列晶片，第一列晶片包括来自第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片；沿第二方向在第四料盘上布置提取的第一列晶片；
提取第二列晶片，第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中剩余的至少一个晶片；相对第一列晶片按预设第二预设间隔沿第二方向布置第二列晶片包括：
从第一料盘上提取第二列晶片；第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中剩余的至少一个晶片；相对第一列晶片按预设第二预设间隔沿第二方向在第四料盘上布置提取的第二列晶片。
这样，在将第一料盘上的第一列晶片转移至第四料盘上，使得第四料盘上的多个晶片之间具有第一预设间隔和第二预设间隔，从而使得第四料盘上的多个晶片之间形成二维阵列排布。进而实现晶片的巨量转移，并提高晶片转移的效率。
在某些实施方案中，沿第一方向布置第一排晶片包括：
从第二料盘上提取第一排晶片，其中第二料盘包括以第一初始间隔排布的第一排晶片和第二排晶片；沿第一方向在第三料盘上布置提取的第一排晶片；
相对第一排晶片按预设第一预设间隔沿第一方向布置第二排晶片包括：
从第二料盘上提取第二排晶片；相对第一排晶片按预设第一预设间隔沿第一方向在第三料盘上布置第二排晶片。
这样，通过将第二料盘上的晶片排布在第三料盘上，不仅实现了多个晶片之间转移，也实现了将晶片按照第一预设间隔进行排布，进而提高了晶片转移的效率。避免了将晶片从第二料盘上转移到其他承载件后，在其他承载件上对晶片进行排布，然后再讲晶片转移至第三料盘上。利用本公开实施例提供的晶片转移方法，可以在转移晶片的同时对晶片进行排布，实现了晶片的巨量转移。
在某些实施方案中，提取第一列晶片，第一列晶片包括来自第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片，沿第二方向布置第一列晶片包括：
从第三料盘上提取第一列晶片，其中第三料盘包括以第二初始间隔排布的第一列晶片和第二列晶片；第一列晶片包括来自第一排晶片中的至少一个晶片和来自第二排晶片中的至少一个晶片；沿第二方向在第五料盘上布置提取的第一列晶片；
提取第二列晶片，第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中剩余的至少一个晶片；相对第一列晶片按预设第二预设间隔沿第二方向布置第二列晶片包括：
从第三料盘上提取第二列晶片；第二列晶片包括来自第一排晶片中剩余的至少一个晶片和来自第二排晶片中剩余的至少一个晶片；相对第一列晶片按预设第二预设间隔沿第二方向在第五料盘上布置第二列晶片。
这样，在将第三料盘上的第一列晶片转移至第五料盘上，使得第五料盘上的多个晶片之间具有第一预设间隔和第二预设间隔，从而使得第五料盘上的多个晶片之间形成二维阵列排布。进而实现晶片的巨量转移，并提高晶片转移的效率。
在某些实施方案中，第一初始间隔小于第一预设间隔。这样，可以使得转移后的多个晶片具有第一预设间隔。第一预设间隔可以根据实际需要进行设置。同时，使得晶圆切割后的多个晶片按照第一预设间隔进行排布。也可以使得第一料盘上的多个晶片在转移至第二料盘后按照第一预设间隔进行排布。
在某些实施方案中，第二初始间隔小于第二预设间隔。这样可以使得转移后的多个晶片具有第二预设间隔，第二预设间隔可以根据实际需要进行设置。同时，可以使得第一料盘上的多个晶片在转移至第三料盘后按照第二预设间隔进行排布。也可以使得第三料盘上的多个晶片在转移至第五料盘后按照第一预设间隔进行排布。
第一预设间隔介于0.5um至5mm之间，第二预设间隔介于0.5um至5mm之间。在某些实施方案中，第一预设间隔介于0.6um至5mm之间，第二预设间隔介于0.6um至5mm之间。第一预设间隔和第二预设间隔为LED显示屏上多个晶片之间所需的间隔。常规分辨率为1920*1080的高清LED显示屏需要1920*1080*3个Micro LED晶片，合计是620万颗晶片。而显示屏上的晶片需要以第一预设间隔和第二预设间隔构成高密度级的二维阵列结构。
第一方向与第二方向之间具有第一预设角度，第一预设角度介于0°至180°之间。第一方向和第二方向之间具有第一预设角度，这样可以根据实际晶片排布的需要选取需要转移的晶片。
在某些实施方案中，第一方向与第二方向互相垂直。第一预设角度为90°。这样可以提高晶片转移的效率和便于调整晶片排布的位置。同时使得多个晶片之间形成二维阵列结构。
在某些实施方案中，在沿第一方向布置第一排晶片前还包括检测晶片的参数，晶片的参数包括晶片的类型、色差、或波长中的一种或多种。晶片的类型包括红光晶片、蓝光晶片、白光晶片、绿光晶片中的一种或多种。
在某些实施方案中，晶片转移方法包括：
S410：沿第一方向布置第一排晶片，第一排晶片包括多个第一子排晶片，第一子排晶片包括多个晶片；
S420：相对第一排晶片按预设第一预设间隔沿第一方向布置第二排晶片，第二排晶片包括多个第二子排晶片，第二子排晶片包括多个晶片；
S430：提取第一列晶片，第一列晶片包括多个第一子列晶片，第一子列晶片包括来自第一子排晶片中的至少一个晶片和来自第二子排晶片中的至少一个晶片；
S440：沿第二方向布置第一列晶片；
S450：提取第二列晶片，第二列晶片包括多个第二子列晶片，第二子列晶片包括来自第一子排晶片中剩余的至少一个晶片和来自第二子排晶片中剩余的至少一个晶片；
S460：相对第一列晶片按预设第二预设间隔沿第二方向布置第二列晶片。
上述的晶片转移方法，通过布置第一排晶片和第二排晶片，以及布置第一列晶片和第二列晶片，其中，第一排晶片包括多个第一子排晶片，第二排晶片包括多个第一子列晶片。在转移晶片的过程中，可以通过布置多个第一子排晶片和多个第二子排晶片、以及多个第一子列晶片和多个第二子列晶片实现多个晶片的转移，从而形成二维阵列结构。
可以理解的，以上实施例仅表达了本公开的优选实施方式，其描述较为具体和详细，但并不能因此而理解为对本公开专利范围的限制；应当指出的是，对于本领域的普通技术人员来说，在不脱离本公司构思的前提下，可以对上述技术特点进行自由组合，还可以做出若干变形和改进，这些都属于本公开的保护范围；因此，凡跟本公开权利要求范围所做的等同变换与修饰，均应属于本公开权利要求的涵盖范围。

Claims (20)

  1. 晶片转移装置，其包括：吸附机构、驱动机构、第一载台、以及第二载台；
    其中：
    所述第一载台和所述第二载台间隔开设置；
    所述吸附机构包括操作头主体，所述操作头主体为内部中空的主体腔体，所述操作头主体的外壁上设置有凸出所述操作头主体外壁的操作工作面，所述操作工作面上设置有与所述主体腔体相连通的至少一个气口，以用于吸附晶片；以及
    所述驱动机构用于驱动所述吸附机构在所述第一载台和所述第二载台之间运行。
  2. 如权利要求1所述的晶片转移装置，其中，所述吸附机构还包括：操作头基座和密封盖板，其中，
    所述操作头基座固定在所述操作主体上与所述操作工作面的位置相对一侧，所述操作头基座内设置有与所述主体腔体相连通的基座腔体；所述基座腔体上设置有腔体开口；以及
    所述密封盖板可拆卸密封固定在所述腔体开口上；所述密封盖板上设置有贯穿所述密封盖板、且与所述基座腔体相连通的至少一个盖板通孔。
  3. 如权利要求1或2所述的晶片转移装置，其中，所述操作头主体外壁上设置有凸台，所述操作工作面位于所述凸台上的一个面上。
  4. 如权利要求1至3中任一权利要求所述的晶片转移装置，其中，所述气口包括多个气孔开口，所述操作头主体外壁内部设置与所述气孔开口数量对应的气孔通道；每个所述气孔通道一端与一个所述气孔开口相连通，另一端与所述主体腔体相连通。
  5. 如权利要求1至4中任一权利要求所述的晶片转移装置，其中，至少一个所述气口为条形开口；以及
    所述操作头主体外壁内部设置与所述条形开口数量对应的条形通槽；每个所述条形通槽的一端与一个所述条形开口相连通，另一端与所述主体腔体相连通。
  6. 如权利要求2至5中任一权利要求所述的晶片转移装置，其中，所述操作头基座与所述操作头主体一体成型。
  7. 如权利要求1至6中任一权利要求所述的晶片转移装置，其中，所述晶片转移装置包括激光发生器，所述激光发生器设置在所述吸附机构的下方以用于照射所述第一载台上的晶片。
  8. 如权利要求7所述的晶片转移装置，其中，所述激光发生器包括紫外线激光发生器。
  9. 晶片转移方法，其包括：
    控制吸附装置从第一载台上吸附第一批晶片，所述第一批晶片包 括至少一个晶片；
    控制所述吸附装置在第二载台上布置所述第一批晶片；
    控制所述吸附装置从所述第一载台上吸附第二批晶片，所述第二批晶片包括至少一个晶片；以及
    按预设排布规则相对所述第一批晶片在所述第二载台上布置所述第二批晶片。
  10. 如权利要求9所述的晶片转移方法，其中，所述控制吸附装置从第一载台上吸附第一批晶片之前还包括：
    控制所述激光发生器发射的激光照射到所述第一载台上的所述第一批晶片。
  11. 晶片转移方法，其包括：
    沿第一方向布置第一排晶片，所述第一排晶片包括多个晶片；
    相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片，所述第二排晶片包括多个晶片；
    提取第一列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片；
    沿第二方向布置所述第一列晶片；
    提取所述第二列晶片，所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；以及
    相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片。
  12. 如权利要求11所述的晶片转移方法，其中，所述沿第一方向布置第一排晶片包括：
    从晶圆上提取所述第一排晶片，其中所述晶圆包括以第一初始间隔排布的第一排晶片和第二排晶片；沿所述第一方向在所述第一料盘上布置提取的所述第一排晶片；以及
    所述相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片包括：
    从所述晶圆上提取所述第二排晶片；相对所述第一排晶片按预设第一预设间隔沿所述第一方向在所述第一料盘上布置提取的所述第二排晶片。
  13. 如权利要求11或12所述的晶片转移方法，其中，所述提取第一列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片，沿第二方向布置所述第一列晶片包括：
    从所述第一料盘上提取所述第一列晶片，其中所述第一料盘包括以第二初始间隔排布的第一列晶片和第二列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片；沿所述第二方向在所述第四料盘上布置提取的所述第一列晶片；以及
    所述提取所述第二列晶片，所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片包括：
    从所述第一料盘上提取所述第二列晶片；所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向在所述第四料盘上布置提取的所述第二列晶片。
  14. 如权利要求11至13中任一权利要求所述的晶片转移方法，其中，所述沿第一方向布置第一排晶片包括：
    从第二料盘上提取所述第一排晶片，其中所述第二料盘包括以第一初始间隔排布的第一排晶片和第二排晶片；沿所述第一方向在所述第三料盘上布置提取的所述第一排晶片；以及
    所述相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片包括：
    从所述第二料盘上提取所述第二排晶片；相对所述第一排晶片按预设第一预设间隔沿所述第一方向在所述第三料盘上布置所述第二排晶片。
  15. 如权利要求11至14中任一权利要求所述的晶片转移方法，其中，所述提取第一列晶片，所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片，沿第二方向布置所述第一列晶片包括：
    从所述第三料盘上提取所述第一列晶片，其中所述第三料盘包括以第二初始间隔排布的第一列晶片和第二列晶片；所述第一列晶片包括来自所述第一排晶片中的至少一个晶片和来自所述第二排晶片中的至少一个晶片；沿所述第二方向在所述第五料盘上布置提取的所述第一列晶片；以及
    所述提取所述第二列晶片，所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片包括：
    从所述第三料盘上提取所述第二列晶片；所述第二列晶片包括来自所述第一排晶片中剩余的至少一个晶片和来自所述第二排晶片中剩余的至少一个晶片；相对所述第一列晶片按预设第二预设间隔沿所述第二方向在所述第五料盘上布置所述第二列晶片。
  16. 如权利要求11至15中任一权利要求所述的晶片转移方法，其中，所述第一初始间隔小于所述第一预设间隔。
  17. 如权利要求11至16中任一权利要求所述的晶片转移方法，其中，所述第二初始间隔小于所述第二预设间隔。
  18. 如权利要求11至17中任一权利要求所述的晶片转移方法，其中，所述第一方向与所述第二方向之间具有第一预设角度，所述第一 预设角度介于0°至180°之间。
  19. 如权利要求18所述的晶片转移方法，其中，所述第一方向与所述第二方向互相垂直。
  20. 如权利要求11至19中任一权利要求所述的晶片转移方法，其中，所述晶片转移方法包括：
    沿所述第一方向布置第一排晶片，所述第一排晶片包括多个第一子排晶片，所述第一子排晶片包括多个晶片；
    相对所述第一排晶片按预设第一预设间隔沿所述第一方向布置第二排晶片，所述第二排晶片包括多个第二子排晶片，所述第二子排晶片包括多个晶片；
    提取第一列晶片，所述第一列晶片包括多个第一子列晶片，所述第一子列晶片包括来自所述第一子排晶片中的至少一个晶片和来自所述第二子排晶片中的至少一个晶片；
    沿所述第二方向布置所述第一列晶片；
    提取所述第二列晶片，所述第二列晶片包括多个第二子列晶片，所述第二子列晶片包括来自所述第一子排晶片中剩余的至少一个晶片和来自所述第二子排晶片中剩余的至少一个晶片；以及
    相对所述第一列晶片按预设第二预设间隔沿所述第二方向布置所述第二列晶片。
PCT/CN2022/075364 2021-02-08 2022-02-07 晶片转移装置和晶片转移方法 WO2022166953A1 (zh)

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CN108962789A (zh) * 2018-06-25 2018-12-07 开发晶照明（厦门）有限公司 微器件转移方法和微器件转移设备
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