WO2022166085A1 - 故障隔离分析方法及计算机可读存储介质 - Google Patents

故障隔离分析方法及计算机可读存储介质 Download PDF

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Publication number
WO2022166085A1
WO2022166085A1 PCT/CN2021/103478 CN2021103478W WO2022166085A1 WO 2022166085 A1 WO2022166085 A1 WO 2022166085A1 CN 2021103478 W CN2021103478 W CN 2021103478W WO 2022166085 A1 WO2022166085 A1 WO 2022166085A1
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package structure
fault
electrical fault
analysis method
electrical
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PCT/CN2021/103478
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English (en)
French (fr)
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徐元杰
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长鑫存储技术有限公司
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Priority to US17/648,457 priority Critical patent/US20220254691A1/en
Publication of WO2022166085A1 publication Critical patent/WO2022166085A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

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  • the present application relates to the technical field of failure analysis, and in particular, to a fault isolation analysis method and a computer-readable storage medium.
  • the packaging of the device becomes more and more complicated. Substrates, wires, chips, etc. in the device may cause short circuit/leakage faults in the device, and it is difficult to determine where the short circuit/leakage occurs in the device.
  • the most commonly used EFA method for analyzing short-circuit faults is the hot spot analysis method, but this method has certain limitations. Since thermal emission is a two-dimensional analysis, it is impossible to determine which layer of the packaged semiconductor device is short-circuited when using the hot-spot analysis method to analyze the short-circuit fault of the device. For devices with high die stack chips, if there is a short-circuit leakage phenomenon in the middle die core, it is possible that the hot spot is blocked by the upper die core, resulting in the failure of the middle die to be detected.
  • the present application provides a fault isolation analysis method, including providing a package structure with electrical faults, the package structure comprising a substrate, a chip structure and interconnecting wires; wherein, the chip structure is bonded on the substrate, and the The interconnection wire electrically connects the chip structure and the substrate; detects whether the interconnection wire in the package structure has an electrical fault, and if the interconnection wire has an electrical fault, it is determined that the package is The electrical fault of the structure is caused by the interconnection wire; otherwise, the interconnection wire is interrupted to electrically isolate the chip structure from the substrate; and continue to detect whether the package structure still has an electrical fault; if If the package structure still has an electrical fault, it is determined that the substrate has an electrical fault; otherwise, it is determined that the chip structure has an electrical fault.
  • the interconnection wires in the package structure are detected first. If the interconnection wire has an electrical fault, it indicates that the electrical fault of the package structure is caused by the interconnection wire. Otherwise, it indicates that an electrical fault exists on the chip structure or the substrate.
  • the connection between the chip structure and the substrate is interrupted to electrically isolate the chip structure from the substrate, and the package structure at this time is tested to determine whether the package structure still has an electrical fault. If the package structure still has an electrical fault after the chip structure is isolated, it can be judged that there is an electrical fault on the substrate; if there is no electrical fault in the package structure after the chip structure is isolated, it can be judged that the chip structure has no electrical fault. There is an electrical fault on it.
  • each element in the package structure By electrically isolating each element in the package structure one by one, after each element is isolated, it is detected whether there is still an electrical fault in the package structure. If not, it indicates that there is an electrical fault on the isolated element; otherwise, it indicates that the electrical fault is in the element that has not been isolated. The above steps are repeated until a component with an electrical fault in the package structure is found.
  • the fault isolation analysis method is used to analyze the failure of the package structure. No matter how complex the package structure is, and no matter how many components in the package structure may cause electrical failures, this method can always correctly find the fault location and determine the fault in the package structure. Which component has an electrical failure.
  • the present application also provides a computer-readable storage medium on which a computer program is stored, wherein, when the computer program is executed by a processor, the steps of the methods described in the foregoing embodiments are implemented.
  • FIG. 1 is a method flowchart of a fault isolation analysis method according to an embodiment of the present application
  • FIG. 2 is a structural block diagram of a packaging structure according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for judging whether an interconnection wire has an electrical fault according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of judging a short-circuit fault of interconnecting wires according to one embodiment of the present application
  • FIG. 5 is a flowchart of a method for judging whether there is an electrical fault according to a distribution image of interconnecting wires according to an embodiment of the present application
  • FIG. 6 is a flowchart of a method for interrupting the interconnection wires according to an embodiment of the present application
  • FIG. 7 is a schematic diagram of an operation of interrupting interconnection wires according to an embodiment of the present application.
  • FIG. 8 is a top-view operation schematic diagram of interconnection wire interruption according to one embodiment of the present application.
  • FIG. 9 is a flowchart of a method for determining whether a chip structure or a substrate has an electrical fault according to an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for verifying a fault analysis result by using a hot spot analysis method according to an embodiment of the present application
  • FIG. 11 is a flowchart of a method for judging whether to perform isolation detection on a chip structure according to an embodiment of the present application.
  • the packaging of the device becomes more and more complicated. Substrates, wires, chips, etc. in the device may cause short circuit/leakage faults in the device, and it is difficult to determine where the short circuit/leakage occurs in the device.
  • the most commonly used EFA method for analyzing short-circuit faults is the hot spot analysis method, but this method has certain limitations. Since thermal emission is a two-dimensional analysis, it is impossible to determine which layer in the packaged semiconductor device is short-circuited if the hot spot is in the overlapped area of the substrate/wire/chip when using the hot spot analysis method to analyze the short circuit fault of the device. Then for a device with a high-mode stack chip, if there is a short-circuit leakage phenomenon in the middle mold core, the hot spot generated by the middle mold core may be blocked by the upper mold core, so that the intermediate failure cannot be detected.
  • FIG. 1 is a method flowchart of a fault isolation analysis method according to an embodiment of the present application.
  • the fault isolation analysis method includes the following steps S100 to S300.
  • S100 Provide a package structure with electrical faults, the package structure includes a substrate, a chip structure, and interconnecting wires; wherein the chip structure is bonded on the substrate, and the interconnecting wires connect the chip structure with the interconnecting wires.
  • the substrates are electrically connected.
  • S300 Otherwise, break the interconnection wires to electrically isolate the chip structure from the substrate; and continue to detect whether the package structure still has an electrical fault; if the package structure still has an electrical fault, then It is determined that the substrate has an electrical fault; otherwise, it is determined that the chip structure has an electrical fault.
  • FIG. 2 is a structural block diagram of a packaging structure according to an embodiment of the present application.
  • the package structure mainly includes three types of components: a chip structure 100 , a substrate 200 and interconnecting wires 300 .
  • the chip structure 100 may include one or more chips, and the chip structure is bonded on the substrate 200 .
  • the chip structure 100 includes a first chip 101 and a second chip 102 .
  • the first chip 101 and the second chip 102 are electrically connected to the substrate 200 through interconnecting wires 300, respectively.
  • the interconnection wire 300 When checking whether the package structure has an electrical fault, it is first determined whether the interconnection wire 300 has an electrical fault. By checking whether each interconnecting wire 300 is bridged or short-circuited with adjacent wires or other nearby components, it is determined whether the interconnecting wire 300 has an electrical fault. When one or more of the interconnecting wires 300 are bridged or short-circuited, it is determined that there is an electrical fault on the interconnecting wires 300, indicating that the electrical fault of the package structure is caused by the interconnecting wires 300, and the interconnecting wires 300 need to be corrected. 300 for repair or replacement.
  • the interconnection wire 300 If there is no electrical fault on the interconnection wire 300 , it indicates that the electrical fault exists on the chip structure 100 or the substrate 300 .
  • the chip structure 100 By breaking the interconnection wires 300 connecting the chip structure 100 and the substrate 200, the chip structure 100 is electrically isolated from the substrate 200, and then it is detected whether the package structure still has an electrical fault. If the electrical fault of the package structure still exists after the chip structure 100 is electrically isolated, it is determined that the electrical fault occurs at the substrate 200; if the electrical fault of the package structure does not exist after the chip structure 100 is electrically isolated, Then, it is determined that the electrical fault occurs on the chip structure 100 .
  • each component By electrically isolating each part of the components in the package structure one by one, after each component is isolated, it is detected whether there is still an electrical fault in the package structure. If not, it indicates that there is an electrical fault on the isolated element; otherwise, it indicates that the electrical fault is in the element that has not been isolated. The above steps are repeated until a component with an electrical fault in the package structure is found.
  • electrically isolating each component it is necessary to ensure that while the package structure is opened to expose the components that need to be isolated, the functionality of the package structure can also be maintained, so that the chip structure, substrate and other components in the package structure can still work normally.
  • the electrical fault includes short circuit and/or leakage.
  • Short circuit and leakage are the most common failure manifestations in semiconductor devices. Many internal and external factors may cause short circuit and leakage of semiconductor devices. Leakage is usually the leakage of current due to insulation damage or other reasons, while short circuit usually refers to the circuit inside the device or part of the circuit being shorted.
  • Steps S210 to S220 are as follows.
  • S220 Determine whether there is an electrical fault in the interconnection wire according to the distribution image of the interconnection wire.
  • each interconnection wire 300 in the package structure When checking whether there is an electrical fault in each interconnection wire 300 in the package structure, it is first necessary to obtain the actual distribution of the interconnection wires 300 in the package structure.
  • the package structure is imaged using an imaging technology, and a distribution image of the interconnection wires 300 inside the package structure can be obtained without destroying the plastic sealing of the package structure.
  • the distribution image of the interconnection wires 300 it is determined whether the interconnection wires 300 are abnormal or not. For example, it can be judged whether there is an electrical fault of short circuit in the interconnection wire 300 by observing whether any lines intersect in the distribution image.
  • a GE phoenix X-ray detector is used to illuminate the package structure to obtain an image of the distribution of the interconnecting wires inside the package structure.
  • the imaging technology is X-ray fluoroscopic imaging technology. Based on X-ray fluoroscopic imaging technology, according to the thickness and density of each component inside the device, the ability to absorb X-rays is different. After X-rays pass through the plastic sealing layer, transillumination images with different intensity difference distributions will be formed.
  • the flat panel detector can display the difference of X-rays in the form of images, realize high-precision imaging detection of the interconnecting wires 300 inside the package structure, and obtain the distribution image of the interconnecting wires 300, so as to accurately judge according to the distribution image of the interconnecting wires 300 Whether the interconnection wires 300 are defective.
  • GE phoenix X-ray inspection machine has the advantages of high resolution, high precision, anti-vibration, etc., and is equipped with comprehensive X-ray image analysis software, which can extract any cross-section and measure shape and size, thus ensuring the reliability of imaging inspection results. sex.
  • X-rays are used to irradiate the package structure at least from a first direction and a second direction to obtain a distribution image of the interconnection wires inside the package structure at least in the first direction and the second direction .
  • the distribution of the interconnecting wires 300 may also be complicated. From a certain point of view, the interconnecting wires 300 are parallel/disjoint to each other, but from another point of view, there may be situations where the interconnecting wires 300 cross each other.
  • At least X-rays from the first direction and the The package structure is irradiated at two different angles in the second direction to obtain the distribution images of the interconnection wires 300 in the first direction and the second direction, and the distribution images in the two directions are combined to determine whether the interconnection wires 300 exist defects, improving the reliability of imaging inspection results.
  • an appropriate X-ray irradiation angle can be selected according to the design of the connection distribution of the wires in the device and the detection requirements.
  • 3D-X-rays can be used to perform 360-degree surround irradiation imaging on the package structure.
  • the specific method is to fix the X-ray angle and rotate the package structure by 360 degrees to obtain clearer results.
  • the first direction is parallel to the horizontal placement direction of the package structure, and the second direction is perpendicular to the horizontal placement direction of the placement structure.
  • the first direction is the side surface of the package structure, and the second direction is the top surface of the package structure.
  • X-rays can be irradiated on the package structure from other preferred inclination angles according to the design of the connection distribution of the interconnecting wires 300 in the device and the inspection requirements, so as to obtain an image that can more clearly show the interconnecting wires inside the package structure. Distribution image of 300 distribution cases.
  • the interconnecting wires comprise gold wires. When there is a production problem in the process of making the gold wire, it may cause the gold wire to cross. When it is found that there are crossed gold lines on the distribution image, it can be determined that the interconnection wire 300 has a short circuit problem.
  • FIG. 4 is a schematic diagram of judging a short-circuit fault of interconnecting wires according to one embodiment of the present application.
  • Figure (a) in FIG. 4 shows a schematic diagram of a normal interconnecting wire without electrical faults. It can be seen that the interconnecting wires 300 are parallel to each other.
  • (b) in FIG. 4 shows a schematic diagram of interconnecting wires with short-circuit faults. It can be seen that there are two interconnecting wires 300 in the figure that intersect, resulting in a short-circuited electrical circuit in the package structure. Sexual failure.
  • the method for judging the mutual Whether the connecting wire has an electrical fault includes the following steps S221 to S222.
  • the package structure includes two chips, which are a first chip 101 and a second chip 102 respectively, and the first chip 101 and the second chip 102 are respectively connected to the substrate 200 through interconnecting wires 300 .
  • X-rays are used to irradiate the package structure to obtain a distribution image, and the interconnection between the first chip 101 and the second chip 102 and the substrate 200 is determined according to the distribution image. Whether the wire 300 has a short circuit.
  • the package structure can be irradiated from various angles such as the top surface and the side surface according to the test requirements.
  • image recognition is performed on the multiple distribution images one by one, and it is judged whether there is any fracture or damage in the distribution of the interconnecting wires 300 shown in the distribution images. and/or anomalies such as crossovers.
  • the interconnection wire 300 If the interconnection wire 300 is broken and/or damaged, it indicates that the interconnection wire 300 has a leakage electrical fault; if there are two or more interconnection wires 300 crossing each other in the distribution image, it indicates the interconnection The wires 300 have short-circuit electrical faults; if the interconnecting wires 300 in the distribution image do not have any abnormality, it indicates that the electrical fault of the packaging structure does not occur on the interconnecting wires 300, and it is judged that the interconnecting wires 300 are normal.
  • the interconnecting wires are broken using a grinder.
  • a grinder When it is judged that the interconnection wires 300 are normal and fault-free, it is necessary to isolate the chip structure 100 and the substrate 200 one by one to judge on which layer the electrical fault occurs.
  • the purpose of isolating the chip structure 100 from the substrate 200 is achieved by breaking the interconnecting wires 300 for conducting the chip structure 100 and the substrate 200 .
  • a grinding machine with high machining precision is used to drill holes in the package structure at the positions of the interconnecting wires 300 that need to be broken, so as to break the interconnecting wires 300 .
  • a grinder to break the interconnecting wires 300, it is necessary to ensure that no damage is caused to other components in the package structure, that is, it is necessary to ensure the functional effectiveness of other components of the package structure.
  • the grinding machine comprises the ASAP-1 IPS (Analog Selected Area Preparation) milling system of NanoLab Technologies.
  • the interconnecting wires 300 are broken using an ASAP milling system.
  • ASAP-1 IPS uses the latest digital technology to make the grinding process highly automated and programmable, enabling ASAP-1 IPS to grind experimental samples thinner, with more precise grinding size/thickness, smoother polishing, and reverse Processing is more accurate to ensure that every important experimental sample is processed to the best possible state for testing.
  • the packaging structure further includes a plastic sealing layer, and the plastic sealing layer is located on the surface of the substrate, and The chip structure 100 and the interconnection wires 300 in the package structure are plastic-packaged.
  • the illustrated use of a grinder to break the interconnecting wires includes the following steps S310 to S320.
  • S310 Use the grinder to form openings in the plastic encapsulation layer, where the openings expose the interconnecting wires to be broken.
  • S320 Use the grinder to break the exposed interconnecting wires based on the openings.
  • the operation of breaking the interconnection wires 300 is completed by using the ASAP milling system.
  • the ASAP milling system digs a rectangular opening in the plastic packaging layer by drilling, and the interconnection wires inside the package structure are exposed through the opening. Then, set the ASAP milling system to continue drilling down the opening according to the position of the interconnecting wire 300 to be interrupted.
  • FIG. 7 is a schematic diagram of an operation of interrupting interconnection wires according to an embodiment of the present application.
  • the parameters of the ASAP milling system are set according to the position of the interconnection wire 300 in the package structure, and the length, width and depth of the opening are set.
  • FIG. 8 is a schematic top-view operation diagram of the interruption of interconnecting wires according to one embodiment of the present application, and the black rectangle in FIG. 8 is the area to be drilled by the ASAP milling system. Control the ASAP milling system to mill the package structure to the opening at the position of the black rectangle as shown in FIG.
  • the downward milling may be continued based on the opening in (a) of FIG. 7 .
  • the parameters of the ASAP milling system are set, and the length, width and depth of the opening are set, so that the ASAP milling system mills the opening to the black rectangle in Fig. 7(b). position, the interconnection wires 300 connecting the second chip 102 and the substrate 200 can be interrupted.
  • the package structure includes a plurality of stacked chip structures, each of which is The chip structures are all electrically connected to the substrate via the interconnecting wires; the interconnecting wires are interrupted to electrically isolate the chip structure from the substrate, and continue to detect whether the package structure still has electricity If the package structure still has an electrical fault, it is determined that the substrate has an electrical fault; otherwise, the determination that the chip structure has an electrical fault includes the following steps S330 to S340 .
  • S330 Disconnect one of the interconnecting wires, continue to detect whether the package structure still has an electrical fault, and if the electrical fault is eliminated, determine that the chip structure connected to the interrupted interconnecting wire has an electrical fault. Sexual failure.
  • the package structure includes two stacked chips, namely the first chip 101 and the second chip.
  • the two chips 102 , the first chip 101 and the second chip 102 respectively, are electrically connected to the substrate 200 via the interconnecting wires 300 .
  • the interconnecting wires 300 connecting the first chip 101 and the substrate 200 are broken using the ASAP milling system to electrically isolate the first chip 101 . After the first chip 101 is isolated, it is checked whether the package structure still has an electrical fault.
  • the electrical fault of the package structure disappears, it means that the electrical fault exists on the first chip 101, and the second chip 102 and the substrate are normal; if the electrical fault still exists in the package structure, it means that the electrical fault does not exist. Present on the second chip 102, the second chip 102 is normal.
  • the second chip 102 When it is judged that the second chip 102 is normal, the second chip 102 needs to be isolated before further judging the location of the electrical fault. Further drilling down using the ASAP milling system breaks the interconnect wires 300 connecting the second chip 102 with the substrate 200 to electrically isolate the second chip 102 . After the second chip 102 is isolated, it is detected whether the package structure still has an electrical fault. If the electrical fault of the package structure disappears, it means that the electrical fault exists on the second chip 102, and the second chip 102 and the substrate are normal; if the electrical fault still exists in the package structure, it means that the electrical fault exists on the second chip 102 On the substrate, the first chip 101 and the second chip 102 are normal.
  • each time the electrical isolation is completed it is detected whether there is still an electrical fault in the package structure. If not, it indicates that there is an electrical fault on the isolated element; otherwise, it indicates that the electrical fault is in the element that has not been isolated. The above steps are repeated until a component with an electrical fault in the package structure is found.
  • electrically isolating each component it is necessary to ensure that while opening the package structure to expose the components to be isolated, it is also necessary to maintain the functionality of the package structure to ensure that components such as chip structures and substrates in the package structure can still work normally.
  • the chip structure includes a memory chip structure.
  • the chip structure includes a dynamic random access memory chip structure.
  • the fault isolation analysis method It also includes the following steps S400 to S500.
  • S400 Use a hot spot analysis method to verify the failure analysis result of the package structure.
  • S500 According to the analysis result of the hot spot analysis method, determine whether to continue to perform isolation detection on the chip structure and the substrate in the package structure.
  • the fault analysis results can be further verified by means of the hot spot analysis method, so as to prevent omissions in the fault analysis results, so as to improve the detection accuracy of the fault isolation analysis method. Rate.
  • the analysis result of the hot spot analysis method matches the above-mentioned fault analysis result, it indicates that the fault analysis result obtained by the above-mentioned electrical failure analysis process is accurate, and it is not necessary to continue the isolation detection of the chip structure 100 and the substrate 200 in the package structure ; If the analysis result of the hot spot analysis method does not match the above fault analysis result, it indicates that the fault analysis result is missing, and the chip structure 100 and the substrate 200 in the package structure need to be isolated and tested.
  • FIG. 11 is a flowchart of a method for judging whether to perform isolation detection on a chip structure according to an embodiment of the present application.
  • the isolation detection of the chip structure and the substrate within the structure includes the following steps S510 to S520.
  • the obtained analysis result shows that the hot spot does not appear near the interconnection wire 300, but it is judged that the interconnection wire 300 has a short circuit problem according to the distribution image obtained by the X-ray. That proves that there are multiple failure reasons in the packaged device, and it is necessary to further isolate the chip structure 100 and the substrate 200 in the packaged device to determine whether there is an electrical fault on the chip structure 100 and/or the substrate 200 .
  • the analysis result obtained by using the hot spot analysis method shows that the hot spot appears near the interconnection wire 300, and it is also judged that there is a problem with the interconnection wire 300 according to the distribution image obtained by the X-ray, it proves that the packaged device has a single failure, and the failure The analysis results are accurate, and the electrical failure analysis process of the packaged device is completed.
  • the fault analysis result determines that the electrical fault occurs on the chip structure 100/substrate 200, and the electrical failure analysis of the packaged device is performed using the hot spot analysis method
  • the obtained analysis result shows that the hot spot does not appear on the chip structure 100/substrate 200.
  • the vicinity of the substrate 200 also shows that there are various failure reasons in the packaged device, and further electrical isolation of each component in the packaged device is required, and electrical failure analysis is performed again to prevent omission of failure analysis results.
  • the fault analysis result determines that the electrical fault occurs on the chip structure 100/substrate 200, and the analysis result using the hot spot analysis method shows that the hot spot also appears on the chip structure 100/substrate 200, it indicates that the above fault analysis result is correct. of.
  • a probe measurement platform is also used to analyze the short-circuited pin position (Pin), so as to verify whether the analysis result of the fault isolation analysis method is correct.
  • Use the probe measurement platform to obtain the current-voltage (I-V) curve file at the pin position, and judge whether there is a short circuit/leakage fault at the pin position according to the current-voltage (I-V) curve file. If the analysis results obtained according to the current-voltage (I-V) curve file match the failure analysis results of this method, it indicates that the above failure analysis results are correct.
  • the use of the probe measurement platform can realize the verification of the electrical fault of the short circuit.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps in the foregoing method embodiments.
  • Non-volatile memory may include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, or optical memory, and the like.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • the RAM may be in various forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

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Abstract

本申请涉及失效分析技术领域，公开了一种故障隔离分析方法及计算机可读存储介质，该方法包括提供存在电性故障的封装结构；检测所述封装结构内的所述互连导线是否存在电性故障，若所述互连导线存在电性故障，则判定所述封装结构的电性故障由所述互连导线导致；否则，打断所述互连导线，将所述芯片结构与所述基板电隔离；并继续检测所述封装结构是否仍然存在电性故障；若所述封装结构仍存在电性故障，则判定所述基板存在电性故障；否则，判定所述芯片结构存在电性故障。无论封装结构有多复杂，也无论封装结构中有多少元件可能导致电性故障，使用所述故障隔离分析方法对封装结构进行失效分析，总是能够准确地找到故障位置，判断封装结构中的哪一元件发生了电性故障。

Description

故障隔离分析方法及计算机可读存储介质
本申请要求于2021年2月7日提交中国专利局，申请号为202110168367.4，申请名称为“故障隔离分析方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及失效分析技术领域，特别是涉及一种故障隔离分析方法以及计算机可读存储介质。
背景技术
目前，由于制作工艺的不断发展，器件的封装变得越来越复杂。器件内的基板、导线、芯片等都可能会导致器件出现短路/漏电故障，且很难确定器件中短路/漏电发生的位置。目前最常用于分析短路故障的EFA方法是热点分析方法，但该方法存在一定的局限性。由于热发射是二维分析，因此使用热点分析方法对器件的短路故障进行分析时，不能判断处封装半导体器件中的哪一层发生了短路。对于具有高模堆芯片的器件，如果中间模芯出现短路漏电现象，则有可能热点被上部模芯所堵塞，从而导致中间的故障无法被检测到。
发明内容
本申请提供了一种故障隔离分析方法，包括提供存在电性故障的封装结构，所述封装结构包括基板、芯片结构及互连导线；其中，所述芯片结构键合于所述基板上，所述互连导线将所述芯片结构与所述基板电连接；检测所述封装结构内的所述互连导线是否存在电性故障，若所述互连导线存在电性故障，则判定所述封装结构的电性故障由所述互连导线导致；否则，打断所述互连导线，将所述芯片结构与所述基板电隔离；并继续检测所述封装结构是否仍然存在电性故障；若所述封装结构仍存在电性故障，则判定所述基板存在电性故障；否则，判定所述芯片结构存在电性故障。
上述故障隔离分析方法，先对封装结构内的互连导线进行检测。若互连导线存在电性故障，则表明封装结构的电性故障是由互连导线导致的。否则，表明电性故障存在于芯片结构或基板上。打断连接芯片结构和基板的连接，以将芯片结构与基板电隔离，对此时的封装结构进行检测，判断封装结构是否仍然存在电性故障。若在芯片结构隔离开来后，封 装结构仍然存在电性故障，则可以判断基板上存在电性故障；若在芯片结构隔离开来后，封装结构就不存在电性故障，则可以判断芯片结构上存在电性故障。通过将封装结构内的各元件逐一进行电隔离，在对每一元件隔离后，检测封装结构是否仍然存在电性故障。若不存在，则表明被隔离开来的元件上存在电性故障；否则，表明电性故障在尚未被隔离的元件中。重复上述步骤，直至找到封装结构中存在电性故障的元件。使用故障隔离分析方法来对封装结构进行失效分析，不管封装结构有多复杂，也不管封装结构中有多少元件可能导致电性故障，本方法总是能够正确地找到故障位置，判断封装结构中的哪一元件发生了电性故障。
本申请还提供了一种计算机可读存储介质，其上存储有计算机程序，其中，所述计算机程序被处理器执行时实现如上述实施例所述的方法的步骤。
附图说明
为了更清楚地说明本说明书实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本说明书中记载的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请其中一实施例的故障隔离分析方法的方法流程图；
图2为本申请其中一实施例的封装结构的结构框图；
图3为本申请其中一实施例的判断互连导线是否存在电性故障的方法流程图；
图4为本申请其中一实施例的互连导线短路故障判断示意图；
图5为本申请其中一实施例的根据互连导线的分布图像判断是否存在电性故障的方法流程图；
图6为本申请其中一实施例的打断所述互连导线的方法流程图；
图7为本申请其中一实施例的互连导线打断的操作示意图；
图8为本申请其中一实施例的互连导线打断的俯视操作示意图；
图9为本申请其中一实施例的判定芯片结构或基板是否存在电性故障的方法流程图；
图10为本申请其中一实施例的使用热点分析方法对故障分析结果进行验证的方法流程图；
图11为本申请其中一实施例的判断是否对芯片结构进行隔离检测的方法流程图。
附图标记说明：
100、芯片结构；101、第一芯片；102、第二芯片；200、基板；300、互连导线。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的优选实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反的，提供这些实施方式的目的是为了对本申请的公开内容理解得更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”、“上”、“下”、“前”、“后”、“周向”以及类似的表述是基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
目前，由于制作工艺的不断发展，器件的封装变得越来越复杂。器件内的基板、导线、芯片等都可能会导致器件出现短路/漏电故障，且很难确定器件中短路/漏电发生的位置。目前最常用于分析短路故障的EFA方法是热点分析方法，但该方法存在一定的局限性。由于热发射是二维分析，因此使用热点分析方法对器件的短路故障进行分析时，如果热点处于基板/导线/芯片重叠区域，就不能判断封装半导体器件中的哪一层发生了短路。那么对于具有高模堆芯片的器件，如果在中间模芯出现了短路漏电现象，则中间模芯产生的热点有可能被上部模芯所堵塞，从而导致中间的故障无法被检测到。
本申请旨在提出一种有效的故障隔离分析方法来对器件的电性失效原因进行分析，了解器件内故障所在位置。本申请提供的故障隔离分析方法在其中一个实施例主要应用于易失性存储类BGA封装器件中。图1为本申请其中一实施例的故障隔离分析方法的方法流程图，在其中一个实施例中，所述故障隔离分析方法包括如下步骤S100至S300。
S100：提供存在电性故障的封装结构，所述封装结构包括基板、芯片结构及互连导线； 其中，所述芯片结构键合于所述基板上，所述互连导线将所述芯片结构与所述基板电连接。
S200：检测所述封装结构内的所述互连导线是否存在电性故障，若所述互连导线存在电性故障，则判定所述封装结构的电性故障由所述互连导线导致。
S300：否则，打断所述互连导线，将所述芯片结构与所述基板电隔离；并继续检测所述封装结构是否仍然存在电性故障；若所述封装结构仍存在电性故障，则判定所述基板存在电性故障；否则，判定所述芯片结构存在电性故障。
首先，提供需要进行故障隔离分析的封装结构。在本实施例中，所述封装结构为DRAM BGA封装结构。图2为本申请其中一实施例的封装结构的结构框图。如图2所示，所述封装结构主要包括芯片结构100、基板200以及互连导线300这三类部件。其中，芯片结构100可以包括一个或多个芯片，所述芯片结构键合于所述基板200上。在本实施例中，所述芯片结构100中包括第一芯片101和第二芯片102。第一芯片101和第二芯片102分别通过互连导线300与基板200电连接。
在检查该封装结构是否存在电性故障时，首先判断互连导线300是否存在电性故障。通过检查各互连导线300是否与相邻导线或者附近其他元件存在桥接或者短路现象，来判断互连导线300是否存在电性故障。当其中一条或多条互连导线300存在桥接或者短路现象，则判断该互连导线300上存在电性故障，表明封装结构的电性故障是由互连导线300导致的，需要对互连导线300进行维修或替换。
若互连导线300不存在电性故障，则表明电性故障存在于芯片结构100或基板300上。通过打断连接芯片结构100和基板200之间连接的互连导线300，将芯片结构100与基板200电隔离，然后检测封装结构是否仍然存在电性故障。若在将芯片结构100电隔离后，封装结构的电性故障仍然存在，则判断电性故障出现在基板200处；若在将芯片结构100电隔离后，封装结构便不存在电性故障了，则判断电性故障出现在芯片结构100上。
通过将封装结构内的各部分元件逐一进行电隔离，在对每一个元件进行隔离后，检测封装结构是否仍然存在电性故障。若不存在，则表明被隔离开来的元件上存在电性故障；否则，表明电性故障在尚未被隔离的元件中。重复上述步骤，直至找到封装结构中存在电性故障的元件。在对各部件进行电隔离时，需要保证在打开封装结构露出所需要隔离的元件的同时，还能够保持封装结构的功能性，确保封装结构内的芯片结构、基板等元件还是可以正常工作的。不管封装结构有多复杂，也不管封装结构中有多少元件可能导致电性故障，使用本申请提供的所述故障隔离分析方法来对封装结构进行失效分析，都能够正确地找到故障位置，判断封装结构中的哪一个元件上发生了电性故障。
在其中一个实施例中，所述电性故障包括短路和/或漏电。导致半导体器件出现电性故障的原因有很多种，短路和漏电则是半导体器件中最为常见的故障表现，许多种内外因素都有可能会导致半导体器件出现短路和漏电。漏电通常是由于绝缘损坏或其他原因而引起的电流泄漏，而短路通常是指器件内部电路或电路中的一部分被短接。在半导体器件出现故障时，首先需要确定是器件种的哪一部分存在电性故障，然后才能进一步地对该部件出现故障的原因进行溯源。
图3为本申请其中一实施例的判断互连导线是否存在电性故障的方法流程图，在其中一个实施例中，所述检测所封装结构内的所述互连导线是否存在电性故障包括如下步骤S210至S220。
S210：获取所述封装结构内部的所述互连导线的分布图像。
S220：根据所述互连导线的分布图像判断所述互连导线是否存在电性故障。
在对封装结构内各互连导线300是否存在电性故障时，首先需要获取封装结构内部互连导线300实际的分布情况。在本实施例中，利用成像技术对所述封装结构进行成像，可以在不破坏该封装结构塑封的情况下获取该封装结构内部互连导线300的分布图像。然后，根据互连导线300的分布图像，对互连导线300是否存在异常进行判断。例如，可以通过观察分布图像中是否有线条出现了交叉，来判断互连导线300是否存在短路的电性故障。
在其中一个实施例中，使用GE phoenix X射线检测机照射所述封装结构，以获取所述封装结构内部的所述互连导线的分布图像。在本实施例中，所述成像技术为X射线透视成像技术。以X射线透视成像技术为基础，根据器件内部各部件的厚度与密度不同，对X射线吸收能力有差异，X射线在透过塑封层后，将形成具有不同强度差分布的透照图像。平板探测器可以将X射线的差异以图像形式显示，实现对封装结构内部互连导线300的高精度成像检测，获取互连导线300的分布图像，从而可以根据互连导线300的分布图像准确判断所述互连导线300是否存在缺陷。GE phoenix X射线检测机具有高分辨率、高精密度、抗震动等优点，并配备有全面的X射线图像分析软件，可以提取任意断面，进行形状以及尺寸的测量，从而确保成像检测结果的可靠性。
在其中一个实施例中，使用X射线至少从第一方向和第二方向照射所述封装结构，以获取所述封装结构内部至少在第一方向和第二方向的所述互连导线的分布图像。当封装结构内元件构成复杂时，互连导线300的分布情况也可能会比较复杂。从某一角度来看各互连导线300彼此平行/不相交，然而从另一个角度来看可能存在互连导线300交叉的情况， 因此，在实际检测时至少需要使用X射线从第一方向和第二方向两个不同的角度来照射封装结构，以获取互连导线300在第一方向和第二方向上的分布图像，并综合两个方向上的分布图像判断所述互连导线300是否存在缺陷，提高成像检测结果的可靠性。在实际检测时，可以根据器件中导线的连接分布设计和检测需求，选择合适的X射线照射角度。
在其中一个实施例中，可以采用3D-X射线对封装结构进行360度环绕照射成像，具体做法为固定X射线角度，使封装结构旋转360度以得到更加清晰的结果。
在其中一个实施例中，所述第一方向与所述封装结构水平放置方向平行，所述第二方向与所述放置结构水平放置方向垂直。在本实施例中，所述第一方向为所述封装结构的侧面，所述第二方向为所述封装结构的顶面。通过分别从侧面和从顶面对所述封装结构照射X光，可以分别获取水平方向和垂直方向上所述封装结构内部的互连导线300分布情况，确保实验人员能够更清晰直观地观察各互连导线300是否与相邻导线或者附近其他元件存在桥接或者短路现象。在实际检测时，可以根据器件中互连导线300的连接分布设计和检测需求，从其他优选的倾斜角度对封装结构照射X光，以获取能够更清晰地展现所述封装结构内部各互连导线300分布情况的分布图像。
在其中一个实施例中，所述互连导线包括金线。当打金线的工艺流程中出现制作问题时，就有可能会导致金线交叉。当发现分布图像上存在交叉的金线时，就可以判断互连导线300存在短路问题。图4为本申请其中一实施例的互连导线短路故障判断示意图，图4中的(a)图展示的是正常无电性故障的互连导线示意图，可见，各互连导线300间彼此平行/不相交；而图4中的(b)图展示的是存在短路故障的互连导线示意图，可见图中存在两条互连导线300存在交叉的情况，从而导致了封装结构出现了短路的电性故障。
图5为本申请其中一实施例的根据互连导线的分布图像判断是否存在电性故障的方法流程图，在其中一个实施例中，所述根据所述互连导线的分布图像判断所述互连导线是否存在电性故障包括如下步骤S221至S222。
S221：当所述互连导线的分布图像中的所述互连导线存在断裂和/或交叉的情况，则判断所述互连导线存在电性故障。
S222：否则，判断所述互连导线正常。
以图2所示的封装结构为例，对根据互连导线300的分布图像判断是否存在电性故障的判断过程进行说明。该封装结构包括两个芯片分别是第一芯片101和第二芯片102，第一芯片101和第二芯片102分别通过互连导线300与基板200相连接。当图2中所示的封装结构存在短路和/或漏电的情况时，首先使用X射线照射封装结构获取分布图像，根据 分布图像判断第一芯片101和第二芯片102与基板200连接的互连导线300是否有短路。在实际应用时，可以根据测试需求从顶面、侧面等多个不同的角度对封装结构进行照射。
在获取了封装结构内部不同角度的互连导线300的分布图像后，分别对多张分布图像逐一进行图像识别，判断分布图像中所展现的各互连导线300的分布情况中是否存在断裂、破损和/或交叉等异常情况。若互连导线300存在断裂和/或破损，则表明该互连导线300存在漏电的电性故障；若分布图像中存在两条或多条互连导线300两两交叉的情况，则表明互连导线300存在短路的电性故障；若分布图像中的各互连导线300不存在任何异常现象，则表明封装结构的电性故障并没有发生在互连导线300上，判断互连导线300正常。
在其中一个实施例中，使用研磨机打断所述互连导线。当判断互连导线300正常无故障时，需要对芯片结构100和基板200逐一进行隔离，来判断电性故障出现在哪一层上。通过打断用于导通芯片结构100和基板200的互连导线300，来实现芯片结构100与基板200隔离的目的。在本实施例中，利用加工精度高的研磨机在需要被打断的互连导线300所在位置对封装结构进行钻孔，以打断互连导线300。在使用研磨机打断互连导线300时，需要保证不会对封装结构内其他部件造成损害，即需要保证封装结构其他部件的功能有效性。
在其中一个实施例中，所述研磨机包括NanoLab Technologies公司的ASAP-1 IPS(Analog Selected Area Preparation)铣削系统。在本实例中，使用ASAP铣削系统打断所述互连导线300。ASAP-1 IPS通过运用最新的数字技术，使得研磨流程具有高自动化以及可编程化等优点，使得ASAP-1 IPS能够将实验样品研磨得更薄，研磨尺寸/厚度更精密，抛光更平坦，反加工更准确，从而确保每个重要的实验样品都能被加工到最佳备测状态。
图6为本申请其中一实施例的打断所述互连导线的方法流程图，在其中一个实施例中，所述封装结构还包括塑封层，所述塑封层位于所述基板的表面，且将封装结构内的芯片结构100及互连导线300塑封。所示使用研磨机打断所述互连导线包括如下步骤S310至S320。
S310：使用所述研磨机于所述塑封层内形成开口，所述开口暴露出需要打断的所述互连导线。
S320：基于所述开口使用所述研磨机将暴露出的所述互连导线打断。
利用ASAP铣削系统完成将互连导线300打断的操作，ASAP铣削系统通过钻孔的方式在塑封层挖一个长方体的开口，通过开口将封装结构内部的互连导线暴露出来。然后， 根据需要打断的互连导线300所在的位置设置ASAP铣削系统继续在开口处向下钻孔，此时开口的长宽深都需要根据互连导线300的位置来设置操作参数。
以图2所示的封装结构为例，对打断互连导线300的过程进行说明。图7为本申请其中一实施例的互连导线打断的操作示意图。当需要打断第一芯片101与基板200连接的互连导线300时，根据该互连导线300在封装结构中所处的位置对ASAP铣削系统进行参数设置，设置开口的长宽深。图8为本申请其中一实施例的互连导线打断的俯视操作示意图，图8中的黑色矩形即为ASAP铣削系统需要钻削的区域。控制ASAP铣削系统在封装结构上铣削至如图7(a)中黑色矩形所在位置的开口，将开口开至该位置即可将第一芯片101与基板200连接的互连导线300打断。
同样地，当需要打断第二芯片102与基板200连接的互连导线300时，可以在图7中的(a)图中开口的基础上，继续向下铣削。根据该互连导线300在封装结构中所处的位置对ASAP铣削系统进行参数设置，设置开口的长宽深，令ASAP铣削系统将开口铣削至如图7中的(b)图中黑色矩形的位置，即可将第二芯片102与基板200连接的互连导线300打断。
图9为本申请其中一实施例的判定芯片结构或基板是否存在电性故障的方法流程图，在其中一个实施例中，所述封装结构内包括多个叠置的所述芯片结构，各所述芯片结构均经由所述互连导线与所述基板电连接；所述打断所述互连导线，将所述芯片结构与所述基板电隔离，并继续检测所述封装结构是否仍然存在电性故障，若所述封装结构仍存在电性故障，则判定所述基板存在电性故障，否则，判定所述芯片结构存在电性故障包括如下步骤S330至S340。
S330：打断一所述互连导线，继续检测所述封装结构是否仍然存在电性故障，若电性故障消除，则判定与打断的所述互连导线相连接的所述芯片结构存在电性故障。
S340：否则，重复上述步骤，直至所有所述互连导线均被打断，继续检测所述封装结构是否仍然存在电性故障，若所述封装结构仍存在电性故障，则判定所述基板存在电性故障，否则，判定与最后打断的所述互连导线相连接的所述芯片结构存在电性故障。
以图2所示的封装结构为例，对判定芯片结构100或基板200是否存在电性故障的判断过程进行说明，该封装结构内包括两个叠置的芯片，分别是第一芯片101和第二芯片102，分别是第一芯片101和第二芯片102均经由互连导线300与基板200电连接。首先，使用ASAP铣削系统将第一芯片101与基板200连接的互连导线300打断，以对第一芯片101进行电隔离。在将第一芯片101隔离开来后，对该封装结构是否仍然存在电性故障进 行检测。若该封装结构的电性故障消失，则表明电性故障存在于第一芯片101上，第二芯片102和基板是正常的；若该封装结构仍然存在电性故障，则表明电性故障并不存在于第二芯片102上，第二芯片102是正常的。
当判断第二芯片102正常时，则需要对第二芯片102进行隔离后再进一步对电性故障的发生位置进行判断。使用ASAP铣削系统进一步向下钻削，将第二芯片102与基板200连接的互连导线300打断，以对第二芯片102进行电隔离。在将第二芯片102隔离开来后，对该封装结构是否仍然存在电性故障进行检测。若该封装结构的电性故障消失，则表明电性故障存在于第二芯片102上，第二芯片102和基板是正常的；若该封装结构仍然存在电性故障，则表明电性故障存在于基板上，第一芯片101和第二芯片102是正常的。
通过将封装结构内的各元件逐一进行电隔离，每当完成一次电隔离后，即对封装结构是否仍然存在电性故障进行检测。若不存在，则表明该被隔离开的元件上存在电性故障；否则，表明电性故障在尚未被隔离的元件中。重复上述步骤，直至找到封装结构中存在电性故障的元件。在对各部件进行电隔离时，需要保证在打开封装结构露出所需要隔离的元件的同时，还需要保持封装结构的功能性，确保封装结构内的芯片结构、基板等元件还是可以正常工作的。
使用本申请提供的故障隔离分析方法对封装结构进行电性失效分析时，不管该封装结构有多复杂，也不管封装结构中有多少元件可能导致电性故障，都能够正确地找到故障所在位置，判断封装结构中的哪一个元件上发生了电性故障。
在其中一个实施例中，所述芯片结构包括存储器芯片结构。
在其中一个实施例中，所述芯片结构包括动态随机存取存储器芯片结构。
图10为本申请其中一实施例的使用热点分析方法对故障分析结果进行验证的方法流程图，在其中一个实施例中，当所述互连导线存在电性故障时，所述故障隔离分析方法还包括如下步骤S400至S500。
S400：使用热点分析方法对所述封装结构的故障分析结果进行验证。
S500：根据所述热点分析方法的分析结果，判断是否要继续对所述封装结构内的所述芯片结构及所述基板进行隔离检测。
半导体器件出现电性失效时，在绝大部分的情况下都是单一失效，同时有两个元件出现电性失效的概率很小，但是仍然存在多种失效的可能。因此，在经过上述实施例中的步骤完成对封装结构的故障分析后，可以借助热点分析方法来对故障分析结果进行进一步的验证，防止故障分析结果存在遗漏，以提高故障隔离分析方法的检测准确率。若热点分析 方法的分析结果与上述故障分析结果相匹配，则表明上述电性失效分析过程所得到的故障分析结果是准确的，不需要继续对封装结构内的芯片结构100及基板200进行隔离检测；若热点分析方法的分析结果与上述故障分析结果不匹配，则表明故障分析结果存在遗漏的情况，需要继续对封装结构内的芯片结构100及基板200进行隔离检测。
图11为本申请其中一实施例的判断是否对芯片结构进行隔离检测的方法流程图，在其中一个实施例中，所述根据所述热点分析方法的分析结果，判断是否要继续对所述封装结构内的所述芯片结构及所述基板进行隔离检测包括如下步骤S510至S520。
S510：若根据热点分析方法判定所述封装结构的电性故障非所述互连导线导致，则判定所述封装结构存在多处故障，需打断所述互连导线，将所述芯片结构与所述基板电隔离；并继续检测所述封装结构是否仍然存在电性故障。
S520：若根据热点分析方法判定所述封装结构的电性故障由所述互连导线导致，则判定所述封装结构存在单一故障，分析结束。
当使用热点分析方法对封装器件进行电性失效分析时，所得的分析结果上显示热点并不是出现在互连导线300附近，而根据X射线获取的分布图像却判断互连导线300存在短路问题，那就证明了该封装器件中存在多种失效原因，需要进一步对封装器件中的芯片结构100和基板200进行隔离，以对芯片结构100和/或基板200上是否存在电性故障进行判断。反之，若使用热点分析方法所得的分析结果上显示热点出现在互连导线300附近，且根据X射线获取的分布图像也判断互连导线300存在问题，则证明该封装器件是单一失效，且故障分析结果是准确的，完成了对该封装器件的电性失效分析过程。
同样地，当故障分析结果判断电性故障出现在芯片结构100/基板200上，而使用热点分析方法对封装器件进行电性失效分析时，所得分析结果上显示热点并不是出现在芯片结构100/基板200附近，也表明了该封装器件中存在多种失效原因，还需要进一步对该封装器件中各部件进行电隔离，并再次进行电性失效分析，防止故障分析结果存在遗漏。反之，若故障分析结果判断电性故障出现在芯片结构100/基板200上，且使用热点分析方法的分析结果上显示热点也出现在芯片结构100/基板200上，则表明上述故障分析结果是正确的。
在其中一个实施例中，还使用探针量测平台对所述短路的引脚位(Pin)进行分析，以验证所述故障隔离分析方法的分析结果是否正确。使用探针量测平台获取引脚位处的电流-电压(I-V)曲线图文件，根据电流-电压(I-V)曲线图文件判断该引脚位处是否存在短路/漏断故障。若根据电流-电压(I-V)曲线图文件所得的分析结果与本方法的故障分析结果相匹配，则表明上述故障分析结果是正确的。在本实施例中，使用探针量测平台可以实现对所述短 路的电性故障的验证。
在一个实施例中，提供了一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现上述各方法实施例中的步骤。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和易失性存储器中的至少一种。非易失性存储器可包括只读存储器(Read-Only Memory，ROM)、磁带、软盘、闪存或光存储器等。易失性存储器可包括随机存取存储器(Random Access Memory，RAM)或外部高速缓冲存储器。作为说明而非局限，RAM可以是多种形式，比如静态随机存取存储器(Static Random Access Memory，SRAM)或动态随机存取存储器(Dynamic Random Access Memory，DRAM)等。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种故障隔离分析方法，包括：
    提供存在电性故障的封装结构，所述封装结构包括基板、芯片结构及互连导线；其中，所述芯片结构键合于所述基板上，所述互连导线将所述芯片结构与所述基板电连接；
    检测所述封装结构内的所述互连导线是否存在电性故障，若所述互连导线存在电性故障，则判定所述封装结构的电性故障由所述互连导线导致；
    否则，打断所述互连导线，将所述芯片结构与所述基板电隔离；并继续检测所述封装结构是否仍然存在电性故障；若所述封装结构仍存在电性故障，则判定所述基板存在电性故障；否则，判定所述芯片结构存在电性故障。
  2. 根据权利要求1所述的故障隔离分析方法，其中，所述电性故障包括短路和/或漏电。
  3. 根据权利要求1所述的故障隔离分析方法，其中，所述检测所封装结构内的所述互连导线是否存在电性故障包括：
    获取所述封装结构内部的所述互连导线的分布图像；
    根据所述互连导线的分布图像判断所述互连导线是否存在电性故障。
  4. 根据权利要求3所述的故障隔离分析方法，其中，使用X射线照射所述封装结构，以获取所述封装结构内部的所述互连导线的分布图像。
  5. 根据权利要求4所述的故障隔离分析方法，其中，使用X射线至少从第一方向和第二方向照射所述封装结构，以获取所述封装结构内部至少在第一方向和第二方向的所述互连导线的分布图像。
  6. 根据权利要求5所述的故障隔离分析方法，其中，所述第一方向与所述封装结构水平放置方向平行，所述第二方向与所述封装结构水平放置方向垂直。
  7. 根据权利要求1所述的故障隔离分析方法，其中，所述互连导线包括金线。
  8. 根据权利要求3所述的故障隔离分析方法，其中，所述根据所述互连导线的分布图像判断所述互连导线是否存在电性故障包括：
    当所述互连导线的分布图像中的所述互连导线存在断裂和/或交叉的情况，则判断所述互连导线存在电性故障；
    否则，判断所述互连导线正常。
  9. 根据权利要求1所述的故障隔离分析方法，其中，使用研磨机打断所述互连导线。
  10. 根据权利要求9所述的故障隔离分析方法，其中，所述封装结构还包括塑封层， 所述塑封层位于所述基板的表面，且将所述芯片结构及所述互连导线塑封；所述使用研磨机打断所述互连导线包括：
    使用所述研磨机于所述塑封层内形成开口，所述开口暴露出需要打断的所述互连导线；
    基于所述开口使用所述研磨机将暴露出的所述互连导线打断。
  11. 根据权利要求1所述的故障隔离分析方法，其中，所述封装结构内包括多个叠置的所述芯片结构，各所述芯片结构均经由所述互连导线与所述基板电连接；所述打断所述互连导线，将所述芯片结构与所述基板电隔离，并继续检测所述封装结构是否仍然存在电性故障，若所述封装结构仍存在电性故障，则判定所述基板存在电性故障，否则，判定所述芯片结构存在电性故障包括：
    打断一所述互连导线，继续检测所述封装结构是否仍然存在电性故障，若电性故障消除，则判定与打断的所述互连导线相连接的所述芯片结构存在电性故障；
    否则，重复上述步骤，直至所有所述互连导线均被打断，继续检测所述封装结构是否仍然存在电性故障，若所述封装结构仍存在电性故障，则判定所述基板存在电性故障，否则，判定与最后打断的所述互连导线相连接的所述芯片结构存在电性故障。
  12. 根据权利要求1所述的故障隔离分析方法，其中，所述芯片结构包括存储器芯片结构。
  13. 根据权利要求12所述的故障隔离分析方法，其中，所述芯片结构包括动态随机存取存储器芯片结构。
  14. 根据权利要求1所述的故障隔离分析方法，其中，当所述互连导线存在电性故障时，所述故障隔离分析方法还包括：
    使用热点分析方法对所述封装结构的故障分析结果进行验证；
    根据所述热点分析方法的分析结果，判断是否要继续对所述封装结构内的所述芯片结构及所述基板进行隔离检测。
  15. 根据权利要求14所述的故障隔离分析方法，其中，所述根据所述热点分析方法的分析结果，判断是否要继续对所述封装结构内的所述芯片结构及所述基板进行隔离检测包括：
    若根据热点分析方法判定所述封装结构的电性故障非所述互连导线导致，则判定所述封装结构存在多处故障，需打断所述互连导线，将所述芯片结构与所述基板电隔离；并继续检测所述封装结构是否仍然存在电性故障；
    若根据热点分析方法判定所述封装结构的电性故障由所述互连导线导致，则判定所述封装结构存在单一故障，分析结束。
  16. 一种计算机可读存储介质，其上存储有计算机程序，其中，所述计算机程序被处理器执行时实现如权利要求1所述的方法的步骤。
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