WO2022166036A1 - 阵列基板及其制备方法、短路修补方法 - Google Patents

阵列基板及其制备方法、短路修补方法 Download PDF

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Publication number
WO2022166036A1
WO2022166036A1 PCT/CN2021/095404 CN2021095404W WO2022166036A1 WO 2022166036 A1 WO2022166036 A1 WO 2022166036A1 CN 2021095404 W CN2021095404 W CN 2021095404W WO 2022166036 A1 WO2022166036 A1 WO 2022166036A1
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Prior art keywords
base substrate
region
orthographic projection
area
metal layer
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PCT/CN2021/095404
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English (en)
French (fr)
Inventor
严佩坚
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/425,675 priority Critical patent/US11990379B2/en
Publication of WO2022166036A1 publication Critical patent/WO2022166036A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a method for preparing the same, and a method for repairing a short circuit.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • GOA Gate Driver on Array
  • Mini-LED Minimum Light Emitting Diode
  • Current requirements multiple TFT parallel structures are usually used as switching units in GOA technology and Mini-LED technology.
  • the GOA unit is connected to the sub-pixel unit in the array substrate through the switch unit, so as to drive the sub-pixel unit to emit light and display.
  • the switch unit when a short circuit occurs between metals on the same layer, it can be repaired, and the overall switch unit can still work.
  • the present application provides an array substrate, a method for preparing the same, and a method for repairing a short circuit, so as to solve the problem that in the existing array substrate, when a short circuit occurs between the upper and lower metal layers, the short circuit cannot be repaired, resulting in a low yield rate, and even the entire The technical problem of the scrapping of the switch unit.
  • the present application provides an array substrate, which includes a base substrate and at least one switch unit disposed on the base substrate, each switch unit includes a plurality of TFTs connected in parallel with each other, and each switch unit includes at least one switch unit. a first TFT group and a second TFT group arranged in two rows;
  • a first metal layer, a gate insulating layer, a semiconductor layer, and a second metal layer are arranged on the base substrate in sequence, the first metal layer is provided with a hollow area, and the semiconductor layer includes the same structure as the first TFT group.
  • the corresponding first area and the second area corresponding to the second TFT group, the orthographic projection of the area between the first area and the second area on the base substrate completely covers the hollow area Orthographic projection on the base substrate.
  • the first metal layer at least includes the gate electrode of the TFT
  • the second metal layer at least includes a first connection wire, a second connection wire, the source electrode of the TFT and the the drain of the TFT
  • the sources of the plurality of TFTs in the first TFT group are connected through the first connection wires, and the drain electrodes of the plurality of TFTs in the second TFT group are connected through the second connection wires connected.
  • the orthographic projection of the first connection trace on the base substrate is close to the side of the first region, which is the same as the orthographic projection of the hollow region on the base substrate. There is a first gap between one side close to the first area;
  • the orthographic projection of the first connection trace on the base substrate is close to the side of the second area and the orthographic projection of the hollow area on the base substrate is close to the side of the second area There is a second gap therebetween.
  • the range of the first gap is 4um-6um
  • the range of the second gap is 4um-6um
  • the orthographic projection of the first region on the base substrate is close to one side of the second region, and the orthographic projection of the hollow region on the base substrate is close to all One side of the first area is converging;
  • the orthographic projection of the second region on the base substrate is close to the side of the first region, which coincides with the side of the orthographic projection of the hollow region on the base substrate that is close to the second region .
  • the gate insulating layer is filled in the hollow area.
  • the present application provides a method for preparing an array substrate, comprising the following steps:
  • a semiconductor layer is formed on the gate insulating layer, the semiconductor layer includes a first region and a second region, and an orthographic projection of a region between the first region and the second region on the base substrate completely covering the orthographic projection of the hollow region on the base substrate;
  • the first metal layer, the gate insulating layer, the semiconductor layer and the second metal layer together form at least one switch unit, each switch unit includes a plurality of TFTs connected in parallel, each The switch unit includes a first TFT group and a second TFT group arranged in at least two rows.
  • the present application provides a method for preparing an array substrate, wherein the etching of the first metal layer to form a hollow area includes the following steps:
  • the first metal layer is etched to form the hollow area.
  • the present application provides a method for preparing an array substrate.
  • the first metal layer includes at least the gate electrode of the TFT, and the second metal layer includes at least a first connection wire, a second connection wire, and a gate of the TFT. a source electrode and a drain electrode of the TFT;
  • the sources of the plurality of TFTs in the first TFT group are connected through the first connection wires, and the drain electrodes of the plurality of TFTs in the second TFT group are connected through the second connection wires connected.
  • the present application provides a preparation method of an array substrate, wherein the orthographic projection of the first connection trace on the base substrate is close to the side of the first region, and the hollowed-out region is on the base substrate There is a first gap between one side of the orthographic projection close to the first area;
  • the orthographic projection of the first connection trace on the base substrate is close to the side of the second area and the orthographic projection of the hollow area on the base substrate is close to the side of the second area There is a second gap therebetween.
  • the present application provides a method for preparing an array substrate, wherein the range of the first gap is 4um-6um, and the range of the second gap is 4um-6um.
  • the present application provides a method for preparing an array substrate.
  • the orthographic projection of the first region on the base substrate is close to the side of the second region, which is different from the orthographic projection of the hollow region on the base substrate.
  • a side of the projection close to the first zone is coincident;
  • the orthographic projection of the second region on the base substrate is close to the side of the first region, which coincides with the side of the orthographic projection of the hollow region on the base substrate that is close to the second region .
  • the present application provides a preparation method of an array substrate, wherein the gate insulating layer is filled in the hollow area.
  • the present application provides a method for repairing a short circuit of an array substrate, comprising the following steps:
  • An array substrate includes a base substrate and at least one switch unit disposed on the base substrate, each of the switch units includes a plurality of TFTs connected in parallel with each other, and each of the switch units includes The first TFT group and the second TFT group are arranged in at least two rows; a first metal layer, a gate insulating layer, a semiconductor layer and a second metal layer are arranged on the base substrate in sequence, and the first metal layer is provided with There is a hollow area, the semiconductor layer includes a first area corresponding to the first TFT group and a second area corresponding to the second TFT group, and the area between the first area and the second area
  • the orthographic projection on the base substrate completely covers the orthographic projection of the hollow region on the base substrate;
  • the laser repairing machine finds the corresponding defect point and the faulty TFT according to the position coordinates of the defect point;
  • the faulty TFT is disconnected by laser irradiating the first cutting point and the second cutting point located on both sides of the defect point, and the first cutting point and the second cutting point are located on the second metal layer , the orthographic projection of the second cutting point on the base substrate falls into the orthographic projection of the hollow region on the base substrate.
  • the orthographic projection of the first cutting point on the base substrate does not coincide with the orthographic projection of the first metal layer on the base substrate.
  • the first metal layer at least includes the gate electrode of the TFT
  • the second metal layer at least includes a first connection wire, a second connection wire, the TFT the source and the drain of the TFT
  • the sources of the plurality of TFTs in the first TFT group are connected through the first connection wires, and the drain electrodes of the plurality of TFTs in the second TFT group are connected through the second connection wires connected.
  • the orthographic projection of the first connection trace on the base substrate is close to one side of the first area, and the hollow area is on the base substrate. There is a first gap between one side of the orthographic projection on the first area close to the first area;
  • the orthographic projection of the first connection trace on the base substrate is close to the side of the second area and the orthographic projection of the hollow area on the base substrate is close to the side of the second area There is a second gap therebetween.
  • the range of the first gap is 4um-6um
  • the range of the second gap is 4um-6um
  • the orthographic projection of the first region on the base substrate is close to the side of the second region, which is different from the side of the hollowed-out region on the base substrate.
  • One side of the orthographic projection close to the first zone is coincident;
  • the orthographic projection of the second region on the base substrate is close to the side of the first region, which coincides with the side of the orthographic projection of the hollow region on the base substrate that is close to the second region .
  • the gate insulating layer is filled in the hollow area.
  • the beneficial effects of the present application are as follows: the array substrate provided by the present application, a method for preparing the same, and a method for repairing a short circuit are provided with a hollow area through the first metal layer, and the semiconductor layer includes a first area corresponding to the first TFT group and a second TFT corresponding to the first area.
  • the second area corresponding to the group, the hollow area is set corresponding to at least part of the area between the first area and the second area.
  • the hollow area is There is no first metal layer, and the laser can cut off part of the second metal layer on both sides of the short-circuit defect through the hollow area from below the first metal layer, so as to damage the relationship between the first metal layer and the second metal layer.
  • the defect points that have short-circuited between them can be repaired, and the overall switching unit can continue to work, thereby reducing yield loss.
  • FIG. 1 is a schematic top-view structure diagram of a first array substrate provided by an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional structure diagram of a first array substrate provided by an embodiment of the present application
  • FIG. 3 is a schematic top-view structure diagram of a second array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a second array substrate provided by an embodiment of the present application.
  • FIG. 5 is a flowchart of a method for preparing an array substrate provided by an embodiment of the present application.
  • 5A to 5G are schematic flowcharts of a method for fabricating an array substrate according to an embodiment of the present application.
  • FIG. 6 is a flowchart of a method for repairing a short circuit of an array substrate according to an embodiment of the present application
  • FIG. 7 is a schematic diagram of a first method for repairing a short circuit of an array substrate according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a second method for repairing a short circuit of an array substrate according to an embodiment of the present application.
  • the present application is directed to an array substrate in the prior art, a method for preparing the same, and a method for repairing a short circuit.
  • the prior art when a short circuit occurs between the upper and lower metal layers, the short circuit cannot be repaired, resulting in a low yield rate, or even causing The entire switch unit is scrapped, and the present application can solve this defect.
  • FIG. 1 is an array substrate provided by the present application, including a base substrate 101 and at least one switch unit 10 disposed on the base substrate 101 , and each of the switch units 10 includes multiple Each of the TFTs 11 connected in parallel with each other, each of the switch units 10 includes a first TFT group 12 and a second TFT group 13 arranged in at least two rows.
  • a first metal layer 102 , a gate insulating layer 103 , a semiconductor layer 104 and a second metal layer 105 are sequentially disposed on the base substrate 101 , and each TFT 11 is composed of at least the first metal layer 102 , the The gate insulating layer 103 , the semiconductor layer 104 and the second metal layer 105 are formed.
  • the first metal layer 102 is provided with a hollow area 1021
  • the semiconductor layer 104 includes a first area 1041 corresponding to the first TFT group 12 and a second area 1042 corresponding to the second TFT group 13
  • the orthographic projection of the region between the first region 1041 and the second region 1042 on the base substrate 101 completely covers the orthographic projection of the hollow region 1021 on the base substrate 101 .
  • the film layer between the first metal layer 102 and the second metal layer 105 has defects, such as conductive particles or holes (due to the The metal material flows into the holes), causing the first metal layer 102 and the second metal layer 105 to be short-circuited. It is explained by taking the presence of conductive particles and foreign objects in the defect as an example. For example, conductive particles and foreign objects also exist in the semiconductor.
  • the first region 1041 and the gate insulating layer 103 of the layer 104 are used, one of the TFTs 11 fails. Since the semiconductor layer 104 is disposed on the entire surface of the first region 1041, one of the TFTs 11 fails. As a result, all the TFTs 11 in the first TFT group 12 cannot work, thereby causing the entire switch unit 10 to be scrapped. In addition, since only one end of the faulty TFT 11 can be disconnected, repair cannot be achieved.
  • the first metal layer 102 does not exist in the hollow region 1021, and both ends of the TFT 11 in failure can be disconnected and located on both sides of the defect point. A part of the second metal layer 105 can be disconnected, so that the short circuit between the first metal layer 102 and the second metal layer 105 can be repaired, and the whole switch unit 10 can continue to work, thereby reducing the yield loss.
  • the first TFT group 12 includes a plurality of first TFTs
  • the second TFT group 13 includes a plurality of second TFTs, a plurality of the first TFTs and a plurality of the second TFTs
  • each of the first TFTs and each of the second TFTs are disposed opposite to each other, and the number of the first TFTs and the number of the second TFTs are equal.
  • the first metal layer 102 at least includes the gate electrode 110 of the TFT 11
  • the second metal layer 105 at least includes a first connecting wire 1051 , a second connecting wire 1052 , the source electrode 111 of the TFT 11 and the The drain 112 of the TFT 11 .
  • the source electrodes 111 of the plurality of first TFTs in the first TFT group 12 are connected through the first connection wiring 1051
  • the drain electrodes of the plurality of second TFTs in the second TFT group 13 112 are connected through the second connection wire 1052, so that the multiple TFTs 11 in the switch unit 10 are connected in parallel.
  • the switch unit 10 When the switch unit 10 is applied to the GOA circuit, the switch unit 10 is located in the GOA area of the display panel, and the two connection ends of the switch unit 10 are respectively connected to the GOA unit and the scan line, and the scan line is connected to the display area of the display panel.
  • the sub-pixel connection is used to control the opening and closing of each sub-pixel, and the control terminal of the switch unit 10 is connected to the driving integrated circuit.
  • the gate 110 of the first TFT and the gate 110 of the second TFT are respectively connected to the driving integrated circuit for obtaining a local display signal and a clock signal, and controlling the GOA unit to turn on the power of each scan line according to the clock signal time, determine the control voltage corresponding to each scan line according to the local display signal, and output the control voltage corresponding to the scan line to the switch unit 10 corresponding to the scan line at the turn-on time of the scan line to control the opening of the scan line or off.
  • the first connection wire 1051 is connected to the corresponding GOA unit, and the second connection wire 1052 is connected to the corresponding scan line. Since this is the prior art, it will not be repeated here.
  • the gate insulating layer 103 is filled in the hollow region 1021 so that the first metal layer 102 is planarized.
  • the hollow area 1021 may completely face the area between the first area 1041 and the second area 1042, or may partially correspond to the area between the first area 1041 and the second area 1042 It is only necessary to ensure that the width of the hollow area 1021 meets the space required for repairing the broken line, which will be described in detail below.
  • the hollow area 1021 is completely facing the area between the first area 1041 and the second area 1042 , specifically, the first area 1041
  • the side of the orthographic projection on the base substrate 101 close to the second area 1042 is coincident with the side of the orthographic projection of the hollow area 1021 on the base substrate 101 close to the first area 1041;
  • the side of the orthographic projection of the second area 1042 on the base substrate 101 is close to the first area 1041 and the orthographic projection of the hollow area 1021 on the base substrate 101 is close to the second area
  • One side of the 1042 coincides.
  • FIG. 3 and FIG. 4 at the same time.
  • the difference between FIG. 3 and FIG. 4 and FIG. 1 and FIG. 2 is that the hollow area 1021 corresponds to the first area 1041 and the first area 1041 .
  • the orthographic projection of the first connection trace 1051 on the base substrate 101 is close to one side of the first region 1041 , and the orthographic projection of the hollow region 1021 on the base substrate 101 There is a first gap d1 between the side close to the first area 1041; the orthographic projection of the first connection trace 1051 on the base substrate 101 is close to the side of the second area 1042, and the A second gap d2 exists between a side of the orthographic projection of the hollow region 1021 on the base substrate 101 close to the second region 1042 .
  • the orthographic projection area of the hollow region 1021 on the base substrate 101 is reduced, so that the influence of the hollow region 1021 on the current can be reduced.
  • the range of the first gap d1 is 4um-6um
  • the range of the second gap d2 is 4um-6um.
  • the present application also provides a method for fabricating an array substrate, the array substrate includes at least one switch unit 10 , each of the switch units 10 includes a plurality of TFTs 11 connected in parallel with each other, and each of the switch units 10 includes a first TFT group 12 and a second TFT group 13 arranged in at least two rows; the method includes the following steps:
  • the base substrate 101 may be a glass substrate, or a substrate of other materials, such as a flexible substrate, a plastic substrate, and the like.
  • the first metal layer 102 covers the base substrate 101 , and the first metal layer 102 can be prepared by deposition, coating or sputtering.
  • the material of layer 102 may include one or more selected from copper, tungsten, chromium, and aluminum.
  • the first metal layer 102 at least includes the gate electrode 110 of the TFT 11 .
  • step S30 includes the following steps:
  • the photoresist layer 106 may be a positive photoresist layer or a negative photoresist layer.
  • a mask 107 By disposing a mask 107 over the photoresist layer 106, the photoresist layer 106 is exposed to light, and then developed to remove part of the photoresist layer 106 to realize the photoresist layer
  • the patterning of the first metal layer 106 facilitates subsequent etching of the first metal layer 102 to realize the patterning of the first metal layer 102 , thereby forming the hollow region 1021 .
  • the mask 107 may be a halftone mask.
  • the gate insulating layer 103 can be prepared by deposition, coating or sputtering, and the gate insulating layer 103 covers the first metal layer 102 and the substrate In the substrate 101 , the gate insulating layer 103 is filled in the hollow region 1021 .
  • the material of the gate insulating layer 103 may include one or more of silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide.
  • S50 forming a semiconductor layer 104 on the gate insulating layer 103, where the semiconductor layer 104 includes a first region 1041 and a second region 1042, and a region between the first region 1041 and the second region 1042 is The orthographic projection on the base substrate 101 completely covers the orthographic projection of the hollow region 1021 on the base substrate 101 .
  • an amorphous silicon layer or an oxide layer can be formed on the gate insulating layer 103 by means of deposition, coating or sputtering.
  • the amorphous silicon layer or the oxide layer is patterned to form the semiconductor layer 104 .
  • a layer of the second metal layer 105 may be formed on the gate insulating layer 103 by means of deposition, coating or sputtering, and the material of the second metal layer 105 may include One or more selected from copper, tungsten, chromium and aluminum, the materials of the first metal layer 102 and the second metal layer 105 may be the same or different. patterning the second metal layer 105 to form the TFT 11 source 111, the TFT The drain 112 of 11, the first connection trace 1051 and the second connection trace 1052.
  • the first metal layer 102 , the gate insulating layer 103 , the semiconductor layer 104 and the second metal layer 105 together constitute at least one switch unit 10 , and each switch unit 10 includes a plurality of mutual For the TFTs 11 connected in parallel, each of the switch units 10 includes a first TFT group 12 and a second TFT group 13 arranged in at least two rows.
  • the first area 1041 is arranged corresponding to the first TFT group 12
  • the second area 1042 is arranged corresponding to the second TFT group 13 .
  • the source electrodes 111 of the plurality of TFTs 11 in the first TFT group 12 are connected through the first connection wiring 1051, and the drain electrodes of the plurality of TFTs 11 in the second TFT group 13 are connected through all the The second connection wires 1052 are connected to each other, so that the multiple TFTs 11 in the switch unit 10 are connected in parallel.
  • an embodiment of the present application further provides a method for repairing a short circuit of an array substrate, including the following steps:
  • S200 Use an array testing machine to test the array substrate, find out a short-circuited defect in the array substrate and a faulty TFT corresponding to the defect, and record the position coordinates of the defect;
  • the position coordinates of the defect points can be recorded in the repair system, so that the laser repair machine can obtain the position coordinates of the corresponding defect points from the repair system.
  • the positions of the defect points in the switch unit 10 are random, but there are no more than two cases, the defect cut points are in the semiconductor layer 104 and the gate insulating layer 103, and /or the defect cut point is in the gate insulating layer 103 .
  • the specific repair process for the defect points in different positions is detailed as follows:
  • the defect is located on the semiconductor layer 104 and the gate insulating layer 103 , causing a corresponding one of the TFTs 11 to fail.
  • the laser repairing machine removes the faulty TFT 11 by laser.
  • the second metal layers 105 on both sides can disconnect the faulty TFT 11 from other normal TFTs 11 so as to achieve repair.
  • the laser position includes a first cutting point Q1 and a second cutting point Q2 located on both sides of the defect point, and the first cutting point Q1 and the second cutting point Q2 are located on the second metal layer 105 , the orthographic projection of the second cutting point Q2 on the base substrate 101 falls within the orthographic projection of the hollow region 1021 on the base substrate 101 .
  • the orthographic projection of the first cutting point Q1 on the base substrate 101 does not coincide with the orthographic projection of the first metal layer 102 on the base substrate 101 .
  • the drain electrode 112 of 11, the second cut-off point Q2 is located at the source electrode 111 of the faulty TFT 11, wherein the orthographic projection of the second cut-off point Q2 on the base substrate 101 falls into the hollow region 1021 where the orthographic projection of the second cut-off point Q2 is located. within the orthographic projection of the base substrate 101 .
  • the defect cut point is on the gate insulating layer 103.
  • the defect point causes a short circuit between the first connection trace 1051 and the first metal layer 102.
  • the laser repairing machine removes the first connection traces 1051 located on both sides of the defect by laser, so as to disconnect some of the first connection traces 1051 from other first connection traces 1051 connected to the source electrode 111 of the TFT 11 Open the connection for patching.
  • the laser position includes a first cutting point Q1 and a second cutting point Q2 , and the first cutting point Q1 and the second cutting point Q2 are both located on the first connection trace 1051 .
  • the first cut point Q1 may be selected to be located on the side of the defect point away from the first metal layer 102, and the second cut point Q2 may be located on the side of the defect point close to the first metal layer 102, wherein the second cut point
  • the orthographic projection of the point Q2 on the base substrate 101 falls within the orthographic projection of the hollow region 1021 on the base substrate 101 .
  • a hollow area is provided through the first metal layer, and the semiconductor layer includes a first area corresponding to the first TFT group and a second TFT group corresponding to the first area.
  • the hollow area is disposed correspondingly to at least part of the area between the first area and the second area.
  • the laser can pass through the hollow area from below the first metal layer to disconnect part of the second metal layer on both sides of the short-circuit defect, so as to reduce the gap between the first metal layer and the second metal layer.
  • the short-circuited defect is repaired, and the overall switch unit can continue to work, thereby reducing yield loss.

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Abstract

本申请提供一种阵列基板及其制备方法、短路修补方法，阵列基板包括至少一个开关单元，每一开关单元包括第一TFT组和第二TFT组；第一金属层上设有镂空区，半导体层包括与第一TFT组对应的第一区以及与第二TFT组对应的第二区，第一区和第二区之间的区域在衬底基板上的正投影完全覆盖镂空区在衬底基板上的正投影。

Description

阵列基板及其制备方法、短路修补方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、短路修补方法。
 背景技术
随着显示技术的发展，薄膜晶体管液晶显示装置（Thin Film Transistor -Liquid Crystal Display，TFT-LCD）因具有高画质、省电、机身薄及应用范围广等优点，而被广泛地应用于各种消费性电子产品。
阵列基板行驱动（Gate Driver on Array，GOA）技术和Mini-LED（微型发光二极管）已经被越来越广泛地应用到液晶显示装置中，为了获取较高的充电率，满足的开关单元的大电流需求，GOA技术和Mini-LED技术中通常采用多个TFT并联结构作为开关单元。以GOA电路为例，GOA单元通过开关单元与阵列基板中的子像素单元连接，以驱动子像素单元发光显示。对于此种类型的开关单元，当同层金属间发生短路时，可进行修补，整体开关单元仍能进行工作。当上下两层金属层之间发生短路时，需要通过激光镭射的方法断开位于短路瑕疵点两侧的部分第二金属层，对第一金属层和第二金属层之间发生短路的瑕疵点进行修补，然而，由于激光需从第一金属层下方照射，容易对第一金属层造成破坏，使得引起短路的瑕疵点无法被修补，从而导致良率较低，甚至导致整体开关单元报废。
综上，亟需提供一种阵列基板及其制备方法、短路修补方法，来解决上述技术问题。
 技术问题
本申请提供一种阵列基板及其制备方法、短路修补方法，以解决现有的阵列基板中，当上下两层金属层之间发生短路时因短路无法修补而导致良率较低，甚至导致整个开关单元报废的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括衬底基板以及设置于所述衬底基板上的至少一个开关单元，每一所述开关单元包括多个相互并联的TFT，每一所述开关单元包括至少呈两行排列的第一TFT组和第二TFT组；
所述衬底基板上依次设置有第一金属层、栅极绝缘层、半导体层和第二金属层，所述第一金属层设有镂空区，所述半导体层包括与所述第一TFT组对应的第一区以及与所述第二TFT组对应的第二区，所述第一区和所述第二区之间的区域在所述衬底基板上的正投影完全覆盖所述镂空区在所述衬底基板上的正投影。
根据本申请提供的阵列基板，所述第一金属层至少包括所述TFT的栅极，所述第二金属层至少包括第一连接走线、第二连接走线、所述TFT的源极和所述TFT的漏极；
所述第一TFT组中的多个所述TFT的源极通过所述第一连接走线相连，所述第二TFT组中的多个所述TFT的漏极通过所述第二连接走线相连。
根据本申请提供的阵列基板，所述第一连接走线在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧之间存在第一间隙；
所述第一连接走线在所述衬底基板上的正投影靠近所述第二区的一侧与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧之间存在第二间隙。
根据本申请提供的阵列基板，所述第一间隙的范围为4um~6um，所述第二间隙的范围为4um~6um。
根据本申请提供的阵列基板，所述第一区在所述衬底基板上的正投影靠近所述第二区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧重合；
所述第二区在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧重合。
根据本申请提供的阵列基板，所述栅极绝缘层填充于所述镂空区。
本申请提供一种阵列基板的制备方法，包括以下步骤：
提供衬底基板；
在所述衬底基板上形成第一金属层；
蚀刻所述第一金属层形成镂空区；
在所述第一金属层上形成栅极绝缘层；
在所述栅极绝缘层上形成半导体层，所述半导体层包括第一区和第二区，所述第一区和所述第二区之间的区域在所述衬底基板上的正投影完全覆盖所述镂空区在所述衬底基板上的正投影；以及
在所述半导体层上形成第二金属层；
其中，所述第一金属层、所述栅极绝缘层、所述半导体层和所述第二金属层共同构成至少一个开关单元，每一所述开关单元包括多个相互并联的TFT，每一所述开关单元包括至少呈两行排列的第一TFT组和第二TFT组。
本申请提供一种阵列基板的制备方法，所述蚀刻所述第一金属层形成镂空区，包括以下步骤：
在所述第一金属层上形成光阻层；
对所述光阻层进行曝光、显影处理；以及
对所述第一金属层进行蚀刻处理，形成所述镂空区。
本申请提供一种阵列基板的制备方法，所述第一金属层至少包括所述TFT的栅极，所述第二金属层至少包括第一连接走线、第二连接走线、所述TFT的源极和所述TFT的漏极；
所述第一TFT组中的多个所述TFT的源极通过所述第一连接走线相连，所述第二TFT组中的多个所述TFT的漏极通过所述第二连接走线相连。
本申请提供一种阵列基板的制备方法，所述第一连接走线在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧之间存在第一间隙；
所述第一连接走线在所述衬底基板上的正投影靠近所述第二区的一侧与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧之间存在第二间隙。
本申请提供一种阵列基板的制备方法，所述第一间隙的范围为4um~6um，所述第二间隙的范围为4um~6um。
本申请提供一种阵列基板的制备方法，所述第一区在所述衬底基板上的正投影靠近所述第二区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧重合；
所述第二区在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧重合。
本申请提供一种阵列基板的制备方法，所述栅极绝缘层填充于所述镂空区。
本申请提供一种阵列基板的短路修补方法，包括以下步骤：
提供一种阵列基板，所述阵列基板包括衬底基板以及设置于所述衬底基板上的至少一个开关单元，每一所述开关单元包括多个相互并联的TFT，每一所述开关单元包括至少呈两行排列的第一TFT组和第二TFT组；所述衬底基板上依次设置有第一金属层、栅极绝缘层、半导体层和第二金属层，所述第一金属层设有镂空区，所述半导体层包括与所述第一TFT组对应的第一区以及与所述第二TFT组对应的第二区，所述第一区和所述第二区之间的区域在所述衬底基板上的正投影完全覆盖所述镂空区在所述衬底基板上的正投影；
采用阵列测试机台对所述阵列基板进行检测，找出所述阵列基板中发生短路的瑕疵点以及所述瑕疵点对应的故障TFT，并记录所述瑕疵点的位置坐标；
镭射修补机台根据所述瑕疵点的位置坐标，找到相应的所述瑕疵点以及所述故障TFT；以及
通过激光镭射位于所述瑕疵点两侧的第一切断点和第二切断点，以使所述故障TFT断开，所述第一切断点和所述第二切断点位于所述第二金属层，所述第二切断点在衬底基板的正投影落入镂空区在所述衬底基板的正投影内。
根据本申请提供的阵列基板的短路修补方法，所述第一切断点在所述衬底基板的正投影与所述第一金属层在所述衬底基板的正投影不重合。
根据本申请提供的阵列基板的短路修补方法，所述第一金属层至少包括所述TFT的栅极，所述第二金属层至少包括第一连接走线、第二连接走线、所述TFT的源极和所述TFT的漏极；
所述第一TFT组中的多个所述TFT的源极通过所述第一连接走线相连，所述第二TFT组中的多个所述TFT的漏极通过所述第二连接走线相连。
根据本申请提供的阵列基板的短路修补方法，所述第一连接走线在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧之间存在第一间隙；
所述第一连接走线在所述衬底基板上的正投影靠近所述第二区的一侧与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧之间存在第二间隙。
根据本申请提供的阵列基板的短路修补方法，所述第一间隙的范围为4um~6um，所述第二间隙的范围为4um~6um。
根据本申请提供的阵列基板的短路修补方法，所述第一区在所述衬底基板上的正投影靠近所述第二区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧重合；
所述第二区在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧重合。
根据本申请提供的阵列基板的短路修补方法，所述栅极绝缘层填充于所述镂空区。
 有益效果
本申请的有益效果为：本申请提供的阵列基板及其制备方法、短路修补方法，通过第一金属层设有镂空区，半导体层包括与第一TFT组对应的第一区以及与第二TFT组对应的第二区，镂空区至少与部分第一区和第二区之间的区域对应设置，当所述第一金属层与所述第二金属层之间发生短路时，由于镂空区处不存在第一金属层，激光可以从第一金属层下方透过所述镂空区断开位于短路瑕疵点两侧的部分所述第二金属层，从而对第一金属层和第二金属层之间发生短路的瑕疵点进行修补，整体开关单元可以继续工作，从而降低良率损失。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的第一种阵列基板的俯视结构示意图；
图2为本申请实施例提供的第一种阵列基板的截面结构示意图；
图3为本申请实施例提供的第二种阵列基板的俯视结构示意图；
图4为本申请实施例提供的第二种阵列基板的截面结构示意图；
图5为本申请实施例提供的一种阵列基板的制备方法的流程图；
图5A~图5G为本申请实施例提供的一种阵列基板的制备方法的流程示意图；
图6为本申请实施例提供的一种阵列基板的短路修补方法的流程图；
图7为本申请实施例提供的第一种阵列基板的短路修补方法的示意图；
图8为本申请实施例提供的第二种阵列基板的短路修补方法的示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有技术的阵列基板及其制备方法、短路修补方法，在现有技术中，当上下两层金属层之间发生短路时，短路处无法修补，从而导致良率较低，甚至导致整个开关单元报废，本申请能够解决该缺陷。
请同时参阅图1和图2，图1为本申请提供的阵列基板，包括衬底基板101以及设置于所述衬底基板101上的至少一个开关单元10，每一所述开关单元10包括多个相互并联的TFT 11，每一所述开关单元10包括至少呈两行排列的第一TFT组12和第二TFT组13。
所述衬底基板101上依次设置有第一金属层102、栅极绝缘层103、半导体层104和第二金属层105，每一所述TFT 11至少由所述第一金属层102、所述栅极绝缘层103、所述半导体层104和所述第二金属层105构成。所述第一金属层102上设置有镂空区1021，所述半导体层104包括与所述第一TFT组12对应的第一区1041以及与所述第二TFT组13对应的第二区1042，所述第一区1041和所述第二区1042之间的区域在所述衬底基板101上的正投影完全覆盖所述镂空区1021在所述衬底基板101上的正投影。
需要说明的是，当所述第一金属层102和所述第二金属层105之间的膜层存在瑕疵点，例如存在导电颗粒异物（particle）或者孔洞(由于所述第二金属层105的金属材料流到孔洞中)，导致所述第一金属层102和所述第二金属层105短路，以瑕疵点存在导电颗粒异物为例进行阐述说明，例如，导电颗粒异物同时存在于所述半导体层104的所述第一区1041和所述栅极绝缘层103时，导致其中一个TFT 11发生故障，由于所述半导体层104在所述第一区1041整面设置，其中一个TFT 11发生故障则会导致第一TFT组12中的所有TFT 11无法工作，从而造成整个开关单元10报废。此外，由于仅能对故障TFT 11的一端断开，导致无法实现修补。
可以理解的是，在本申请实施例中，所述镂空区1021处不存在第一金属层102，发生故障的所述TFT 11的两端均可以断开，位于所述瑕疵点两侧表面上的部分所述第二金属层105可以断开，从而可实现对第一金属层102和第二金属层105之间发生短路的瑕疵点进行修补，整体开关单元10可以继续工作，从而降低良率损失。
在本申请实施例中，所述第一TFT组12包括多个第一TFT，所述第二TFT组13包括多个第二TFT，多个所述第一TFT和多个所述第二TFT并联连接，每一所述第一TFT和每一所述第二TFT相对设置，所述第一TFT的数量和所述第二TFT的数量相等。
所述第一金属层102至少包括所述TFT 11的栅极110，所述第二金属层105至少包括第一连接走线1051、第二连接走线1052、所述TFT 11的源极111和所述TFT 11的漏极112。所述第一TFT组12中的多个所述第一TFT的源极111通过所述第一连接走线1051相连，所述第二TFT组13中的多个所述第二TFT的漏极112通过所述第二连接走线1052相连，从而使得所述开关单元10中的多个TFT 11实现并联连接。
所述开关单元10应用于GOA电路时，所述开关单元10位于显示面板的GOA区，所述开关单元10的两连接端分别与GOA单元和扫描线连接，扫描线与显示面板的显示区的子像素连接，用于控制每个子像素的开启和关闭，所述开关单元10的控制端连接驱动集成电路。具体地，所述第一TFT的栅极110和所述第二TFT的栅极110分别连接驱动集成电路，用于获取局部显示信号和时钟信号，根据时钟信号控制GOA单元开启每条扫描线的时间，根据局部显示信号确定每条扫描线对应的控制电压，并在该扫描线的开启时间向该扫描线对应的所述开关单元10输出该扫描线对应的控制电压，控制该扫描线的开启或关闭。所述第一连接走线1051连接对应的GOA单元，所述第二连接走线1052连接对应的扫描线。由于此为现有技术，故在此不再赘述。
所述栅极绝缘层103填充于所述镂空区1021，使得所述第一金属层102平坦化。
进一步地，所述镂空区1021可以完全正对所述第一区1041和所述第二区1042之间的区域，也可以部分对应所述第一区1041和所述第二区1042之间的区域，只需保证所述镂空区1021的宽度满足断线修补所需空间即可，下面将进行具体阐述说明。
一种实施方式中，请继续参照图1和图2，所述镂空区1021完全正对所述第一区1041和所述第二区1042之间的区域，具体地，所述第一区1041在所述衬底基板101上的正投影靠近所述第二区1042的一侧与所述镂空区1021在所述衬底基板101上的正投影靠近所述第一区1041的一侧重合；所述第二区1042在所述衬底基板101上的正投影靠近所述第一区1041的一侧与所述镂空区1021在所述衬底基板101上的正投影靠近所述第二区1042的一侧重合。采用此种结构，对于与所述第一区1041和所述第二区1042之间的区域对应设置的所述栅极绝缘层103，由于此区域不存在所述第一金属层102，即使在此区域中的任意位置存在瑕疵点，也不会造成所述第一金属层102和所述第二金属层105之间发生短路，降低了发生故障的概率，提高了良率。
另一种实施方式中，请同时参阅图3和图4，图3、图4与图1、图2的不同之处在于，所述镂空区1021部分对应所述第一区1041和所述第二区1042之间的区域。具体地，所述第一连接走线1051在所述衬底基板101上的正投影靠近所述第一区1041的一侧，与所述镂空区1021在所述衬底基板101上的正投影靠近所述第一区1041的一侧之间存在第一间隙d1；所述第一连接走线1051在所述衬底基板101上的正投影靠近所述第二区1042的一侧，与所述镂空区1021在所述衬底基板101上的正投影靠近所述第二区1042的一侧之间存在第二间隙d2。采用此种结构，相比上述实施方式，所述镂空区1021在所述衬底基板101的正投影面积减小，从而能够降低所述镂空区1021对电流的影响。
具体地，所述第一间隙d1的范围为4um~6um，所述第二间隙d2的范围为4um~6um。
请参阅图5，本申请还提供一种阵列基板的制备方法，所述阵列基板包括至少一个开关单元10，每一所述开关单元10包括多个相互并联的TFT 11，每一所述开关单元10包括至少呈两行排列的第一TFT组12和第二TFT组13；所述方法包括以下步骤：
S10：提供衬底基板101。
具体地，请参阅图5A，所述衬底基板101可以为玻璃基板，也可以为其他材料的基板，例如柔性基板、塑料基板等。
S20：在所述衬底基板101上形成第一金属层102。
具体地，请参阅图5B，所述第一金属层102覆盖所述衬底基板101，所述第一金属层102可以通过沉积、涂布或溅射的方式制备而成，所述第一金属层102的材料可以包括选自铜、钨、铬和铝中的一种或多种。在本实施例中，所述第一金属层102至少包括所述TFT 11的栅极110。
S30：蚀刻所述第一金属层102上形成镂空区1021。
具体地，步骤S30包括以下步骤：
S301：在所述第一金属层102上形成光阻层106；
S302：对所述光阻层106进行曝光、显影处理；以及
S303：对所述第一金属层102进行蚀刻处理，形成所述镂空区1021。
具体地，请参阅图5C和图5D，所述光阻层106可以为正性光阻层，也可以为负性光阻层。通过在所述光阻层106上方设置掩膜板（mask）107，对所述光阻层106进行曝光，其后进行显影，从而移除部分所述光阻层106以实现所述光阻层106的图案化，方便后续对所述第一金属层102进行刻蚀处理实现所述第一金属层102的图案化，从而形成所述镂空区1021。所述掩膜板107可以为半色调掩膜板。
S40：在所述第一金属层102上形成栅极绝缘层。
具体地，请参阅图5E，所述栅极绝缘层103可以通过沉积、涂布或溅射的方式制备而成，所述栅极绝缘层103覆盖所述第一金属层102以及所述衬底基板101，所述栅极绝缘层103填充于所述镂空区1021。所述栅极绝缘层103的材料可以包括氧化硅、氮化硅、氮氧化硅或氧化铝的一种或多种。
S50：在所述栅极绝缘层103上形成半导体层104，所述半导体层104包括第一区1041和第二区1042，所述第一区1041和所述第二区1042之间的区域在所述衬底基板101上的正投影完全覆盖所述镂空区1021在所述衬底基板101上的正投影。
具体地，请参阅图5F，首先，可以通过沉积、涂布或溅射的方式在所述栅极绝缘层103上形成一层非晶硅层或氧化物层，接着，通过一道黄光制程对所述非晶硅层或氧化物层进行图案化处理，形成所述半导体层104。
S60：在所述半导体层104上形成第二金属层105。
具体地，请参阅图5G，可以通过沉积、涂布或溅射的方式在所述栅极绝缘层103上形成一层所述第二金属层105，所述第二金属层105的材料可以包括选自铜、钨、铬和铝中的一种或多种，所述第一金属层102和所述第二金属层105的材料可以相同，也可以不同。对所述第二金属层105进行图案化处理以形成所述TFT 11的源极111、所述TFT 11的漏极112、第一连接走线1051和第二连接走线1052。
其中，所述第一金属层102、所述栅极绝缘层103、所述半导体层104和所述第二金属层105共同构成至少一个开关单元10，每一所述开关单元10包括多个相互并联的TFT 11，每一所述开关单元10包括至少呈两行排列的第一TFT组12和第二TFT组13。所述第一区1041与所述第一TFT组12对应设置，所述第二区1042与所述第二TFT组13对应设置。所述第一TFT组12中的多个所述TFT 11的源极111通过所述第一连接走线1051相连，所述第二TFT组13中的多个所述TFT 11的漏极通过所述第二连接走线1052相连，从而使得所述开关单元10中的多个TFT 11实现并联连接。
请参阅图6，本申请实施例还提供一种阵列基板的短路修补方法，包括以下步骤：
S100：提供上述阵列基板；
S200：采用阵列测试机台对所述阵列基板进行检测，找出所述阵列基板中发生短路的瑕疵点以及所述瑕疵点对应的故障TFT，并记录所述瑕疵点的位置坐标；
S300：镭射修补机台根据所述瑕疵点的位置坐标，找到相应的所述瑕疵点以及所述故障TFT；以及
S400：通过激光镭射位于所述瑕疵点两侧的第一切断点Q1和第二切断点Q2，以使所述故障TFT断开，所述第一切断点Q1和所述第二切断点Q2位于所述第二金属层105，所述第二切断点Q2在衬底基板101的正投影落入镂空区1021在所述衬底基板101的正投影内。
具体地，瑕疵点的位置坐标可以记录于修复系统中，便于镭射修补机台从修复系统中获取相应瑕疵点的位置坐标。
需要说明的是，瑕疵点在所述开关单元10中产生的位置是随机的，但不外乎两种情况，所述瑕疵切断点于所述半导体层104和所述栅极绝缘层103，和/或所述瑕疵切断点于所述栅极绝缘层103。对于不同位置的瑕疵点的具体修补过程详述如下：
请参阅图7，所述瑕疵点位于所述半导体层104和所述栅极绝缘层103，导致对应的一个TFT 11发生故障，此种情况下，镭射修补机台通过激光镭射去除位于故障TFT 11两侧的所述第二金属层105，以使故障TFT 11与其它正常TFT 11断开连接，从而实现修补。具体地，激光镭射位置包括位于所述瑕疵点两侧的第一切断点Q1和第二切断点Q2，所述第一切断点Q1和所述第二切断点Q2位于所述第二金属层105，所述第二切断点Q2在衬底基板101的正投影落入镂空区1021在所述衬底基板101的正投影内。
具体地，所述第一切断点Q1在所述衬底基板101的正投影与第一金属层102在所述衬底基板101的正投影不重合。可以选择将所述第一切断点Q1位于故障TFT 11的漏极112，所述第二切断点Q2位于故障TFT 11的源极111，其中，所述第二切断点Q2在所述衬底基板101的正投影落入所述镂空区1021在所述衬底基板101的正投影内。
请参阅图8，所述瑕疵切断点于所述栅极绝缘层103，例如，所述瑕疵点导致第一连接走线1051和所述第一金属层102之间发生短路，此种情况下，镭射修补机台通过激光镭射去除位于瑕疵点两侧的所述第一连接走线1051，以使部分第一连接走线1051与部分其它连接TFT 11的源极111的第一连接走线1051断开连接，从而实现修补。具体地，激光镭射位置包括第一切断点Q1和第二切断点Q2，所述第一切断点Q1和所述第二切断点Q2均位于所述第一连接走线1051上。可以选择将所述第一切断点Q1位于瑕疵点远离第一金属层102的一侧，所述第二切断点Q2位于瑕疵点靠近第一金属层102的一侧，其中，所述第二切断点Q2在所述衬底基板101的正投影落入所述镂空区1021在所述衬底基板101的正投影内。
有益效果为：本申请实施例提供的阵列基板及其制备方法、短路修补方法，通过第一金属层设有镂空区，半导体层包括与第一TFT组对应的第一区以及与第二TFT组对应的第二区，镂空区至少与部分第一区和第二区之间的区域对应设置，当所述第一金属层与所述第二金属层之间发生短路时，由于镂空区处不存在第一金属层，激光可以从第一金属层下方透过所述镂空区断开位于短路瑕疵点两侧的部分所述第二金属层，从而对第一金属层和第二金属层之间发生短路的瑕疵点进行修补，整体开关单元可以继续工作，从而降低良率损失。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括衬底基板以及设置于所述衬底基板上的至少一个开关单元，每一所述开关单元包括多个相互并联的TFT，每一所述开关单元包括至少呈两行排列的第一TFT组和第二TFT组；
    所述衬底基板上依次设置有第一金属层、栅极绝缘层、半导体层和第二金属层，所述第一金属层设有镂空区，所述半导体层包括与所述第一TFT组对应的第一区以及与所述第二TFT组对应的第二区，所述第一区和所述第二区之间的区域在所述衬底基板上的正投影完全覆盖所述镂空区在所述衬底基板上的正投影。
  2. 根据权利要求1所述的阵列基板，其中所述第一金属层至少包括所述TFT的栅极，所述第二金属层至少包括第一连接走线、第二连接走线、所述TFT的源极和所述TFT的漏极；
    所述第一TFT组中的多个所述TFT的源极通过所述第一连接走线相连，所述第二TFT组中的多个所述TFT的漏极通过所述第二连接走线相连。
  3. 根据权利要求2所述的阵列基板，其中所述第一连接走线在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧之间存在第一间隙；
    所述第一连接走线在所述衬底基板上的正投影靠近所述第二区的一侧与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧之间存在第二间隙。
  4. 根据权利要求3所述的阵列基板，其中所述第一间隙的范围为4um~6um，所述第二间隙的范围为4um~6um。
  5. 根据权利要求1所述的阵列基板，其中所述第一区在所述衬底基板上的正投影靠近所述第二区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧重合；
    所述第二区在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧重合。
  6. 根据权利要求1所述的阵列基板，其中所述栅极绝缘层填充于所述镂空区。
  7. 一种阵列基板的制备方法，包括以下步骤：
    提供衬底基板；
    在所述衬底基板上形成第一金属层；
    蚀刻所述第一金属层形成镂空区；
    在所述第一金属层上形成栅极绝缘层；
    在所述栅极绝缘层上形成半导体层，所述半导体层包括第一区和第二区，所述第一区和所述第二区之间的区域在所述衬底基板上的正投影完全覆盖所述镂空区在所述衬底基板上的正投影；以及
    在所述半导体层上形成第二金属层；
    其中，所述第一金属层、所述栅极绝缘层、所述半导体层和所述第二金属层共同构成至少一个开关单元，每一所述开关单元包括多个相互并联的TFT，每一所述开关单元包括至少呈两行排列的第一TFT组和第二TFT组。
  8. 根据权利要求7所述的阵列基板的制备方法，其中所述蚀刻所述第一金属层形成镂空区，包括以下步骤：
    在所述第一金属层上形成光阻层；
    对所述光阻层进行曝光、显影处理；以及
    对所述第一金属层进行蚀刻处理，形成所述镂空区。
  9. 根据权利要求7所述的阵列基板的制备方法，其中所述第一金属层至少包括所述TFT的栅极，所述第二金属层至少包括第一连接走线、第二连接走线、所述TFT的源极和所述TFT的漏极；
    所述第一TFT组中的多个所述TFT的源极通过所述第一连接走线相连，所述第二TFT组中的多个所述TFT的漏极通过所述第二连接走线相连。
  10. 根据权利要求9所述的阵列基板的制备方法，其中所述第一连接走线在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧之间存在第一间隙；
    所述第一连接走线在所述衬底基板上的正投影靠近所述第二区的一侧与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧之间存在第二间隙。
  11. 根据权利要求10所述的阵列基板的制备方法，其中所述第一间隙的范围为4um~6um，所述第二间隙的范围为4um~6um。
  12. 根据权利要求7所述的阵列基板的制备方法，其中所述第一区在所述衬底基板上的正投影靠近所述第二区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧重合；
    所述第二区在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧重合。
  13. 根据权利要求7所述的阵列基板的制备方法，其中所述栅极绝缘层填充于所述镂空区。
  14. 一种阵列基板的短路修补方法，包括以下步骤：
    提供一种阵列基板，所述阵列基板包括衬底基板以及设置于所述衬底基板上的至少一个开关单元，每一所述开关单元包括多个相互并联的TFT，每一所述开关单元包括至少呈两行排列的第一TFT组和第二TFT组；所述衬底基板上依次设置有第一金属层、栅极绝缘层、半导体层和第二金属层，所述第一金属层设有镂空区，所述半导体层包括与所述第一TFT组对应的第一区以及与所述第二TFT组对应的第二区，所述第一区和所述第二区之间的区域在所述衬底基板上的正投影完全覆盖所述镂空区在所述衬底基板上的正投影；
    采用阵列测试机台对所述阵列基板进行检测，找出所述阵列基板中发生短路的瑕疵点以及所述瑕疵点对应的故障TFT，并记录所述瑕疵点的位置坐标；
    镭射修补机台根据所述瑕疵点的位置坐标，找到相应的所述瑕疵点以及所述故障TFT；以及
    通过激光镭射位于所述瑕疵点两侧的第一切断点和第二切断点，以使所述故障TFT断开，所述第一切断点和所述第二切断点位于所述第二金属层，所述第二切断点在衬底基板的正投影落入镂空区在所述衬底基板的正投影内。
  15. 根据权利要求14所述的阵列基板的短路修补方法，其中所述第一切断点在所述衬底基板的正投影与所述第一金属层在所述衬底基板的正投影不重合。
  16. 根据权利要求14所述的阵列基板的短路修补方法，其中所述第一金属层至少包括所述TFT的栅极，所述第二金属层至少包括第一连接走线、第二连接走线、所述TFT的源极和所述TFT的漏极；
    所述第一TFT组中的多个所述TFT的源极通过所述第一连接走线相连，所述第二TFT组中的多个所述TFT的漏极通过所述第二连接走线相连。
  17. 根据权利要求16所述的阵列基板的短路修补方法，其中所述第一连接走线在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧之间存在第一间隙；
    所述第一连接走线在所述衬底基板上的正投影靠近所述第二区的一侧与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧之间存在第二间隙。
  18. 根据权利要求17所述的阵列基板的短路修补方法，其中所述第一间隙的范围为4um~6um，所述第二间隙的范围为4um~6um。
  19. 根据权利要求14所述的阵列基板的短路修补方法，其中所述第一区在所述衬底基板上的正投影靠近所述第二区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第一区的一侧重合；
    所述第二区在所述衬底基板上的正投影靠近所述第一区的一侧，与所述镂空区在所述衬底基板上的正投影靠近所述第二区的一侧重合。
  20. 根据权利要求14所述的阵列基板的短路修补方法，其中所述栅极绝缘层填充于所述镂空区。
PCT/CN2021/095404 2021-02-05 2021-05-24 阵列基板及其制备方法、短路修补方法 WO2022166036A1 (zh)

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