WO2022165782A1 - 像素电路及其驱动方法、阵列基板、显示面板 - Google Patents

像素电路及其驱动方法、阵列基板、显示面板 Download PDF

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Publication number
WO2022165782A1
WO2022165782A1 PCT/CN2021/075706 CN2021075706W WO2022165782A1 WO 2022165782 A1 WO2022165782 A1 WO 2022165782A1 CN 2021075706 W CN2021075706 W CN 2021075706W WO 2022165782 A1 WO2022165782 A1 WO 2022165782A1
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Prior art keywords
circuit
node
signal
light
coupled
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PCT/CN2021/075706
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English (en)
French (fr)
Inventor
程鸿飞
郝学光
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/075706 priority Critical patent/WO2022165782A1/zh
Priority to US18/044,114 priority patent/US20230343287A1/en
Priority to EP21923795.5A priority patent/EP4202898A4/en
Priority to CN202180000171.2A priority patent/CN115244607A/zh
Publication of WO2022165782A1 publication Critical patent/WO2022165782A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and a driving method thereof, an array substrate and a display panel.
  • an OLED display panel includes a plurality of pixel units arranged in an array, the pixel units in the same row are connected to the same grid line, the pixel units in the same column are connected to the same data line, and each pixel unit is provided on the grid line. The display is performed under the driving of the scan signal and the data signal provided by the data line.
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, an array substrate and a display panel.
  • a pixel circuit may include a driving circuit, a data writing circuit, an initialization circuit, a first lighting control circuit, a first storage circuit, a second storage circuit, and a second lighting control circuit.
  • the driving circuit is coupled to the first node, the second node and the third node, and can provide a driving current to the light emitting element.
  • the data writing circuit is coupled to the first node, and can provide the data signal from the data signal terminal to the driving circuit according to the driving signal from the driving signal terminal.
  • the initialization circuit may provide the initialization signal from the initialization signal terminal to the second node according to the reset signal from the reset signal terminal.
  • the first lighting control circuit may provide the first voltage signal from the first voltage signal terminal to the third node according to the first lighting control signal from the first lighting control signal terminal.
  • the first storage circuit may store the voltage difference between the first voltage signal terminal and the second node.
  • the second storage circuit may store the voltage difference between the first node and the second node.
  • the second light-emitting control circuit can control to provide the driving current to the light-emitting element according to the second light-emitting control signal from the second light-emitting control signal terminal.
  • the first storage circuit may include a first capacitor.
  • the first capacitor may be coupled between the first voltage signal terminal and the second node.
  • the second storage circuit may include a second capacitor.
  • the second capacitor may be coupled between the first node and the second node.
  • the data writing circuit may include a first transistor.
  • the control electrode of the first transistor is coupled to the driving signal end, the first electrode is coupled to the data signal end, and the second electrode is coupled to the first node.
  • the initialization circuit may include a second transistor.
  • the control electrode of the second transistor is coupled to the reset signal end, the first electrode is coupled to the initialization signal end, and the second electrode is coupled to the second node.
  • the first light emission control circuit may include a third transistor.
  • the control electrode of the third transistor is coupled to the first light-emitting control signal terminal, the first electrode is coupled to the first voltage signal terminal, and the second electrode is coupled to the third node.
  • the second light emission control circuit may include a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the second light-emitting control signal terminal, the first electrode is coupled to the second node, and the second electrode is coupled to the light-emitting element.
  • the driving circuit may include a driving transistor.
  • the control electrode of the driving transistor is coupled to the first node, the first electrode is coupled to the second node, and the second electrode is coupled to the third node.
  • the data writing circuit may further provide the reference signal from the data signal terminal to the driving circuit according to the driving signal.
  • the pixel circuit may further include a third storage circuit, a first reference circuit, and a second reference circuit.
  • One end of the third storage circuit is coupled to the first node, the other end is coupled to the data writing circuit via the fourth node, and can store the voltage difference between the fourth node and the first node.
  • the first reference circuit may provide the first reference signal from the first reference signal terminal to the first node according to the reset signal.
  • the second reference circuit may provide the second reference signal from the second reference signal terminal to the fourth node according to the reset signal.
  • the third storage circuit may include a third capacitor.
  • the third capacitor is coupled between the fourth node and the first node.
  • the first reference circuit may include a fifth transistor.
  • the control electrode of the fifth transistor is coupled to the reset signal end, the first electrode is coupled to the first reference signal end, and the second electrode is coupled to the first node.
  • the second reference circuit may include a sixth transistor. The control electrode of the sixth transistor is coupled to the reset signal end, the first electrode is coupled to the second reference signal end, and the second electrode is coupled to the fourth node.
  • the first reference signal and the second reference signal may be the same signal.
  • a drive signal and a reset signal can be provided to turn on the data writing circuit and the initialization circuit, the reference signal from the data signal terminal is provided to the first node through the data writing circuit, and the initialization signal is provided to the second node through the initialization circuit .
  • a driving signal and a first light-emitting control signal can be provided to turn on the data writing circuit and the first light-emitting control circuit, the reference signal is kept provided to the first node through the data writing circuit, and the first light-emitting control circuit is The voltage signal is provided to the third node to charge the first storage circuit and the second storage circuit to compensate the driving circuit.
  • a driving signal can be provided to turn on the data writing circuit, so as to provide the data signal from the data signal terminal to the first node.
  • the first light-emitting control signal and the second light-emitting control signal can be provided to turn on the first light-emitting control circuit and the second light-emitting control circuit, and the driving current of the driving circuit is provided to the light-emitting element to make the light-emitting element emit light.
  • a reset signal may be provided to turn on the initialization circuit, the first reference circuit and the second reference circuit, the initialization signal is provided to the second node through the initialization circuit, and the first reference signal is provided to the first node through the first reference circuit , the second reference signal is provided to the fourth node through the second reference circuit.
  • the first lighting control signal can be provided to turn on the first lighting control circuit, the first voltage signal is provided to the third node through the first lighting control circuit, and the first storage circuit, the second storage circuit and the third storage circuit are provided with the first voltage signal to the third node. circuit charging to compensate the drive circuit.
  • a driving signal can be provided to turn on the data writing circuit, so as to provide the data signal from the data signal terminal to the fourth node.
  • the first light-emitting control signal and the second light-emitting control signal can be provided to turn on the first light-emitting control circuit and the second light-emitting control circuit, and the driving current of the driving circuit can be supplied to the light-emitting element to make the light-emitting element emit light.
  • an array substrate is provided.
  • the array substrate may include a plurality of pixel circuits of the first aspect of the present disclosure.
  • a display panel includes the array substrate of the fourth aspect of the present disclosure.
  • FIG. 1 shows a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 shows an exemplary circuit diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic block diagram of a pixel circuit according to another embodiment of the present disclosure
  • FIG. 4 shows an exemplary circuit diagram of a pixel circuit according to another embodiment of the present disclosure
  • FIG. 5 shows a timing diagram of signals in a pixel circuit according to an embodiment of the present disclosure
  • 6A is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in an initialization stage
  • 6B is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a compensation stage
  • 6C is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a data writing stage
  • FIG. 6D is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a light-emitting stage
  • FIG. 7 shows a timing diagram of signals in a pixel circuit according to another embodiment of the present disclosure.
  • 8A is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in an initialization stage
  • 8B is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a compensation stage
  • 8C is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a data writing stage
  • FIG. 8D is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a light-emitting stage
  • FIG. 9 shows a flowchart of a method for driving a pixel circuit according to an embodiment of the present disclosure
  • FIG. 10 shows a flowchart of a method for driving a pixel circuit according to another embodiment of the present disclosure
  • FIG. 11 shows a schematic diagram of an array substrate according to an embodiment of the present disclosure.
  • Words like "connected” or “coupled” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “Down”, “Left”, “Right”, etc. are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change relatively.
  • An OLED display device usually includes a plurality of pixel units arranged in an array, and each pixel unit can realize the basic function of driving the OLED to emit light through a pixel circuit.
  • each pixel unit can realize the basic function of driving the OLED to emit light through a pixel circuit.
  • the gate voltage of the driving transistor that directly drives the OLED to emit light the magnitude of the current between the source and the drain of the driving transistor can be controlled to realize the change of the luminous brightness.
  • the threshold voltages of different driving transistors are different due to process variation. And with the prolongation of the working time and the change of the use environment, the threshold voltage of the driving transistor will drift.
  • the different positions of the pixel units may also lead to different voltage drops (I-R Drop) of the power supply, thereby affecting the current driving the OLED.
  • I-R Drop voltage drops
  • the capacitance of each OLED in the OLED display device may also be different, the driving current will be affected.
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, an array substrate and a display panel.
  • the pixel circuit can compensate the deviation and drift of the threshold voltage of the driving transistor, compensate the brightness difference between the far end and the near end of the power supply caused by IR Drop, avoid the influence of the capacitance of the OLED itself, and prevent the OLED from emitting light by mistake, thereby improving the use of The display effect of the display panel of the pixel circuit.
  • FIG. 1 shows a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 100 may include a driving circuit 110 , a data writing circuit 120 , an initialization circuit 130 , a first lighting control circuit 140 , a first storage circuit 150 , a second storage circuit 160 and a second lighting control circuit 170 .
  • the pixel circuit 100 may be used to drive the light-emitting element 200 in the corresponding pixel unit to emit light.
  • the control terminal of the driving circuit 110 is coupled to the first node N1 , the first terminal is coupled to the second node N2 , and the second terminal is coupled to the third node N3 .
  • the driving circuit 110 may provide the driving current I DS to the light emitting element 200 .
  • the driving circuit 110 may provide the driving current I for driving the light emitting element 200 to emit light according to the voltage difference between its control terminal and the first terminal (ie, the voltage difference between the first node N1 and the second node N2 ) DS .
  • the data writing circuit 120 may receive the driving signal via the driving signal terminal GA, and receive the data signal or the reference signal via the data signal terminal DA.
  • the data writing circuit 120 can also be coupled to the first node N1 and further coupled to the control terminal of the driving circuit 110 .
  • the data writing circuit 120 may provide the data signal or the reference signal from the data signal terminal DA to the first node N1 , ie, the control terminal of the driving circuit 110 , according to the driving signal from the driving signal terminal GA.
  • the driving signal terminal GA may be connected to a gate line corresponding to the pixel unit, so the driving signal may be a scan signal for the pixel unit.
  • the data signal terminal DA can be connected to a data line corresponding to the pixel unit, and the data line can correspondingly provide data signals or reference signals in different time periods.
  • the data writing circuit 120 may be directly connected with the first node N1 to directly provide the required signal to the N1 node, as shown in FIG. 1 .
  • the data writing circuit 120 may also be indirectly coupled with the first node N1 to indirectly provide the desired signal to the N1 node, as will be described in detail below in conjunction with FIG. 3 .
  • the initialization circuit 130 may receive the reset signal through the reset signal terminal RST, and receive the initialization signal through the initialization signal terminal VINI.
  • the initialization circuit 130 can also be coupled to the second node N2 and further coupled to the first end of the driving circuit 110 .
  • the initialization circuit 130 may provide the initialization signal from the initialization signal terminal VINI to the second node N2 , that is, the first terminal of the driving circuit 110 , according to the reset signal from the reset signal terminal RST.
  • the first lighting control circuit 140 can receive the first lighting control signal through the first lighting control signal terminal EM1 and receive the first voltage signal through the first voltage signal terminal VDD.
  • the first light emission control circuit 140 can also be coupled to the third node N3 and further coupled to the second end of the driving circuit 110 .
  • the first lighting control circuit 140 can provide the first voltage signal from the first voltage signal terminal VDD to the third node N3 according to the first lighting control signal from the first lighting control signal terminal EM1, that is, drive the the second end of the circuit 110 .
  • the first storage circuit 150 may be coupled to the first voltage signal terminal VDD and the second node N2 to store the voltage difference between the first voltage signal terminal VDD and the second node N2.
  • the second storage circuit 160 may be coupled to the first node N1 and the second node N2 to store the voltage difference between the first node N1 and the second node N2.
  • the second lighting control circuit 170 can receive the second lighting control signal via the second lighting control signal terminal EM2.
  • the second light emitting control circuit 170 can also be coupled to the second node N2 and further coupled to the first end of the driving circuit 110 .
  • the second light emitting control circuit 170 may also be coupled to the light emitting element 200 .
  • the second light-emitting control circuit 170 may control the driving current I DS to be supplied to the light-emitting element 200 according to the second light-emitting control signal from the second light-emitting control signal terminal EM2 .
  • the second light-emitting control circuit 170 can control the on-off between the driving circuit 110 and the light-emitting element 200 according to the second light-emitting control signal, thereby preventing the light-emitting element 200 from emitting light by mistake, and effectively isolating the light-emitting element 200 itself.
  • one end of the light emitting element 200 can be coupled to the second light emitting control circuit 170, and the other end can be coupled to the second voltage signal terminal VSS to receive the second voltage signal.
  • the light emitting element 200 can emit light according to the driving current I DS provided by the driving circuit 110 under the control of the first lighting control circuit 140 and the second lighting control circuit 170 .
  • the driving current I DS in the driving circuit 110 is only related to the data signal and the reference signal of the data signal terminal DA, and the specific analysis is as follows. Since the driving current I DS is independent of the characteristics of the elements in the driving circuit 110 and the power supply voltage (eg, the first voltage signal, the second voltage signal), the display uniformity can be improved. In addition, the second lighting control circuit 170 can separate the driving circuit 110 from the light-emitting element 200 in the non-light-emitting stage, thereby preventing the light-emitting element 200 from emitting false light and avoiding the influence of the capacitance of the light-emitting element 200 on the driving current I DS .
  • the first voltage signal terminal VDD maintains an input DC high level signal
  • the DC high level is referred to as the first voltage
  • the second voltage signal terminal VSS maintains an input DC low level signal
  • the DC low level is called a second voltage, which is lower than the first voltage.
  • the initialization signal terminal VINI for example, keeps a DC low level signal input. The following embodiments are the same and will not be repeated.
  • the first node N1 , the second node N2 , the third node N3 and the fourth node N4 mentioned later do not represent actual components, but represent related circuit connections in the circuit diagram. meeting point. The following embodiments are the same and will not be repeated.
  • FIG. 2 shows an exemplary circuit diagram of a pixel circuit, such as the pixel circuit 100 of FIG. 1 , according to an embodiment of the present disclosure.
  • the pixel circuit includes: a driving transistor DT, first to fourth transistors (eg, as switching transistors) T1, T2, T3, T4, a first capacitor C1 and a second capacitor C2.
  • the transistors employed may be N-type transistors or P-type transistors.
  • the transistors may be N-type or P-type field effect transistors (MOSFETs), or N-type or P-type bipolar transistors (BJTs).
  • MOSFETs N-type or P-type field effect transistors
  • BJTs N-type or P-type bipolar transistors
  • the gate of the transistor is referred to as the gate. Since the source and drain of the transistor are symmetrical, no distinction is made between the source and the drain, that is, the source of the transistor may be the first electrode (or the second electrode), and the drain may be the second electrode (or the second electrode). one pole).
  • an N-type field effect transistor (NMOS) is taken as an example for detailed description.
  • NMOS N-type field effect transistor
  • an N-type transistor is turned on in response to a control very high signal.
  • the driving circuit 110 may include a driving transistor DT.
  • the control electrode of the driving transistor DT serves as the control terminal of the driving circuit 110 and is coupled to the first node N1.
  • the first pole of the driving transistor DT serves as the first terminal of the driving circuit 110 and is coupled to the second node N2.
  • the second pole of the driving transistor DT serves as the second terminal of the driving circuit 110 and is coupled to the third node N3.
  • the driving transistor DT is an N-type transistor.
  • the data writing circuit 120 may include a first transistor T1.
  • the control electrode of the first transistor T1 is coupled to the driving signal terminal GA to receive the driving signal, the first electrode is coupled to the data signal terminal DA to receive the data signal or the reference signal, and the second electrode is coupled to the first node N1 (the driving transistor DT). control pole) is coupled.
  • the first transistor T1 is an N-type transistor.
  • the initialization circuit 130 may include a second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the reset signal terminal RST to receive the reset signal, the first electrode is coupled to the initialization signal terminal VINI to receive the initialization signal, and the second electrode is coupled to the second node N2 (the first electrode of the driving transistor DT). pole) coupled.
  • the second transistor T2 is an N-type transistor.
  • the first lighting control circuit 140 may include a third transistor T3.
  • the control electrode of the third transistor T3 is coupled to the first lighting control signal terminal EM1 to receive the first lighting control signal, the first electrode is coupled to the first voltage signal terminal VDD to receive the first voltage signal, and the second electrode and the first voltage signal terminal VDD are coupled to receive the first voltage signal.
  • the three nodes N3 (the second pole of the driving transistor DT) are coupled.
  • the third transistor T3 is an N-type transistor.
  • the first storage circuit 150 may include a first capacitor C1.
  • the first terminal of the first capacitor C1 is coupled to the first voltage signal terminal VDD, and the second terminal is coupled to the second node N2.
  • the second storage circuit 160 may include a second capacitor C2.
  • the first end of the second capacitor C2 is coupled to the first node N1, and the second end is coupled to the second node N2.
  • the second light emission control circuit 170 may include a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is coupled to the second light-emitting control signal terminal EM2 to receive the light-emitting control signal, the first electrode is coupled to the second node N2, and the second electrode is coupled to the light-emitting element 200 .
  • the fourth transistor T4 is an N-type transistor.
  • one or more of the driving circuit 110 , the data writing circuit 120 , the initialization circuit 130 , the first lighting control circuit 140 , the first storage circuit 150 , the second storage circuit 160 and the second lighting control circuit 170 are also It may be a circuit composed of other elements, not limited to the above.
  • the light-emitting element 200 is, for example, various types of OLEDs, such as top emission, bottom emission, double-side emission, etc., which can emit red, green, blue, or white light, which is not limited by the embodiments of the present disclosure.
  • the positive electrode of the OLED is coupled to the second electrode of the fourth transistor T4
  • the negative electrode is coupled to the second voltage signal terminal VSS to receive the second voltage signal.
  • FIG. 2 also schematically shows the capacitance Coled of the OLED itself, which is connected in parallel with both ends of the OLED.
  • the data signal terminal provides the data signal and the reference signal at different time periods.
  • the reference signal may be separately provided in other manners without transmitting the reference signal through the data signal terminal. Therefore, the data signal terminal can only transmit the data signal, thereby simplifying the design of the driving circuit. For specific details, please refer to the description of the following embodiments.
  • FIG. 3 shows a schematic block diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit 300 may include a driving circuit 110 , a data writing circuit 120 , an initialization circuit 130 , a first lighting control circuit 140 , a first storage circuit 150 , a second storage circuit 160 , and a second lighting control circuit 170 , a third storage circuit 310 , a first reference circuit 320 and a second reference circuit 330 . Except for the third storage circuit 310 , the first reference circuit 320 and the second reference circuit 330 , the structures and functions of the elements of the pixel circuit in FIG. 3 are similar to those of the pixel circuit in FIG. 1 , and thus will not be repeated.
  • the light-emitting element 200 in FIG. 3 also has the same structure and function as the light-emitting element 200 in FIG. 1 .
  • a third storage circuit 310 is additionally provided between the driving circuit 110 and the data writing circuit 120 .
  • one end of the third storage circuit 310 is coupled to the control end of the driving circuit 110 via the first node N1, and the other end is coupled to the data writing circuit 120 via the fourth node N4.
  • the data writing circuit 120 may provide the data signal from the data signal terminal DA to the fourth node N4 according to the driving signal from the driving signal terminal GA.
  • the third storage circuit 310 may store the voltage difference between the fourth node N4 and the first node N1.
  • the first reference circuit 320 may receive the reset signal via the reset signal terminal RST, and receive the first reference signal via the first reference signal terminal REF1.
  • the first reference circuit 320 may also be coupled to the first node N1.
  • the first reference circuit 320 may provide the first reference signal from the first reference signal terminal REF1 to the first node N1 according to the reset signal from the reset signal terminal RST to control the voltage of the first node N1.
  • the second reference circuit 330 may receive the reset signal via the reset signal terminal RST, and receive the second reference signal via the second reference signal terminal REF2.
  • the second reference circuit 330 may also be coupled to the fourth node N4.
  • the second reference circuit 330 may provide the second reference signal from the second reference signal terminal REF2 to the fourth node N4 according to the reset signal from the reset signal terminal RST to control the voltage of the fourth node N4.
  • the first reference signal and the second reference signal may be the same signal, eg, the same low level signal. In other embodiments, the first reference signal and the second reference signal may also be different signals.
  • FIG. 4 shows an exemplary circuit diagram of a pixel circuit, such as the pixel circuit of FIG. 3 , according to an embodiment of the present disclosure.
  • the pixel circuit includes: a driving transistor DT, first to sixth transistors (for example, as switching transistors) T1, T2, T3, T4, T5, T6, first to third capacitors C1, C2, C3. Except for the third capacitor C3 , the fifth transistor T5 and the sixth transistor T6 , the structures and functions of the elements of the pixel circuit in FIG. 4 are similar to those of the pixel circuit in FIG. 2 , and thus will not be repeated.
  • the light-emitting element in FIG. 4 also has the same structure and function as the light-emitting element in FIG. 2 .
  • the transistors employed may be N-type transistors or P-type transistors.
  • the transistors may be N-type or P-type field effect transistors (MOSFETs), or N-type or P-type bipolar transistors (BJTs).
  • MOSFETs N-type or P-type field effect transistors
  • BJTs N-type or P-type bipolar transistors
  • the gate of the transistor is referred to as the gate. Since the source and drain of the transistor are symmetrical, no distinction is made between the source and the drain, that is, the source of the transistor may be the first electrode (or the second electrode), and the drain may be the second electrode (or the second electrode). one pole).
  • an N-type field effect transistor (NMOS) is taken as an example for detailed description.
  • NMOS N-type field effect transistor
  • an N-type transistor is turned on in response to a control very high signal.
  • the third storage circuit 310 may include a third capacitor C3.
  • the first end of the third capacitor C3 is coupled to the fourth node N4, and the second end is coupled to the first node N1.
  • the first reference circuit 320 may include a fifth transistor T5.
  • the control electrode of the fifth transistor T5 is coupled to the reset signal terminal RST to receive the reset signal, the first electrode is coupled to the first reference signal terminal REF1 to receive the first reference signal REF1, and the second electrode is coupled to the first node N1 .
  • the fifth transistor T5 is an N-type transistor.
  • the second reference circuit 330 may include a sixth transistor T6.
  • the control electrode of the sixth transistor T6 is coupled to the reset signal terminal RST to receive the reset signal, the first electrode is coupled to the second reference signal terminal REF2 to receive the second reference signal REF2, and the second electrode is coupled to the fourth node N4 .
  • the sixth transistor T6 is an N-type transistor.
  • one or more of the third storage circuit 310 , the first reference circuit 320 and the second reference circuit 330 may also be circuits composed of other elements, which are not limited to those described above.
  • FIG. 5 shows a timing diagram of signals used to drive pixel circuits of embodiments of the present disclosure.
  • the pixel circuit is, for example, the pixel circuit shown in FIG. 2 .
  • the working process of the pixel circuit includes four stages, which are an initial stage P1 , a compensation stage P2 , a data writing stage P3 and a light-emitting stage P4 .
  • FIG. 6A is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in an initialization stage.
  • FIG. 6B is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a compensation stage.
  • FIG. 6C is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a data writing stage.
  • FIG. 6D is an equivalent circuit diagram of the pixel circuit shown in FIG. 2 in a light-emitting stage.
  • the symbols VDD, VSS and VINI are used to represent both the corresponding voltage signal terminals and the corresponding voltages.
  • the first voltage signal terminal VDD provides a high-level signal
  • the second voltage signal terminal VSS provides a low-level signal
  • the initialization signal terminal VINI provides a low-level signal.
  • the symbols RST, GA, EM1 and EM2 are used to represent both the corresponding signal terminals and the corresponding signals;
  • the symbol Vref not only represents the reference signal at the data signal terminal DA, but also the corresponding voltage;
  • the symbol Vdata It not only represents the data signal at the data signal terminal DA, but also represents the corresponding voltage.
  • the transistors marked with "x" in FIGS. 6A, 6B, 6C and 6D all indicate that the transistors are in an off state in the corresponding stage.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the driving transistor DT are all made of N-type transistors as an example.
  • the working process of the pixel circuit in 2 is described.
  • the high-level driving signal GA and the reset signal RST, and the low-level first and second lighting control signals EM1 and EM2 are provided.
  • the data signal terminal DA provides a reference signal Vref, such as a low level signal.
  • the first transistor T1 is turned on under the control of the high-level driving signal GA to provide the reference signal Vref of the data signal terminal DA to the first node N1, so that the first node
  • the voltage V N1 of N1 ie, the gate of the drive transistor
  • the second transistor T2 is turned on under the control of the high-level reset signal RST to supply the low-level initialization signal VINI to the second node N2, so that the second node N2 (ie, the first pole of the driving transistor) is Voltage V N2 is initialized to VINI.
  • the third transistor T3 is turned off under the control of the first light emission control signal EM1 of a low level to separate the first voltage signal terminal VDD and the driving transistor DT.
  • the fourth transistor T4 is turned off under the control of the second light emission control signal EM2 of a low level to separate the driving transistor DT from the OLED, so that the driving current I DS in the driving transistor DT is not transmitted to the OLED, thereby avoiding The OLED emits light by mistake.
  • a high-level driving signal GA and a first lighting control signal EM1, and a low-level reset signal RST and a second lighting control signal EM2 are provided.
  • the data signal terminal DA keeps providing the reference signal Vref, eg, a low level signal.
  • the first transistor T1 is turned on under the control of the high-level driving signal GA to keep the reference signal Vref of the data signal terminal DA supplied to the first node N1. Therefore, the voltage V N1 of the first node N1 remains at Vref.
  • the third transistor T3 is turned on under the control of the high-level first light emission control signal EM1 to provide the first voltage signal VDD to the third node N3.
  • the driving transistor DT is turned on.
  • the driving current I DS in the driving transistor DT charges the second node N2 to raise the voltage V N2 of the second node N2 up to Vref-Vth.
  • Vth is the threshold voltage of the driving transistor DT.
  • the first capacitor C1 stores the voltage difference between the first voltage signal terminal VDD and the second node N2
  • the second capacitor C2 stores the voltage difference between the first node N1 and the second node N2.
  • the fourth transistor T4 is turned off under the control of the low-level second light-emitting control signal EM2 to disconnect the path between the driving transistor DT and the OLED, so that the driving current I DS will not be transmitted to the OLED, thereby avoiding The OLED emits light by mistake.
  • the second transistor T2 is turned off under the control of the reset signal RST of a low level.
  • a high-level driving signal GA As shown in FIG. 5 , in the data writing phase P3, a high-level driving signal GA, a low-level reset signal RST, a first lighting control signal EM1 and a second lighting control signal EM2 are provided.
  • the data signal terminal DA provides the data signal Vdata.
  • the first transistor T1 is kept on under the control of the high-level driving signal, so as to provide the data signal Vdata at the data signal terminal to the first node N1, so that the first node N1
  • the voltage V N1 of N1 is Vdata.
  • the second transistor T2 is turned off under the control of the low-level reset signal RST
  • the third transistor T3 is turned off under the control of the low-level first lighting control signal EM1
  • the fourth transistor T4 is turned off under the control of the low-level first lighting control signal EM1 It is turned off under the control of the light-emitting control signal EM2.
  • the first capacitor C1 stores the voltage difference between the first voltage signal terminal VDD and the second node N2
  • the second capacitor C2 stores the voltage difference between the first node N1 and the second node N2. Therefore, as the voltage V N1 of the first node N1 changes, the voltage V N2 of the second node N2 also changes accordingly.
  • the voltage V N2 of the second node N2 can be calculated as: Vref-Vth+(C2/(C2+C1))*(Vdata-Vref).
  • the fourth transistor T4 disconnects the path between the driving transistor DT and the OLED, the driving current I DS will not be transmitted to the OLED, thereby preventing the OLED from emitting light by mistake. At the same time, the influence of the capacitance of the OLED itself on the driving current I DS is also avoided.
  • the first light-emitting control signal and the second light-emitting control signal of high level, and the driving signal GA and the reset signal RST of low level are provided.
  • the third transistor T3 is turned on under the control of the high-level first light-emitting control signal EM1 to connect the first voltage signal terminal VDD with the driving transistor DT.
  • the fourth transistor T4 is turned on under the control of the high-level second light-emitting control signal EM2 to connect the driving transistor DT with the OLED.
  • the first transistor T1 is turned off under the control of the low-level driving signal GA
  • the second transistor T2 is turned off under the control of the low-level reset signal RST.
  • the first capacitor C1 maintains the voltage difference between the first voltage signal terminal VDD and the second node N2
  • the second capacitor C2 maintains the voltage difference between the first node N1 and the second node N2. Therefore, the voltages of the first node N1 and the second node N2 are the same as in the previous stage.
  • the driving current I DS of the driving transistor DT is supplied to the OLED to emit light.
  • the drive current I DS can be calculated according to the following equation:
  • ⁇ , C ox , W, L are constant values related to the driving transistor DT itself, where ⁇ is the electron mobility of the driving transistor DT, Co ox is the gate unit capacitance of the driving transistor DT, W is the channel width of the driving transistor DT, and L is the channel length of the driving transistor DT.
  • Vgs represents the gate (here, the control electrode) and source (here, the first electrode) of the drive transistor DT.
  • Vth represents the threshold voltage of the drive transistor DT.
  • the driving current flowing through the light emitting element OLED is no longer related to the threshold voltage of the driving transistor DT, the power supply voltage (eg, the first voltage VDD, the second voltage VSS) or the capacitance Coled of the light emitting element itself. Therefore, the compensation of the pixel circuit can be realized, and the problems of threshold voltage drift of the driving transistor DT due to the process and long-term operation, and the different positions of the pixel units caused by the different power supply voltages provided to the pixel circuits are solved.
  • the problem, as well as the problem that the capacitance Coled of the light-emitting element itself is different, can eliminate its influence on the driving current, so that the display effect of the display device using the same can be improved.
  • the pixel circuit is, for example, the pixel circuit shown in FIG. 4 .
  • the working process of the pixel circuit includes four stages, namely, an initial stage P1, a compensation stage P2, a data writing stage P3, and a light-emitting stage P4.
  • FIG. 8A is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in an initialization stage.
  • FIG. 8B is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a compensation stage.
  • FIG. 8C is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a data writing stage.
  • FIG. 8D is an equivalent circuit diagram of the pixel circuit shown in FIG. 4 in a light-emitting stage.
  • the symbols VDD, VSS and VINI are used to represent both the corresponding voltage signal terminals and the corresponding voltages.
  • the first voltage signal terminal VDD provides a high-level signal
  • the second voltage signal terminal VSS provides a low-level signal
  • the initialization signal terminal VINI provides a low-level signal.
  • the symbols RST, GA, EM1 and EM2 are used to represent both the corresponding signal terminals and the corresponding signals; the symbol Vdata is used to represent both the data signal at the data signal terminal DA and the corresponding voltage.
  • the symbol Vref1 represents both the first reference signal at the first reference signal terminal REF1 and the corresponding voltage
  • the symbol Vref2 both represents the second reference signal at the second reference signal terminal REF2 , also used to represent the corresponding voltage.
  • transistors marked with "x" in FIGS. 8A, 8B, 8C and 8D all indicate that the transistors are in an off state in the corresponding stage.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor DT all use N-type transistors as an example, in conjunction with FIG. 7 and FIG. 8A, FIG. 8B , FIG. 8C and FIG. 8D illustrate the operation process of the pixel circuit in FIG. 4 .
  • a reset signal RST of a high level, a driving signal GA of a low level, a first lighting control signal EM1 and a second lighting control signal EM2 are provided.
  • FIG. 7 exemplarily shows the signal at the data signal terminal DA, it should be understood that the data signal terminal may provide a data signal or any signal, which is not limited, and will be described in detail below.
  • the second transistor T2 in the initialization phase P1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 are all turned on under the control of the reset signal RST of a high level, so as to provide the initialization signal Vini of a low level To the second node N2, the first reference signal Vref1 is supplied to the first node N1, and the second reference signal Vref2 is supplied to the fourth node N4.
  • the voltage V N1 of the first node N1 (ie, the control electrode of the driving transistor) is initialized to Vref1
  • the voltage V N2 of the second node N2 (ie, the first electrode of the driving transistor) is initialized to VINI
  • the first The voltage V N4 of the four-node N4 is initialized to Vref2.
  • the first transistor T1 is turned off under the control of the low-level driving signal GA, thereby separating the data signal terminal DA from the fourth node N4. Since the signal on the data signal terminal DA will not be transmitted to the fourth node N4, there is no need to limit the signal on the data signal terminal DA. That is to say, the data signal terminal DA does not need to transmit a reference signal, which may be a data signal or an arbitrary signal.
  • the third transistor T3 is turned off under the control of the low-level first light emission control signal EM1 to separate the first voltage signal terminal VDD and the driving transistor DT.
  • the fourth transistor T4 is turned off under the control of the second light emission control signal EM2 of a low level to separate the driving transistor DT from the OLED, so that the driving current I DS in the driving transistor DT is not transmitted to the OLED, thereby avoiding The OLED emits light by mistake.
  • the data signal terminal DA can provide a data signal or an arbitrary signal, which is not limited.
  • the first transistor T1 is turned off under the control of the low-level driving signal GA, so the signal on the data signal terminal DA will not be transmitted to the fourth node N4, so the data signal terminal
  • the signal on the DA can be a data signal or an arbitrary signal.
  • the fifth transistor T5 and the sixth transistor T6 are turned off under the control of the reset signal RST of a low level. Since the third capacitor stores the voltage difference between the fourth node N4 and the first node N1, the first node N1 and the fourth node N4 maintain the voltage of the previous stage, that is, the voltage V N1 of the first node N1 is Vref1, The voltage V N4 of the fourth node N4 is Vref2.
  • the third transistor T3 is turned on under the control of the high-level first light emission control signal EM1 to provide the first voltage signal VDD to the third node N3.
  • the first capacitor C1 stores the voltage difference between the first voltage signal terminal VDD and the second node N2, and the second capacitor C2 stores the voltage difference between the first node N1 and the second node N2.
  • the driving transistor DT is turned on.
  • the driving current I DS in the driving transistor DT charges the second node N2 to raise the voltage V N2 of the second node N2 up to Vref1-Vth.
  • Vth is the threshold voltage of the driving transistor DT.
  • the fourth transistor T4 is turned off under the control of the low-level second light-emitting control signal EM2 to disconnect the path between the driving transistor DT and the light-emitting element 200, so that the driving current I DS will not be transmitted to the OLED, thereby avoiding The OLED emits light by mistake.
  • the second transistor T2 is turned off under the control of the reset signal RST of a low level.
  • a high-level driving signal GA As shown in FIG. 7 , in the data writing phase P3, a high-level driving signal GA, a low-level reset signal RST, a first lighting control signal EM1 and a second lighting control signal EM2 are provided.
  • the data signal terminal DA provides the data signal Vdata.
  • the first transistor T1 is turned on under the control of the high-level driving signal GA, so as to provide the data signal Vdata of the data signal terminal DA to the fourth node N4, so that the The voltage V N4 of the fourth node N4 is Vdata.
  • the first capacitor C1 stores the voltage difference between the first voltage signal terminal VDD and the second node N2
  • the second capacitor C2 stores the voltage difference between the first node N1 and the second node N2
  • the third capacitor stores the fourth node N4 and the voltage difference between the first node N1. Therefore, as the voltage V N4 of the fourth node N4 changes, the voltage V N1 of the first node N1 and the voltage V N2 of the second node N2 also change accordingly.
  • the voltages of the first node N1 and the second node N2 can be calculated as:
  • the fourth transistor T4 disconnects the path between the driving transistor DT and the OLED, the driving current I DS will not be transmitted to the OLED, thereby preventing the OLED from emitting light by mistake. At the same time, the influence of the capacitance of the OLED itself on the driving current I DS is also avoided.
  • the data signal terminal DA can provide a data signal or any signal, which is not limited.
  • the third transistor T3 is turned on under the control of the high-level first light-emitting control signal EM1 to connect the first voltage signal terminal VDD with the driving transistor DT.
  • the fourth transistor T4 is turned on under the control of the high-level second light-emitting control signal EM2 to connect the driving transistor DT with the OLED.
  • the first transistor T1 is turned off under the control of the low-level driving signal GA
  • the second transistor T2 the fifth transistor T5 and the sixth transistor T6 are turned off under the control of the low-level reset signal RST.
  • the first capacitor C1 maintains the voltage difference between the first voltage signal terminal VDD and the second node N2
  • the second capacitor C2 maintains the voltage difference between the first node N1 and the second node N2
  • the third capacitor stores the fourth node The voltage difference between N4 and the first node N1. Therefore, the voltage V N1 of the first node N1 , the voltage V N2 of the second node N2 , and the voltage V N4 of the fourth node N4 are all stored by capacitors, which are the same as the previous stage.
  • the driving current I DS of the driving transistor DT is supplied to the OLED to emit light.
  • the drive current I DS can be calculated according to the following equation:
  • ⁇ , C ox , W, L are constant values related to the driving transistor DT itself, where ⁇ is the electron mobility of the driving transistor DT, Co ox is the gate unit capacitance of the driving transistor DT, W is the channel width of the driving transistor DT, and L is the channel length of the driving transistor DT.
  • V gs represents the gate (here, the control electrode) and source (here, the first electrode) of the drive transistor DT.
  • V th represents the threshold voltage of the drive transistor DT.
  • the driving current flowing through the light emitting element OLED is no longer related to the threshold voltage of the driving transistor DT, the power supply voltage (eg, the first voltage VDD, the second voltage VSS) or the capacitance Coled of the light emitting element itself. Therefore, the compensation of the pixel circuit can be realized, and the problems of threshold voltage drift of the driving transistor DT due to the process and long-term operation, and the different positions of the pixel units caused by the different power supply voltages provided to the pixel circuits are solved.
  • the problem, as well as the problem that the capacitance Coled of the light-emitting element itself is different, can eliminate its influence on the driving current, so that the display effect of the display device using the same can be improved.
  • the data signal terminal can transmit only the data signal without transmitting other reference signals, thereby simplifying the driving circuit design.
  • first reference signal Vref1 and the second reference signal Vref2 may be the same signal. In other examples, the first reference signal Vref1 and the second reference signal Vref2 may also be different signals.
  • FIG. 9 shows a schematic flowchart of a method for driving a pixel circuit according to an embodiment of the present invention.
  • the pixel circuit is, for example, the pixel circuit shown in FIG. 1 , and the circuit structure of the pixel circuit shown in FIG. 2 can be adopted, for example.
  • step S910 in the initialization stage, a drive signal and a reset signal may be provided to turn on the data writing circuit and the initialization circuit, the reference signal from the data signal terminal is provided to the first node through the data writing circuit, and the initialization circuit An initialization signal is provided to the second node.
  • step S920 in the compensation stage, a driving signal and a first light-emitting control signal may be provided to turn on the data writing circuit and the first light-emitting control circuit, the reference signal is maintained to be provided to the first node through the data writing circuit, and the first light-emitting control The circuit provides the first voltage signal to the third node to charge the first storage circuit and the second storage circuit to compensate the drive circuit.
  • a driving signal may be provided to turn on the data writing circuit, so as to provide the data signal from the data signal terminal to the first node.
  • step S940 in the light-emitting stage, the first light-emitting control signal and the second light-emitting control signal may be provided to turn on the first light-emitting control circuit and the second light-emitting control circuit, and the driving current of the driving circuit is provided to the light-emitting element to make the light-emitting element emit light .
  • the driving method shown in FIG. 9 may be implemented by using the timing diagram of the signals of the pixel circuit shown in FIG. 5 and the above related descriptions.
  • steps S910 , S920 , S930 and S940 are used to represent the sequence of the method for driving the pixel circuit in the embodiment of the present invention, it does not constitute a limitation to the embodiment of the present invention. Any suitable order of execution is included within the scope of this disclosure.
  • FIG. 10 shows a schematic flowchart of a method for driving a pixel circuit according to an embodiment of the present invention.
  • the pixel circuit is, for example, the pixel circuit shown in FIG. 3 , and the circuit structure of the pixel circuit shown in FIG. 4 can be adopted, for example.
  • a reset signal can be provided to turn on the initialization circuit, the first reference circuit and the second reference circuit, the initialization signal is provided to the second node through the initialization circuit, the first reference circuit is A reference signal is provided to the first node, and a second reference signal is provided to the fourth node through the second reference circuit.
  • a first lighting control signal can be provided to turn on the first lighting control circuit, and the first voltage signal is provided to the third node through the first lighting control circuit, and the first storage circuit and the second storage circuit are provided with a first voltage signal. and the third storage circuit is charged to compensate the drive circuit.
  • a driving signal may be provided to turn on the data writing circuit, so as to provide the data signal from the data signal terminal to the fourth node.
  • step S1040 in the light-emitting stage, the first light-emitting control signal and the second light-emitting control signal may be provided to turn on the first light-emitting control circuit and the second light-emitting control circuit, and the driving current of the driving circuit is provided to the light-emitting element to make the light-emitting element emit light .
  • the driving method shown in FIG. 10 may be implemented by using the timing diagram of the signals of the pixel circuit shown in FIG. 7 and the above related descriptions.
  • steps S1010 , S1020 , S1030 and S1040 are used to represent the sequence of the method for driving the pixel circuit in the embodiment of the present invention, it does not constitute a limitation to the embodiment of the present invention. Any suitable order of execution is included within the scope of this disclosure.
  • FIG. 11 shows a schematic diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate 1100 may include a plurality of pixel circuits, such as pixel circuits according to embodiments of the present disclosure.
  • a plurality of pixel circuits eg, pixel circuits 1011, 1012, 1021, 1022, etc.
  • embodiments of the present disclosure also provide a display panel including the above array substrate, and a display device including the display panel.
  • the display device may be, for example, a display screen, a mobile phone, a tablet computer, a camera, a wearable device, or the like.
  • the embodiments of the present disclosure it is possible to compensate for the deviation and drift of the threshold voltages of the driving transistors in a plurality of pixel circuits, as well as to compensate for the brightness difference between the far end and the near end of the power supply caused by the IR drop, and to avoid the capacitance Coled of the light emitting element itself.
  • the influence of the drive current can improve the uniformity and display quality of the display.
  • the light-emitting element can be prevented from erroneously emitting light in the non-light-emitting stage.
  • the data signal terminal may only transmit the data signal without transmitting other reference signals, thereby simplifying the design of the driving circuit.

Abstract

本公开的实施例公开了像素电路及其驱动方法、阵列基板和显示面板。像素电路包括驱动电路、数据写入电路、初始化电路、第一发光控制电路、第一存储电路、第二存储电路和第二发光控制电路。驱动电路耦接第一节点、第二节点和第三节点，并向发光元件提供驱动电流。数据写入电路耦接第一节点，根据驱动信号将数据信号提供至驱动电路。初始化电路根据复位信号将初始化信号提供至第二节点。第一发光控制电路根据第一发光控制信号将第一电压信号提供至第三节点。第一存储电路存储第一电压信号端和第二节点之间的电压差。第二存储电路存储第一节点和第二节点之间的电压差。第二发光控制电路根据第二发光控制信号，控制向发光元件提供驱动电流。

Description

像素电路及其驱动方法、阵列基板、显示面板 技术领域
本公开涉及显示技术领域，具体地，涉及像素电路及其驱动方法、阵列基板和显示面板。
背景技术
随着显示技术的发展，相对于传统的液晶显示(Liquid Crystal Display，LCD)面板，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示面板具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点。通常，在OLED显示面板中，包括阵列排布的多个像素单元，同一行的像素单元连接到同一条栅线，同一列的像素单元连接到同一条数据线，每个像素单元在栅线提供的扫描信号和数据线提供的数据信号的驱动下进行显示。
发明内容
本公开的实施例提供了一种像素电路及其驱动方法、阵列基板和显示面板。
根据本公开的第一方面，提供了一种像素电路。像素电路可包括驱动电路、数据写入电路、初始化电路、第一发光控制电路、第一存储电路、第二存储电路和第二发光控制电路。驱动电路耦接第一节点、第二节点和第三节点，并可向发光元件提供驱动电流。数据写入电路耦接第一节点，并可根据来自驱动信号端的驱动信号，将来自数据信号端的数据信号提供至驱动电路。初始化电路可根据来自复位信号端的复位信号，将来自初始化信号端的初始化信号提供至第二节点。第一发光控制电路可根据来自第一发光控制信号端的第一发光控制信号，将来自第一电压信号端的第一电压信号提供至第三节点。第一存储电路可存储第一电压信号端和第二节点 之间的电压差。第二存储电路可存储第一节点和第二节点之间的电压差。第二发光控制电路可根据来自第二发光控制信号端的第二发光控制信号，控制向发光元件提供驱动电流。
在本公开的实施例中，第一存储电路可包括第一电容。第一电容可被耦接在第一电压信号端和第二节点之间。第二存储电路可包括第二电容。第二电容可被耦接在第一节点和第二节点之间。
在本公开的实施例中，数据写入电路可包括第一晶体管。第一晶体管的控制极耦接驱动信号端，第一极耦接数据信号端，以及第二极耦接第一节点。
在本公开的实施例中，初始化电路可包括第二晶体管。第二晶体管的控制极耦接复位信号端，第一极耦接初始化信号端，以及第二极耦接第二节点。
在本公开的实施例中，第一发光控制电路可包括第三晶体管。第三晶体管的控制极耦接第一发光控制信号端，第一极耦接第一电压信号端，以及第二极耦接第三节点。
在本公开的实施例中，第二发光控制电路可包括第四晶体管。第四晶体管的控制极耦接第二发光控制信号端，第一极耦接第二节点，以及第二极耦接发光元件。
在本公开的实施例中，驱动电路可包括驱动晶体管。驱动晶体管的控制极耦接第一节点，第一极耦接第二节点，第二极耦接第三节点。
在本公开的实施例中，数据写入电路还可根据驱动信号，将来自数据信号端的参考信号提供至驱动电路。
在本公开的实施例中，像素电路还可包括第三存储电路、第一参考电路和第二参考电路。第三存储电路的一端耦接第一节点，另一端经由第四节点耦接数据写入电路，并可存储第四节点和第一节点之间的电压差。第一参考电路可根据复位信号，将来自第一参考信号端的第一参考信号提供至第一节点。第二参考电路可根据复位信号，将来自第二参考信号端的第二参考信号提供至第四节点。
在本公开的实施例中，第三存储电路可包括第三电容。第三电容被耦接在第四节点和第一节点之间。
在本公开的实施例中，第一参考电路可包括第五晶体管。第五晶体管的控制极耦接复位信号端，第一极耦接第一参考信号端，以及第二极耦接第一节点。第二参考电路可包括第六晶体管。第六晶体管的控制极耦接复位信号端，第一极耦接第二参考信号端，以及第二极耦接第四节点。
在本公开的实施例中，第一参考信号和第二参考信号可以是相同的信号。
根据本公开的第二方面，提供了一种用于驱动本公开的像素电路的方法。在初始化阶段，可提供驱动信号和复位信号以开启数据写入电路和初始化电路，通过数据写入电路将来自数据信号端的参考信号提供至第一节点，通过初始化电路将初始化信号提供至第二节点。在补偿阶段，可提供驱动信号和第一发光控制信号以开启数据写入电路和第一发光控制电路，通过数据写入电路保持向第一节点提供参考信号，通过第一发光控制电路将第一电压信号提供至第三节点，对第一存储电路和第二存储电路充电，以补偿驱动电路。在数据写入阶段，可提供驱动信号以开启数据写入电路，以将来自数据信号端的数据信号提供至第一节点。在发光阶段，可提供第一发光控制信号和第二发光控制信号以开启第一发光控制电路和第二发光控制电路，将驱动电路的驱动电流提供给发光元件以使发光元件发光。
根据本公开的第三方面，提供了一种用于驱动本公开的像素电路的方法。在初始化阶段，可提供复位信号以开启初始化电路、第一参考电路和第二参考电路，通过初始化电路将初始化信号提供至第二节点，通过第一参考电路将第一参考信号提供至第一节点，通过第二参考电路将第二参考信号提供至第四节点。在补偿阶段，可提供第一发光控制信号以开启第一发光控制电路，通过第一发光控制电路将第一电压信号提供至第三节点，对第一存储电路、第二存储电路和第三存储电路充电，以补偿驱动电路。在数据写入阶段，可提供驱动信号以开启数据写入电路，以将来自数据信号端的数据信号提供至第四节点。在发光阶段，可提供第一发光控制信号 和第二发光控制信号以开启第一发光控制电路和第二发光控制电路，将驱动电路的驱动电流提供给发光元件以使发光元件发光。
根据本公开的第四方面，提供了一种阵列基板。阵列基板可包括本公开的第一方面的多个像素电路。
根据本公开的第五方面，提供了一种显示面板。显示面板包括本公开的第四方面的阵列基板。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅是本公开的一些实施例，而非对本公开的限制，其中：
图1示出了根据本公开的实施例的像素电路的示意性框图；
图2示出了根据本公开的实施例的像素电路的示例性电路图；
图3示出了根据本公开的另一实施例的像素电路的示意性框图；
图4示出了根据本公开的另一实施例的像素电路的示例性电路图；
图5示出了根据本公开的实施例的像素电路中的信号的时序图；
图6A为图2所示的像素电路在初始化阶段的等效电路图；
图6B为图2所示的像素电路在补偿阶段的等效电路图；
图6C为图2所示的像素电路在数据写入阶段的等效电路图；
图6D为图2所示的像素电路在发光阶段的等效电路图；
图7示出了根据本公开的另一实施例的像素电路中的信号的时序图；
图8A为图4所示的像素电路在初始化阶段的等效电路图；
图8B为图4所示的像素电路在补偿阶段的等效电路图；
图8C为图4所示的像素电路在数据写入阶段的等效电路图；
图8D为图4所示的像素电路在发光阶段的等效电路图；
图9示出了根据本公开的实施例的用于驱动像素电路的方法的流程图；
图10示出了根据本公开的另一实施例的用于驱动像素电路的方法的流程图；
图11示出了根据本公开的实施例的阵列基板的示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开的实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而并非全部的实施例。基于所描述的本公开的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
在本公开的描述中，除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所述领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量显示，而是表示存在至少一个。“多个”表示两个或两个以上。“包括”或者“包含”等类似的词语意旨出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“连接”或者“耦接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相对地改变。
下面将参照附图详细描述根据本公开的各个实施例。需要注意的是，在附图中，相同的附图标记指示基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
OLED显示装置通常包括多个按阵列排布的像素单元，每个像素单元可以通过像素电路来实现驱动OLED发光的基本功能。通常，可通过改变直接驱动OLED发光的驱动晶体管的栅极电压，来控制驱动晶体管的源极与漏极之间电流的大小以实现发光亮度的变化。然而，在制作驱动晶体管的过程中，由于工艺偏差会导致不同的驱动晶体管的阈值电压存在差异。并且随着工作时间延长及使用环境改变，驱动晶体管的阈值电压会发生漂 移。另一方面，在显示器件中，各像素单元所处的位置不同也可能导致电源的压降(I-R Drop)不同，从而对驱动OLED的电流产生影响。此外，由于OLED显示装置中的各OLED本身的电容也可能不同，从而对驱动电流产生影响。
本公开的实施例提供了一种像素电路及其驱动方法、阵列基板和显示面板。该像素电路可补偿驱动晶体管的阈值电压的偏差及漂移，补偿由于IR Drop引起的电源远端与近端之间的亮度差异，避免OLED本身的电容的影响，并防止OLED误发光，从而提高采用该像素电路的显示面板的显示效果。
图1示出了根据本公开的实施例的像素电路的示意性框图。如图1所示，像素电路100可包括驱动电路110、数据写入电路120、初始化电路130、第一发光控制电路140、第一存储电路150、第二存储电路160和第二发光控制电路170。在实施例中，像素电路100可用于驱动对应像素单元中的发光元件200发光。
如图1所示，驱动电路110的控制端耦接第一节点N1，第一端耦接第二节点N2，第二端耦接第三节点N3。驱动电路110可向发光元件200提供驱动电流I DS。例如，驱动电路110可根据其控制端和第一端之间的电压差(即，第一节点N1和第二节点N2之间的电压差)来提供用于驱动发光元件200发光的驱动电流I DS。
数据写入电路120可经由驱动信号端GA接收驱动信号，并经由数据信号端DA接收数据信号或者参考信号。数据写入电路120还可耦接到第一节点N1，进而与驱动电路110的控制端耦接。在实施例中，数据写入电路120可根据来自驱动信号端GA的驱动信号，将来自数据信号端DA的数据信号或参考信号提供至第一节点N1，即驱动电路110的控制端。在示例中，驱动信号端GA可与对应于该像素单元的栅线连接，因此驱动信号可以是用于该像素单元的扫描信号。此外，数据信号端DA可与对应于该像素单元的数据线连接，数据线可在不同时间段相应地提供数据信号或参考信号。
在本发明的实施例中，数据写入电路120可以与第一节点N1直接连接以直接将所需信号提供到N1节点，如图1所示。此外，数据写入电路120也可以与第一节点N1间接耦接，以间接地将所需信号提供到N1节点，如下面将结合图3所详细描述的。
初始化电路130可经由复位信号端RST接收复位信号，并经由初始化信号端VINI接收初始化信号。初始化电路130还可耦接到第二节点N2，进而与驱动电路110的第一端耦接。在实施例中，初始化电路130可根据来自复位信号端RST的复位信号，将来自初始化信号端VINI的初始化信号提供至第二节点N2，即驱动电路110的第一端。
第一发光控制电路140可经由第一发光控制信号端EM1接收第一发光控制信号，并经由第一电压信号端VDD接收第一电压信号。第一发光控制电路140还可耦接到第三节点N3，进而与驱动电路110的第二端耦接。在实施例中，第一发光控制电路140可根据来自第一发光控制信号端EM1的第一发光控制信号，将来自第一电压信号端VDD的第一电压信号提供至第三节点N3，即驱动电路110的第二端。
第一存储电路150可与第一电压信号端VDD和第二节点N2耦接，以存储第一电压信号端VDD和第二节点N2之间的电压差。
第二存储电路160可与第一节点N1和第二节点N2耦接，以存储第一节点N1和第二节点N2之间的电压差。
第二发光控制电路170可经由第二发光控制信号端EM2接收第二发光控制信号。第二发光控制电路170还可耦接到第二节点N2，进而与驱动电路110的第一端耦接。此外，第二发光控制电路170还可耦接到发光元件200。在实施例中，第二发光控制电路170可根据来自第二发光控制信号端EM2的第二发光控制信号，控制向发光元件200提供驱动电流I DS。也就是说，第二发光控制电路170可根据第二发光控制信号来控制驱动电路110与发光元件200之间的通断，由此可以防止发光元件200误发光，并有效隔离发光元件200本身的电容对驱动电流I DS的影响。
此外，发光元件200的一端可与第二发光控制电路170耦接，另一端 可与第二电压信号端VSS耦接以接收第二电压信号。在实施例中，发光元件200可在第一发光控制电路140和第二发光控制电路170的控制下，根据驱动电路110提供的驱动电流I DS而发光。
在本公开的实施例中，驱动电路110中的驱动电流I DS仅与数据信号端DA的数据信号和参考信号相关，具体分析见下文。由于驱动电流I DS与驱动电路110中的元件的特性以及电源电压(例如，第一电压信号、第二电压信号)无关，因此可提高显示的均一性。此外，第二发光控制电路170可在非发光阶段将驱动电路110与发光元件200分隔开，从而防止发光元件200误发光，并避免发光元件200本身的电容对驱动电流I DS的影响。
需要说明的是，本公开的实施例中的第一电压信号端VDD例如保持输入直流高电平信号，将该直流高电平称为第一电压。第二电压信号端VSS例如保持输入直流低电平信号，将该直流低电平称为第二电压，其低于第一电压。此外，在示例中，初始化信号端VINI例如保持输入直流低电平信号。以下各实施例与此相同，不再赘述。
另外，在本公开的实施例中，第一节点N1、第二节点N2、第三节点N3以及后文提到的第四节点N4并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。以下各实施例与此相同，不再赘述。
图2示出了根据本公开的实施例的像素电路的示例性电路图，该像素电路例如是图1的像素电路100。如图2所示，该像素电路包括：驱动晶体管DT、第一至第四晶体管(例如，作为开关晶体管)T1、T2、T3、T4、第一电容C1和第二电容C2。
在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本公开的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。
在本公开的实施例中，以N型场效应晶体管(NMOS)为例进行详细的描述。例如，N型晶体管响应于控制极为高电平信号而开启。
如图2所示，驱动电路110可包括驱动晶体管DT。驱动晶体管DT的控制极作为驱动电路110的控制端，和第一节点N1耦接。驱动晶体管DT的第一极作为驱动电路110的第一端，和第二节点N2耦接。驱动晶体管DT的第二极作为驱动电路110的第二端，和第三节点N3耦接。例如，驱动晶体管DT是N型晶体管。
数据写入电路120可包括第一晶体管T1。第一晶体管T1的控制极和驱动信号端GA耦接以接收驱动信号，第一极和数据信号端DA耦接以接收数据信号或参考信号，以及第二极和第一节点N1(驱动晶体管DT的控制极)耦接。在示例中，第一晶体管T1为N型晶体管。
初始化电路130可包括第二晶体管T2。第二晶体管T2的控制极和复位信号端RST耦接以接收复位信号，第一极和初始化信号端VINI耦接以接收初始化信号，以及第二极和第二节点N2(驱动晶体管DT的第一极)耦接。在示例中，第二晶体管T2为N型晶体管。
第一发光控制电路140可包括第三晶体管T3。第三晶体管T3的控制极和第一发光控制信号端EM1耦接以接收第一发光控制信号，第一极和第一电压信号端VDD耦接以接收第一电压信号，以及第二极和第三节点N3(驱动晶体管DT的第二极)耦接。在示例中，第三晶体管T3为N型晶体管。
第一存储电路150可包括第一电容C1。第一电容C1的第一端和第一电压信号端VDD耦接，且第二端和第二节点N2耦接。
第二存储电路160可包括第二电容C2。第二电容C2的第一端和第一节点N1耦接，且第二端和第二节点N2耦接。
第二发光控制电路170可包括第四晶体管T4。第四晶体管T4的控制极和第二发光控制信号端EM2耦接以接收发光控制信号，第一极和第二节点N2耦接，以及第二极和发光元件200耦接。在示例中，第四晶体管T4为N型晶体管。
可以理解地，驱动电路110、数据写入电路120、初始化电路130、第一发光控制电路140、第一存储电路150、第二存储电路160和第二发光控 制电路170中的一个和多个也可以是由其它元件组成的电路，而不限于以上所描述的。
此外，发光元件200例如是各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光，本公开的实施例对此不作限制。如图2所示，OLED的正极耦接第四晶体管T4的第二极，且负极耦接第二电压信号端VSS以接收第二电压信号。图2还示意性地示出了OLED本身的电容Coled，其与OLED两端并联。
在以上实施例中，数据信号端在不同时间段提供数据信号和参考信号。然而，根据本公开的其它实施例，也可以通过其它方式单独提供参考信号，而无需通过数据信号端传递参考信号。由此，数据信号端可以只传递数据信号，从而简化了驱动电路设计。具体细节可参见如下实施例的描述。
图3示出了根据本公开的另一实施例的像素电路的示意性框图。如图3所示，像素电路300可包括驱动电路110、数据写入电路120、初始化电路130、第一发光控制电路140、第一存储电路150、第二存储电路160、第二发光控制电路170、第三存储电路310、第一参考电路320和第二参考电路330。除第三存储电路310、第一参考电路320和第二参考电路330外，图3中的像素电路的各元件与图1中的像素电路的各元件的结构和功能类似，因此不再赘述。此外，图3中的发光元件200也与图1中的发光元件200的结构和功能相同。
如图3所示，在驱动电路110和数据写入电路120之间额外设置第三存储电路310。例如，第三存储电路310的一端经由第一节点N1和驱动电路110的控制端耦接，另一端经由第四节点N4和数据写入电路120耦接。在实施例中，数据写入电路120可根据来自驱动信号端GA的驱动信号，将来自数据信号端DA的数据信号提供至第四节点N4。第三存储电路310可存储第四节点N4和第一节点N1之间的电压差。
第一参考电路320可经由复位信号端RST接收复位信号，并经由第一参考信号端REF1接收第一参考信号。第一参考电路320还可耦接到第一节点N1。在实施例中，第一参考电路320可根据来自复位信号端RST的 复位信号，将来自第一参考信号端REF1的第一参考信号提供至第一节点N1，以控制第一节点N1的电压。
第二参考电路330可经由复位信号端RST接收复位信号，并经由第二参考信号端REF2接收第二参考信号。第二参考电路330还可耦接到第四节点N4。在实施例中，第二参考电路330可根据来自复位信号端RST的复位信号，将来自第二参考信号端REF2的第二参考信号提供至第四节点N4，以控制第四节点N4的电压。
在实施例中，第一参考信号和第二参考信号可以是相同的信号，例如相同的低电平信号。在另外的实施例中，第一参考信号和第二参考信号也可以是不同的信号。
图4示出了根据本公开的实施例的像素电路的示例性电路图，该像素电路例如是图3的像素电路。如图4所示，该像素电路包括：驱动晶体管DT、第一至第六晶体管(例如，作为开关晶体管)T1、T2、T3、T4、T5、T6、第一至第三电容C1、C2、C3。除第三电容C3、第五晶体管T5和第六晶体管T6外，图4中的像素电路的各元件与图2中的像素电路的各元件的结构和功能类似，因此不再赘述。此外，图4中的发光元件也与图2中的发光元件的结构和功能相同。
在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本公开的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。
在本公开的实施例中，以N型场效应晶体管(NMOS)为例进行详细的描述。例如，N型晶体管响应于控制极为高电平信号而开启。
如图3所示，第三存储电路310可包括第三电容C3。第三电容C3的第一端和第四节点N4耦接，且第二端和第一节点N1耦接。
第一参考电路320可包括第五晶体管T5。第五晶体管T5的控制极和复位信号端RST耦接以接收复位信号，第一极和第一参考信号端REF1耦 接以接收第一参考信号REF1，以及第二极和第一节点N1耦接。在示例中，第五晶体管T5为N型晶体管。
第二参考电路330可包括第六晶体管T6。第六晶体管T6的控制极和复位信号端RST耦接以接收复位信号，第一极和第二参考信号端REF2耦接以接收第二参考信号REF2，以及第二极和第四节点N4耦接。在示例中，第六晶体管T6为N型晶体管。
可以理解地，第三存储电路310、第一参考电路320和第二参考电路330中的一个和多个也可以是由其它元件组成的电路，而不限于以上所描述的。
图5示出了用于驱动本公开的实施例的像素电路的信号的时序图。像素电路例如是图2所示的像素电路。如图5所示，像素电路的工作过程包括四个阶段，分别为初始阶段P1、补偿阶段P2、数据写入阶段P3和发光阶段P4。
图6A为图2所示的像素电路在初始化阶段的等效电路图。图6B为图2所示的像素电路在补偿阶段的等效电路图。图6C为图2所示的像素电路在数据写入阶段的等效电路图。图6D为图2所示的像素电路在发光阶段的等效电路图。
在图5以及图6A、图6B、图6C和图6D中，符号VDD、VSS和VINI既用于表示相应的电压信号端，也用于表示相应的电压。在示例中，第一电压信号端VDD提供高电平信号，第二电压信号端VSS提供低电平信号，初始化信号端VINI提供低电平信号。此外，符号RST、GA、EM1和EM2既用于表示相应的信号端，也用于表示相应的信号；符号Vref既表示数据信号端DA处的参考信号，也用于表示相应的电压；符号Vdata既表示数据信号端DA处的数据信号，也用于表示相应的电压。此外，在图6A、图6B、图6C和图6D中用“×”标识的晶体管均表示该晶体管在对应阶段内处于截止状态。
下面以第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和驱动晶体管DT均采用N型晶体管为例，结合图5以及图6A、图6B、 图6C和图6D对图2中的像素电路的工作过程进行说明。
如图5所示，在初始化阶段P1，提供高电平的驱动信号GA和复位信号RST，以及低电平的第一发光控制信号EM1和第二发光控制信号EM2。数据信号端DA提供参考信号Vref，例如低电平信号。
如图6A所示，在初始化阶段P1，第一晶体管T1在高电平的驱动信号GA的控制下导通，以将数据信号端DA的参考信号Vref提供至第一节点N1，使得第一节点N1(即，驱动晶体管的控制极)的电压V N1被初始化为Vref。第二晶体管T2在高电平的复位信号RST的控制下导通，以将低电平的初始化信号VINI提供至第二节点N2，使得第二节点N2(即，驱动晶体管的第一极)的电压V N2被初始化为VINI。
此外，第三晶体管T3在低电平的第一发光控制信号EM1的控制下关断，以将第一电压信号端VDD和驱动晶体管DT分隔开。第四晶体管T4在低电平的第二发光控制信号EM2的控制下关断，以将驱动晶体管DT与OLED分隔开，使得驱动晶体管DT中的驱动电流I DS不会传递到OLED，从而避免OLED误发光。
如图5所示，在补偿阶段P2，提供高电平的驱动信号GA和第一发光控制信号EM1，以及低电平的复位信号RST和第二发光控制信号EM2。数据信号端DA保持提供参考信号Vref，例如低电平信号。
如图6B所示，在补偿阶段P2，第一晶体管T1在高电平的驱动信号GA的控制下导通，以保持将数据信号端DA的参考信号Vref提供至第一节点N1。因此，第一节点N1的电压V N1保持为Vref。第三晶体管T3在高电平的第一发光控制信号EM1的控制下导通，以将第一电压信号VDD提供至第三节点N3。在此情况下，驱动晶体管DT导通。驱动晶体管DT中的驱动电流I DS对第二节点N2充电，以使第二节点N2的电压V N2升高直至Vref-Vth。Vth为驱动晶体管DT的阈值电压。此外，第一电容C1存储第一电压信号端VDD和第二节点N2之间的电压差，第二电容C2存储第一节点N1和第二节点N2之间的电压差。
另外，第四晶体管T4在低电平的第二发光控制信号EM2的控制下关 断，以将驱动晶体管DT与OLED之间的通路断开，使得驱动电流I DS不会传递到OLED，从而避免OLED误发光。第二晶体管T2在低电平的复位信号RST的控制下关断。
如图5所示，在数据写入阶段P3，提供高电平的驱动信号GA，以及低电平的复位信号RST、第一发光控制信号EM1和第二发光控制信号EM2。数据信号端DA提供数据信号Vdata。
如图6C所示，在数据写入阶段P3，第一晶体管T1在高电平的驱动信号的控制下保持导通，以将数据信号端的数据信号Vdata提供至第一节点N1，使得第一节点N1的电压V N1为Vdata。
第二晶体管T2在低电平的复位信号RST的控制下关断，第三晶体管T3在低电平的第一发光控制信号EM1的控制下关断，第四晶体管T4在低电平的第二发光控制信号EM2的控制下关断。此外，第一电容C1存储第一电压信号端VDD和第二节点N2之间的电压差，且第二电容C2存储第一节点N1和第二节点N2之间的电压差。因此，随着第一节点N1的电压V N1改变，第二节点N2的电压V N2也相应地改变。
根据第一电容C1和第二电容C2的分压，可将第二节点N2的电压V N2计算为：Vref-Vth+(C2/(C2+C1))*(Vdata-Vref)。
由于第四晶体管T4将驱动晶体管DT与OLED之间的通路断开，使得驱动电流I DS不会传递到OLED，从而避免OLED误发光。同时，也避免了OLED本身的电容对驱动电流I DS的影响。
如图5所示，在发光阶段P4，提供高电平的第一发光控制信号和第二发光控制信号，以及低电平的驱动信号GA和复位信号RST。
如图6D所示，在发光阶段P4，第三晶体管T3在高电平的第一发光控制信号EM1的控制下导通，以将第一电压信号端VDD与驱动晶体管DT连接。第四晶体管T4在高电平的第二发光控制信号EM2的控制下导通，以将驱动晶体管DT与OLED连接。
此外，第一晶体管T1在低电平的驱动信号GA的控制下关断，第二晶体管T2在低电平的复位信号RST的控制下关断。第一电容C1保持第一电 压信号端VDD和第二节点N2之间的电压差，且第二电容C2保持第一节点N1和第二节点N2之间的电压差。因此，第一节点N1和第二节点N2的电压与上一阶段相同。
在此阶段，驱动晶体管DT的驱动电流I DS被提供给OLED以使其发光。驱动电流I DS可根据如下等式来计算：
Figure PCTCN2021075706-appb-000001
Figure PCTCN2021075706-appb-000002
Figure PCTCN2021075706-appb-000003
Figure PCTCN2021075706-appb-000004
在以上公式中，μ、C ox、W、L均是与驱动晶体管DT本身相关的常数值，其中，μ为驱动晶体管DT的电子迁移率，C ox为驱动晶体管DT的栅极单位电容量，W为驱动晶体管DT的沟道宽，L为驱动晶体管DT的沟道长。Vgs表示驱动晶体管DT的栅极(这里为控制极)和源极(这里为第一极)。Vth表示驱动晶体管DT的阈值电压。
由以上公式可以看出，流经发光元件OLED的驱动电流不再与驱动晶体管DT的阈值电压、电源电压(例如，第一电压VDD、第二电压VSS)或发光元件本身的电容Coled有关。由此，可以实现对该像素电路的补偿，解决了驱动晶体管DT由于工艺制程及长时间的操作造成阈值电压漂移的问题、由于各像素单元的位置不同造成向各像素电路提供的电源电压不同的问题、以及发光元件本身的电容Coled不同的问题，消除其对驱动电流的影响，从而可以改善采用其的显示装置的显示效果。
图7示出了用于驱动本公开的实施例的像素电路的信号的时序图。像素电路例如是图4所示的像素电路。如图7所示，像素电路的工作过程包括四个阶段，分别为初始阶段P1、补偿阶段P2、数据写入阶段P3和发光阶段P4。
图8A为图4所示的像素电路在初始化阶段的等效电路图。图8B为图4所示的像素电路在补偿阶段的等效电路图。图8C为图4所示的像素电路在数据写入阶段的等效电路图。图8D为图4所示的像素电路在发光阶段的等效电路图。
在图7以及图8A、图8B、图8C和图8D中，符号VDD、VSS和VINI既用于表示相应的电压信号端，也用于表示相应的电压。在示例中，第一电压信号端VDD提供高电平信号，第二电压信号端VSS提供低电平信号，初始化信号端VINI提供低电平信号。此外，符号RST、GA、EM1和EM2既用于表示相应的信号端，也用于表示相应的信号；符号Vdata既表示数据信号端DA处的数据信号，也用于表示相应的电压。此外，在以下描述中，例如，符号Vref1既表示第一参考信号端REF1处的第一参考信号，也用于表示相应的电压；符号Vref2既表示第二参考信号端REF2处的第二参考信号，也用于表示相应的电压。
此外，在图8A、图8B、图8C和图8D中用“×”标识的晶体管均表示该晶体管在对应阶段内处于截止状态。
下面以第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和驱动晶体管DT均采用N型晶体管为例，结合图7以及图8A、图8B、图8C和图8D对图4中的像素电路的工作过程进行说明。
如图7所示，在初始化阶段P1，提供高电平的复位信号RST，以及低电平的驱动信号GA、第一发光控制信号EM1和第二发光控制信号EM2。此外，图7虽然示例性地示出数据信号端DA处的信号，但可以理解，数据信号端可以提供数据信号或任意信号，对此不进行限制，以下将对此进行详细描述。
如图8A所示，在初始化阶段P1，第二晶体管T2、第五晶体管T5和第六晶体管T6均在高电平的复位信号RST的控制下导通，以将低电平的初始化信号Vini提供至第二节点N2，将第一参考信号Vref1提供至第一节点N1，并且将第二参考信号Vref2提供至第四节点N4。由此，第一节点 N1(即，驱动晶体管的控制极)的电压V N1被初始化为Vref1，第二节点N2(即，驱动晶体管的第一极)的电压V N2被初始化为VINI，以及第四节点N4的电压V N4被初始化为Vref2。
此外，第一晶体管T1在低电平的驱动信号GA的控制下关断，从而将数据信号端DA与第四节点N4分隔开。由于数据信号端DA上的信号不会传递到第四节点N4，因此无需对数据信号端DA上的信号进行限制。也就是说，数据信号端DA无需传递参考信号，其可以是数据信号或任意信号。
另外，第三晶体管T3在低电平的第一发光控制信号EM1的控制下关断，以将第一电压信号端VDD和驱动晶体管DT分隔开。第四晶体管T4在低电平的第二发光控制信号EM2的控制下关断，以将驱动晶体管DT与OLED分隔开，使得驱动晶体管DT中的驱动电流I DS不会传递到OLED，从而避免OLED误发光。
如图7所示，在补偿阶段P2，提供高电平的第一发光控制信号EM1，以及低电平的驱动信号GA、复位信号RST和第二发光控制信号EM2。与初始阶段相同地，数据信号端DA可以提供数据信号或任意信号，对此不进行限制。
如图8B所示，在补偿阶段P2，第一晶体管T1在低电平的驱动信号GA的控制下关断，因此数据信号端DA上的信号不会传递到第四节点N4，所以数据信号端DA上的信号可以是数据信号或任意信号。第五晶体管T5和第六晶体管T6在低电平的复位信号RST的控制下关断。由于第三电容存储第四节点N4和第一节点N1之间的电压差，所以第一节点N1和第四节点N4保持上一阶段的电压，即，第一节点N1的电压V N1为Vref1，第四节点N4的电压V N4为Vref2。
第三晶体管T3在高电平的第一发光控制信号EM1的控制下导通，以将第一电压信号VDD提供至第三节点N3。第一电容C1存储第一电压信号端VDD和第二节点N2之间的电压差，第二电容C2存储第一节点N1和第二节点N2之间的电压差。在此阶段，驱动晶体管DT导通。驱动晶体管DT中的驱动电流I DS对第二节点N2充电，以使第二节点N2的电压V N2 升高直至Vref1-Vth。Vth为驱动晶体管DT的阈值电压。
第四晶体管T4在低电平的第二发光控制信号EM2的控制下关断，以将驱动晶体管DT与发光元件200之间的通路断开，使得驱动电流I DS不会传递到OLED，从而避免OLED误发光。另外，第二晶体管T2在低电平的复位信号RST的控制下关断。
如图7所示，在数据写入阶段P3，提供高电平的驱动信号GA，以及低电平的复位信号RST、第一发光控制信号EM1和第二发光控制信号EM2。数据信号端DA提供数据信号Vdata。
如图8C所示，在数据写入阶段P3，第一晶体管T1在高电平的驱动信号GA的控制下导通，以将数据信号端DA的数据信号Vdata提供至第四节点N4，以使得第四节点N4的电压V N4为Vdata。
第一电容C1存储第一电压信号端VDD和第二节点N2之间的电压差，第二电容C2存储第一节点N1和第二节点N2之间的电压差，第三电容存储第四节点N4和第一节点N1之间的电压差。因此，随着第四节点N4的电压V N4改变，第一节点N1的电压V N1和第二节点N2的电压V N2也相应地改变。
根据第三电容C3、第二电容C2和第一电容C1的分压，可将第一节点N1和第二节点N2的电压计算为：
Figure PCTCN2021075706-appb-000005
Figure PCTCN2021075706-appb-000006
由于第四晶体管T4将驱动晶体管DT与OLED之间的通路断开，使得驱动电流I DS不会传递到OLED，从而避免OLED误发光。同时，也避免了OLED本身的电容对驱动电流I DS的影响。
如图7所示，在发光阶段P4，提供高电平的第一发光控制信号EM1和第二发光控制信号EM2，以及低电平的驱动信号GA和复位信号RST。如上文描述的，数据信号端DA可以提供数据信号或任意信号，对此不进行限制。
如图8D所示，在发光阶段P4，第三晶体管T3在高电平的第一发光控制信号EM1的控制下导通，以将第一电压信号端VDD与驱动晶体管DT连接。第四晶体管T4在高电平的第二发光控制信号EM2的控制下导通，以将驱动晶体管DT与OLED连接。
此外，第一晶体管T1在低电平的驱动信号GA的控制下关断，第二晶体管T2、第五晶体管T5和第六晶体管T6在低电平的复位信号RST的控制下关断。第一电容C1保持第一电压信号端VDD和第二节点N2之间的电压差，第二电容C2保持第一节点N1和第二节点N2之间的电压差，且第三电容存储第四节点N4和第一节点N1之间的电压差。因此，第一节点N1的电压V N1、第二节点N2的电压V N2、第四节点N4的电压V N4均通过电容而存储，并与上一阶段相同。
在此阶段，驱动晶体管DT的驱动电流I DS被提供给OLED以使其发光。驱动电流I DS可根据如下等式来计算：
Figure PCTCN2021075706-appb-000007
Figure PCTCN2021075706-appb-000008
在以上公式中，μ、C ox、W、L均是与驱动晶体管DT本身相关的常数值，其中，μ为驱动晶体管DT的电子迁移率，C ox为驱动晶体管DT的栅极单位电容量，W为驱动晶体管DT的沟道宽，L为驱动晶体管DT的沟道长。V gs表示驱动晶体管DT的栅极(这里为控制极)和源极(这里为 第一极)。V th表示驱动晶体管DT的阈值电压。
由以上公式可以看出，流经发光元件OLED的驱动电流不再与驱动晶体管DT的阈值电压、电源电压(例如，第一电压VDD、第二电压VSS)或发光元件本身的电容Coled有关。由此，可以实现对该像素电路的补偿，解决了驱动晶体管DT由于工艺制程及长时间的操作造成阈值电压漂移的问题、由于各像素单元的位置不同造成向各像素电路提供的电源电压不同的问题、以及发光元件本身的电容Coled不同的问题，消除其对驱动电流的影响，从而可以改善采用其的显示装置的显示效果。
另外，通过独立地提供第一参考信号和第二参考信号，使得数据信号端可以只传递数据信号，而无需传递其它参考信号，从而简化了驱动电路设计。
进一步地，在示例中，第一参考信号Vref1和第二参考信号Vref2可以是相同的信号。在其它示例中，第一参考信号Vref1和第二参考信号Vref2也可以是不同的信号。
图9示出了根据本发明实施例的用于驱动像素电路的方法的示意性流程图。该像素电路例如是图1所示的像素电路，并且例如可采用图2所示的像素电路的电路结构。
在方法中，在步骤S910，在初始化阶段，可提供驱动信号和复位信号以开启数据写入电路和初始化电路，通过数据写入电路将来自数据信号端的参考信号提供至第一节点，通过初始化电路将初始化信号提供至第二节点。
在步骤S920，在补偿阶段，可提供驱动信号和第一发光控制信号以开启数据写入电路和第一发光控制电路，通过数据写入电路保持向第一节点提供参考信号，通过第一发光控制电路将第一电压信号提供至第三节点，对第一存储电路和第二存储电路充电，以补偿驱动电路。
然后，在步骤S930，在数据写入阶段，可提供驱动信号以开启数据写入电路，以将来自数据信号端的数据信号提供至第一节点。
在步骤S940，在发光阶段，可提供第一发光控制信号和第二发光控制 信号以开启第一发光控制电路和第二发光控制电路，将驱动电路的驱动电流提供给发光元件以使发光元件发光。
在本公开的实施例中，可采用图5所示的像素电路的信号的时序图和以上相关描述来实现图9所示的驱动方法。
本领域的技术人员可以理解，虽然在本发明的实施例中以步骤S910、S920、S930和S940来表示驱动像素电路的方法的顺序，但并不构成对本发明的实施例的限制。任何合适的执行顺序均被包括在本公开所保护的范围内。
图10示出了根据本发明实施例的用于驱动像素电路的方法的示意性流程图。该像素电路例如是图3所示的像素电路，并且例如可采用图4所示的像素电路的电路结构。
在方法中，在步骤S1010，在初始化阶段，可提供复位信号以开启初始化电路、第一参考电路和第二参考电路，通过初始化电路将初始化信号提供至第二节点，通过第一参考电路将第一参考信号提供至第一节点，通过第二参考电路将第二参考信号提供至第四节点。
在步骤S1020，在补偿阶段，可提供第一发光控制信号以开启第一发光控制电路，通过第一发光控制电路将第一电压信号提供至第三节点，对第一存储电路、第二存储电路和第三存储电路充电，以补偿驱动电路。
在步骤S1030，在数据写入阶段，可提供驱动信号以开启数据写入电路，以将来自数据信号端的数据信号提供至第四节点。
在步骤S1040，在发光阶段，可提供第一发光控制信号和第二发光控制信号以开启第一发光控制电路和第二发光控制电路，将驱动电路的驱动电流提供给发光元件以使发光元件发光。
在本公开的实施例中，可采用图7所示的像素电路的信号的时序图和以上相关描述来实现图10所示的驱动方法。
本领域的技术人员可以理解，虽然在本发明的实施例中以步骤S1010、S1020、S1030和S1040来表示驱动像素电路的方法的顺序，但并不构成对本发明的实施例的限制。任何合适的执行顺序均被包括在本公开所保护的 范围内。
图11示出了根据本公开实施例的阵列基板的示意图。阵列基板1100可包括多个像素电路，例如根据本公开实施例的像素电路。如图11所示，多个像素电路(例如，像素电路1011、1012、1021、1022等)可被设置为矩阵状。
另一方面，本公开的实施例还提供了一种包括以上阵列基板的显示面板，以及包括该显示面板的显示装置。显示装置例如可以是显示屏、移动电话、平板计算机、照相机、可穿戴式设备等。
根据本公开的实施例，可补偿多个像素电路中的驱动晶体管的阈值电压的偏差和漂移，以及补偿IR drop引起的电源远端与近端的亮度差异，并避免发光元件本身的电容Coled对驱动电流的影响，从而可以提高显示的均一性和显示品质。另外，还可避免发光元件在非发光阶段误发光。
在一些实施例中，数据信号端可以只传递数据信号，而无需传递其它参考信号，从而简化了驱动电路设计。
以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (17)

  1. 一种像素电路，包括：驱动电路、数据写入电路、初始化电路、第一发光控制电路、第一存储电路、第二存储电路和第二发光控制电路，其中，
    所述驱动电路耦接第一节点、第二节点和第三节点，并被配置为向发光元件提供驱动电流；
    所述数据写入电路耦接所述第一节点，被配置为根据来自驱动信号端的驱动信号，将来自数据信号端的数据信号提供至所述驱动电路；
    所述初始化电路被配置为根据来自复位信号端的复位信号，将来自初始化信号端的初始化信号提供至所述第二节点；
    所述第一发光控制电路被配置为根据来自第一发光控制信号端的第一发光控制信号，将来自第一电压信号端的第一电压信号提供至所述第三节点；
    所述第一存储电路被配置为存储所述第一电压信号端和所述第二节点之间的电压差；
    所述第二存储电路被配置为存储所述第一节点和所述第二节点之间的电压差；
    所述第二发光控制电路被配置为根据来自第二发光控制信号端的第二发光控制信号，控制向所述发光元件提供所述驱动电流。
  2. 根据权利要求1所述的像素电路，其中，
    所述第一存储电路包括:
    第一电容，其被耦接在所述第一电压信号端和所述第二节点之间。
    所述第二存储电路包括:
    第二电容，其被耦接在所述第一节点和所述第二节点之间。
  3. 根据权利要求1所述的像素电路，其中，所述数据写入电路包括：
    第一晶体管，所述第一晶体管的控制极耦接所述驱动信号端，第一极耦接所述数据信号端，以及第二极耦接所述第一节点。
  4. 根据权利要求1所述的像素电路，其中，所述初始化电路包括：
    第二晶体管，所述第二晶体管的控制极耦接所述复位信号端，第一极耦接所述初始化信号端，以及第二极耦接所述第二节点。
  5. 根据权利要求1所述的像素电路，其中，所述第一发光控制电路包括:
    第三晶体管，所述第三晶体管的控制极耦接所述第一发光控制信号端，第一极耦接所述第一电压信号端，以及第二极耦接所述第三节点。
  6. 根据权利要求1所述的像素电路，其中，所述第二发光控制电路包括:
    第四晶体管，所述第四晶体管的控制极耦接所述第二发光控制信号端，第一极耦接所述第二节点，以及第二极耦接所述发光元件。
  7. 根据权利要求1所述的像素电路，其中，所述驱动电路包括:
    驱动晶体管，所述驱动晶体管的控制极耦接所述第一节点，第一极耦接所述第二节点，第二极耦接所述第三节点。
  8. 根据权利要求1至7中任一项所述的像素电路，其中，所述数据写入电路还被配置为根据所述驱动信号，将来自所述数据信号端的参考信号提供至所述驱动电路。
  9. 根据权利要求1至7中任一项所述的像素电路，还包括：第三存储电路、第一参考电路和第二参考电路，其中，
    所述第三存储电路的一端耦接所述第一节点，另一端经由第四节点耦接所述数据写入电路，并被配置为存储所述第四节点和所述第一节点之间的电压差；
    所述第一参考电路被配置为根据所述复位信号，将来自第一参考信号端的第一参考信号提供至所述第一节点；
    所述第二参考电路被配置为根据所述复位信号，将来自第二参考信号端的第二参考信号提供至所述第四节点。
  10. 根据权利要求9所述的像素电路，其中，所述第三存储电路包括:
    第三电容，其被耦接在所述第四节点和所述第一节点之间。
  11. 根据权利要求9所述的像素电路，其中，
    所述第一参考电路包括：
    第五晶体管，所述第五晶体管的控制极耦接所述复位信号端，第一极耦接所述第一参考信号端，以及第二极耦接所述第一节点；以及
    所述第二参考电路包括：
    第六晶体管，所述第六晶体管的控制极耦接所述复位信号端，第一极耦接所述第二参考信号端，以及第二极耦接所述第四节点。
  12. 根据权利要求9所述的像素电路，其中，所述第一参考信号和所述第二参考信号是相同的信号。
  13. 一种用于驱动如权利要求1至8中任一项所述的像素电路的方法，包括:
    初始化阶段，提供所述驱动信号和所述复位信号以开启所述数据写入电路和所述初始化电路，通过所述数据写入电路将来自所述数据信号端的参考信号提供至所述第一节点，通过所述初始化电路将所述初始化信号提供至所述第二节点；
    补偿阶段，提供所述驱动信号和所述第一发光控制信号以开启所述数据写入电路和所述第一发光控制电路，通过所述数据写入电路保持向所述第一节点提供所述参考信号，通过所述第一发光控制电路将所述第一电压信号提供至所述第三节点，对所述第一存储电路和所述第二存储电路充电，以补偿所述驱动电路；
    数据写入阶段，提供所述驱动信号以开启所述数据写入电路，以将来自所述数据信号端的数据信号提供至所述第一节点；
    发光阶段，提供所述第一发光控制信号和所述第二发光控制信号以开启所述第一发光控制电路和所述第二发光控制电路，将所述驱动电路的驱动电流提供给发光元件以使所述发光元件发光。
  14. 一种用于驱动如权利要求9至12中任一项所述的像素电路的方法，包括:
    初始化阶段，提供所述复位信号以开启所述初始化电路、所述第一参 考电路和所述第二参考电路，通过所述初始化电路将所述初始化信号提供至所述第二节点，通过所述第一参考电路将所述第一参考信号提供至所述第一节点，通过所述第二参考电路将所述第二参考信号提供至所述第四节点；
    补偿阶段，提供所述第一发光控制信号以开启所述第一发光控制电路，通过所述第一发光控制电路将所述第一电压信号提供至所述第三节点，对所述第一存储电路、所述第二存储电路和所述第三存储电路充电，以补偿所述驱动电路；
    数据写入阶段，提供所述驱动信号以开启所述数据写入电路，以将来自所述数据信号端的数据信号提供至所述第四节点；
    发光阶段，提供所述第一发光控制信号和所述第二发光控制信号以开启所述第一发光控制电路和所述第二发光控制电路，将所述驱动电路的驱动电流提供给发光元件以使所述发光元件发光。
  15. 根据权利要求14所述的方法，其中，所述第一参考信号和所述第二参考信号是相同的信号。
  16. 一种阵列基板，包括如权利要求1至12中任一项所述的多个像素电路。
  17. 一种显示面板，包括如权利要求16所述的阵列基板。
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