WO2022160972A1 - 一种锁相环耦合下模块化多电平换流器序阻抗建模的方法 - Google Patents

一种锁相环耦合下模块化多电平换流器序阻抗建模的方法 Download PDF

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WO2022160972A1
WO2022160972A1 PCT/CN2021/137273 CN2021137273W WO2022160972A1 WO 2022160972 A1 WO2022160972 A1 WO 2022160972A1 CN 2021137273 W CN2021137273 W CN 2021137273W WO 2022160972 A1 WO2022160972 A1 WO 2022160972A1
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phase
locked loop
mmc
impedance
model
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邓富金
周赟
张建忠
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东南大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/381—Dispersed generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/10—Numerical modelling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/04—Power grid distribution networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2203/00—Indexing scheme relating to details of circuit arrangements for AC mains or AC distribution networks
    • H02J2203/20—Simulating, e g planning, reliability check, modelling or computer assisted design [CAD]

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  • the invention belongs to the technical field of multilevel power electronic converters, in particular to a method for modeling sequence impedance of a modular multilevel converter under phase-locked loop coupling.
  • Modular Multilevel Converter With the continuous development of current technology, Modular Multilevel Converter (MMC) has the advantages of high output level, low output harmonics, low switching loss, and easy modular expansion. Therefore, it is widely used in flexible DC transmission. field is more and more widely used. Different from traditional generators with high damping and large inertia, if a grid-connected inverter with weak damping and low inertia is used, the equivalent impedance of the grid line can no longer be ignored. If the equivalent impedance of the converter side does not match the impedance of the grid line, the grid-connected cascaded system will appear resonance and affect its stable and reliable operation.
  • MMC Modular Multilevel Converter
  • the grid-connected system based on MMC usually adopts a current closed-loop control strategy, which mainly includes control links such as AC side current control, circulating current suppression and phase-locked loop.
  • control links such as AC side current control, circulating current suppression and phase-locked loop.
  • few literatures design the controller parameters of MMC from the perspective of system stability, which leads to blindly testing the controller parameters when applying these control strategies.
  • the setting of the controller parameters directly affects the port impedance characteristics of the converter, and also affects the stability of the cascade system operation. Therefore, it is necessary to study the impedance modeling method suitable for MMC to guide the parameter design of the MMC controller. .
  • the mathematical model of MMC is a complex system with time-varying, nonlinear, multi-frequency, and multi-input and multi-output.
  • the traditional small-signal modeling method based on classical control theory cannot be directly applied to MMC.
  • the state space method based on modern control theory can effectively model multiple state variables and the coupling relationship between state variables.
  • researchers have combined the state space theory with the multi-harmonic linearization theory to form the harmonic state space theory. , has been able to build a high-precision model for the MMC ontology.
  • the MMC grid-connected system based on current closed-loop control is a multi-dimensional coupling model.
  • phase locked loop Phase Locked Loop
  • the purpose of the present invention is to provide a method for modeling the sequence impedance of a modular multi-level converter under phase-locked loop coupling, by establishing a frequency-domain phase-locked loop to output a small phase angle signal and the grid q
  • the relationship model of shaft voltage small signal is used to analyze the double mirror frequency coupling effect in the output modulation signal of the control link caused by the phase angle disturbance. Substitute the system model into the harmonic state space matrix, and calculate the current response considering the interactive coupling between the control system and the converter.
  • the method comprehensively considers the mirror frequency coupling of the control system and the multi-harmonic coupling of the MMC itself, and establishes an accurate MMC port impedance model.
  • a method for modeling sequence impedance of a modular multilevel converter under phase-locked loop coupling comprising the following steps:
  • circuit topology model established in the S1 is as follows:
  • R is the parasitic resistance of the MMC bridge arm
  • L is the filter inductance of the MMC bridge arm
  • C arm is the equivalent capacitance of the bridge arm
  • n u is the modulation signal of the upper bridge arm
  • n l is the modulation signal of the lower bridge arm
  • ic is the output current of the MMC interphase circulating current side
  • ig is the output current of the MMC interphase AC side
  • U dc is DC voltage
  • ug is the AC grid voltage.
  • phase-locked loop output phase angle small signal ⁇ relationship model in S2 is as follows:
  • ⁇ U g is the amplitude of the injected disturbance voltage
  • ⁇ p is the injected disturbance angular frequency
  • the phase-locked link transfer function is defined as H PLL .
  • ⁇ e refp/n [ ⁇ e dp/n cos( ⁇ + ⁇ )- ⁇ e qp/n sin( ⁇ + ⁇ )]2/U dc (5)
  • the impedance calculation formula in the S5 is as follows:
  • ⁇ U g ( ⁇ p ) is the complex vector form of grid-connected voltage disturbance at ⁇ p
  • ⁇ I g ( ⁇ p ) is the complex vector form of grid-connected current disturbance at ⁇ p .
  • the method for modeling the sequence impedance of a modular multilevel converter under phase-locked loop coupling proposed by the present invention is simple and clear, easy to calculate, easy to understand and implement, and is aimed at the existing problems in the MMC grid-connected system based on current closed-loop control.
  • the problem of the interactive coupling between the control system and the circuit topology by analyzing the double mirror frequency coupling effect in the output modulation signal of the control link caused by the phase angle disturbance, and comprehensively considering the combination of the multi-harmonic coupling effect of the MMC itself, to establish an accurate
  • the proposed modeling method is aimed at the common MMC that adopts current closed-loop control, and the half-bridge sub-module is used inside the MMC.
  • circuit topology and control structure are relatively common, and it is easy to establish a mathematical model; on the other hand , The physical meaning of the impedance analysis method is clear, the modeling process is modular, and it is easy to understand and implement, and the impedance of the inverter port can be measured on-site to verify the correctness of the theoretical modeling;
  • the method for modeling the sequence impedance of the modular multilevel converter under the coupling of the phase-locked loop proposed by the present invention has high precision and high practical value for establishing the MMC impedance model;
  • the MMC usually adopts a cascade structure, and the bridge arm adopts Capacitors are used as energy storage components.
  • Capacitors are used as energy storage components.
  • DC and fundamental frequency components during steady-state operation they will also couple to generate harmonic components of twice or more frequencies.
  • the introduction of capacitors theoretically increases the state variables of the system.
  • harmonic state space theory can accurately and effectively analyze complex systems with time-varying, nonlinear, multi-frequency, and multi-input and multi-output characteristics;
  • the method for modeling the sequence impedance of a modular multilevel converter under phase-locked loop coupling proposed by the present invention reveals the establishment of a relationship model between the phase-locked loop output phase angle small signal and the grid q-axis voltage small signal, and controls dq Shaft output control small signal and dq-axis current small signal, dq-axis current steady-state operating point, phase angle small signal and current controller relationship model;
  • the method for modeling the sequence impedance of a modular multilevel converter under phase-locked loop coupling proposed by the present invention reveals that the output a-phase of the control system includes fp and Concrete expressions for two frequency modulated small signals.
  • FIG. 1 is a block diagram of a three-phase MMC grid-connected system according to an embodiment of the present invention
  • FIG. 2 is a block diagram of a sub-module unit according to an embodiment of the present invention.
  • Fig. 3 is the MMC single-phase equivalent circuit of the embodiment of the present invention.
  • FIG. 4 is a block diagram of a phase-locked loop control according to an embodiment of the present invention.
  • Fig. 5 is the current closed-loop control block diagram of the embodiment of the present invention.
  • FIG. 6 is a block diagram of the interactive coupling between the control link and the converter of the MMC grid-connected system according to an embodiment of the present invention
  • Fig. 7 is the MMC positive sequence impedance under the ideal phase-locked loop of the embodiment of the present invention.
  • Fig. 8 is the MMC negative sequence impedance under the ideal phase-locked loop of the embodiment of the present invention.
  • Fig. 9 is the MMC positive-sequence impedance considering the phase-locked loop disturbance of the embodiment of the present invention.
  • FIG. 10 shows the MMC positive-sequence impedance considering phase-locked loop disturbance according to an embodiment of the present invention.
  • the present invention proposes a modularized multi-level converter impedance modeling method considering phase-locked loop coupling.
  • the topology of the MMC in the present invention adopts a three-phase six-bridge structure, and each bridge arm is composed of n half-bridge structure sub-modules and a bridge arm inductance L cascaded.
  • Each sub-module is composed of two power switch tubes T 1 , T 2 , two diodes D 1 , D 2 and an electrolytic capacitor.
  • Figure 3 shows the MMC single-phase equivalent circuit based on the average model.
  • the three-phase grid voltages u ga , u gb , and u gc are transformed by abc/ dq to obtain the dq-axis voltages ud and u q .
  • the phase angle ⁇ of the grid A phase is obtained through the integral link; as shown in Figure 5, the three-phase grid currents i ga , i gb , and i gc are transformed by abc/dq to obtain the dq -axis currents id , i q , dq -axis current reference idref , i qref and dq -axis current id, iq are subtracted and then pass through the current controller to obtain dq -axis control signals ed, eq, ed, eq are finally divided by dq /abc transformation
  • a method for modeling sequence impedance of a modular multilevel converter under phase-locked loop coupling includes: establishing the relationship between the small signal of the output phase angle of the frequency-domain phase-locked loop and the small signal of the q-axis voltage of the power grid Then, the dq-axis output control small-signal model is established, and then the modulation small-signal expression of the a-phase is derived according to the dq-axis output control small signal. Finally, the system model is substituted into the harmonic state space matrix to calculate the current response when the injected voltage is disturbed, and Calculate the MMC port impedance model based on the impedance definition.
  • the above method specifically includes the following steps:
  • the current-controlled MMC grid-connected system is divided into two parts: circuit topology and control link, and relevant parameters are obtained.
  • circuit topology model is established as follows:
  • R is the parasitic resistance of the MMC bridge arm
  • L is the filter inductance of the MMC bridge arm
  • C arm is the equivalent capacitance of the bridge arm
  • n u is the modulation signal of the upper bridge arm
  • n l is the modulation signal of the lower bridge arm
  • ic is the output current of the MMC interphase circulating current side
  • ig is the output current of the MMC interphase AC side
  • U dc is DC voltage
  • ug is the AC grid voltage.
  • ⁇ U g is the amplitude of the injected disturbance voltage
  • ⁇ p is the injected disturbance angular frequency.
  • H PLL phase-locked link transfer function
  • the frequency modulated small signal is as follows:
  • ⁇ e refp/n [ ⁇ e dp/n cos( ⁇ + ⁇ )- ⁇ e qp/n sin( ⁇ + ⁇ )]2/U dc (5)
  • ⁇ U g ( ⁇ p ) is the complex vector form of grid-connected voltage disturbance at ⁇ p
  • ⁇ I g ( ⁇ p ) is the complex vector form of grid-connected current disturbance at ⁇ p .
  • the positive and negative sequence impedances of MMC under ideal PLL are basically the same, and the three-phase system is in a symmetrical state; as shown in Figure 9 and Figure 10, considering the existence of positive and negative sequence impedances of MMC under PLL disturbance The difference is obvious. It can be seen that the symmetry of the three-phase system is destroyed after the introduction of the phase-locked loop.
  • the MMC theoretical impedance is highly consistent with the simulated impedance curve, which verifies the correctness of the impedance modeling.
  • the invention is especially suitable for the MMC grid-connected system under the current closed-loop control.
  • the proposed method not only establishes an accurate and effective phase-locked loop output characteristic model, but also establishes a high-precision MMC port impedance model .
  • description with reference to the terms “one embodiment,” “example,” “specific example,” etc. means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one aspect of the present invention. in one embodiment or example.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本发明公开一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，包括如下步骤：S1、建立电路拓扑模型；S2、建立锁相环输出特性模型；S3、建立dq轴下PI控制器输出控制小信号模型；S4、推导调制小信号；S5、计算MMC端口阻抗。本发明通过分析由相角扰动引起的控制环节输出调制信号中存在二倍镜像频率耦合效应，并综合考虑MMC自身多谐波耦合效应结合，从而建立精确的MMC端口阻抗模型，一方面所提出的建模方法针对常见的采用电流闭环控制的MMC，MMC内部采用半桥子模块，电路拓扑结构和控制结构均较为常见，易于建立数学模型；另一方面，阻抗分析法的物理意义明确、建模过程模块化，易于理解和实施，且逆变器端口阻抗可现场测量便于验证理论建模的正确性。

Description

一种锁相环耦合下模块化多电平换流器序阻抗建模的方法 技术领域
本发明属于多电平电力电子变换器技术领域，具体涉及一种锁相环耦合下模块化多电平换流器序阻抗建模的方法。
背景技术
随着现在科技的不断发展，模块化多电平转换器(Modular Multilevel Converter,MMC)具有输出电平高、输出谐波低、开关损耗低、易于模块化扩展等优势，因此其在柔性直流输电领域得到越来越广泛的应用。与传统具有高阻尼、大惯量特性的发电机不同，若采用具有弱阻尼、低惯量的特性的并网逆变器具有，电网线路等效阻抗不再可以忽略不计。如果变流器侧等效阻抗与电网线路阻抗不匹配，并网级联系统将会出现谐振现象影响其稳定可靠运行。
基于MMC的并网系统通常采用电流闭环控制策略，主要包括交流侧电流控制、环流抑制以及锁相环等控制环节。但是目前少有文献从系统稳定性的角度设计MMC的控制器参数，导致在应用这些控制策略时盲目凑试控制器参数。然而，控制器参数的设置直接影响着变流器的端口阻抗特性，同时也影响着级联系统运行的稳定性，因此有必要研究适用于MMC的阻抗建模方法从而指导MMC控制器的参数设计。
MMC的数学模型是一个时变、非线性、多频率、且多输入多输出的复杂系统，基于经典控制理论的传统小信号建模方法无法直接应用于MMC。基于现代控制理论的状态空间方法，能够有效针对多个状态变量及状态变量间的耦合关系建模，近年来科研人员将状态空间理论与多谐波线性化理论相结合形成的谐 波状态空间理论，已经能够针对MMC本体建立高精度模型。然而，基于电流闭环控制的MMC并网系统是一个多维度耦合模型，除了MMC自身的多谐波耦合，在采用锁相环(Phase Locked Loop，PLL)控制系统中存在二倍镜像频率耦合现象，这种复杂的交互耦合特性进一步提高了建模的复杂度。目前已有的研究存在以下两点不足：一方面，针对频域的锁相环理论模型的建立尚不完善；另一方面，锁相环二倍频镜像耦合特性对MMC端口阻抗特性的影响有待分析。因此本文提出的阻抗建模方法具有重要的意义。
发明内容
针对现有技术的不足，本发明的目的在于提供一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，通过建立频域锁相环输出相角小信号与电网q轴电压小信号的关系模型，分析由相角扰动引起的控制环节输出调制信号中存在二倍镜像频率耦合效应。将系统模型代入谐波状态空间矩阵中，计算考虑控制系统与变流器交互耦合下的电流响应。该方法综合考虑了控制系统的镜像频率耦合与MMC自身多谐波耦合，建立了精确的MMC端口阻抗模型。
本发明的目的可以通过以下技术方案实现：
一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，包括如下步骤：
S1、建立电路拓扑模型
将电流控制的MMC并网系统，分为电路拓扑与控制环节两部分并获取相关参数；
S2、建立锁相环输出特性模型
根据相角扰动下abc/dq变换公式以及锁相环控制信号通路，建立锁相环输出相角小信号△θ跟电网q轴电网电压小信号和锁相环控制器G pll的关系模型；
S3、建立dq轴下PI控制器输出控制小信号模型
根据电流闭环控制通路，建立dq轴下控制小信号△e d和△e q跟dq轴下电流小信号△i d和△i q、dq轴下电流稳态工作点i d和i q、相角小信号△θ以及电流控制器G i关系模型；
S4、推导调制小信号
根据控制小信号△e d和△e q和考虑相角扰动下dq/abc变换公式，得到a相控制系统输出f p频次和由锁相环耦合作用产生的
Figure PCTCN2021137273-appb-000001
频次的调制小信号；
S5、计算MMC端口阻抗
将系统模型代入谐波状态空间矩阵中，计算注入电压扰动△u g时的电流响应△i g，最后根据端口阻抗定义计算MMC端口阻抗。
进一步的，所述S1中建立电路拓扑模型如下：
Figure PCTCN2021137273-appb-000002
公式(1)中，R为MMC桥臂寄生电阻，L为MMC桥臂滤波电感，C arm为桥臂等效电容，
Figure PCTCN2021137273-appb-000003
为上桥臂电容电压之和，
Figure PCTCN2021137273-appb-000004
为下桥臂电容电压之和，n u为上桥臂调制信号，n l为下桥臂调制信号，i c为MMC相间环流侧输出电流，i g为MMC相间交流侧输出电流，U dc为直流电压，u g为交流电网电压。
进一步的，所述S2中锁相环输出相角小信号△θ关系模型如下：
Figure PCTCN2021137273-appb-000005
公式(2)中，
Figure PCTCN2021137273-appb-000006
为注入正负序扰动时的控制器频率偏移，下标p/n表示注入正负序扰动时的变量，u d为电网电压d轴稳态工作点；
Figure PCTCN2021137273-appb-000007
△U g为所注入扰动电压幅值，ω p为所注入扰动角频率，定义锁相环节传递函数为H PLL。
进一步的，所述S3中dq轴下系统输出控制小信号关系模型如下：
Figure PCTCN2021137273-appb-000008
Figure PCTCN2021137273-appb-000009
进一步的，所述S4中a相控制系统输出调制小信号的计算如下：
Δe refp/n＝[Δe dp/ncos(θ+Δθ)-Δe qp/nsin(θ+Δθ)]2/U dc    (5)
公式(5)中，θ为电网电压相位，现定义θ＝ωt，电网角频率ω＝100πrad/s，将各变量的具体表达式带入上式可以得到控制系统输出a相包含f p和
Figure PCTCN2021137273-appb-000010
频次的调制小信号：
Figure PCTCN2021137273-appb-000011
进一步的，所述S5中阻抗计算公式如下：
Figure PCTCN2021137273-appb-000012
公式(7)中，△U g(ω p)为并网电压扰动的在ω p处的复向量形式，△I g(ω p)为并网电流扰动的在ω p处的复向量形式。
本发明的有益效果：
1、本发明提出的锁相环耦合下模块化多电平换流器序阻抗建模的方法，简单明了，计算方便，易于理解和实施，针对基于电流闭环控制的MMC并网系统中存在的控制系统与电路拓扑间的交互耦合的问题，通过分析由相角扰动引 起的控制环节输出调制信号中存在二倍镜像频率耦合效应，并综合考虑了MMC自身多谐波耦合效应结合，从而建立精确的MMC端口阻抗模型，一方面所提出的建模方法针对常见的采用电流闭环控制的MMC，MMC内部采用半桥子模块，电路拓扑结构和控制结构均较为常见，易于建立数学模型；另一方面，阻抗分析法的物理意义明确、建模过程模块化，易于理解和实施，且逆变器端口阻抗可现场测量便于验证理论建模的正确性；
2、本发明提出的锁相环耦合下模块化多电平换流器序阻抗建模的方法，建立MMC阻抗模型精度高，实用价值高；MMC通常采用级联式的结构，桥臂中采用电容作为储能元件，在稳态运行时除了存在直流和基频成分外，还会耦合产生二倍及以上频率的谐波成分；此外引入电容的同时，理论上也增加了系统的状态变量，而采用谐波状态空间理论能够准确有效地分析具有时变、非线性、多频率、且多输入多输出特性的的复杂系统；
3、本发明提出的锁相环耦合下模块化多电平换流器序阻抗建模的方法，揭示了建立锁相环输出相角小信号与电网q轴电压小信号的关系模型，控制dq轴输出控制小信号与dq轴电流小信号、dq轴电流稳态工作点、相角小信号以及电流控制器关系模型；
4、本发明提出的锁相环耦合下模块化多电平换流器序阻抗建模的方法，揭示了控制系统输出a相包含f p和
Figure PCTCN2021137273-appb-000013
两个频率调制小信号的具体表达式。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例的三相MMC并网系统框图；
图2是本发明实施例的子模块单元框图；
图3是本发明实施例的MMC单相等效电路；
图4是本发明实施例的锁相环控制框图；
图5是本发明实施例的电流闭环控制框图；
图6是本发明实施例的MMC并网系统控环节与变流器交互耦合框图；
图7是本发明实施例的理想锁相环下MMC正序阻抗；
图8是本发明实施例的理想锁相环下MMC负序阻抗；
图9是本发明实施例的考虑锁相环扰动下MMC正序阻抗；
图10是本发明实施例的考虑锁相环扰动下MMC正序阻抗。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
实施例1
本发明针对采用电流闭环控制的MMC并网系统，提出了考虑锁相环耦合下模块化多电平换流器阻抗建模方法。如图1、图2、图3所示，本发明中MMC的拓扑采用三相六桥臂结构，每个桥臂由n个半桥结构的子模块以及一个桥臂电感L级联构成，每个子模块由两个功率开关管T 1、T 2，两个二极管D 1、D 2和一个电解电容组成。其中图3为基于平均模型的MMC单相等效电路。
如图4所示，三相电网电压u ga、u gb、u gc经过abc/dq变换得到dq轴电压u d、u q，q轴电压u q经过锁相环控制器再与电网基频角频率ω 1相加后，经过积分环 节，得到电网A相相角θ；如图5所示，三相电网电流i ga、i gb、i gc经过abc/dq变换得到dq轴电流i d、i q，dq轴电流参考i dref、i qref与dq轴电流i d、i q相减再经过电流控制器得到dq轴控制信号e d、e q，e d、e q经过dq/abc变换最后除以U dc/2进行标幺化得到三相电流控制基频调制信号e refa、e refb、e refc。
如图6所示，一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，包括：建立频域锁相环输出相角小信号与电网q轴电压小信号的关系模型，接着建立dq轴输出控制小信号模型，进而根据dq轴输出控制小信号推导a相的调制小信号表达式，最后将系统模型代入谐波状态空间矩阵计算注入电压扰动时的电流响应，并根据阻抗定义计算MMC端口阻抗模型。
上述方法具体包括如下步骤：
S1、建立电路拓扑模型
将电流控制的MMC并网系统，分为电路拓扑与控制环节两部分并获取相关参数，建立电路拓扑模型如下：
Figure PCTCN2021137273-appb-000014
公式(1)中，R为MMC桥臂寄生电阻，L为MMC桥臂滤波电感，C arm为桥臂等效电容，
Figure PCTCN2021137273-appb-000015
为上桥臂电容电压之和，
Figure PCTCN2021137273-appb-000016
为下桥臂电容电压之和，n u为上桥臂调制信号，n l为下桥臂调制信号，i c为MMC相间环流侧输出电流，i g为MMC相间交流侧输出电流，U dc为直流电压，u g为交流电网电压。
S2、建立锁相环输出特性模型
根据相角扰动下abc/dq变换公式以及锁相环控制信号通路，建立锁相环输 出相角小信号△θ跟电网q轴电网电压小信号和锁相环控制器G pll的关系模型如下：
Figure PCTCN2021137273-appb-000017
公式(2)中，
Figure PCTCN2021137273-appb-000018
为注入正负序扰动时的控制器频率偏移，下标p/n表示注入正负序扰动时的变量，u d为电网电压d轴稳态工作点。
Figure PCTCN2021137273-appb-000019
其中△U g为所注入扰动电压幅值，ω p为所注入扰动角频率。定义锁相环节传递函数为H PLL。
S3、建立dq轴下PI控制器输出控制小信号模型
根据电流闭环控制通路，建立dq轴下控制小信号△e d和△e q跟dq轴下电流小信号△i d和△i q、dq轴下电流稳态工作点i d和i q、相角小信号△θ以及电流控制器G i关系模型如下：
Figure PCTCN2021137273-appb-000020
Figure PCTCN2021137273-appb-000021
S4、推导调制小信号
根据控制小信号△e d和△e q和考虑相角扰动下dq/abc变换公式，得到a相控制系统输出f p频次和由锁相环耦合作用产生的
Figure PCTCN2021137273-appb-000022
频次的调制小信号如下：
Δe refp/n＝[Δe dp/ncos(θ+Δθ)-Δe qp/nsin(θ+Δθ)]2/U dc   (5)
公式(5)中，θ为电网电压相位，现定义θ＝ωt，电网角频率ω＝100πrad/s，将各变量的具体表达式带入上式可以得到控制系统输出a相包含f p和
Figure PCTCN2021137273-appb-000023
频次的调制小信号：
Figure PCTCN2021137273-appb-000024
S5、计算MMC端口阻抗
将系统模型代入谐波状态空间矩阵中，计算注入电压扰动△u g时的电流响应△i g，最后根据端口阻抗定义计算MMC端口阻抗：
Figure PCTCN2021137273-appb-000025
公式(7)中，△U g(ω p)为并网电压扰动的在ω p处的复向量形式，△I g(ω p)为并网电流扰动的在ω p处的复向量形式。
如图7、图8所示，理想锁相环下MMC正负序阻抗基本一致，三相系统处于对称状态；如图9、图10所示，考虑锁相环扰动下MMC正负序阻抗存在明显区别，可见引入锁相环后破坏了三相系统的对称性。
综上所示，MMC理论阻抗与仿真阻抗曲线高度吻合，验证了阻抗建模的正确性。本发明尤其适用于电流闭环控制下的MMC并网系统，与现有的方法相比，所提出的方法不仅建立了准确有效的锁相环输出特性模型，而且建立了高精度的MMC端口阻抗模型。
在本说明书的描述中，参考术语“一个实施例”、“示例”、“具体示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上显示和描述了本发明的基本原理、主要特征和本发明的优点。本行业的技术人员应该了解，本发明不受上述实施例的限制，上述实施例和说明书中 描述的只是说明本发明的原理，在不脱离本发明精神和范围的前提下，本发明还会有各种变化和改进，这些变化和改进都落入要求保护的本发明范围内。

Claims (6)

  1. 一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，其特征在于，包括如下步骤：
    S1、建立电路拓扑模型
    将电流控制的MMC并网系统，分为电路拓扑与控制环节两部分并获取相关参数；
    S2、建立锁相环输出特性模型
    根据相角扰动下abc/dq变换公式以及锁相环控制信号通路，建立锁相环输出相角小信号△θ跟电网q轴电网电压小信号和锁相环控制器G pll的关系模型；
    S3、建立dq轴下PI控制器输出控制小信号模型
    根据电流闭环控制通路，建立dq轴下控制小信号△e d和△e q跟dq轴下电流小信号△i d和△i q、dq轴下电流稳态工作点i d和i q、相角小信号△θ以及电流控制器G i关系模型；
    S4、推导调制小信号
    根据控制小信号△e d和△e q和考虑相角扰动下dq/abc变换公式，得到a相控制系统输出f p频次和由锁相环耦合作用产生的
    Figure PCTCN2021137273-appb-100001
    频次的调制小信号；
    S5、计算MMC端口阻抗
    将系统模型代入谐波状态空间矩阵中，计算注入电压扰动△u g时的电流响应△i g，最后根据端口阻抗定义计算MMC端口阻抗。
  2. 根据权利要求1所述的一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，其特征在于，所述S1中建立电路拓扑模型如下：
    Figure PCTCN2021137273-appb-100002
    公式(1)中，R为MMC桥臂寄生电阻，L为MMC桥臂滤波电感，C arm为桥臂等效电容，
    Figure PCTCN2021137273-appb-100003
    为上桥臂电容电压之和，
    Figure PCTCN2021137273-appb-100004
    为下桥臂电容电压之和，n u为上桥臂调制信号，n l为下桥臂调制信号，i c为MMC相间环流侧输出电流，i g为MMC相间交流侧输出电流，U dc为直流电压，u g为交流电网电压。
  3. 根据权利要求1所述的一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，其特征在于，所述S2中锁相环输出相角小信号△θ关系模型如下：
    Figure PCTCN2021137273-appb-100005
    公式(2)中，
    Figure PCTCN2021137273-appb-100006
    为注入正负序扰动时的控制器频率偏移，下标p/n表示注入正负序扰动时的变量，u d为电网电压d轴稳态工作点；
    Figure PCTCN2021137273-appb-100007
    △U g为所注入扰动电压幅值，ω p为所注入扰动角频率，定义锁相环节传递函数为H PLL。
  4. 根据权利要求1所述的一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，其特征在于，所述S3中dq轴下系统输出控制小信号关系模型如下：
    Figure PCTCN2021137273-appb-100008
    Figure PCTCN2021137273-appb-100009
  5. 根据权利要求1所述的一种锁相环耦合下模块化多电平换流器序阻抗建 模的方法，其特征在于，所述S4中a相控制系统输出调制小信号的计算如下：
    Δe refp/n＝[Δe dp/ncos(θ+Δθ)-Δe qp/nsin(θ+Δθ)]2/U dc  (5)
    公式(5)中，θ为电网电压相位，现定义θ＝ωt，电网角频率ω＝100πrad/s，将各变量的具体表达式带入上式可以得到控制系统输出a相包含f p和
    Figure PCTCN2021137273-appb-100010
    频次的调制小信号：
    Figure PCTCN2021137273-appb-100011
  6. 根据权利要求1所述的一种锁相环耦合下模块化多电平换流器序阻抗建模的方法，其特征在于，所述S5中阻抗计算公式如下：
    Figure PCTCN2021137273-appb-100012
    公式(7)中，△U g(ω p)为并网电压扰动的在ω p处的复向量形式，△I g(ω p)为并网电流扰动的在ω p处的复向量形式。
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