WO2022156130A1 - 半导体结构及其制备方法、半导体器件 - Google Patents

半导体结构及其制备方法、半导体器件 Download PDF

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Publication number
WO2022156130A1
WO2022156130A1 PCT/CN2021/100192 CN2021100192W WO2022156130A1 WO 2022156130 A1 WO2022156130 A1 WO 2022156130A1 CN 2021100192 W CN2021100192 W CN 2021100192W WO 2022156130 A1 WO2022156130 A1 WO 2022156130A1
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Prior art keywords
electrode layer
layer
substrate
semiconductor structure
hollow cavity
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English (en)
French (fr)
Inventor
曹先雷
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/462,041 priority Critical patent/US11894418B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure, a preparation method thereof, and a semiconductor device.
  • Capacitor is an important device in dynamic random access memory (DRAM), and the performance of capacitor affects the storage performance of DRAM device.
  • the capacitor generally includes an upper plate, a dielectric and a lower plate.
  • the upper plate and the lower plate respectively form the inner and outer surfaces of the column, and the dielectric is arranged between the upper plate and the lower plate.
  • the present application provides a semiconductor structure, a preparation method thereof, and a semiconductor device, which can effectively increase the area of electrodes in the semiconductor structure, thereby improving the capacitance and stability of the semiconductor structure, and optimizing the semiconductor structure. device memory performance.
  • the present application provides a semiconductor structure, including:
  • a substrate which includes an active region.
  • the first electrode layer is disposed on the substrate and is electrically connected to the active region, and the first electrode layer extends along a direction perpendicular to the substrate.
  • the dielectric layer is disposed on the surface of the first electrode layer.
  • the second electrode layer is disposed on the surface of the dielectric layer.
  • both the surface of the first electrode layer and the surface of the dielectric layer are provided with uneven structures.
  • the semiconductor structure provided by the present application by setting the substrate, facilitates the formation of an active region in the substrate, and provides a structural basis for the subsequent semiconductor structure.
  • the electrical signal transmission between the source or drain electrode in the active region and the first electrode layer is facilitated.
  • a dielectric layer is provided on the surface
  • a second electrode layer is formed on the surface of the dielectric layer
  • a capacitor structure of a semiconductor structure is formed by using the first electrode layer, the dielectric layer and the second electrode layer. Both the surface of the first electrode layer and the surface of the dielectric layer are provided with uneven structures, which helps to increase the surface area of the electrodes in the capacitor structure, thereby improving the capacitance of the semiconductor structure.
  • a surface of the first electrode layer on the side close to the dielectric layer is provided with a plurality of first protrusions and a plurality of first depressions, and the first protrusions and the first depressions
  • the first convex parts and the first concave parts are staggered and connected end to end in sequence.
  • the first electrode layer is cylindrical, the first electrode layer has a central axis, the reference plane is perpendicular to the substrate, and the distance between the reference plane and the central axis is the distance from the first convex portion to the central axis and the distance from the first concave portion to the central axis.
  • Such an arrangement can reduce the difficulty of arranging the uneven structure on the surface of the first electrode layer and help to increase the surface area of the first electrode layer.
  • the dielectric layer is a concave-convex structure
  • the dielectric layer includes a plurality of first bending parts and a plurality of second bending parts, and the first bending parts and the second bending parts are respectively located in the first neutral
  • the first curved portion and the second curved portion are staggered and connected end to end in sequence.
  • the first neutral plane is perpendicular to the substrate, and the distance between the first neutral plane and the reference plane is an average of the distance from the first curved portion to the reference plane and the distance from the second curved portion to the reference plane.
  • Such an arrangement can reduce the difficulty of arranging the dielectric layer, and at the same time increase the amount of stored charges in the dielectric layer, which helps to increase the capacitance of the semiconductor structure.
  • a surface of the second electrode layer on the side close to the dielectric layer is provided with a plurality of second protrusions and a plurality of second recesses, the second protrusions and the second recesses.
  • the second protruding parts and the second concave parts are staggered and connected end to end in sequence.
  • the second neutral plane is perpendicular to the substrate, and the distance between the second neutral plane and the reference plane is the average value of the distance from the second convex portion to the reference plane and the distance from the second concave portion to the reference plane.
  • Such an arrangement can reduce the difficulty of arranging the uneven structure on the surface of the second electrode layer and help to increase the surface area of the second electrode layer.
  • the first curved portion, the second curved portion, the first convex portion, the first concave portion, the second convex portion and the second concave portion are all arc-shaped or hemispherical shape.
  • Such an arrangement can avoid sharp corners or dead corner structures in the first electrode layer, the dielectric layer and the second electrode layer, improve the uniformity of charge storage of the capacitor, and reduce the leakage current.
  • the projection of the first electrode layer on the substrate is a first annular shape
  • the projection of the dielectric layer on the substrate includes a second annular shape and a third annular shape
  • the second annular shape is sleeved on the first annular shape.
  • the inner side of one ring is sleeved on the outer side of the first ring.
  • the projection of the second electrode layer on the substrate includes a solid portion and a fourth annular shape, the solid portion is located inside the second annular shape, and the fourth annular shape is sleeved outside the third annular shape.
  • Such an arrangement facilitates that the first electrode layer, the dielectric layer and the second electrode layer form a stacked columnar structure, which helps to increase the surface area of the electrodes in the semiconductor structure and increases the stability of the semiconductor structure. Increase the capacitance of the semiconductor structure.
  • an electrical contact portion is provided between the first electrode layer and the active region, and the first electrode layer is electrically connected to the active region through the electrical contact portion.
  • a common electrode layer is provided on the side of the second electrode layer away from the substrate, and the second electrode layer is electrically connected to the common electrode layer.
  • the material of the first electrode layer includes a mixture of one or more of tungsten, titanium, nickel, cobalt, titanium nitride and tungsten nitride.
  • the material of the second electrode layer includes one or more of silicon, germanium, silicon-germanium compound, tungsten, titanium, nickel, cobalt, titanium nitride and tungsten nitride. mix.
  • the material of the dielectric layer includes a mixture of one or more of hafnium oxide, zirconium oxide and zirconium aluminum oxide.
  • the present application provides a method for preparing a semiconductor structure, comprising:
  • a substrate is provided, the substrate has an active region.
  • a sacrificial layer with a hollow cavity is formed, the sacrificial layer is located on the substrate, and the inner sidewall of the hollow cavity has an uneven structure.
  • a first electrode layer is formed, the first electrode layer is located on the inner sidewall of the hollow cavity, the surface of the first electrode layer has an uneven structure, and the first electrode layer is electrically connected to the active region.
  • a dielectric layer is formed, and the dielectric layer is located on the surface of the first electrode layer.
  • a second electrode layer is formed, and the second electrode layer is located on the surface of the dielectric layer.
  • the method for preparing a semiconductor structure provided by the present application, by setting a substrate and forming an active region in the substrate, it is convenient to provide a structural basis for the subsequent semiconductor structure.
  • a sacrificial layer with a hollow cavity on the substrate By forming a sacrificial layer with a hollow cavity on the substrate, and arranging a first electrode layer on the inner sidewall of the hollow cavity, the surface of the first electrode layer is formed on the surface of the first electrode layer by utilizing the uneven structure on the inner sidewall of the hollow cavity. The same bumpy structure.
  • the first electrode layer is electrically connected to the active region, so as to facilitate the transmission of electrical signals between the source or drain electrode in the active region and the first electrode layer, by arranging a dielectric layer on the surface of the first electrode layer, and A second electrode layer is formed on the surface of the dielectric layer, and a capacitor structure of a semiconductor structure is formed by using the first electrode layer, the dielectric layer and the second electrode layer.
  • the uneven structure on the surface of the first electrode layer and the surface of the dielectric layer helps to increase the surface area of the electrodes in the capacitor structure, thereby improving the capacitance of the semiconductor structure.
  • the sacrificial layer is located on the substrate, and the inner sidewall of the hollow cavity has an uneven structure, specifically including: :
  • a sacrificial layer is formed, the sacrificial layer is located on the substrate, and the material of the sacrificial layer is different from that of the substrate.
  • the sacrificial layer is etched to form a columnar hollow cavity in the sacrificial layer.
  • the inner sidewall surface of the hollow cavity is processed to form an uneven structure on the inner sidewall surface of the hollow cavity.
  • Such an arrangement can help to form an uneven structure on the inner sidewall surface of the hollow cavity, and reduce the difficulty of forming the uneven structure on the first electrode layer.
  • the step of forming an uneven structure on the inner sidewall surface of the hollow cavity specifically includes:
  • a photoresist layer is formed, and the photoresist layer is located on the inner sidewall surface of the hollow cavity.
  • the inner sidewall surface of the hollow cavity is etched, and the same uneven structure as the photoresist layer is formed on the inner sidewall surface of the hollow cavity.
  • Such an arrangement can utilize the standing wave effect during the exposure process to form an uneven structure on the inner sidewall surface of the hollow cavity, thereby reducing the difficulty of forming the uneven structure.
  • the present application provides a semiconductor device including a substrate, a transistor, a bit line, a word line and the above-mentioned semiconductor structure.
  • the bit line is arranged on the substrate, the word line is arranged alternately on the bit line, the gate of the transistor is connected to the word line, the source and drain of the transistor are formed in the active area of the substrate, and the drain of the transistor is connected to the bit line connected, the source of the transistor is connected to the first electrode layer of the semiconductor structure.
  • the surface of the first electrode layer and the surface of the dielectric layer are provided with uneven structures, which helps to increase the surface area of the electrodes in the formed capacitor structure, thereby improving the semiconductor structure.
  • the semiconductor structure is mainly used to store data in semiconductor devices. By connecting the gate of the transistor with the word line, the drain of the transistor with the bit line, and the source of the transistor with the first electrode layer of the semiconductor structure, it is convenient for word lines.
  • the line controls the opening or closing of the transistor, and then reads the data information stored in the semiconductor structure through the bit line, or writes the data information into the semiconductor structure through the bit line for storage, so as to realize the data access of the semiconductor device. Improvements help improve the access performance of semiconductor devices.
  • FIG. 1 is a schematic structural diagram of a capacitor in the related art
  • FIG. 2 is a schematic structural diagram of a sacrificial layer of a semiconductor structure provided on a substrate according to an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of forming a hollow cavity in a sacrificial layer of a semiconductor structure provided by an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of forming a photoresist layer on an inner sidewall surface of a hollow cavity of a sacrificial layer of a semiconductor structure provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of the photoresist layer of the sacrificial layer of the semiconductor structure provided by the embodiment of the present application after exposure processing;
  • FIG. 6 is a schematic structural diagram of forming an uneven structure on an inner sidewall surface of a hollow cavity of a sacrificial layer of a semiconductor structure provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of forming a first electrode layer on an inner sidewall surface of a hollow cavity of a sacrificial layer of a semiconductor structure according to an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of the first electrode layer of the semiconductor structure provided on the substrate according to the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of forming a dielectric layer on the surface of the first electrode layer of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of the second electrode layer of the semiconductor structure provided on the substrate according to the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a semiconductor structure connected to an active region and a common electrode layer according to an embodiment of the present application;
  • FIG. 13 is a schematic partial structure diagram of part I in FIG. 12 provided by an embodiment of the application.
  • FIG. 14 is a schematic structural diagram of the section A-A in FIG. 10 according to an embodiment of the application.
  • 15 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 16 is a schematic flowchart of forming an uneven structure on the inner sidewall surface of the hollow cavity of the sacrificial layer of the method for fabricating the semiconductor structure provided by the embodiment of the present application;
  • FIG. 17 is a schematic flowchart of processing a sidewall surface of a hollow cavity in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 18 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • 100-semiconductor structure 10, 1-substrate; 11-active region; 20-first electrode layer; 21-first protrusion; 22-first recess; 23-reference plane; 24-first ring 30-dielectric layer; 31-first bend; 32-second bend; 33-first neutral plane; 34-second ring; 35-third ring; 40-second electrode layer; 41-second raised part; 42-second recessed part; 43-second neutral plane; 44-solid part; 45-fourth annular; 50, 5-common electrode layer; 60-sacrificial layer; 61 - hollow cavity; 70 - photoresist layer; 200 - semiconductor device; 201 - word line; 202 - electrical contact; 203 - shallow trench isolation; 204 - source region; 205 - drain region; 206 - gate 207-insulating layer; 208-interlayer dielectric layer; 2-lower plate; 3-dielectric layer; 4-upper plate.
  • FIG. 1 is a schematic structural diagram of a capacitor in the related art.
  • the inventor of the present application found in the actual research process that the current capacitor generally includes an upper plate 4, a dielectric layer 3 and a lower plate 2.
  • the capacitor is a columnar capacitor
  • the upper plate 4 and The lower electrode plate 2 forms a columnar inner surface and an outer surface respectively
  • the dielectric layer 3 is disposed between the upper electrode plate 4 and the lower electrode plate 2 .
  • the capacitor is arranged on the substrate 1 , the lower electrode plate 2 can be electrically connected to the active area of the substrate 1 , and the upper electrode plate 4 can be electrically connected to the common electrode layer 5 to realize the electrical connection of the capacitor.
  • the upper electrode plate 4 and the lower electrode plate 2 are planar structures, and the area of the capacitor electrodes is the planar area of the two.
  • the structural stability of the columnar capacitor decreases as the length of the columnar capacitor increases. When the length of the columnar capacitor reaches a certain value, there is a risk of collapse or tilt of the columnar capacitor, resulting in the upper plate 4 and lower plate 2 of the capacitor.
  • There are limitations in the way of increasing the amount of capacitor charge which also affects the stability of the capacitor structure and further affects the storage performance of the DRAM device.
  • the semiconductor structure, the preparation method thereof, and the semiconductor device provided in the embodiments of the present application facilitate the formation of an active region in the substrate by setting the substrate, and provide a structural basis for the subsequent semiconductor structure.
  • the electrical signal transmission between the source or drain electrode in the active region and the first electrode layer is facilitated.
  • a dielectric layer is provided on the surface
  • a second electrode layer is formed on the surface of the dielectric layer
  • a capacitor structure of a semiconductor structure is formed by using the first electrode layer, the dielectric layer and the second electrode layer.
  • Both the surface of the first electrode layer and the surface of the dielectric layer are provided with uneven structures, which helps to increase the surface area of the electrodes in the capacitor structure, thereby improving the capacitance of the semiconductor structure.
  • the semiconductor structure is mainly used to store data in a semiconductor device, by connecting the gate of the transistor with the word line, the drain of the transistor with the bit line, and the source of the transistor with the first electrode layer of the semiconductor structure , it is convenient for the word line to control the opening or closing of the transistor, and then read the data information stored in the semiconductor structure through the bit line, or write the data information into the semiconductor structure through the bit line for storage, and realize the data access of the semiconductor device, Improvements in semiconductor structures help improve the access performance of semiconductor devices.
  • FIG. 2 is a schematic structural diagram of a sacrificial layer of a semiconductor structure provided on a substrate according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of forming a hollow cavity in a sacrificial layer of a semiconductor structure according to an embodiment of the present application.
  • 4 is a schematic structural diagram of forming a photoresist layer on an inner sidewall surface of a hollow cavity of a sacrificial layer of a semiconductor structure according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of the photoresist layer of the sacrificial layer of the semiconductor structure provided by the embodiment of the present application after exposure processing.
  • FIG. 3 is a schematic structural diagram of forming a hollow cavity in a sacrificial layer of a semiconductor structure according to an embodiment of the present application.
  • 4 is a schematic structural diagram of forming a photoresist layer on an inner sidewall surface of a hollow cavity of a sacrificial layer of
  • FIG. 6 is a schematic structural diagram of forming a concave-convex structure on an inner sidewall surface of a hollow cavity of a sacrificial layer of a semiconductor structure according to an embodiment of the present application.
  • 7 is a schematic structural diagram of forming a first electrode layer on an inner sidewall surface of a hollow cavity of a sacrificial layer of a semiconductor structure according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of the first electrode layer of the semiconductor structure provided on the substrate according to the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of forming a dielectric layer on the surface of the first electrode layer of the semiconductor structure provided by the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of the second electrode layer of the semiconductor structure provided on the substrate according to the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a semiconductor structure connected to an active region and a common electrode layer according to an embodiment of the present application.
  • FIG. 13 is a schematic partial structure diagram of part I in FIG. 12 according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of the section A-A in FIG. 10 according to an embodiment of the present application.
  • FIG. 15 is a schematic flowchart of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of the second electrode layer of the semiconductor structure provided on the substrate according to the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a semiconductor structure connected to an active region and a common electrode layer according to an embodiment of the present application.
  • FIG. 16 is a schematic flowchart of forming an uneven structure on the inner sidewall surface of the hollow cavity of the sacrificial layer of the method for fabricating the semiconductor structure provided by the embodiment of the present application.
  • FIG. 17 is a schematic flowchart of processing a sidewall surface of a hollow cavity in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 18 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • an embodiment of the present application provides a semiconductor structure 100 , including:
  • Substrate 10 which includes active region 11 .
  • the first electrode layer 20 is disposed on the substrate 10 and is electrically connected to the active region 11 , and the first electrode layer 20 extends in a direction perpendicular to the substrate 10 .
  • the dielectric layer 30 is disposed on the surface of the first electrode layer 20 .
  • the second electrode layer 40 is disposed on the surface of the dielectric layer 30 .
  • the surface of the first electrode layer 20 and the surface of the dielectric layer 30 are both provided with uneven structures.
  • the semiconductor structure 100 provided in this embodiment may be a capacitor in a semiconductor device, and the semiconductor device may be a dynamic random access memory.
  • the substrate 10 in this embodiment may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, or silicon-on-insulator (SOI for short), etc., or known to those skilled in the art. Other materials, the substrate 10 may provide a support base for the remaining structural layers on the substrate 10 .
  • a semiconductor layer exists in the substrate 10, and the semiconductor layer can be formed by doping. According to different types of doped particles, the doped semiconductor layer can be divided into N-type and P-type.
  • an active region 11 will be formed in the semiconductor layer, and the active region 11 may include a source region and a drain region, and the source region and the drain region are connected by a channel region. When there is conduction in the channel region During current flow, the source region and the drain region of the active region 11 are electrically connected.
  • the substrate 10 may also be a broader concept, for example, the substrate 10 may also include a Landing PAD, a Contact Plug (Storage Node Contact), a dielectric layer, an Active Area 11 (Active Area), etc., The contact plug penetrates through the dielectric layer, the contact pad is electrically connected to the active area 11 through the contact plug, and the first electrode layer 20 is electrically connected to the active area 11 through the contact pad and the contact plug.
  • the first electrode layer 20 is disposed on the substrate 10 and is electrically connected to the active region 11 , which may be electrically connected to the source region or the drain region of the active region 11 .
  • an electrical contact portion 202 is provided between the first electrode layer 20 and the active region 11 , and the first electrode layer 20 is electrically connected to the active region 11 through the electrical contact portion 202 .
  • the substrate 10 and the first electrode layer 20 are not in direct contact, and other layer structures are provided between the two, so the electrical contact portion 202 can be used to realize the connection between the two.
  • One end of the electrical contact portion 202 is electrically connected to the first electrode layer 20
  • the other end of the electrical contact portion 202 is connected to the active region in the substrate 10 after passing through the remaining layer structure between the substrate 10 and the first electrode layer 20 .
  • the electrical contact portion 202 may be a contact plug (Node Contact), which can reduce the difficulty of setting the electrical connection between the first electrode layer 20 and the active region 11 in the semiconductor structure 100 and facilitate the electrical signals in the semiconductor structure 100 access process. Referring to FIG.
  • the first electrode layer 20 may be a cylindrical structure disposed on the substrate 10 , the surface of the first electrode layer 20 is formed with an uneven structure, and the surface of the first electrode layer 20 may be The inner wall surface and the outer wall surface of the cylindrical first electrode layer 20 .
  • the dielectric layer 30 is located on the surface of the first electrode layer 20 , which can cover the inner wall surface and the outer wall surface of the first electrode layer 20 , and cover the first electrode layer 20 away from the substrate 10 . on the end of the side. Based on the uneven structure of the first electrode layer 20 , the dielectric layer 30 is thus formed with an uneven structure that matches the uneven structure of the first electrode layer 20 .
  • the "fit" here may mean that the first electrode layer 20 and the dielectric layer 30 have the same uneven structure, the concave position corresponds to the convex position, and the concave depth or the convex depth may be equal.
  • the uneven structure formed on the surface of the dielectric layer 30 may refer to the surface of the dielectric layer 30 on the side close to the first electrode layer 20 and the surface on the side away from the first electrode layer 20 .
  • the dielectric layer 30 is located between the first electrode layer 20 and the second electrode layer 40 , and can be made of materials with high dielectric constant.
  • the dielectric layer 30 can block the gap between the first electrode layer 20 and the second electrode layer 40 Movement of free charges.
  • the material of the dielectric layer 30 may include one or more mixtures of hafnium oxide, zirconium oxide, and zirconium-aluminum oxide. In actual use, the user can adjust the material of the dielectric layer 30 as required. This embodiment does not be restricted.
  • a second electrode layer 40 may also be provided on the dielectric layer 30 , and the second electrode layer 40 may be wrapped around the outside of the dielectric layer 30 . Because of the uneven structure, correspondingly, a corresponding uneven structure is formed on the surface of the second electrode layer 40 on the side close to the dielectric layer 30 .
  • the upper electrode plate 4 and the lower electrode plate 2 of the capacitor are both planar structures.
  • the uneven structure of the embodiment can effectively increase the surface area of the first electrode layer 20 and the second electrode layer 40 in the unit area, and increase the surface area of the dielectric layer 30 in the unit area, thereby increasing the amount of charge stored in the semiconductor structure 100 .
  • the increase of the surface area may be related to the degree of concavity and convexity of the uneven structure. Within a certain range, by increasing the degree of concavity and convexity of the uneven structure, the increase of the surface area can be increased, thereby increasing the capacitance of the semiconductor structure 100 .
  • the surface of the first electrode layer 20 on the side close to the dielectric layer 30 is provided with a plurality of first protrusions 21 and a plurality of first recesses 22 .
  • the first protrusions 21 and the first concave portion 22 are respectively located on opposite sides of the reference surface 23 , and the first convex portion 21 and the first concave portion 22 are staggered and connected end to end in sequence.
  • the first electrode layer 20 is cylindrical, the first electrode layer 20 has a central axis 25, the reference plane 23 is perpendicular to the substrate 10, and the distance from the reference plane 23 to the central axis 25 is the distance from the first protrusion 21 to the central axis The average value of the distance of 25 and the distance from the first recessed portion 22 to the central axis 25 .
  • the central axis 25 of the first electrode layer 20 may be the central axis of the cylindrical structure, and the distance between the reference plane 23 and the central axis 25 may be the part shown in a in FIG. 13 . Since the first electrode layer 20 has a cylindrical structure, the three-dimensional structure of the reference plane 23 may also be cylindrical. The first protruding portion 21 may protrude toward one side of the reference surface 23 , and the first concave portion 22 may be recessed toward the other side of the reference surface 23 , and they are located on opposite sides of the reference surface 23 respectively.
  • the distance from the first convex portion 21 to the central axis 25 may refer to the distance between the maximum curvature of the first convex portion 21 and the central axis 25, and the distance from the first concave portion 22 to the central axis 25 may also be the first
  • the distance between the maximum curvature of the concave portion 22 and the central axis 25, the average value of the two distances can be a.
  • the dielectric layer 30 has a concave-convex structure, and the dielectric layer 30 includes a plurality of first curved portions 31 and a plurality of second curved portions 32.
  • the first curved portions 31 and the second curved portions 32 are respectively located on opposite sides of the first neutral plane 33 and have opposite bending directions.
  • the first curved portion 31 and the second curved portion 32 are staggered and connected end to end in sequence.
  • the first neutral plane 33 is perpendicular to the substrate 10 , and the distance between the first neutral plane 33 and the reference plane 23 is the distance from the first curved portion 31 to the reference plane 23 and the distance from the second curved portion 32 to the reference plane 23 average of.
  • the distance between the first neutral plane 33 and the reference plane 23 can be the part shown in b in FIG. 13
  • the first curved portion 31 can be curved toward the side of the first neutral plane 33
  • the second curved portion The portion 32 may be curved toward the other side of the first neutral plane 33 , such that the first curved portion 31 and the second curved portion 32 are located on opposite sides of the first neutral plane 33 , respectively.
  • the distance between the first curved portion 31 and the reference plane 23 may refer to the distance between the maximum curvature of the first curved portion 31 and the reference plane 23 , and the distance between the second curved portion 32 and the reference plane 23 It may refer to the distance between the second curved portion 32 and the reference plane 23, and the average value of the two distances may be b.
  • the surface of the second electrode layer 40 on the side close to the dielectric layer 30 is provided with a plurality of second protrusions 41 and a plurality of second recesses 42.
  • the second protrusions The part 41 and the second concave part 42 are respectively located on opposite sides of the second neutral plane 43 , and the second convex part 41 and the second concave part 42 are staggered and connected end to end in sequence.
  • the second neutral plane 43 is perpendicular to the substrate 10
  • the distance between the second neutral plane 43 and the reference plane 23 is the distance between the second convex portion 41 and the reference plane 23 and the distance between the second concave portion 42 and the reference plane 23 . average distance.
  • the distance between the second neutral plane 43 and the reference plane 23 may be the part shown in c in FIG. 13 , and the second protrusion 41 may be convex toward one side of the second neutral plane 43 , The second concave portion 42 may be concave toward the other side of the second neutral surface 43 , so that the second convex portion 41 and the second concave portion 42 are respectively located on opposite sides of the second neutral surface 43 .
  • the distance between the second raised portion 41 and the reference surface 23 may refer to the distance between the maximum curvature of the second raised portion 41 and the reference surface 23 , and the distance between the second recessed portion 42 and the reference surface 23 The distance may refer to the distance between the maximum curvature of the second concave portion 42 and the reference plane 23 , and the average value of the two distances may be c.
  • the first curved portion 31 , the second curved portion 32 , the first convex portion 21 , the first concave portion 22 , the second convex portion 41 and the second concave portion 42 are all arc-shaped or hemispherical. It should be noted that the arc shape or the hemispherical shape can ensure that there is no corner structure in the first electrode layer 20, the dielectric layer 30 and the second electrode layer 40, and the corner structure has a small angle or a sharp corner position, This leads to the accumulation of charges at the position accommodation, which reduces the uniformity of charge distribution between the first electrode layer 20 and the second electrode layer 40 , and also leads to the problem of outgoing leakage current in the semiconductor structure 100 .
  • first curved portion 31 , the first protruding portion 21 and the second protruding portion 41 are all portions that are bent in the same direction, and their curvatures may be the same, and the three are fitted in sequence.
  • second curved portion 32 , the first concave portion 22 and the second concave portion 42 can all be curved in the same direction, and the three can have the same degree of curvature and be fitted in sequence. This arrangement can improve the first electrode layer 20 . , the structural matching of the dielectric layer 30 and the second electrode layer 40 , thereby improving the structural stability of the semiconductor structure 100 .
  • the upper electrode plate 4 , the dielectric layer 3 and the lower electrode plate 2 of the planar structure are based on the first electrode layer 20 , the dielectric layer 30 and the second electrode layer 40 . All three have curved parts, so in the direction parallel to the substrate 10, the thickness of the three is increased, which can increase the stability and prevent the problem of tipping contact in the capacitor.
  • the projection of the first electrode layer 20 on the substrate 10 is the first ring 24
  • the projection of the dielectric layer 30 on the substrate 10 includes the second ring 34 and the third ring 35 , the second ring 34 .
  • the ring 34 is sheathed on the inner side of the first ring 24
  • the third ring 35 is sheathed on the outer side of the first ring 24 .
  • the projection of the second electrode layer 40 on the substrate 10 includes a solid portion 44 and a fourth annular shape 45 .
  • the first electrode layer 20 , the dielectric layer 30 and the second electrode layer 40 can form a layer-by-layer structure, which can increase the corresponding area of the first electrode layer 20 and the second electrode layer 40 in the semiconductor structure 100 , thereby increasing the charge storage area and increasing the charge storage capacity.
  • the outer layer structure can be used to limit and fix the inner layer structure, thereby improving the structural stability of the semiconductor structure 100 .
  • the fourth ring 45 of the second electrode layer 40 is formed by projecting the inner wall surface of the second electrode layer 40 on the substrate 10 , and the external structure of the second electrode layer 40 can be set according to the structure in the semiconductor device. Add restrictions.
  • the solid portion 44 of the second electrode layer 40 may be cylindrical as shown in FIG. 14 . In actual use, it may also be a polygonal columnar structure, and the specific shape of the solid portion 44 is not limited in this embodiment.
  • the projections of the first electrode layer 20 , the dielectric layer 30 and the second electrode layer 40 on the substrate 10 refer to the projections of the portion at the section A-A in FIG. 10 on the substrate 10 .
  • a common electrode layer 50 is provided on the side of the second electrode layer 40 away from the substrate 10 , and the second electrode layer 40 is electrically connected to the common electrode layer 50 .
  • Such an arrangement can reduce the difficulty of electrical connection arrangement of the second electrode layer 40 in the semiconductor structure 100 and facilitate the access process of electrical signals in the semiconductor structure 100 .
  • the material of the first electrode layer 20 includes a mixture of one or more of tungsten, titanium, nickel, cobalt, titanium nitride and tungsten nitride.
  • the specific material of the first electrode layer 20 needs to be adjusted, which is not limited in this embodiment.
  • the material of the second electrode layer 40 includes a mixture of one or more of silicon, germanium, silicon-germanium compound, tungsten, titanium, nickel, cobalt, titanium nitride and tungsten nitride,
  • the user can adjust the specific material of the second electrode layer 40 as required, which is not limited in this embodiment.
  • an embodiment of the present application further provides a method for preparing a semiconductor structure, which can be used to prepare the above-mentioned semiconductor structure 100 .
  • the preparation method of the semiconductor structure includes:
  • a substrate is provided, the substrate has an active region.
  • the substrate 10 can provide a structural basis for the subsequent sacrificial layer 60 and the semiconductor structure 100 .
  • the material of the substrate 10 and the formation method of the active region 11 are described in the above-mentioned semiconductor structure 100 and will not be repeated here. .
  • S21 forming a sacrificial layer, the sacrificial layer is located on the substrate, and the material of the sacrificial layer is different from that of the substrate.
  • the sacrificial layer 60 may be formed on the substrate 10 by a deposition method, and the material of the sacrificial layer 60 may be different from that of the substrate 10 to facilitate the subsequent formation of the hollow cavity 61 in the sacrificial layer 60 .
  • dry etching can be used for etching, or wet etching, such as chemical liquid etching, can be selected.
  • wet etching such as chemical liquid etching
  • a selective etching method of the sacrificial layer 60 can be selected.
  • the chemical liquid etches it, and the substrate 10 is the etch stop layer during the etching process of the sacrificial layer 60 .
  • the inner diameter of the cylindrical hollow cavity 61 can be set as required, which is not limited in this embodiment.
  • S23 processing the inner sidewall surface of the hollow cavity to form an uneven structure on the inner sidewall surface of the hollow cavity.
  • it can specifically include:
  • the photoresist layer 70 can be formed by deposition or spin coating, and the photoresist layer 70 can be made of photosensitive materials, and the photosensitive materials can include but are not limited to polymethyl methacrylate, polymethyl methacrylate Glutarimide and phenolic resins.
  • the photosensitive material can fill the hollow cavity to form a solid structure filling the hollow cavity 61 to form the photoresist layer 70 .
  • the exposure of the photoresist layer 70 here can be performed by one-step exposure and one-step development, for example, ultraviolet light (UV), deep ultraviolet (DUV), and extreme ultraviolet (EUV) are selected for one step.
  • the photoresist layer 70 with uneven structure can be obtained by exposing and then developing. When the ultraviolet light irradiates the photoresist layer 70 , under the influence of the standing wave effect, an uneven structure is formed on the surface of the photoresist layer 70 close to the sidewall of the sacrificial layer 60 .
  • the photoresist layer 70 At the interface between the photoresist layer 70 and the sacrificial layer 60, light will be reflected, and the reflected light and the incident light will interfere, so that the light intensity distribution along the depth direction of the photoresist layer 70 is uneven, thereby forming unevenness Structure. Based on the change in the physicochemical properties of the exposed photoresist layer 70 , part of the photoresist layer 70 with the changed properties may be removed by etching, thereby forming the uneven photoresist layer 70 .
  • S233 Etch the inner sidewall surface of the hollow cavity, and form the same uneven structure as the photoresist layer on the inner sidewall surface of the hollow cavity.
  • dry etching can be used to etch the inner wall surface of the hollow cavity 61 along the uneven structure of the photoresist layer 70 , so that the inner wall of the hollow cavity 61 is etched.
  • the same uneven structure is formed on the wall surface. That is, the uneven structure is transferred from the photoresist layer 70 onto the sacrificial layer 60 .
  • the first electrode layer 20 can be formed on the inner sidewall surface of the hollow cavity 61 by a deposition method. Since the inner sidewall surface of the hollow cavity 61 has an uneven structure, the first electrode layer 20 is deposited on the inner sidewall surface of the hollow cavity 61 . When the electrode layer 20 is used, the material of the first electrode layer 20 may be distributed along the uneven structure, so that the same structure as the uneven structure is formed on the first electrode layer 20 .
  • the thickness of the first electrode layer 20 may be 5-30 nm, for example, the thickness of the first electrode layer 20 may be 10 nm, 15 nm, and 25 nm. In actual use, the user can adjust the specific thickness value of the first electrode layer 20 within the above range according to the overall structure of the semiconductor structure 100 .
  • the sacrificial layer 60 needs to be removed to avoid the influence of the sacrificial layer 60 on the subsequent layer structure.
  • the sacrificial layer 60 may be removed by liquid etching.
  • the dielectric layer 30 and the second electrode layer 40 formed on the first electrode layer 20 will follow the uneven structure. distribution to form a corresponding uneven structure.
  • the thicknesses of the dielectric layer 30 and the second electrode layer 40 can both be 5-30 nm. In actual use, the user can adjust the specific thickness values of the dielectric layer 30 and the second electrode layer 40 within the above range according to the overall structure of the semiconductor structure 100 .
  • the substrate 10 by setting the substrate 10 and forming the active region 11 in the substrate 10 , it is convenient to provide a structural basis for the subsequent semiconductor structure 100 .
  • the sacrificial layer 60 By forming the sacrificial layer 60 with the hollow cavity 61 on the substrate 10 and disposing the first electrode layer 20 on the inner sidewall surface of the hollow cavity 61, the uneven structure on the inner sidewall surface of the hollow cavity 61 can be used in the first electrode layer.
  • the surface of an electrode layer 20 forms the same uneven structure.
  • the first electrode layer 20 is electrically connected to the active region 11 , which facilitates the transmission of electrical signals between the source or drain electrode in the active region 11 and the first electrode layer 20 , through the surface of the first electrode layer 20 .
  • the dielectric layer 30 is provided, and the second electrode layer 40 is formed on the surface of the dielectric layer 30 , and the capacitor structure of the semiconductor structure 100 is formed by the first electrode layer 20 , the dielectric layer 30 and the second electrode layer 40 .
  • the uneven structure on the surface of the first electrode layer 20 and the surface of the dielectric layer 30 helps to increase the surface area of the electrodes in the capacitor structure, thereby improving the capacitance of the semiconductor structure 100 .
  • an embodiment of the present application further provides a semiconductor device 200 , which includes a substrate 10 , a transistor, a bit line, a word line 201 and the above-mentioned semiconductor structure 100 .
  • the gate of the transistor is connected to the word line 201, the source and drain of the transistor are formed in the active region 11 of the substrate 10, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the semiconductor structure through electrical contact 202
  • the first electrode layer 20 of 100 is connected.
  • FIG. 2 to FIG. 12 only show the relative positional relationship between the semiconductor structure 100 and the substrate 10 , and the semiconductor structure 100 is not directly connected to the substrate 10 touch.
  • the embedded word lines 201 are formed in the substrate 10 , and the bit lines and the word lines 201 may be arranged to cross each other, that is, the extension directions of the two are interlaced with each other.
  • a gate oxide layer 206 is formed outside the word line 201 , an insulating layer 207 is provided on the side of the word line 201 away from the substrate 10 , and the word line 201 is electrically connected to the gate of the transistor.
  • Shallow trench isolations 203 are formed between adjacent word lines 201 to separate the word lines 201 .
  • a doping layer is formed between adjacent shallow trench isolations 203 , and the doping layer is doped with different particles to form a source region 204 or a drain region 205 in the active region 11 .
  • the source region 204 is electrically connected with the first electrode layer 20 through the electrical contact portion 202, and the drain region 205 is electrically connected with the bit line.
  • the electrical contact 202 may be part of the substrate 10 .
  • the semiconductor structures 100 are formed above the word lines 201 , and the semiconductor structures 100 are arranged in an array.
  • An interlayer dielectric layer 208 is formed between adjacent semiconductor structures 100 to isolate the adjacent semiconductor structures 100 .
  • Each semiconductor structure 100 is disposed corresponding to one transistor structure, and the first electrode layer 20 in the semiconductor structure 100 may be electrically connected to the source region of the active region 11 through the electrical contact portion 202 .
  • the semiconductor device 200 may include a plurality of memory cells, each of which includes a transistor and the semiconductor structure 100 .
  • the semiconductor structure 100 may be used to store data, and the transistors may control access to the data by the semiconductor structure 100 .
  • the voltage signal on the word line 201 can control the opening or closing of the transistor, and then read the data information stored in the semiconductor structure 100 through the bit line, or write the data information into the semiconductor structure 100 through the bit line for storage, so as to realize the The data access of the semiconductor device 200, therefore, when the above-mentioned semiconductor structure 100 of this embodiment is applied to the semiconductor device 200, the access performance of the semiconductor device 200 can be improved.

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Abstract

本申请提供一种半导体结构及其制备方法、半导体器件，涉及半导体技术领域，旨在解决目前电容电量低且稳定性较差的问题。该半导体结构包括衬底，其包括有源区。第一电极层，其设置于衬底上，且电连接至有源区，第一电极层沿垂直于衬底的方向延伸。电介质层，其设置于第一电极层的表面。第二电极层，其设置于电介质层的表面。其中，第一电极层的表面和电介质层的表面均设置有凹凸不平的结构。本申请能够有效增加半导体结构中电极的面积，从而提高半导体结构的电容量和稳定性，优化半导体器件的存储性能。

Description

半导体结构及其制备方法、半导体器件
本申请要求于2021年1月25日提交中国专利局、申请号为202110098759.8、申请名称为“半导体结构及其制备方法、半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构及其制备方法、半导体器件。
背景技术
电容是动态随机存取存储器(dynamic random access memory，简称DRAM)中的重要器件，电容的性能影响DRAM器件的存储性能。
随着DRAM集成度提高，工艺不断微缩，使得单位电容的面积和以及单位电容的间距逐渐减小，因此需要保证在有限的空间中，电容能够提供足够的电容量以维持DRAM的信号强度。电容一般包括上极板、电介质和下极板，当电容为柱状电容时，上极板和下极板分别形成柱状的内侧表面和外侧表面，电介质设置在上极板和下极板之间，通过增加柱状的长度以提高电容的表面积，从而增加存储于电容中的电荷数量。
然而，目前电容量的提升方式容易导致电容稳定性较低，容易引起电容倾倒接触的问题，影响DRAM器件的存储性能。
发明内容
为了解决背景技术中提到的至少一个问题，本申请提供一种半导体结构及其制备方法、半导体器件，能够有效增加半导体结构中电极的面积，从而提高半导体结构的电容量和稳定性，优化半导体器件的存储性能。
为了实现上述目的，第一方面，本申请提供一种半导体结构，包括：
衬底，其包括有源区。
第一电极层，其设置于衬底上，且电连接至有源区，第一电极层沿垂直于衬底的方向延伸。
电介质层，其设置于第一电极层的表面。
第二电极层，其设置于电介质层的表面。
其中，第一电极层的表面和电介质层的表面均设置有凹凸不平的结构。
本申请提供的半导体结构，通过设置衬底，便于在衬底中形成有源区，并且为后续的半导体结构提供结构基础。通过设置第一电极层，并将第一电极层电连接至有源区，便于有源区中的源极或漏极与第一电极层之间的电信号传输，通过在第一电极层的表面设置电介质层，并在电介质层的表面形成第二电极层，利用第一电极层、电介质层和第二电极层形成半导体结构的电容结构。通过将第一电极层的表面和电介质层的表面均设置有凹凸不平的结构，有助于增加电容结构中电极的表面积，从而提高半导体结构的电容量。
在上述的半导体结构中，可选的是，第一电极层靠近电介质层一侧的表面上设置有多个第一凸起部和多个第一凹陷部，第一凸起部和第一凹陷部分别位于基准面的相对两侧，第一凸起部和第一凹陷部相互交错且依次首尾连接。
第一电极层为圆筒状，第一电极层具有中轴线，基准面垂直于衬底，基准面至中轴线之间的距离是第一凸起部至中轴线的距离与第一凹陷部至中轴线的距离的平均值。
这样的设置可以减少第一电极层表面凹凸不平结构的设置难度，并且有助于增加第一电极层的表面积。
在上述的半导体结构中，可选的是，电介质层为凹凸结构，电介质层包括多个第一弯曲部和多个第二弯曲部，第一弯曲部和第二弯曲部分别位于第一中性面的相对两侧且弯曲方向相反，第一弯曲部和第二弯曲部相互交错且依次首尾连接。
第一中性面垂直于衬底，第一中性面与基准面之间的距离是第一弯曲部至基准面的距离与第二弯曲部至基准面的距离的平均值。
这样的设置可以减小电介质层的设置难度，同时提高电介质层的存储电荷量，有助于提升半导体结构的电容量。
在上述的半导体结构中，可选的是，第二电极层靠近电介质层一侧的表面上设置有多个第二凸起部和多个第二凹陷部，第二凸起部和第二凹陷部分别位于第二中性面的相对两侧，第二凸起部和第二凹陷部相互交错且依次首尾连接。
第二中性面垂直于衬底，第二中性面与基准面之间的距离是第二凸起部至基准面的距离与第二凹陷部至基准面的距离的平均值。
这样的设置可以减少第二电极层表面凹凸不平结构的设置难度，并且有助于增加第二电极层的表面积。
在上述的半导体结构中，可选的是，第一弯曲部、第二弯曲部、第一凸起部、第一凹陷部、第二凸起部和第二凹陷部均为圆弧状或半球状。
这样的设置可以避免第一电极层、电介质层和第二电极层中出现尖角或者死角结构，提高电容的电荷存储均匀性，减少漏电流的情况。
在上述的半导体结构中，可选的是，第一电极层在衬底上的投影为第一环形，电介质层在衬底上的投影包括第二环形和第三环形，第二环形套在第一环形的内侧，第三环形套在第一环形的外侧。
第二电极层在衬底上的投影包括实心部和第四环形，实心部位于第二环形的内侧，第四环形套设在第三环形的外侧。
这样的设置便于第一电极层，电介质层和第二电极层形成叠层柱状结构，有助于提高半导体结构中电极的表面积，增加半导体结构的稳定性。提升半导体结构的电容量。
在上述的半导体结构中，可选的是，第一电极层与有源区之间设置有电接触部，第一电极层通过电接触部与有源区电连接。这样的设置可以减小半导体结构中第一电极层与有源区的电连接设置的难度，便于半导体结构中的电信号存取过程。
在上述的半导体结构中，可选的是，第二电极层的远离衬底一侧设置有公共电极层，第二电极层电连接至公共电极层。这样的设置可以减小半导体结构中第二电极层的电连接设置的难度，便于半导体结构中的电信号存取过程。
在上述的半导体结构中，可选的是，第一电极层的材料包括钨、钛、镍、钴、氮化钛和氮化钨中的一种或多种的混合。
在上述的半导体结构中，可选的是，第二电极层的材料包括硅、锗、硅锗化合物、钨、钛、镍、钴、氮化钛和氮化钨中的一种或多种的混合。
在上述的半导体结构中，可选的是，电介质层的材料包括氧化铪、氧化锆和锆铝氧化物中的一种或多种混合。
第二方面，本申请提供一种半导体结构的制备方法，包括：
提供衬底，衬底具有有源区。
形成具有中空腔体的牺牲层，牺牲层位于衬底上，中空腔体的内侧壁面上具有凹凸不平的结构。
形成第一电极层，第一电极层位于中空腔体的内侧壁面上，第一电极层的表面具有凹凸不平的结构，第一电极层电连接至有源区。
去除牺牲层。
形成电介质层，电介质层位于第一电极层的表面。
形成第二电极层，第二电极层位于电介质层的表面。
本申请提供的半导体结构的制备方法，通过设置衬底，并在衬底中形成有源区，便于为后续的半导体结构提供结构基础。通过在衬底上形成具有中空腔体的牺牲层，并且在中空腔体的内侧壁面上设置第一电极层，利用中空腔体内侧壁面上的凹凸不平的结构，在第一电极层的表面形成相同的凹凸不平的结构。并且，将第一电极层电连接至有源区，便于有源区中的源极或漏极与第一电极层之间的电信号传输，通过在第一电极层的表面设置电介质层，并在电介质层的表面形成第二电极层，利用第一电极层、电介质层和第二电极层形成半导体结构的电容结构。第一电极层的表面和电介质层的表面的凹凸不平结构，有助于增加电容结构中电极的表面积，从而提高半导体结构的电容量。
在上述的半导体结构的制备方法中，可选的是，在形成具有中空腔体的牺牲层，牺牲层位于衬底上，中空腔体的内侧壁面上具有凹凸不平的结构的步骤中，具体包括：
形成牺牲层，牺牲层位于衬底上，牺牲层与衬底的材料不同。
刻蚀牺牲层，在牺牲层中形成柱状的中空腔体。
处理中空腔体的内侧壁面，在中空腔体的内侧壁面上形成凹凸不平的结构。
这样的设置可以将有助于在中空腔体的内侧壁面上形成凹凸不平的结构，减小第一电极层上凹凸不平结构的形成难度。
在上述的半导体结构的制备方法中，可选的是，在处理中空腔体的内侧壁面，在中空腔体的内侧壁面上形成凹凸不平的结构的步骤中，具体包括：
形成光刻胶层，光刻胶层位于中空腔体的内侧壁面上。
曝光光刻胶层，在光刻胶层上形成凹凸不平的结构。
刻蚀中空腔体的内侧壁面，在中空腔体的内侧壁面上形成与光刻胶层相同的凹凸不平的结构。
这样的设置可以利用曝光处理过程中的驻波效应，在中空腔体的内侧壁面上形成凹凸不平的结构，减小凹凸不平结构的形成难度。
第三方面，本申请提供一种半导体器件，包括衬底、晶体管、位线、字线和上述的半导体结构。
位线设置在衬底上，字线交错设置在位线上，晶体管的栅极与字线连接，晶体管的源极和漏极形成在衬底的有源区中，晶体管的漏极与位线连接，晶体管的源极与半导体结构的第一电极层连接。
本申请提供的半导体器件，通过在半导体结构中，将第一电极层的表面和电介质层的表面均设置有凹凸不平的结构，有助于增加所形成的电容结构中电极的表面积，从而提高半导体结构的电容量。半导体结构在半导体器件中主要用于存储数据，通过将晶体管的栅极与字线连接，将晶体管的漏极与位线连接，将晶体管的源极与半导体结构的第一电极层连接，便于字线控制晶体管的打开或关闭，进而通过位线读取存储在半导体结构中的数据信息，或者通过位线将数据信息写入到半导体结构中进行存储，实现半导体器件的数据存取，半导体结构的改进有助于提升半导体器件的存取性能。
本申请的构造以及它的其他发明目的及有益效果将会通过结合附图而对优选实施例的描述而更加明显易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作以简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中电容的结构示意图；
图2为本申请实施例提供的半导体结构的牺牲层在衬底上的结构示意图；
图3为本申请实施例提供的半导体结构的牺牲层中形成中空腔体的结构示意图；
图4为本申请实施例提供的半导体结构的牺牲层的中空腔体的内侧壁面上形成光刻胶层的结构示意图；
图5为本申请实施例提供的半导体结构的牺牲层的光刻胶层经过曝光处理的结构示意图；
图6为本申请实施例提供的半导体结构的牺牲层的中空腔体的内侧壁面上形成凹凸不平结构的结构示意图；
图7为本申请实施例提供的半导体结构的牺牲层的中空腔体的内侧壁面上形成第一电极层的结构示意图；
图8为本申请实施例提供的半导体结构的第一电极层在衬底上的结构示意图；
图9为本申请实施例提供的半导体结构的第一电极层的表面形成电介质层的结构示意图；
图10为本申请实施例提供的半导体结构的结构示意图；
图11为本申请实施例提供的半导体结构的第二电极层在衬底上的结构示意图；
图12为本申请实施例提供的半导体结构与有源区以及公共电极层连接的结构示意图；
图13为本申请实施例提供的图12中I部分的局部结构示意图；
图14为本申请实施例提供的图10中A-A截面的结构示意图；
图15为本申请实施例提供的半导体结构的制备方法的流程示意图；
图16为本申请实施例提供的半导体结构的制备方法的牺牲层的中空腔体内侧壁面上形成凹凸不平的结构的流程示意图；
图17为本申请实施例提供的半导体结构的制备方法的处理中空腔体内侧壁面的流程示意图；
图18为本申请实施例提供的半导体器件的结构示意图。
附图标记说明：
100-半导体结构；10、1-衬底；11-有源区；20-第一电极层；21-第一凸起部；22-第一凹陷部；23-基准面；24-第一环形；25-中轴线；30-电介质层；31-第一弯曲部；32-第二弯曲部；33-第一中性面；34-第二环形；35-第三环形；40-第二电极层；41-第二凸起部；42-第二凹陷部；43-第二中性面；44-实心部；45-第四环形；50、5-公共电极层；60-牺牲层；61-中空腔体；70-光刻胶层；200-半导体器件；201-字线；202-电接触部；203-浅沟道隔离；204-源极区；205-漏极区；206-栅极氧化层；207-绝缘层；208-层间介质层；2-下极板；3-介电层；4-上极板。
具体实施方式
图1为相关技术中电容的结构示意图。参照图1所示，本申请的发明人在实际研究过程中发现，目前的电容一般包括上极板4、介电层3和下极板2，当电容为柱状电容时，上极板4和下极板2分别形成柱状的内侧表面和外侧表面，介电层3设置在上极板4和下极板2之间。该电容设置在衬底1上，下极板2可以电连接至衬底1的有源区，上极板4可以电连接至公共电极层5，实现电容的电连接。目前的电容中，上极板4和下极板2为平面结构，电容电极的面积即为两者的平面面积。这种情况下，一般需要通过增加柱状的长度以提高电容电极的表面积，目的在于增加存储于电容中的电荷数量。然而，柱状电容的结构稳定性随着柱状电容的长度增加而减小，当柱状电容长度达到一定数值后，会存在柱状电容坍塌或倾斜的风险，导致电容的上极板4和下极板2之间电接触，这样增加电容电荷量的方式存在局限性，也影响电容结构的稳定性，进一步地影响DRAM器件的存储性能。
有鉴于此，本申请实施例提供的半导体结构及其制备方法、半导体器件，该半导体结构通过设置衬底，便于在衬底中形成有源区，并且为后续的半导体结构提供结构基础。通过设置第一电极层，并将第一电极层电连接至有源区，便于有源区中的源极或漏极与第一电极层之间的电信号传输，通过在第一电极层的表面设置电介质层，并在电介质层的表面形成第二电极层，利用第一电极层、电介质层和第二电极层形成半导体结构的电容结构。通过将第一电极层的表面和电介质层的表面均设置有凹凸不平的结构，有助于增加电容结构中电极的表面积，从而提高半导体结构的电容量。
其中，该半导体结构在半导体器件中主要用于存储数据，通过将晶体管的栅极与字线连接，将晶体管的漏极与位线连接，将晶体管的源极与半导体结构的第一电极层连接，便于字线控制晶体管的打开或关闭，进而通过位线读取存储在半导体结构中的数据信息，或者通过位线将数据信息写入到半导体结构中进行存储，实现半导体器件的数据存取，半导体结构的改进有助于提升半导体器件的存取性能。
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请的优选实施例中的附图，对本申请实施例中的技术方案进行更加详细的描述。在附图中，自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。所描述的实施例是本申请一部分实施例，而不是全部的实施例。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。下面结合附图对本申请的实施例进行详细说明。
图2为本申请实施例提供的半导体结构的牺牲层在衬底上的结构示意图。图3为本申请实施例提供的半导体结构的牺牲层中形成中空腔体的结构示意图。图4为本申请实施例提供的半导体结构的牺牲层的中空腔体的内侧壁面上形成光刻胶层的结构示意图。图5为本申请实施例提供的半导体结构的牺牲层的光刻胶层经过曝光处理的结构示意图。图6为本申请实施例提供的半导体结构的牺牲层的中空腔体的内侧壁面上形成凹凸不平结构的结构示意图。图7为本申请实施例提供的半导体结构的牺牲层的中空腔体的内侧壁面上形成第一电极层的结构示意图。图8为本申请实施例提供的半导体结构的第一电极层在衬底上的结构示意图。图9为本申请实施例提供的半导体结构的第一电极层的表面形成电介质层的结构示意图。图10为本申请实施例提供的半导体结构的结构示意图。图11为本申请实施例提供的半导体结构的第二电极层在衬底上的结构示意图。图12为本申请实施例提供的半导体结构与有源区以及公共电极层连接的结构示意图。图13为本申请实施例提供的图12中I部分的局部结构示意图。图14为本申请实施例提供的图10中A-A截面的结构示意图。图15为本申请实施例提供的半导体结构的制备方法的流程示意图。图16为本申请实施例提供的半导体结构的制备方法的牺牲层的中空腔体内侧壁面上形成凹凸不平的结构的流程示意图。图17为本申请实施例提供的半导体结构的制备方法的处理中空腔体内侧壁面的流程示意图；图18为本申请实施例提供的半导体器件的结构示意图。
参照图2至图18所示，本申请实施例提供一种半导体结构100，包括：
衬底10，其包括有源区11。第一电极层20，其设置于衬底10上，且电连接至有源区11，第一电极层20沿垂直于衬底10的方向延伸。电介质层30，其设置于第一电极层20的表面。第二电极层40，其设置于电介质层30的表面。
其中，第一电极层20的表面和电介质层30的表面均设置有凹凸不平的结构。
需要说明的是，本实施例提供的半导体结构100可以为半导体器件中的电容，该半导体器件可以为动态随机存取存储器。其中，本实施例中的衬底10可以为单晶硅、多晶硅、无定型硅、硅锗化合物或绝缘体上硅(silicon-on-insulator，简称为SOI)等，或者本领域技术人员已知的其他材料，该衬底10可以为衬底10上的其余结构层提供支撑基础。衬底10中存在半导体层，半导体层可以通过掺杂形成，根据掺杂粒子的类型不同，可以 将掺杂后的半导体层分为N型和P型。其中，半导体层中会形成有源区11，该有源区11可以包括源极区和漏极区，源极区和漏极区之间通过沟道区连接，当沟道区中存在导通电流时，有源区11的源极区和漏极区电连接。该衬底10还可以是一个更宽泛的概念，例如衬底10还可以包括接触焊盘(Landing PAD)、接触插塞(Storage Node Contact)、介质层、有源区11(Active Area)等，接触插塞贯穿介质层，接触焊盘通过接触插塞与有源区11电连接，第一电极层20通过接触焊盘和接触插塞电连接至有源区11。
其中，结合图18所示，第一电极层20设置在衬底10上，并与有源区11电连接，其可以与有源区11的源极区或漏极区电连接。具体的，第一电极层20与有源区11之间设置有电接触部202，第一电极层20通过电接触部202与有源区11电连接。
基于该半导体结构100应用在半导体器件中，衬底10与第一电极层20之间并非直接接触，两者之间会设置其余层结构，因此可以利用电接触部202实现两者的连接。电接触部202的一端与第一电极层20电连接，电接触部202的另一端穿过衬底10与第一电极层20之间的其余层结构后，与衬底10中的有源区11电连接。该电接触部202可以为接触插塞(Node Contact)，这样的设置可以减小半导体结构100中第一电极层20与有源区11的电连接设置的难度，便于半导体结构100中的电信号存取过程。参照图8所示，第一电极层20可以为设置在衬底10上的圆筒状结构，第一电极层20的表面上形成有凹凸不平的结构，该第一电极层20的表面可以是圆筒状的第一电极层20的内壁面和外壁面。
参照图9所示，电介质层30位于第一电极层20的表面，其可以包覆在第一电极层20的内壁面和外壁面上，并且包覆在第一电极层20远离衬底10一侧的端部上。基于第一电极层20的凹凸不平的结构，因此电介质层30形成有与第一电极层20的凹凸不平的结构相适配的凹凸不平的结构。此处的“相适配”可以是指第一电极层20和电介质层30的凹凸不平的结构相同，且凹陷位置与凸起位置相对应，凹陷深度或者凸起深度可以相等。电介质层30的表面形成凹凸不平的结构可以是指电介质层30靠近第一电极层20一侧的表面以及远离第一电极层20一侧的表面。
进一步地，电介质层30位于第一电极层20和第二电极层40之间，可以选用高介电常数的材料制备，电介质层30可以阻断第一电极层20和第二电极层40之间自由电荷的移动。该电介质层30的材料可以包括氧化铪、氧化锆和锆铝氧化物中的一种或多种混合，在实际使用中，用户可以根据需要调整电介质层30的材料，本实施例对此并不加以限制。
参照图10所示，在电介质层30上还可以设置第二电极层40，第二电极层40可以包裹在电介质层30的外部，基于电介质层30靠近第二电极层40一侧的表面上具有凹凸不平的结构，因此与之相对应地，第二电极层40靠近电介质层30一侧的表面上会形成相适配的凹凸不平的结构。
需要指出的是，基于第一电极层20和第二电极层40上均具有凹凸不平的结构，因此相比于相关技术中，电容的上极板4和下极板2均为平面结构，本实施例的凹凸不平的结构可以有效增加单位区域内第一电极层20和第二电极层40的表面积，并且增加单位区域内电介质层30的表面积，因此提升该半导体结构100中所存储的电荷量。其中，表面积的增加程度可以与凹凸不平结构的凹凸程度相关，在一定范围内，通过增大凹凸不平的结构的凹凸程度可以提高表面积的增加量，从而提升半导体结构100的电容量。
具体的，结合图12和图13所示，第一电极层20靠近电介质层30一侧的表面上设置有多个第一凸起部21和多个第一凹陷部22，第一凸起部21和第一凹陷部22分别位于基准面23的相对两侧，第一凸起部21和第一凹陷部22相互交错且依次首尾连接。
第一电极层20为圆筒状，第一电极层20具有中轴线25，基准面23垂直于衬底10，基准面23至中轴线25之间的距离是第一凸起部21至中轴线25的距离与第一凹陷部22至中轴线25的距离的平均值。
需要说明的是，第一电极层20的中轴线25可以是圆筒状结构的中心轴线，基准面23与中轴线25之间的距离可以是图13中a示出的部分。基于第一电极层20为圆筒状结构，因此基准面23的三维结构也可以为圆筒状。第一凸起部21可以朝基准面23的一侧凸起，第一凹陷部22可以朝基准面23的另一侧凹陷，两者分别位于基准面23的相对两侧。第一凸起部21至中轴线25的距离可以是指第一凸起部21弯曲度最大处与中轴线25之间的距离，第一凹陷部22至中轴线25的距离同样可以是第一凹陷部22弯曲度最大处与中轴线25之间的距离，这两个距离的平均值可为a。
具体的，继续参照图12和图13所示，电介质层30为凹凸结构，电介质层30包括多个第一弯曲部31和多个第二弯曲部32，第一弯曲部31和第二弯曲部32分别位于第一中性面33的相对两侧且弯曲方向相反，第一弯曲部31和第二弯曲部32相互交错且依次首尾连接。第一中性面33垂直于衬底10，第一中性面33与基准面23之间的距离是第一弯曲部31至基准面23的距离与第二弯曲部32至基准面23的距离的平均值。
需要说明的是，第一中性面33与基准面23之间的距离可以是图13中b示出的部分，第一弯曲部31可以朝第一中性面33一侧弯曲，第二弯曲部32可以朝第一中性面33的另一侧弯曲，使得第一弯曲部31和第二弯曲部32分别位于第一中性面33的相对两侧。其中，第一弯曲部31与基准面23之间的距离可以是指第一弯曲部31上弯曲度最大处与基准面23之间的距离，第二弯曲部32与基准面23之间的距离可以是指第二弯曲部32与基准面23之间的距离，这两个距离的平均值可以是b。
具体的，继续参照图12和图13所示，第二电极层40靠近电介质层30一侧的表面上设置有多个第二凸起部41和多个第二凹陷部42，第二凸起部41和第二凹陷部42分别位于第二中性面43的相对两侧，第二凸起部41和第二凹陷部42相互交错且依次首尾连接。第二中性面43垂直于衬底10，第二中性面43与基准面23之间的距离是第二凸起部41至基准面23的距离与第二凹陷部42至基准面23的距离的平均值。
需要说明的是，第二中性面43与基准面23之间的距离可以是图13中c示出的部分，第二凸起部41可以朝第二中性面43的一侧凸起，第二凹陷部42可以朝第二中性面43的另一侧凹陷，使得第二凸起部41和第二凹陷部42分别位于第二中性面43的相对两侧。其中，第二凸起部41与基准面23之间的距离可以是指第二凸起部41的弯曲度最大处与基准面23之间的距离，第二凹陷部42与基准面23之间的距离可以是指第二凹陷部42的弯曲度最大处与基准面23之间的距离，这两个距离的平均值可以为c。
其中，第一弯曲部31、第二弯曲部32、第一凸起部21、第一凹陷部22、第二凸起部41和第二凹陷部42均为圆弧状或半球状。需要说明的是，圆弧状或者半球状可以保证第一电极层20、电介质层30以及第二电极层40中均不存在拐角结构，拐角结构中存在角度较小的夹角或尖角位置，导致此处的位置容置产生电荷聚集，降低了电荷在第一 电极层20和第二电极层40之间的分布均匀性，同时也会导致半导体结构100中出线漏电流的问题。
进一步地，第一弯曲部31、第一凸起部21以及第二凸起部41均为朝同一方向弯曲的部分，其弯曲度可以相同，三者依次嵌合。同理地，第二弯曲部32、第一凹陷部22和第二凹陷部42可以均朝同一方向弯曲，三者弯曲度可以相同，且依次嵌合，这样的设置可以提高第一电极层20，电介质层30和第二电极层40三者结构上的匹配度，从而提高半导体结构100的结构稳定性。并且，需要指出的是，相比于相关技术中，平面结构的上极板4、介电层3和下极板2而言，基于第一电极层20，电介质层30和第二电极层40三者均存在弯曲的部分，因此在平行于衬底10的方向上，三者的厚度有所增加，可以增加稳定性，防止发生电容中倾倒接触的问题。
结合图10和图14所示，第一电极层20在衬底10上的投影为第一环形24，电介质层30在衬底10上的投影包括第二环形34和第三环形35，第二环形34套在第一环形24的内侧，第三环形35套在第一环形24的外侧。第二电极层40在衬底10上的投影包括实心部44和第四环形45，实心部44位于第二环形34的内侧，第四环形45套设在第三环形35的外侧。
需要说明的是，第一电极层20、电介质层30和第二电极层40可以形成层层套叠的结构，这样可以增加半导体结构100中第一电极层20和第二电极层40的对应面积，从而增加电荷存储区域，提高电荷存储量。并且，层层套叠的结构，可以利用外层结构对内层结构进行限位和固定，从而提高该半导体结构100的结构稳定性。
其中，第二电极层40的第四环形45是第二电极层40的内壁面在衬底10上投影形成的，第二电极层40的外部结构可以根据半导体器件中的结构设置，此处不加限制。第二电极层40的实心部44可以为图14中示出的圆柱状，在实际使用中，其还可以是多边形柱状结构，本实施例对该实心部44的具体形状并不加以限制。
需要指出的是，本实施例中，第一电极层20、电介质层30以及第二电极层40在衬底10上的投影特指图10中A-A截面处的部分在衬底10上的投影。
参照图12所示，第二电极层40的远离衬底10一侧设置有公共电极层50，第二电极层40电连接至公共电极层50。这样的设置可以减小半导体结构100中第二电极层40的电连接设置的难度，便于半导体结构100中的电信号存取过程。
作为一种可实现的实施方式，第一电极层20的材料包括钨、钛、镍、钴、氮化钛和氮化钨中的一种或多种的混合，在实际使用中，用户可以根据需要调整第一电极层20的具体材料，本实施例对此并不加以限制。
作为一种可实现的实施方式，第二电极层40的材料包括硅、锗、硅锗化合物、钨、钛、镍、钴、氮化钛和氮化钨中的一种或多种的混合，在实际使用中，用户可以根据需要调整第二电极层40的具体材料，本实施例对此并不加以限制。
参照图15至图17所示，同时结合图2至图14所示，在上述的基础上，本申请实施例还提供一种半导体结构的制备方法，该方法可以用于制备上述的半导体结构100。具体的，该半导体结构的制备方法包括：
S1：提供衬底，衬底具有有源区。
需要说明的是，该衬底10可以为后续的牺牲层60和半导体结构100提供结构基础， 衬底10的材料和有源区11形成方式在上述半导体结构100中写明，此处不再赘述。
S2：形成具有中空腔体的牺牲层，牺牲层位于衬底上，中空腔体的内侧壁面上具有凹凸不平的结构。
需要说明的是，在该S2中，具体可以包括：
S21：形成牺牲层，牺牲层位于衬底上，牺牲层与衬底的材料不同。
其中，参考图2，该牺牲层60可以选用沉积的方式形成在衬底10上，牺牲层60的材料可以与衬底10不同，便于后续在牺牲层60中形成中空腔体61。
S22：刻蚀牺牲层，在牺牲层中形成柱状的中空腔体。
其中，参考图3，刻蚀可以选用干法刻蚀，或者选用湿法刻蚀，例如化学液体刻蚀，基于牺牲层60和衬底10的材料不同，可以选用选择性刻蚀牺牲层60的化学液体对其进行刻蚀，衬底10即为牺牲层60刻蚀过程中的刻蚀停止层。柱状中空腔体61的内径可以根据需要设定，本实施例对此并不加以限制。
S23：处理中空腔体的内侧壁面，在中空腔体的内侧壁面上形成凹凸不平的结构。在该步骤中，具体可以包括：
S231：形成光刻胶层，光刻胶层填充满空腔体内部。
需要说明的是，该光刻胶层70可以通过沉积或者旋涂的方式形成，光刻胶层70可以选用感光材料制成，感光材料可以包括但不限于聚甲基丙烯酸甲酯、聚甲基戊二酰亚胺以及酚醛树脂。其中，该感光材料可以填充中空腔体，从而形成填满该中空腔体61的实心结构，从而形成该光刻胶层70。
S232：曝光光刻胶层，在光刻胶层上形成凹凸不平的结构。
参考图5，需要说明的是，此处曝光光刻胶层70，可以利用一步曝光和一步显影，例如选用紫外光(UV)、深紫外光(DUV)以及极紫外光(EUV)等进行一步曝光，然后再经过显影可以得到凹凸不平结构的光刻胶层70。紫外光在照射光刻胶层70时，受到驻波效应的影响，会在光刻胶层70靠近牺牲层60的侧壁的表面形成凹凸不平的结构。在光刻胶层70和牺牲层60的界面处，光线会被反射，这些反射光和入射光会形成干涉，使得光强沿着光刻胶层70的深度方向分布不均匀，从而形成凹凸不平的结构。基于经过曝光处理的光刻胶层70的物理化学特性发生变化，继而通过刻蚀的方式可以将特性发生变化的部分光刻胶层70去除，从而形成凹凸不平的光刻胶层70。
S233：刻蚀中空腔体的内侧壁面，在中空腔体的内侧壁面上形成与光刻胶层相同的凹凸不平的结构。
参考图6，需要说明的是，可以选用干法刻蚀的方式，沿着光刻胶层70的凹凸不平的结构对中空腔体61的内壁面进行刻蚀，从而在中空腔体61的内侧壁面上形成相同的凹凸不平的结构。即，将凹凸不平的结构从光刻胶层70转移到牺牲层60上。
S3：形成第一电极层，第一电极层位于中空腔体的内侧壁面上，第一电极层的表面具有凹凸不平的结构，第一电极层电连接至有源区。
参考图7，需要说明的是，第一电极层20可以选用沉积的方式形成在中空腔体61的内侧壁面上，基于中空腔体61的内侧壁面上具有凹凸不平的结构，因此在沉积第一电极层20时，第一电极层20的材料可以沿着凹凸不平的结构分布，从而在第一电极层20上形成与该凹凸不平的结构相同的结构。
其中，第一电极层20的厚度可以为5-30nm，例如，第一电极层20的厚度可以为10nm、15nm以及25nm等。在实际使用中，用户可以根据半导体结构100的整体结构在上述范围内调整第一电极层20的具体厚度值。
S4：去除牺牲层。
参考图8，需要说明的是，在沉积第一电极层20后，需要继续形成电介质层30和第二电极层40，因此需要去除牺牲层60，避免牺牲层60对后续层结构的影响。牺牲层60可以选用液体刻蚀的方式去除。
S5：形成电介质层，电介质层位于第一电极层的表面。
具体可以参考图9。
S6：形成第二电极层，第二电极层位于电介质层的表面。
参考图10，需要说明的是，基于第一电极层20上具有凹凸不平的结构，因此在第一电极层20上形成的电介质层30和第二电极层40均会沿着该凹凸不平的结构分布，从而形成相对应的凹凸不平的结构。电介质层30和第二电极层40的厚度可以均为5-30nm，在实际使用中，用户可以根据半导体结构100的整体结构在上述范围内调整电介质层30和第二电极层40的具体厚度值。
本申请实施例提供的半导体结构的制备方法，通过设置衬底10，并在衬底10中形成有源区11，便于为后续的半导体结构100提供结构基础。通过在衬底10上形成具有中空腔体61的牺牲层60，并且在中空腔体61的内侧壁面上设置第一电极层20，利用中空腔体61内侧壁面上的凹凸不平的结构，在第一电极层20的表面形成相同的凹凸不平的结构。并且，将第一电极层20电连接至有源区11，便于有源区11中的源极或漏极与第一电极层20之间的电信号传输，通过在第一电极层20的表面设置电介质层30，并在电介质层30的表面形成第二电极层40，利用第一电极层20、电介质层30和第二电极层40形成半导体结构100的电容结构。第一电极层20的表面和电介质层30的表面的凹凸不平结构，有助于增加电容结构中电极的表面积，从而提高半导体结构100的电容量。
进一步地，在上述的基础上，参照图18所示，本申请实施例还提供一种半导体器件200，包括衬底10、晶体管、位线、字线201和上述的半导体结构100。
晶体管的栅极与字线201连接，晶体管的源极和漏极形成在衬底10的有源区11中，晶体管的漏极与位线连接，晶体管的源极通过电接触部202与半导体结构100的第一电极层20连接。
需要说明的是，衬底10和半导体结构100之间存在多层结构，图2至图12中仅示出了半导体结构100和衬底10的相对位置关系，半导体结构100并非直接与衬底10接触。具体的，衬底10中形成有埋入式的字线201，位线和字线201可以交叉设置，即两者的延伸方向相互交错。其中，字线201的外部形成有栅极氧化层206，字线201远离衬底10的一侧上设置有绝缘层207，字线201与晶体管的栅极电连接。相邻的字线201之间形成有浅沟道隔离203，以将字线201分隔开。相邻的浅沟道隔离203之间形成有掺杂层，掺杂层通过掺杂不同的粒子，形成有源区11中的源极区204或者漏极区205。
其中，源极区204与第一电极层20通过电接触部202电连接，漏极区205与位线电连接。该电接触部202可以属于衬底10的一部分。在字线201上方形成有半导体结构100，该半导体结构100呈阵列排布，相邻的半导体结构100之间形成有层间介质层208， 以隔绝相邻的半导体结构100。每个半导体结构100对应一个晶体管结构设置，半导体结构100中的第一电极层20可以通过电接触部202电连接至有源区11的源极区。
该半导体器件200可以包括多个存储单元，每个存储单元中均包括有晶体管和半导体结构100。半导体结构100可以用于存储数据，而晶体管可以控制半导体结构100对数据的存取。字线201上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在半导体结构100中的数据信息，或者通过位线将数据信息写入到半导体结构100中进行存储，实现该半导体器件200的数据存取，因此当本实施例的上述的半导体结构100应用在该半导体器件200中，可以提升半导体器件200的存取性能。
在上述描述中，需要理解的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以使固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。术语“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或者位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或者暗示所指的装置或者元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。在本申请的描述中，“多个”的含义是两个或两个以上，除非是另有精确具体地规定。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构，包括：
    衬底，其包括有源区；
    第一电极层，其设置于所述衬底上，且电连接至所述有源区，所述第一电极层沿垂直于所述衬底的方向延伸；
    电介质层，其设置于所述第一电极层的表面；
    第二电极层，其设置于所述电介质层的表面；
    其中，所述第一电极层的表面和所述电介质层的表面均设置有凹凸不平的结构。
  2. 根据权利要求1所述的半导体结构，其中，所述第一电极层靠近所述电介质层一侧的表面上设置有多个第一凸起部和多个第一凹陷部，所述第一凸起部和所述第一凹陷部分别位于基准面的相对两侧，所述第一凸起部和所述第一凹陷部相互交错且依次首尾连接；
    所述第一电极层为圆筒状，所述第一电极层具有中轴线，所述基准面垂直于所述衬底，所述基准面至所述中轴线之间的距离是所述第一凸起部至所述中轴线的距离与所述第一凹陷部至所述中轴线的距离的平均值。
  3. 根据权利要求2所述的半导体结构，其中，所述电介质层为凹凸结构，所述电介质层包括多个第一弯曲部和多个第二弯曲部，所述第一弯曲部和所述第二弯曲部分别位于第一中性面的相对两侧且弯曲方向相反，所述第一弯曲部和所述第二弯曲部相互交错且依次首尾连接；
    所述第一中性面垂直于所述衬底，所述第一中性面与所述基准面之间的距离是所述第一弯曲部至所述基准面的距离与所述第二弯曲部至所述基准面的距离的平均值。
  4. 根据权利要求3所述的半导体结构，其中，所述第二电极层靠近所述电介质层一侧的表面上设置有多个第二凸起部和多个第二凹陷部，所述第二凸起部和所述第二凹陷部分别位于第二中性面的相对两侧，所述第二凸起部和所述第二凹陷部相互交错且依次首尾连接；
    所述第二中性面垂直于所述衬底，所述第二中性面与所述基准面之间的距离是所述第二凸起部至所述基准面的距离与所述第二凹陷部至所述基准面的距离的平均值。
  5. 根据权利要求4所述的半导体结构，其中，所述第一弯曲部、所述第二弯曲部、所述第一凸起部、所述第一凹陷部、所述第二凸起部和所述第二凹陷部均为圆弧状或半球状。
  6. 根据权利要求1-5中任一项所述的半导体结构，其中，所述第一电极层在所述衬底上的投影为第一环形，所述电介质层在所述衬底上的投影包括第二环形和第三环形，所述第二环形套在所述第一环形的内侧，所述第三环形套在 所述第一环形的外侧；
    所述第二电极层在所述衬底上的投影包括实心部和第四环形，所述实心部位于所述第二环形的内侧，所述第四环形套设在所述第三环形的外侧。
  7. 根据权利要求1-5中任一项所述的半导体结构，其中，所述第一电极层与所述有源区之间设置有电接触部，所述第一电极层通过所述电接触部与所述有源区电连接。
  8. 根据权利要求1-5中任一项所述的半导体结构，其中，所述第二电极层的远离所述衬底一侧设置有公共电极层，所述第二电极层电连接至所述公共电极层。
  9. 根据权利要求1-5中任一项所述的半导体结构，其中，所述第一电极层的材料包括钨、钛、镍、钴、氮化钛和氮化钨中的一种或多种的混合。
  10. 根据权利要求1-5中任一项所述的半导体结构，其中，所述第二电极层的材料包括硅、锗、硅锗化合物、钨、钛、镍、钴、氮化钛和氮化钨中的一种或多种的混合。
  11. 根据权利要求1-5中任一项所述的半导体结构，其中，所述电介质层的材料包括氧化铪、氧化锆和锆铝氧化物中的一种或多种混合。
  12. 一种半导体结构的制备方法，其中，包括：
    提供衬底，所述衬底具有有源区；
    形成具有中空腔体的牺牲层，所述牺牲层位于所述衬底上，所述中空腔体的内侧壁面上具有凹凸不平的结构；
    形成第一电极层，所述第一电极层位于所述中空腔体的内侧壁面上，所述第一电极层的表面具有凹凸不平的结构，所述第一电极层电连接至所述有源区；
    去除所述牺牲层；
    形成电介质层，所述电介质层位于所述第一电极层的表面；
    形成第二电极层，所述第二电极层位于所述电介质层的表面。
  13. 根据权利要求12所述的半导体结构的制备方法，其中，在所述形成具有中空腔体的牺牲层，所述牺牲层位于所述衬底上，所述中空腔体的内侧壁面上具有凹凸不平的结构的步骤中，具体包括：
    形成牺牲层，所述牺牲层位于所述衬底上，所述牺牲层与所述衬底的材料不同；
    刻蚀所述牺牲层，在所述牺牲层中形成柱状的中空腔体；
    处理所述中空腔体的内侧壁面，在所述中空腔体的内侧壁面上形成凹凸不平的结构。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，在所述处理所述中空腔体的内侧壁面，在所述中空腔体的内侧壁面上形成凹凸不平的结构的步骤中，具体包括：
    形成光刻胶层，所述光刻胶层位于所述中空腔体的内侧壁面上；
    曝光所述光刻胶层，在所述光刻胶层上形成凹凸不平的结构；
    刻蚀所述中空腔体的内侧壁面，在所述中空腔体的内侧壁面上形成与所述光刻胶层相同的凹凸不平的结构。
  15. 一种半导体器件，其中，包括衬底、晶体管、位线、字线和如权利要求1-11中任一项所述的半导体结构；
    所述位线设置在所述衬底上，所述字线交错设置在所述位线上，所述晶体管的栅极与所述字线连接，所述晶体管的源极和漏极形成在所述衬底的有源区中，所述晶体管的漏极与所述位线连接，所述晶体管的源极与所述半导体结构的第一电极层连接。
PCT/CN2021/100192 2021-01-25 2021-06-15 半导体结构及其制备方法、半导体器件 Ceased WO2022156130A1 (zh)

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