WO2022151919A1 - 气密性射频mems器件的制作方法及气密性射频mems器件 - Google Patents

气密性射频mems器件的制作方法及气密性射频mems器件 Download PDF

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WO2022151919A1
WO2022151919A1 PCT/CN2021/139235 CN2021139235W WO2022151919A1 WO 2022151919 A1 WO2022151919 A1 WO 2022151919A1 CN 2021139235 W CN2021139235 W CN 2021139235W WO 2022151919 A1 WO2022151919 A1 WO 2022151919A1
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layer
sio
dielectric layer
radio frequency
intermediate product
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PCT/CN2021/139235
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English (en)
French (fr)
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刘泽文
张玉龙
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清华大学
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components

Definitions

  • the invention relates to the technical field of air-tight radio frequency MEMS devices, in particular to a manufacturing method of an air-tight radio frequency MEMS device and an air-tight radio frequency MEMS device.
  • Radio frequency micro-electromechanical systems is one of the important application fields of MEMS technology, and it is also a research hotspot in the field of MEMS since the 1990s.
  • RF MEMS devices have excellent microwave performance such as high isolation, low loss, high linearity, low power consumption, and wide frequency band, as well as small size and easy integration.
  • RF MEMS are used for signal processing in RF and microwave frequency circuits and are a technology that will have a significant impact on the RF architecture of existing radar and communications.
  • RF MEMS itself has a special structure that is incomparable to traditional ICs, the requirements for packaging form and reliability are more stringent.
  • RF MEMS devices with high-reliability packaging structures have become one of the key areas of current MEMS research.
  • At least one metal is used as a thin structural material in RF MEMS devices, so the packaging of RF devices must be low-temperature packaging to avoid the influence of high temperature on the structure; RF MEMS devices contain movable Cantilever beam or double-ended fixed beam structure is susceptible to adhesion failure due to the influence of water vapor and some impurities in the external environment, so the packaging of RF MEMS chips must be hermetically sealed.
  • gold-silicon, silicon-silicon melting, anodic bonding and other packaging forms with a bonding temperature >300° C. are not suitable for radio frequency MEMS devices.
  • the organic adhesive bonding packaging process can realize low temperature packaging and lateral interconnection of leads, but the air tightness of organic material packaging is much lower than that of metal packaging; although metal packaging can ensure the strength and air tightness of the packaging, but
  • the lateral interconnection signal extraction of the leads cannot be realized, and a through-hole signal extraction process must be used, and the through-holes located in the cavity also increase the probability of air leakage.
  • the introduction of the package top cover and the metal package sealing ring will bring additional parasitic effects to the RF signal transmission line, affecting the RF performance of the device.
  • the designer actively researches and innovates, in order to create a method for manufacturing a radio frequency MEMS device with a hermetic package structure, so that it has more industrial application value.
  • an object of the present invention is to propose a method for manufacturing an airtight radio frequency MEMS device.
  • the fabricated airtight radio frequency MEMS device has reliable structure, good airtightness, good radio frequency performance, low parasitic effect and high production efficiency. , the production cost is low, and it is suitable for mass production.
  • S1 Process a TGV filled via structure on the substrate wafer to form a first intermediate product
  • S3 depositing and growing a second SiO 2 dielectric layer on the upper surface of the second intermediate product, and processing an interlayer interconnecting via structure in the second SiO 2 dielectric layer, and the interlayer interconnecting through holes the structure is electrically connected to the first pad to form a third intermediate product;
  • S6 deposit a sacrificial layer on the upper surface of the fifth intermediate product, process a bonding ring in the sacrificial layer, the bottom of the bonding ring is fixed with the fourth SiO 2 dielectric layer, Anchor points are processed in the sacrificial layer, the fourth SiO 2 dielectric layer, the third SiO 2 dielectric layer and the second SiO 2 dielectric layer, and the bottom of the anchor point is electrically connected to another transmission line. connection, an upper electrode plate is processed on the upper surface of the sacrificial layer, the upper electrode plate is electrically connected to the top of the anchor point, and the anchor point, the upper electrode plate and the contact bump are within the bond ring, thereby forming the sixth intermediate product piece;
  • S8 Make a package cover plate, the bottom surface of the package cover plate has a package inner cavity, and the upper side of the package cover plate and the lower side of the package cover plate except for the package inner cavity have masking layers, so A bonding sealing ring is arranged on the masking layer on the lower side of the package cover plate, and the package inner cavity is located in the bonding sealing ring;
  • the manufacturing method of the air-tight radio frequency MEMS device has the following advantages: first, the transmission line (such as the coplanar waveguide transmission line) is led out of the package cavity in combination with the rewiring process, so as to realize the TGV filling.
  • the solid through-hole structure is external, which greatly improves the airtightness of the airtight radio frequency MEMS device, which is beneficial to improve the reliability of the airtight radio frequency MEMS device.
  • the introduction of the bonding sealing ring on the packaging cover plate can be guaranteed, but at the same time, it will bring additional parasitic effects to the RF signal transmission line and affect the radio frequency performance of the device; by setting the second SiO 2 dielectric layer, the third SiO 2 dielectric layer, and the fourth SiO 2 dielectric layer It can not only thicken the thickness of the dielectric layer between the transmission line and the bonding ring, but also reduce the distance between the pull-down electrode and the upper plate (ie, the cantilever beam), and reduce the pull-down voltage.
  • the bonding ring of the fifth intermediate product is aligned with the bonding sealing ring of the package cover plate for wafer-level metal bonding, which can provide good air tightness While completing the airtight packaging, it avoids the influence of high temperature packaging on the structure of airtight RF MEMS devices;
  • the packaging method is wafer level packaging, which is suitable for mass production of airtight RF MEMS devices. Improve production efficiency and reduce production costs.
  • the upper surface of the first intermediate product piece, the upper surface of the second intermediate product piece, the upper surface of the third intermediate product piece and the fourth intermediate product is a polished flat surface.
  • the specific processing step of the TGV filling the through hole structure is: after the through hole is made on the substrate wafer, the through hole is A metal conductive layer is plated on the inner peripheral wall of the metal conductive layer, and then an insulating medium is filled in the first through hole that has been plated with the metal conductive layer, so as to process the TGV filled through hole structure, or in the through hole The conductive metal is completely filled, thereby processing the TGV filled via structure.
  • the processing of the transmission line and the first pad in the first SiO 2 dielectric layer specifically includes the following steps: in the first The transmission line pattern cavity and the first pad pattern cavity (photolithography and etching) exposing the substrate wafer are first processed in the SiO 2 dielectric layer; A first metal adhesion layer and a first metal circuit layer are sequentially deposited and grown in the pattern cavity, and the first metal adhesion layer is used for fixing the first metal circuit layer.
  • the processing of the interlayer interconnection via structure in the second SiO 2 dielectric layer specifically includes the following steps: in the second SiO 2 dielectric layer 2.
  • the interlayer interconnecting via pattern cavity is first processed in the dielectric layer, and then a second metal adhesion layer and a second metal circuit layer are sequentially deposited and grown in the interlayer interconnection via pattern cavity.
  • the adhesive layer is used for fixing the second metal circuit layer.
  • processing the pull-down electrode and the second pad in the third SiO 2 dielectric layer specifically includes the following steps: in the third SiO 2 dielectric layer
  • the pull-down electrode pattern cavity and the second pad pattern cavity are first processed in the SiO 2 dielectric layer, and then the third metal adhesion layer and the second pad pattern cavity are deposited and grown respectively in the pull-down electrode pattern cavity and the second pad pattern cavity.
  • the third metal circuit layer in the third SiO 2 dielectric layer.
  • the fourth SiO 2 dielectric layer, the third SiO 2 dielectric layer and the second SiO 2 dielectric layer are processed first
  • Making contact bumps specifically includes the following steps: processing a contact bump pattern cavity in the fourth SiO 2 dielectric layer, the third SiO 2 dielectric layer and the second SiO 2 dielectric layer; A fourth metal adhesion layer and a metal bump layer are sequentially deposited and grown at the contact bump pattern cavity, and the metal bump layer is processed to form the contact bump.
  • the processing of the bonding ring in the sacrificial layer specifically includes the following steps: first processing the bonding ring pattern in the sacrificial layer cavity, and then the bonding ring is fabricated in the bonding ring pattern cavity.
  • the processing of anchor points in the dielectric layer specifically includes the following steps: firstly processing anchor points in the sacrificial layer, the fourth SiO 2 dielectric layer, the third SiO 2 dielectric layer and the second SiO 2 dielectric layer point pattern cavity, and then make anchor points in the anchor point pattern cavity.
  • the sacrificial layer is an organic sacrificial layer or an inorganic sacrificial layer.
  • the release of the sacrificial layer adopts a dry release method or a wet release method.
  • the manufacturing method of the package cover plate is as follows: simultaneously depositing the masking layer on the upper side and the lower side of the high-resistance silicon wafer, patterning the masking layer on the lower side, and the encapsulation cavity is etched in the masking layer on the lower side and the high-resistance silicon wafer.
  • the bonding sealing ring is made by depositing a fifth metal adhesion layer and a metal bonding layer respectively, and the fifth metal adhesion layer is used for bonding the The metal bonding layer is fixed.
  • the second aspect of the present invention also provides an airtight radio frequency MEMS device.
  • the airtight radio frequency MEMS device is manufactured by using the manufacturing method of the airtight radio frequency MEMS device according to any one of the embodiments of the first aspect of the present invention .
  • FIG. 1 is a schematic diagram of the first process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.
  • FIG. 2 is a schematic diagram of the second process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.
  • FIG. 3 is a schematic diagram of a third process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.
  • FIG. 4 is a schematic diagram of a fourth process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.
  • FIG. 5 is a schematic diagram of the fifth process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.
  • FIG. 6 is a schematic diagram of the sixth process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.
  • FIG. 7 is a schematic diagram of the seventh process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram of the airtight radio frequency MEMS device of the present invention.
  • the first SiO 2 dielectric layer 3 The transmission line 4 The first pad 5
  • the fourth SiO 2 dielectric layer 11 contacts the bumps 12
  • the manufacturing method of the airtight radio frequency MEMS device 1000 includes the following steps:
  • a first SiO2 dielectric layer 3 is deposited and grown on the upper surface of the first intermediate product, and a transmission line 4 and a first pad 5 are processed in the first SiO2 dielectric layer 3, The transmission line 4 and the first pad 5 are respectively electrically connected to the corresponding TGV filled via structure 2, thereby forming a second intermediate product;
  • a second SiO 2 dielectric layer 6 is deposited and grown on the upper surface of the second intermediate product, and an interlayer interconnection via structure 7 is processed in the second SiO 2 dielectric layer 6 .
  • the interconnecting via structure 7 is electrically connected to the first pad 5, thereby forming a third intermediate product;
  • a third SiO2 dielectric layer 8 is deposited and grown on the upper surface of the third intermediate product, and a pull-down electrode 9 and a second pad 10 are processed in the third SiO2 dielectric layer 8, The second pad 10 is electrically connected to the interlayer interconnect via structure 7, thereby forming a fourth intermediate product;
  • a fourth SiO2 dielectric layer 11 is deposited and grown on the upper surface of the fourth intermediate product, and the fourth SiO2 dielectric layer 11, the third SiO2 dielectric layer 8 and the Contact bumps 12 are processed in the two SiO2 dielectric layers 6, and the bottoms of the contact bumps 12 are electrically connected to a transmission line 4, thereby forming a fifth intermediate product;
  • a sacrificial layer 13 is deposited on the upper surface of the fifth intermediate product, a bonding ring 14 is processed in the sacrificial layer 13, and the bottom of the bonding ring 14 is fixed with the fourth SiO2 dielectric layer 11 ,
  • An anchor point 15 is processed in the sacrificial layer 13, the fourth SiO 2 dielectric layer 11, the third SiO 2 dielectric layer 8 and the second SiO 2 dielectric layer 6, and the bottom of the anchor point 15 is electrically connected to another transmission line 4,
  • An upper electrode plate 16 is processed on the upper surface of the sacrificial layer 13, the upper electrode plate 16 is electrically connected to the top of the anchor point 15, and the anchor point 15, the upper electrode plate 16 and the contact bump 12 are all located in the bonding ring 14, Thereby forming a sixth intermediate product piece;
  • a package cover plate 17 is fabricated.
  • the bottom surface of the package cover plate 17 has a package inner cavity 1702 , and the upper side of the package cover plate 17 and the lower side of the package cover plate 17 except for the package inner cavity 1702 are provided with
  • the masking layer 1703, the masking layer 1703 on the lower side of the package cover plate 17 is provided with a bonding sealing ring 1704, and the packaging inner cavity 1702 is located in the bonding sealing ring 1704;
  • wafer-level solder balls 18 are implanted on the lower surface of the substrate wafer 1 of the eighth intermediate product, and the eighth intermediate product is diced to obtain the final airtightness RF MEMS devices.
  • the manufacturing method of the airtight radio frequency MEMS device has the following advantages: first, the transmission line 4 (such as the coplanar waveguide transmission line 4) is led out of the package cavity 1702 in combination with the rewiring process, The realization of the TGV filled through-hole structure 2 is external, which greatly improves the air tightness of the airtight radio frequency MEMS device 1000, which is beneficial to improve the reliability of the airtight radio frequency MEMS device.
  • the transmission line 4 such as the coplanar waveguide transmission line 4
  • the realization of the TGV filled through-hole structure 2 is external, which greatly improves the air tightness of the airtight radio frequency MEMS device 1000, which is beneficial to improve the reliability of the airtight radio frequency MEMS device.
  • the keys on the packaging cover plate 17 can ensure the air tightness of the package, but at the same time it will bring additional parasitic effects to the RF signal transmission line 4 and affect the radio frequency performance of the device; by setting the second SiO 2 dielectric layer and the third SiO 2 dielectric layer layer, the fourth SiO2 dielectric layer can not only thicken the thickness of the dielectric layer between the transmission line 4 and the bonding ring 14, but also reduce the distance between the pull-down electrode 9 and the upper plate 16 (ie, the cantilever beam), reducing the The pull-down voltage, without affecting the pull-down voltage, alleviates the parasitic effect problem brought by the sealing ring of the metal package; Aligning wafer-level metal bonding can provide good air tightness.
  • Wafer-level packaging is suitable for mass production of 1000 air-tight RF MEMS devices, improving production efficiency and reducing production costs.
  • the upper surface of the first intermediate product piece, the upper surface of the second intermediate product piece, the upper surface of the third intermediate product piece and the upper surface of the fourth intermediate product piece are all polished and flat noodle.
  • the stress of the airtight radio frequency MEMS device 1000 can be reduced, the flatness of the cantilever beam (ie the upper plate 16 ) of the airtight radio frequency MEMS device 1000 can be increased, and the interlayer interconnection of the airtight radio frequency MEMS device 1000 can be improved. electrical contact properties.
  • the upper surface of the first intermediate product piece, the upper surface of the second intermediate product piece, the upper surface of the third intermediate product piece, and the upper surface of the fourth intermediate product piece are all polished flat surfaces, which can be processed by CMP (chemical Mechanical polishing) polishing process.
  • step S1 the specific processing steps of the TGV filling the through-hole structure 2 are as follows: after making through-holes on the substrate wafer 1, plating on the inner peripheral wall of the through-holes A metal conductive layer, such as a copper layer, is filled with an insulating medium in the first through hole that has been plated with the metal conductive layer, so as to process the TGV filled through hole structure 2, or all the through holes are filled with conductive metal, such as copper , thereby processing the TGV filled via structure 2 .
  • the conductivity of the TGV filled via structure 2 is achieved.
  • the substrate wafer 1 can be a glass wafer.
  • step S2 the transmission line 4 and the first pad 5 are processed in the first SiO 2 dielectric layer 3, which specifically includes the following steps: in the first SiO 2 dielectric layer 3
  • the transmission line pattern cavity and the first pad pattern cavity exposing the substrate wafer 1 are processed first; and then the first metal adhesion layer and the first pad pattern cavity are sequentially deposited and grown in the transmission line pattern cavity and the first pad pattern cavity respectively.
  • a metal circuit layer, and the first metal adhesion layer is used for fixing the first metal circuit layer. Therefore, the processing is convenient, the processed transmission line 4 and the first pad 5 are of good quality, and there is no risk of falling off.
  • the transmission line pattern cavity and the first pad pattern cavity can be obtained by photolithography and etching the first SiO 2 dielectric layer 3 to expose the substrate wafer 1 , and this processing method has good selectivity and repeatability. Good, high production efficiency and low cost.
  • step S3 the interlayer interconnection via structure 7 is processed in the second SiO 2 dielectric layer 6 , which specifically includes the following steps:
  • the inter-layer interconnecting through-hole pattern cavity is processed, and then a second metal adhesion layer and a second metal circuit layer are deposited and grown in the inter-layer interconnected through-hole pattern cavity respectively, and the second metal adhesion layer is used for fixing the second metal adhesion layer. metal wiring layer. Therefore, the processing is convenient, and the processed interlayer interconnecting via structure 7 is of good quality.
  • the interlayer interconnecting through-hole pattern cavity can be obtained by photolithography and etching the second SiO 2 dielectric layer 6 , and this processing method has good selectivity, good repeatability, high production efficiency and low cost.
  • step S4 the pull-down electrode 9 and the second pad 10 are processed in the third SiO 2 dielectric layer 8 , which specifically includes the following steps: in the third SiO 2 dielectric layer 8
  • the pull-down electrode pattern cavity and the second pad pattern cavity are processed first, and then the third metal adhesion layer and the third metal circuit layer are deposited and grown in the pull-down electrode pattern cavity and the second pad pattern cavity respectively. Therefore, the processing is convenient, and the processed pull-down electrodes 9 and the second pads 10 are of good quality.
  • the pull-down electrode pattern cavity and the second pad pattern cavity can be obtained by photolithography and etching the third SiO 2 dielectric layer 8 .
  • This processing method has good selectivity, good repeatability, high production efficiency and low cost .
  • contact bumps 12 are first processed in the fourth SiO 2 dielectric layer 11 , the third SiO 2 dielectric layer 8 and the second SiO 2 dielectric layer 6 . It includes the following steps: processing the contact bump pattern cavity in the fourth SiO 2 dielectric layer 11, the third SiO 2 medium layer 8 and the second SiO 2 medium layer 6, and then depositing and growing the contact bump pattern cavity in turn.
  • the fourth metal adhesion layer and the metal bump layer are processed to form the contact bumps 12 .
  • the contact bumps 12 can be processed, and the quality of the contact bumps 12 is good
  • the contact bump pattern cavity can be obtained by photolithography and etching the fourth SiO 2 dielectric layer 11 , the third SiO 2 dielectric layer 8 and the second SiO 2 dielectric layer 6 , and this processing method has good selectivity , Good repeatability, high production efficiency and low cost.
  • step S6 the bonding ring 14 is processed in the sacrificial layer 13, which specifically includes the following steps: first processing the bonding ring pattern cavity in the sacrificial layer, and then processing the bonding ring in the sacrificial layer. Bonded rings 14 are made in the ring pattern cavity. Therefore, the bonding ring 14 can be easily processed, and the quality of the bonding ring 14 is good
  • the bonding ring pattern cavity can be obtained by photolithography and etching the sacrificial layer 13, and this processing method has good selectivity, good repeatability, high production efficiency and low cost.
  • step S6 the anchor points 15 are processed in the sacrificial layer 13 , the fourth SiO 2 dielectric layer 11 , the third SiO 2 dielectric layer 8 and the second SiO 2 dielectric layer 6 .
  • step S6 which specifically includes the following steps: firstly process the anchor point pattern cavity in the sacrificial layer 13, the fourth SiO 2 dielectric layer 11, the third SiO 2 dielectric layer 8 and the second SiO 2 dielectric layer 6, and then process the anchor point pattern cavity in the anchor point pattern cavity.
  • Make Anchor Point 15. Therefore, the anchor point 15 can be easily processed, and the quality of the anchor point 15 is good.
  • the anchor pattern cavity can be obtained by photolithography and etching the sacrificial layer 13, the fourth SiO2 dielectric layer 11, the third SiO2 dielectric layer 8 and the second SiO2 dielectric layer 6.
  • This processing method Good selectivity, good repeatability, high production efficiency and low cost.
  • the sacrificial layer 13 is an organic sacrificial layer 13 or an inorganic sacrificial layer 13 .
  • the organic layer can be a polyimide sacrificial layer 13
  • the inorganic sacrificial layer 13 can be a silicon sacrificial layer 13 .
  • the release of the sacrificial layer 13 adopts a dry release method or a wet release method.
  • the sacrificial layer 13 is a polyimide sacrificial layer 13
  • the sacrificial layer 13 can be released by a dry method
  • the sacrificial layer 13 is a silicon sacrificial layer 13
  • the sacrificial layer 13 can be released by a wet method, which can be easily and completely removed sacrificial layer 13 .
  • the manufacturing method of the package cover plate 17 is as follows: simultaneously depositing a masking layer 1703 on the upper side and the lower side of the high-resistance silicon wafer 1701, patterning the lower side A masking layer 1703 is formed, and a package cavity 1702 is etched from the lower masking layer 1703 and the high-resistance silicon wafer 1701 . Therefore, the processing is convenient, and the packaging cover plate 17 can be processed to reduce the leakage of radio frequency signals.
  • the masking layer 1703 is a Si 3 N 4 masking layer 1703 . Therefore, the etching selection ratio is high, and the package inner cavity 1702 can be easily processed.
  • the bonding sealing ring 1704 is made by depositing a fifth metal bonding layer and a metal bonding layer respectively, and the fifth metal bonding layer is used to fix the metal bonding layer . Therefore, the processing is convenient, and the quality of the bonding ring 14 can be guaranteed.
  • the sealing bonding ring 14 is made of one, two or more combination metals of Cu/Sn, Au/Sn, Au/Sn/Cu, Ge/Al and Au/Au can be selected according to actual needs.
  • the second aspect of the present invention also provides an air-tight radio frequency MEMS device 1000 .
  • the airtight radio frequency MEMS device 1000 according to the embodiment of the second aspect of the present invention is manufactured by using the manufacturing method of the airtight radio frequency MEMS device 1000 according to any embodiment of the first aspect of the present invention.

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Abstract

一种气密性射频MEMS器件的制作方法，包括步骤：在衬底圆片（1）上加工出TGV填实通孔结构（2）；沉积生长出第一SiO 2介质层（3），加工出传输线路（4）及第一焊盘（5）；沉积生长出第二SiO 2介质层（6），加工出层间互联通孔结构（7）；沉积生长出第三SiO 2介质层（8），加工出下拉电极（9）和第二焊盘（10）；沉积生长出第四SiO 2介质层（11），加工出接触凸点（12）；沉积牺牲层（13），加工出键合环（14）、锚点（15）和上极板（16）；释放牺牲层（13）；制作封装盖板（17）；进行圆片级金属键合；进行晶圆级植锡球（18）并进行划片，得到气密性射频MEMS器件。气密性射频MEMS器件的制作方法提高了封装气密性，缓解了金属封装密封环带入的寄生效应问题，适合批量化生产，提高了生产效率。还提供了一种气密性射频MEMS器件。

Description

气密性射频MEMS器件的制作方法及气密性射频MEMS器件
相关申请的交叉引用
本申请基于申请号为：202110036541.X，申请日为2021年01月12日的中国专利申请提出，并要求该件中国专利申请的优先权，该件中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及气密性射频MEMS器件技术领域，尤其是涉及一种气密性射频MEMS器件的制作方法及气密性射频MEMS器件。
背景技术
射频微机电系统(射频MEMS)是MEMS技术的重要应用领域之一，也是二十世纪九十年代以来MEMS领域的研究热点。射频微机电系统器件具有高隔离度、低损耗、高线性度、低功耗、宽频带等优异的微波性能，同时具有尺寸小、易于集成的特点。射频MEMS用于射频和微波频率电路中的信号处理，是一项将能对现有雷达和通讯中射频结构产生重大影响的技术。然而由于射频MEMS本身具有传统IC不可比拟的特殊的结构，对封装形式及可靠性要求更为严格，具有高可靠性封装结构的射频MEMS器件成为当前MEMS研究的关键领域之一。
在射频MEMS器件中至少会用到一种金属(金或铝等)作为薄结构材料，因此对射频器件的封装必须是低温封装，以避免高温对结构的影响；射频MEMS器件中包含有可动悬臂梁或者双端固支梁结构，容易受到外界环境中水汽及一些杂质的影响而发生粘连失效，所以针对射频MEMS芯片的封装必须采用气密性密封封装。现有技术中，金-硅、硅硅熔融、阳极键合等键合温度＞300℃的封装形式均不适用于射频MEMS器件。有机粘结剂键合封装工艺可以实现低温封装及引线的横向互连，但有机材料封装的气密性相对金属封装要低很多；采用金属封装时虽然可以保证封装的强度及气密性，但现有技术中无法实现引线的横向互连信号引出，必须使用通孔信号引出工艺，而位于腔体内的通孔同样增加了漏气的几率。同时，封装上盖及金属封装密封环的引入，会给射频信号传输线带来额外的寄生效应，影响器件的射频性能。
有鉴于上述的缺陷，本设计人，积极加以研究创新，以期创设一种制造具有气密性封装结构的射频MEMS器件的制作方法，使其更具有产业上的利用价值。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一。为此，本发明的一个目的在于提出一种气密性射频MEMS器件的制作方法，制作出的气密性射频MEMS器件结构可靠，气密性好，射频性能好，寄生效应低，生产效率高，生产成本低，适于批量生产。
根据本发明第一方面实施例的气密性射频MEMS器件的制作方法，包括如下步骤：
S1：在衬底圆片上加工出TGV填实通孔结构，从而形成第一中间产品件；
S2：在所述第一中间产品件的上表面上沉积生长出第一SiO 2介质层，在所述第一SiO 2介质层中加工出传输线路及第一焊盘，所述传输线路及所述第一焊盘分别与对应的所述TGV填实通孔结构电连接，从而形成第二中间产品件；
S3：在所述第二中间产品件的上表面上沉积生长出第二SiO 2介质层，在所述第二SiO 2介质层中加工出层间互联通孔结构，所述层间互联通孔结构与所述第一焊盘电连接，从而形成第三中间产品件；
S4：在所述第三中间产品件的上表面上沉积生长出第三SiO 2介质层，在所述第三SiO 2介质层中加工出下拉电极和第二焊盘，所述第二焊盘与所述层间互联通孔结构电连接，从而形成第四中间产品件；
S5：在所述第四中间产品件的上表面上沉积生长出第四SiO 2介质层，在所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出接触凸点，所述接触凸点的底部与一个所述传输线路电连接，从而形成第五中间产品件；
S6：在所述第五中间产品件的上表面上沉积牺牲层，在所述牺牲层中加工出键合环，所述键合环的底部与所述第四SiO 2介质层固定，在所述牺牲层、所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出锚点，所述锚点的底部与另一个所述传输线路电连接，在所述牺牲层的上表面上加工出上极板，所述上极板与所述锚点的顶部电连接相连，所述锚点、所述上极板和所述接触凸点均位于所述键合环内，从而形成所述第六中间产品件；
S7：释放所述第六中间产品件中的所述牺牲层，从而形成第七中间产品件；
S8：制作封装盖板，所述封装盖板的底面具有封装内腔，所述封装盖板的上侧和所述封装盖板的下侧除去所述封装内腔的部位均具有掩蔽层，所述封装盖板的下侧的所述掩蔽层上设有键合密封环，所述封装内腔位于所述键合密封环内；
S9：将所述第七中间产品件的所述键合环与所述封装盖板的所述键合密封环对齐，进行圆片级金属键合，从而形成第八中间产品件；
S10：在所述第八中间产品件的所述衬底圆片的下表面上进行晶圆级植锡球，并对所述第八中间产品进行划片，从而得到最终的所述气密性射频MEMS器件。
根据本发明第一方面实施例的气密性射频MEMS器件的制作方法，具有如下的优点：第一、结合再布线工艺将传输线路(如共面波导传输线路)引出封装内腔，实现TGV填实通孔结构外置，大大地提高气密性射频MEMS器件的封装气密性，有利于提高气密性射频MEMS器件的可靠性；第二、封装盖板上的键合密封环的引入，可以保证封装气密性，但同时会给RF信号传输线路带来额外的寄生效应，影响器件的射频性能；通过设置第二SiO 2介质层、第三SiO 2介质层、第四SiO 2介质层既可以加厚传输线路与键合环之间的介质层厚度，又可以减小下拉电极与上极板(即悬臂梁)之间的间距，降低下拉电压，在不影响下拉电压的情况下，缓解了金属封装密封环带入的寄生效应问题；第三、将第五中间产品件的键合环与封装盖板的键合密封环对齐进行圆片级金属键合，可以提供良好的气密性，在完成气密性封装的同时，避免了高温封装对气密性射频MEMS器件结构带入的影响；第四、封装方式为圆片级封装，适合气密性射频MEMS器件批量化生产，提高生产效率，降低生产成本。
根据本发明第一方面的一个实施例，所述第一中间产品件的上表面、所述第二中间产品件的上表面、所述第三中间产品件的上表面和所述第四中间产品件的上表面均为抛光平整面。
根据本发明第一方面的一个实施例，在所述步骤S1中，所述TGV填实通孔结构的具体加工步骤为：在所述衬底圆片上制作出通孔后，在所述通孔的内周壁上镀金属导电层，再在已镀过所述金属导电层的所述第一通孔内填充绝缘介质，从而加工出所述TGV填实通孔结构，或在所述通孔内全部填实导电金属，从而加工出所述TGV填实通孔结构。
根据本发明第一方面的一个实施例，在所述步骤S2中，所述在所述第一SiO 2介质层中加工出传输线路及第一焊盘，具体包括如下步骤：在所述第一SiO 2介质层中先加工出露出所述衬底圆片的传输线路图形腔及第一焊盘图形腔(光刻并刻蚀)；再在所述传输线路图形腔及所述第一焊盘图形腔中依次分别沉积生长出第一金属粘附层和第一金属线路层，所述第一金属粘附层用于粘固所述第一金属线路层。
根据本发明第一方面的一个实施例，在所述步骤S3中，所述在所述第二SiO 2介质层中加工出层间互联通孔结构，具体包括如下步骤：在所述第二SiO 2介质层中先加工出层间互联通孔图形腔，再在所述层间互联通孔图形腔中依次分别沉积生长出第二金属粘附层和第二金属线路层，所述第二金属粘附层用于粘固所述第二金属线路层。
根据本发明第一方面的一个实施例，在所述步骤S4中，所述在所述第三SiO 2介质 层中加工出下拉电极和第二焊盘，具体包括如下步骤：在所述第三SiO 2介质层中先加工出下拉电极图形腔和第二焊盘图形腔，再在所述下拉电极图形腔和所述第二焊盘图形腔中依次分别沉积生长出第三金属粘附层和第三金属线路层。
根据本发明第一方面的一个实施例，在所述步骤S5中，所述在所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中先加工出接触凸点，具体包括如下步骤：在所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出接触凸点图形腔，再在所述接触凸点图形腔处依次分别沉积生长出第四金属粘附层和金属凸点层，对所述金属凸点层加工以形成所述接触凸点。
根据本发明第一方面的一个实施例，在所述步骤S6中，所述在所述牺牲层中加工出键合环，具体包括如下步骤：在所述牺牲层中先加工出键合环图形腔，再在所述键合环图形腔中制作出所述键合环。
根据本发明第一方面的一个实施例，在所述步骤S6中，所述在所述牺牲层、所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出锚点，具体包括如下步骤：在所述牺牲层、所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中先加工出锚点图形腔，再在所述锚点图形腔中制作出锚点。
根据本发明第一方面的一个实施例，在所述步骤S6中，所述牺牲层为有机牺牲层或无机牺牲层。
根据本发明第一方面的一个实施例，在所述步骤S7中，所述牺牲层的释放采用干法释放或湿法释放。
根据本发明第一方面的一个实施例，在所述步骤S8中，所述封装盖板的制作方法为：在高阻硅圆片的上侧和下侧同时淀积所述掩蔽层，图形化下侧的所述掩蔽层，并在下侧的所述掩蔽层及所述高阻硅圆片中刻蚀出所述封装内腔。
根据本发明第一方面的一个实施例，所述键合密封环采用分别沉积制作第五金属粘附层和金属键合层而制成的，所述第五金属粘附层用于将所述金属键合层固定。
本发明第二方面还提出了一种气密性射频MEMS器件。
根据本发明第二方面实施例的气密性射频MEMS器件，所述气密性射频MEMS器件为采用根据本发明第一方面任意一个实施例所述的气密性射频MEMS器件的制作方法制作的。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1是本发明气密性射频MEMS器件的制作方法的第一种过程示意图。
图2是本发明气密性射频MEMS器件的制作方法的第二种过程示意图。
图3是本发明气密性射频MEMS器件的制作方法的第三种过程示意图。
图4是本发明气密性射频MEMS器件的制作方法的第四种过程示意图。
图5是本发明气密性射频MEMS器件的制作方法的第五种过程示意图。
图6是本发明气密性射频MEMS器件的制作方法的第六种过程示意图。
图7是本发明气密性射频MEMS器件的制作方法的第七种过程示意图。
图8是本发明气密性射频MEMS器件的剖面结构示意图。
附图标记：
气密性射频MEMS器件1000
衬底圆片1 TGV填实通孔结构2
第一SiO 2介质层3 传输线路4 第一焊盘5
第二SiO 2介质层6 层间互联通孔结构7
第三SiO 2介质层8 下拉电极9 第二焊盘10
第四SiO 2介质层11 接触凸点12
牺牲层13 键合环14 锚点15 上极板16
封装盖板17
高阻硅圆片1701 封装内腔1702 掩蔽层1703 键合密封环1704
锡球18
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
下面结合图1至图8来描述本发明气密性射频MEMS器件的制作方法及气密性射频MEMS器件1000。
如图1至图8所示，根据本发明第一方面实施例的气密性射频MEMS器件1000的制作方法，包括如下步骤：
S1：如图1所示，在衬底圆片1上加工出TGV填实通孔结构2，从而形成第一中间产品件；
S2：如图2所示，在第一中间产品件的上表面上沉积生长出第一SiO 2介质层3，在第一SiO 2介质层3中加工出传输线路4及第一焊盘5，传输线路4及第一焊盘5分别与对应的TGV填实通孔结构2电连接，从而形成第二中间产品件；
S3：如图3所示，在第二中间产品件的上表面上沉积生长出第二SiO 2介质层6，在第二SiO 2介质层6中加工出层间互联通孔结构7，层间互联通孔结构7与第一焊盘5电连接，从而形成第三中间产品件；
S4：如图3所示，在第三中间产品件的上表面上沉积生长出第三SiO 2介质层8，在第三SiO 2介质层8中加工出下拉电极9和第二焊盘10，第二焊盘10与层间互联通孔结构7电连接，从而形成第四中间产品件；
S5：如图3和图4所示，在第四中间产品件的上表面上沉积生长出第四SiO 2介质层11，在第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6中加工出接触凸点12，接触凸点12的底部与一个传输线路4电连接，从而形成第五中间产品件；
S6：如图5所示，在第五中间产品件的上表面上沉积牺牲层13，在牺牲层13中加工出键合环14，键合环14的底部与第四SiO 2介质层11固定，在牺牲层13、第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6中加工出锚点15，锚点15的底部与另一个传输线路4电连接，在牺牲层13的上表面上加工出上极板16，上极板16与锚点15的顶部电连接相连，锚点15、上极板16和接触凸点12均位于键合环14内，从而形成第六中间产品件；
S7：如图6所示，释放第六中间产品件中的牺牲层13，从而形成第七中间产品件；
S8：如图7所示，制作封装盖板17，封装盖板17的底面具有封装内腔1702，封装盖板17的上侧和封装盖板17的下侧除去封装内腔1702的部位均具有掩蔽层1703，封装盖板17的下侧的掩蔽层1703上设有键合密封环1704，封装内腔1702位于键合密封环1704内；
S9：如图8所示，将第七中间产品件的键合环14与封装盖板17的键合密封环1704对齐，进行圆片级金属键合，从而形成第八中间产品件；
S10：如图8所示，在第八中间产品件的衬底圆片1的下表面上进行晶圆级植锡球18，并对第八中间产品进行划片，从而得到最终的气密性射频MEMS器件。
根据本发明第一方面实施例的气密性射频MEMS器件的制作方法，具有如下的优点：第一、结合再布线工艺将传输线路4(如共面波导传输线路4)引出封装内腔1702，实现TGV 填实通孔结构2外置，大大地提高气密性射频MEMS器件1000的封装气密性，有利于提高气密性射频MEMS器件的可靠性；第二、封装盖板17上的键合密封环1704的引入，可以保证封装气密性，但同时会给RF信号传输线路4带来额外的寄生效应，影响器件的射频性能；通过设置第二SiO 2介质层、第三SiO 2介质层、第四SiO 2介质层既可以加厚传输线路4与键合环14之间的介质层厚度，又可以减小下拉电极9与上极板16(即悬臂梁)之间的间距，降低下拉电压，在不影响下拉电压的情况下，缓解了金属封装密封环带入的寄生效应问题；第三、将第五中间产品件的键合环14与封装盖板17的键合密封环1704对齐进行圆片级金属键合，可以提供良好的气密性，在完成气密性封装的同时，避免了高温封装对气密性射频MEMS器件1000结构带入的影响；第四、封装方式为圆片级封装，适合气密性射频MEMS器件1000批量化生产，提高生产效率，降低生产成本。
根据本发明第一方面的一个实施例，第一中间产品件的上表面、第二中间产品件的上表面、第三中间产品件的上表面和第四中间产品件的上表面均为抛光平整面。这样，可以减小气密性射频MEMS器件1000的应力，增加气密性射频MEMS器件1000的悬臂梁(即上极板16)的平坦性，提高气密性射频MEMS器件1000的层间互联的电接触性能。
优选的，第一中间产品件的上表面、第二中间产品件的上表面、第三中间产品件的上表面、第四中间产品件的上表面均为抛光平整面，可以分别通过CMP(化学机械抛光)抛光工艺加工得到。
根据本发明第一方面的一个实施例，在步骤S1中，TGV填实通孔结构2的具体加工步骤为：在衬底圆片1上制作出通孔后，在通孔的内周壁上镀金属导电层，例如铜层，再在已镀过金属导电层的第一通孔内填充绝缘介质，从而加工出TGV填实通孔结构2，或在通孔内全部填实导电金属，例如铜，从而加工出TGV填实通孔结构2。由此，实现了TGV填实通孔结构2的导电性。
优选的，衬底圆片1可以选用玻璃圆片。
根据本发明第一方面的一个实施例，在步骤S2中，在第一SiO 2介质层3中加工出传输线路4及第一焊盘5，具体包括如下步骤：在第一SiO 2介质层3中先加工出露出衬底圆片1的传输线路图形腔及第一焊盘图形腔；再在传输线路图形腔及第一焊盘图形腔中依次分别沉积生长出第一金属粘附层和第一金属线路层，第一金属粘附层用于粘固第一金属线路层。由此，加工方便，加工出的传输线路4及第一焊盘5品质好,无脱落风险。
需要说明的是，传输线路图形腔及第一焊盘图形腔可以通过光刻并刻蚀第一SiO 2介质层3并露出衬底圆片1而获得，这种加工方法选择性好、重复性好、生产效率高、成本低。
根据本发明第一方面的一个实施例，在步骤S3中，在第二SiO 2介质层6中加工出层间互联通孔结构7，具体包括如下步骤：在第二SiO 2介质层6中先加工出层间互联通孔图形腔，再在层间互联通孔图形腔中依次分别沉积生长出第二金属粘附层和第二金属线路层，第二金属粘附层用于粘固第二金属线路层。由此，加工方便，加工出的层间互联通孔结构7品质好。
需要说明的是，层间互联通孔图形腔可以通过光刻并刻蚀第二SiO 2介质层6获得，这种加工方法选择性好、重复性好、生产效率高、成本低。
根据本发明第一方面的一个实施例，在步骤S4中，在第三SiO 2介质层8中加工出下拉电极9和第二焊盘10，具体包括如下步骤：在第三SiO 2介质层8中先加工出下拉电极图形腔和第二焊盘图形腔，再在下拉电极图形腔和第二焊盘图形腔中依次分别沉积生长出第三金属粘附层和第三金属线路层。由此，加工方便，加工出的下拉电极9和第二焊盘10品质好。
需要说明的是，下拉电极图形腔和第二焊盘图形腔可以通过光刻并刻蚀第三SiO 2介质层8获得，这种加工方法选择性好、重复性好、生产效率高、成本低。
根据本发明第一方面的一个实施例，在步骤S5中，在第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6中先加工出接触凸点12，具体包括如下步骤：在第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6中加工出接触凸点图形腔，再在接触凸点图形腔处依次分别沉积生长出第四金属粘附层和金属凸点层，对金属凸点层加工以形成接触凸点12。由此，可以加工出接触凸点12，接触凸点12品质好
需要说明的是，接触凸点图形腔可以通过光刻并刻蚀第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6而获得，这种加工方法选择性好、重复性好、生产效率高、成本低。
根据本发明第一方面的一个实施例，在步骤S6中，在牺牲层13中加工出键合环14，具体包括如下步骤：在牺牲层中先加工出键合环图形腔，再在键合环图形腔中制作出键合环14。由此，可以方便加工出键合环14，键合环14品质好
需要说明的是，键合环图形腔可以通过光刻并刻蚀牺牲层13而获得，这种加工方法选择性好、重复性好、生产效率高、成本低。
根据本发明第一方面的一个实施例，在步骤S6中，在牺牲层13、第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6中加工出锚点15，具体包括如下步骤：在牺牲层13、第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6中先加工出锚点图形腔，再在锚点图形腔中制作出锚点15。由此，可以方便加工出锚点15，锚点15 品质好。
需要说明的是，锚点图形腔可以通过光刻并刻蚀牺牲层13、第四SiO 2介质层11、第三SiO 2介质层8及第二SiO 2介质层6而获得，这种加工方法选择性好、重复性好、生产效率高、成本低。
根据本发明第一方面的一个实施例，在步骤S6中，牺牲层13为有机牺牲层13或无机牺牲层13。例如，有机层可以选择聚酰亚胺牺牲层13，无机牺牲层13可以为硅牺牲层13。
根据本发明第一方面的一个实施例，在步骤S7中，牺牲层13的释放采用干法释放或湿法释放。特别地，当牺牲层13为聚酰亚胺牺牲层13时可以采用干法释放牺牲层13，当牺牲层13为硅牺牲层13时可以采用湿法释放牺牲层13，这样可以方便彻底地去除牺牲层13。
根据本发明第一方面的一个实施例，在步骤S8中，封装盖板17的制作方法为：在高阻硅圆片1701的上侧和下侧同时淀积掩蔽层1703，图形化下侧的掩蔽层1703，并在下侧的掩蔽层1703及高阻硅圆片1701中刻蚀出封装内腔1702。由此，加工方便，加工出封装盖板17可以减少射频信号的泄露。
根据本发明第一方面进一步的实施例，掩蔽层1703为Si 3N 4掩蔽层1703。由此，刻蚀选择比高，可以方便地加工出封装内腔1702。
根据本发明第一方面进一步的实施例，键合密封环1704采用分别沉积制作第五金属粘附层和金属键合层而制成的，第五金属粘附层用于将金属键合层固定。由此，加工方便，可以保证键合环14的品质。
根据本发明第一方面进一步的实施例，密封键合环14为采用Cu/Sn、Au/Sn、Au/Sn/Cu、Ge/Al和Au/Au的一种、两种或多种组合金属制得，可以根据实际需要进行选择。
本发明第二方面还提出了一种气密性射频MEMS器件1000。
根据本发明第二方面实施例的气密性射频MEMS器件1000，气密性射频MEMS器件1000为采用根据本发明第一方面任意一个实施例的气密性射频MEMS器件1000的制作方法制作的。
尽管已经示出和描述了本发明的实施例，本领域的普通技术人员可以理解：在不脱离本发明的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由权利要求及其等同物限定。

Claims (14)

  1. 一种气密性射频MEMS器件的制作方法，其特征在于，包括如下步骤：
    S1：在衬底圆片上加工出TGV填实通孔结构，从而形成第一中间产品件；
    S2：在所述第一中间产品件的上表面上沉积生长出第一SiO 2介质层，在所述第一SiO 2介质层中加工出传输线路及第一焊盘，所述传输线路及所述第一焊盘分别与对应的所述TGV填实通孔结构电连接，从而形成第二中间产品件；
    S3：在所述第二中间产品件的上表面上沉积生长出第二SiO 2介质层，在所述第二SiO 2介质层中加工出层间互联通孔结构，所述层间互联通孔结构与所述第一焊盘电连接，从而形成第三中间产品件；
    S4：在所述第三中间产品件的上表面上沉积生长出第三SiO 2介质层，在所述第三SiO 2介质层中加工出下拉电极和第二焊盘，所述第二焊盘与所述层间互联通孔结构电连接，从而形成第四中间产品件；
    S5：在所述第四中间产品件的上表面上沉积生长出第四SiO 2介质层，在所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出接触凸点，所述接触凸点的底部与一个所述传输线路电连接，从而形成第五中间产品件；
    S6：在所述第五中间产品件的上表面上沉积牺牲层，在所述牺牲层中加工出键合环，所述键合环的底部与所述第四SiO 2介质层固定，在所述牺牲层、所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出锚点，所述锚点的底部与另一个所述传输线路电连接，在所述牺牲层的上表面上加工出上极板，所述上极板与所述锚点的顶部电连接相连，所述锚点、所述上极板和所述接触凸点均位于所述键合环内，从而形成所述第六中间产品件；
    S7：释放所述第六中间产品件中的所述牺牲层，从而形成第七中间产品件；
    S8：制作封装盖板，所述封装盖板的底面具有封装内腔，所述封装盖板的上侧和所述封装盖板的下侧除去所述封装内腔的部位均具有掩蔽层，所述封装盖板的下侧的所述掩蔽层上设有键合密封环，所述封装内腔位于所述键合密封环内；
    S9：将所述第七中间产品件的所述键合环与所述封装盖板的所述键合密封环对齐，进行圆片级金属键合，从而形成第八中间产品件；
    S10：在所述第八中间产品件的所述衬底圆片的下表面上进行晶圆级植锡球，并对所述第八中间产品进行划片，从而得到最终的所述气密性射频MEMS器件。
  2. 根据权利要求1所述的气密性射频MEMS器件的制作方法，其特征在于，所述第 一中间产品件的上表面、所述第二中间产品件的上表面、所述第三中间产品件的上表面和所述第四中间产品件的上表面均为抛光平整面。
  3. 根据权利要求1-2中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S1中，所述TGV填实通孔结构的具体加工步骤为：在所述衬底圆片上制作出通孔后，在所述通孔的内周壁上镀金属导电层，再在已镀过所述金属导电层的所述第一通孔内填充绝缘介质，从而加工出所述TGV填实通孔结构，或在所述通孔内全部填实导电金属，从而加工出所述TGV填实通孔结构。
  4. 根据权利要求1-3中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S2中，所述在所述第一SiO 2介质层中加工出传输线路及第一焊盘，具体包括如下步骤：在所述第一SiO 2介质层中先加工出露出所述衬底圆片的传输线路图形腔及第一焊盘图形腔；再在所述传输线路图形腔及所述第一焊盘图形腔中依次分别沉积生长出第一金属粘附层和第一金属线路层，所述第一金属粘附层用于粘固所述第一金属线路层。
  5. 根据权利要求1-4中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S3中，所述在所述第二SiO 2介质层中加工出层间互联通孔结构，具体包括如下步骤：在所述第二SiO 2介质层中先加工出层间互联通孔图形腔，再在所述层间互联通孔图形腔中依次分别沉积生长出第二金属粘附层和第二金属线路层，所述第二金属粘附层用于粘固所述第二金属线路层。
  6. 根据权利要求1-5中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S4中，所述在所述第三SiO 2介质层中加工出下拉电极和第二焊盘，具体包括如下步骤：在所述第三SiO 2介质层中先加工出下拉电极图形腔和第二焊盘图形腔，再在所述下拉电极图形腔和所述第二焊盘图形腔中依次分别沉积生长出第三金属粘附层和第三金属线路层。
  7. 根据权利要求1-6中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S5中，所述在所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中先加工出接触凸点，具体包括如下步骤：在所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出接触凸点图形腔，再在所述接触凸点图形腔处依次分别沉积生长出第四金属粘附层和金属凸点层，对所述金属凸点层加工以形成所述接触凸点。
  8. 根据权利要求1-7中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S6中，所述在所述牺牲层中加工出键合环，具体包括如下步骤：在 所述牺牲层中先加工出键合环图形腔，再在所述键合环图形腔中制作出所述键合环。
  9. 根据权利要求1-8中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S6中，所述在所述牺牲层、所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中加工出锚点，具体包括如下步骤：在所述牺牲层、所述第四SiO 2介质层、所述第三SiO 2介质层及所述第二SiO 2介质层中先加工出锚点图形腔，再在所述锚点图形腔中制作出锚点。
  10. 根据权利要求1-9中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S6中，所述牺牲层为有机牺牲层或无机牺牲层。
  11. 根据权利要求1-10中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S7中，所述牺牲层的释放采用干法释放或湿法释放。
  12. 根据权利要求1-11中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，在所述步骤S8中，所述封装盖板的制作方法为：在高阻硅圆片的上侧和下侧同时淀积所述掩蔽层，图形化下侧的所述掩蔽层，并在下侧的所述掩蔽层及所述高阻硅圆片中刻蚀出所述封装内腔。
  13. 根据权利要求1-12中任意一项所述的气密性射频MEMS器件的制作方法，其特征在于，所述键合密封环采用分别沉积制作第五金属粘附层和金属键合层而制成的，所述第五金属粘附层用于将所述金属键合层固定。
  14. 一种气密性射频MEMS器件，其特征在于，所述气密性射频MEMS器件为采用根据权利要求1-13中任意一项所述的气密性射频MEMS器件的制作方法制作的。
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