WO2022151714A1 - 半导体结构的制造方法和半导体结构的制造设备 - Google Patents

半导体结构的制造方法和半导体结构的制造设备 Download PDF

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Publication number
WO2022151714A1
WO2022151714A1 PCT/CN2021/110077 CN2021110077W WO2022151714A1 WO 2022151714 A1 WO2022151714 A1 WO 2022151714A1 CN 2021110077 W CN2021110077 W CN 2021110077W WO 2022151714 A1 WO2022151714 A1 WO 2022151714A1
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semiconductor structure
substrate
chuck
manufacturing
support column
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PCT/CN2021/110077
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English (en)
French (fr)
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李世鸿
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长鑫存储技术有限公司
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Priority to US17/453,850 priority Critical patent/US20220223426A1/en
Publication of WO2022151714A1 publication Critical patent/WO2022151714A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for fabricating a semiconductor structure and a device for fabricating a semiconductor structure.
  • Etching is a commonly used process technique in the fabrication of semiconductor structures. Etching is a major process of patterning associated with photolithography. Photolithography etching refers to first exposing the photoresist by photolithography, and then etching the part to be removed by other means.
  • residues such as photoresist and oxide layers are typically removed using a combination of dry and wet processes. For example, oxygen plasma ashing is used first, followed by wet chemical cleaning with organic solvents at high temperature.
  • oxygen plasma ashing is used first, followed by wet chemical cleaning with organic solvents at high temperature.
  • the residues are not easily removed completely, and new residues are easily generated, thereby affecting the performance of the semiconductor structure.
  • Embodiments of the present application provide a method for fabricating a semiconductor structure and a device for fabricating a semiconductor structure, so as to ensure that residues are completely removed and no new residues are generated, thereby improving the performance of the semiconductor structure.
  • embodiments of the present application provide a method for manufacturing a semiconductor structure, including: providing a substrate; forming a patterned photoresist layer on the substrate, and using the patterned photoresist layer as a mask etching the substrate; after etching the substrate, using a plasma asher to perform plasma ashing treatment on the patterned photoresist layer and the residues generated by etching; the plasma ashing treatment The process is carried out in an oxygen-free environment.
  • Embodiments of the present application further provide a manufacturing equipment for a semiconductor structure, which is suitable for performing plasma ashing treatment on residues on the semiconductor structure.
  • the semiconductor structure includes a substrate, including: a chuck and at least three supporting columns; the The chuck is used to provide a heat source; the support column is located on the chuck, the support column is located on the chuck, the support column is used to carry the substrate, and make the substrate and the chuck break away.
  • the technical solutions provided by the embodiments of the present application have the following advantages: in this embodiment, the photoresist and the remaining impurities are ashed in an oxygen-free environment, so that the oxide layer can be obtained more thoroughly. removed without generating new oxide impurities.
  • the support column is used to carry the substrate and disengage the substrate from the chuck. That is, the support column can avoid the direct contact between the chuck and the substrate, thereby reducing the heating rate of the substrate, reducing the oxidizing ability of the surface of the metal layer, avoiding the formation of an additional oxide layer to block the conductivity of the metal, and reducing the oxygen atoms in the oxide layer.
  • the degree of diffusion of a metal layer enables the semiconductor structure to have good electrical properties.
  • 1-3 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure.
  • 4-6 are schematic structural diagrams corresponding to each step in the manufacturing method of the semiconductor structure provided by the first embodiment of the present application.
  • FIG. 7 is a schematic diagram of the plasma ashing process provided by the first embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a chuck and a support column according to the first embodiment of the present application.
  • a substrate 44 is provided, and the substrate 44 includes a first dielectric layer 42 , a first metal layer 41 located between adjacent first dielectric layers 42 , and the first metal layer 41 and the first dielectric layer 42 . on the second dielectric layer 43 ; a patterned photoresist layer 46 is formed on the second dielectric layer 43 .
  • the second dielectric layer 43 is etched using the patterned photoresist layer 46 (refer to FIG.
  • the first oxide layer 48 a is likely to be formed on the surface of the first metal layer 41 .
  • the patterned photoresist layer 46 is removed; in the process of removing the patterned photoresist layer 46, an oxygen plasma ashing technique is usually used, and oxygen will further aggravate the oxidation reaction, and the first oxide layer 48a Not only can it not be completely removed, but it will be further thickened and transformed into the second oxide layer 48; in addition, oxygen will oxidize the non-ashable residues in the photoresist, thereby forming a more difficult to remove impurity layer 45, The impurity layer 45 can adversely affect the performance of the semiconductor structure; after removing the patterned photoresist layer 46 (refer to FIG. 1 ), a second metal layer 49 filling the vias 47 (refer to FIG. 2 ) is formed, due to the second oxidation
  • the layer 48 has a larger resistance, which causes the series resistance of the first metal layer 41 and the second metal layer 49 to increase. Increased resistance results in slower operating rates and reduced electrical performance of the semiconductor structure.
  • an embodiment of the present application provides a method for manufacturing a semiconductor structure, which includes: after etching a substrate, plasma ashing is performed on the patterned photoresist and the residue produced by the etching using a plasma asher Treatment; the process of plasma ashing treatment is carried out in an oxygen-free environment.
  • plasma ashing treatment can not only remove the original oxide layer, but also avoid the generation of new residues, thereby ensuring that the semiconductor structure has good electrical properties.
  • the substrate 14 may include an isolation layer and a conductive layer, and the isolation structure is used to isolate a plurality of conductive layers.
  • the substrate 14 includes a first metal layer 11 , a first dielectric layer 12 and a second dielectric layer 13 , the first metal layer 11 is located in the first dielectric layer 12 ; the second dielectric layer 13 is located in the first dielectric layer 12 , and cover the first metal layer 11 .
  • the first dielectric layer 12 and the second dielectric layer 13 are isolation layers for defining the first metal layer 11 and the second metal layer formed subsequently.
  • the material of the first dielectric layer 12 is an insulating material, such as silicon dioxide.
  • the material of the first dielectric layer may also be silicon nitride, silicon nitride carbide or silicon oxynitride.
  • the material of the first metal layer 11 has a lower resistivity, such as copper. In other embodiments, the material of the first metal layer may also be tungsten, tantalum or titanium.
  • the material of the second dielectric layer 13 is an insulating material, such as silicon dioxide.
  • the material of the second dielectric layer may also be silicon nitride, silicon nitride carbide or silicon oxynitride.
  • a patterned photoresist layer 16 is formed on the substrate 14 .
  • a photoresist layer is coated on the substrate 14, and the photoresist layer is exposed to light.
  • the exposed photoresist layer may be treated with a solvent to remove part of the photoresist to form a patterned photoresist layer 16 .
  • the substrate 14 is etched using the patterned photoresist layer 16 as a mask.
  • the second dielectric layer 13 is etched using the patterned photoresist layer 16 as a mask to form through holes 17 in the second dielectric layer 13 to expose the first metal layer 11 .
  • dry etching is used to remove part of the second dielectric layer 13, and the etching gas can be carbon tetrafluoride, trifluoromethane and oxygen. Due to the oxidizing properties of the above-mentioned etching gas, residues such as the oxide layer 15 may be generated on the first metal layer 11 . In other embodiments, wet etching may also be used to remove part of the second dielectric layer.
  • a plasma ashing machine is used to perform plasma ashing treatment on the patterned photoresist layer 16 (refer to FIG. 5 ) and the residues produced by etching.
  • the process of plasma ashing treatment is as follows: performed in an oxygen-free environment.
  • the plasma ashing treatment in an oxygen-free environment can avoid further thickening of the oxide layer 15 (refer to FIG. 5 ), and can also completely remove the oxide layer 15 , thereby ensuring that the semiconductor structure has a lower resistance.
  • substances that are difficult to ashing in the photoresist will not be oxidized, and these substances that are difficult to ashing can be completely removed by a subsequent cleaning process.
  • a reactive gas 23 is introduced, and the reactive gas 23 includes H 2 N 2 or NH 3 .
  • H 2 N 2 or NH 3 has a certain reducibility, which can further remove the residual oxide on the first metal layer 11 , and can also avoid the generation of new oxide on the first metal layer 11 .
  • H 2 N 2 or NH 3 is less corrosive and will not cause great damage to the first dielectric layer 12 and the second dielectric layer 13 .
  • the flow rate of H 2 N 2 ranges from 3000 sccm to 10,000 sccm, for example, it can be 4,000 sccm, 5,000 sccm or 8,000 sccm.
  • the process time can be shortened to a certain extent, and damage to the semiconductor structure can also be avoided.
  • the flow rate of NH 3 is 1000 seem to 10000 seem.
  • it may be 2000 sccm, 4000 sccm or 7000 sccm.
  • the process time can be shortened to a certain extent, and damage to the semiconductor structure can also be avoided.
  • the reactive gas 23 further includes nitrogen gas.
  • Nitrogen as an inactive gas, can improve the hardness and wear resistance of the semiconductor structure to a certain extent.
  • the plasma generated by nitrogen has a greater bombardment force on the surface of the semiconductor structure, so the nitrogen can also improve the ashing effect, thereby increasing the cleanliness of the semiconductor structure.
  • the chamber temperature is relatively low and is in the range of 50° to 250°, for example, 100°C, 110°C, 120°C, 150°C or 200°C. It can be understood that if the chamber temperature is higher, the oxygen atoms in the oxide layer 15 (refer to FIG. 5 ) have greater activity. Before the oxide layer 15 is completely ashed, the oxygen atoms in the oxide layer 15 may face diffusion in the first metal layer 11 . If the content of oxygen atoms in the first metal layer 11 increases, the resistance of the first metal layer 11 will increase, thereby reducing the operating speed of the semiconductor structure. If the chamber temperature is too low, the plasma ashing process time may be increased. When the chamber temperature is within the above range, the probability of diffusion of oxygen atoms in the oxide layer 15 can be reduced, and the time of the plasma ashing treatment can be kept within a reasonable range.
  • the chamber pressure is in the range of 50-2000 mtorr.
  • the chamber pressure can be 100mtorr, 500mtorr, 1000mtorr.
  • the efficiency of ashing treatment can be improved, and the lower the pressure is, the more the metal surface can be prevented from being oxidized.
  • the radio frequency power is 1000W ⁇ 5000W, such as 2000W, 3000W or 4000W.
  • the energy of the plasma can be increased, thereby improving the ashing degree of the photoresist and oxide.
  • FIG. 7 is a schematic diagram of plasma ashing treatment
  • FIG. 8 is a schematic structural diagram of a chuck and a support column
  • FIG. 8(a) is a top view of the chuck and the support column
  • FIG. 8(b) is a top view of the support column
  • FIG. 8 (c) is a front view of the support column.
  • the plasma asher includes a chuck 22 and at least three support columns 21; the chuck 22 is used to provide a heat source, and the support columns 21 are used to carry the substrate 14 and make the substrate 14 and the chuck 22 break away.
  • the support column 21 pushes up the substrate 14 , which can avoid direct contact between the substrate 14 and the chuck 22 , thereby reducing the heating speed of the substrate 14 .
  • a lower heating rate can reduce the degree of diffusion of oxygen atoms in the oxide layer 15 (refer to FIG. 5 ), thereby avoiding a great influence on the conductivity of the first metal layer 11 (refer to FIG. 5 ).
  • the temperature change process of the substrate 14 includes a heating stage and a constant temperature stage. It is worth noting that the oxide layer 15 (refer to FIG. 5 ) and the patterned photoresist layer 16 (refer to FIG. 5 ) are simultaneously ashed during the heating stage, and at the end of the heating stage, most of the oxide layer 15 is removed; in the constant temperature stage, the remaining patterned photoresist layer 16 is mainly ashed.
  • the main reason for controlling the removal process of the oxide layer 15 (refer to FIG. 5 ) and the patterned photoresist layer 16 (refer to FIG. 5 ) in stages is: at lower temperatures, the diffusion rate of oxygen atoms in the oxide layer 15 It is relatively slow, and has little effect on the resistance of the first metal layer 11; in the heating stage, the temperature of the substrate 14 is relatively low, so most of the oxide layer 15 is removed in this stage, which can avoid the subsequent constant temperature stage. The atoms diffuse violently. In the constant temperature stage, the temperature of the substrate 14 is relatively high, so that the removal speed of the patterned photoresist layer 16 can be accelerated, thereby shortening the process time.
  • the height of the support column 21 in the heating stage is greater than that in the constant temperature stage. It can be understood that if the height of the support column 21 is higher in the heating stage, the heat received by the substrate 14 can be reduced, thereby reducing the probability of diffusion of oxygen atoms. The heat received by the photoresist layer 14 is reduced, so as to ensure that the substrate 14 has a higher temperature, so as to speed up the ashing process of the patterned photoresist layer 16, improve the efficiency and reduce the cost.
  • the height of the support column 21 in the direction perpendicular to the upper surface of the chuck 22 is gradually reduced; in the constant temperature stage, the height of the support column 21 in the direction perpendicular to the upper surface of the chuck 22 is maintained. constant.
  • the main reason is that: at the beginning of the heating stage, that is, when the chuck 22 just started to provide a heat source, the temperature of the substrate 14 changes to a greater degree; as the chuck 22 continues to supply heat, the temperature of the substrate 14 changes gradually.
  • the support column 21 has a relatively high height, which can reduce the degree of temperature change of the substrate 14; as the temperature continues to rise, the height of the support column 21 gradually decreases, which can ensure that the substrate 14 can reach the preset temperature quickly. Therefore, the time of plasma ashing treatment of photoresist is shortened.
  • the heating rate of the substrate 14 is 5°C/sec-20°C/sec, specifically 8°C/sec, 12°C/sec or 18°C/sec.
  • the degree of diffusion of oxygen atoms can be reduced, and the oxide layer 15 can be completely removed.
  • the height of the support column 21 in the direction perpendicular to the upper surface of the chuck 22 may be 3 mm ⁇ 20 mm, and specifically may be 8 mm, 12 mm or 18 mm.
  • the height of the support column 21 is within the above range, it can ensure that the substrate 14 can have a suitable heating rate, thereby reducing the diffusion rate of oxygen atoms in the oxide layer 15, and can also reasonably control the time of the plasma ashing treatment.
  • the height of the support column may also remain unchanged.
  • the distances from the plurality of support columns 21 to the central axis of the chuck 22 may be equal. In this way, after the base 14 is placed on the support column 21 , the base 14 can be subjected to a relatively uniform force, thereby improving the stability of the base 14 .
  • the support column 21 may be composed of a plurality of sleeve rods nested in sequence; when the sleeve rod is stretched, the height of the support column 21 increases; when the sleeve rod shrinks, the height of the support column 21 decreases.
  • a top rod may also be provided inside the support column, and the expansion and contraction of the top rod can control the rise or fall of the support column.
  • the material of the support column 21 is ceramic.
  • the thermal conductivity of the ceramic is small, which can prevent the chuck 22 from rapidly transferring heat to the substrate 14 through the support column 21, so that the heating rate of the substrate 14 can be reduced to reduce the diffusion rate of oxygen atoms, thereby avoiding increasing the first metal layer. 11 resistors.
  • the material of the support column may also be a metal with low thermal conductivity.
  • SO 3 gas is introduced to process the substrate 14 .
  • SO 3 gas has strong oxidizing property and can further remove impurities such as organic matter.
  • SO 3 gas is anhydrous gas, and the temperature of the chamber is low during the ventilation process.
  • the anhydrous SO 3 gas at low temperature is difficult to oxidize the first metal layer 11 , therefore, the above treatment process will not generate new oxide impurities, and will not adversely affect the electrical properties of the first metal layer 11 .
  • the semiconductor structure is cleaned with a mixed solution of dilute sulfur peroxide and hydrofluoric acid (DSP, dilute sulfuric-peroxide-HF), and a dilute hydrofluoric acid solution (DHF, dilute HF).
  • DSP dilute sulfur peroxide and hydrofluoric acid
  • DHF dilute hydrofluoric acid solution
  • the above solution can further remove impurities such as oxides and inorganic substances.
  • the mass concentration of H 2 O 2 is 1-5 wt %; the mass concentration of H 2 SO 4 is 1-10 wt %; the mass concentration of HF is 0.01-0.08 wt %.
  • concentration of each component is within the above range, impurities can be completely removed, and damage to the semiconductor structure can also be avoided.
  • a second metal layer 19 is formed on the first metal layer 11, and the second metal layer 19 also fills the through hole 17 (refer to FIG. 5).
  • the oxide layer 15 on the surface of the first metal layer 11 is relatively completely removed, the first metal layer 11 and the second metal layer 19 have lower series resistance, and the electrical performance of the semiconductor structure is better.
  • the material of the first metal layer 11 includes low-resistance metals such as copper, tungsten, titanium, gold, tantalum or silver, so as to reduce the resistance of the semiconductor structure and improve the operation efficiency of the semiconductor structure.
  • the patterned photoresist layer 16 and the remaining impurities such as the oxide layer 15 are ashed in an oxygen-free environment, so that the oxide layer 15 can be removed more thoroughly, and no New residues are produced.
  • using the support column 21 to lift the substrate 14 can avoid the direct contact between the chuck 22 and the substrate 14, thereby reducing the heating rate of the substrate 14, preventing the oxygen atoms in the oxide layer 15 from diffusing toward the first metal layer 11, and further Affects the electrical properties of semiconductor structures.
  • FIGS. 7-8 are schematic diagrams provided in this embodiment.
  • the semiconductor structure includes a substrate 14, and the manufacturing equipment of the semiconductor structure includes: a chuck 22 and at least three support columns 21; the chuck 22 is used to provide The heat source, the support column 21 is used to carry the substrate 14 and disengage the substrate 14 from the chuck 22 .
  • the support column 21 lifts the substrate 14 to avoid direct contact between the substrate 14 and the chuck 22 , thereby reducing the heating speed of the substrate 14 .
  • a lower heating rate can reduce the degree of diffusion of oxygen atoms in the oxide layer 15 (refer to FIG. 5 ), thereby avoiding a great influence on the conductivity of the first metal layer 11 (refer to FIG. 5 ).
  • the temperature change process of the substrate 14 includes a heating stage and a constant temperature stage. It is worth noting that, in the heating stage, the oxide layer 15 and the patterned photoresist layer 16 (refer to FIG. 5 ) will be ashed at the same time, and at the end of the heating stage, the oxide layer 15 will be relatively completely removed; During the constant temperature stage, the remaining patterned photoresist layer 16 is mainly ashed.
  • the main reason for controlling the removal process of the oxide layer 15 and the patterned photoresist layer 16 in stages is that: at a lower temperature, the diffusion speed of oxygen atoms in the oxide layer 15 is slow, and the diffusion rate of the first metal layer 11 is relatively slow.
  • the influence of resistance is small; in the heating stage, the temperature of the substrate 14 is relatively low, therefore, the oxide layer 15 is completely removed in this stage, which can avoid the violent diffusion of oxygen atoms in the subsequent constant temperature stage.
  • the temperature of the substrate 14 is relatively high, so that the removal speed of the patterned photoresist layer 16 can be accelerated, thereby shortening the process time.
  • the height of the support column 21 in the heating stage is greater than that in the constant temperature stage. It can be understood that if the height of the support column 21 is higher in the heating stage, the heat received by the substrate 14 can be reduced, thereby reducing the probability of diffusion of oxygen atoms. The heat received by 14 ensures that the substrate 14 has a higher temperature, so as to speed up the ashing process of the patterned photoresist layer 16 .
  • the height of the support column 21 in the direction perpendicular to the upper surface of the chuck 22 is gradually reduced; in the constant temperature stage, the height of the support column 21 in the direction perpendicular to the upper surface of the chuck 22 is maintained. constant.
  • the main reason is that: at the beginning of the heating stage, that is, when the chuck 22 just started to provide a heat source, the temperature of the substrate 14 changes to a greater degree; as the chuck 22 continues to supply heat, the temperature of the substrate 14 changes gradually.
  • the support column 21 has a relatively high height, which can reduce the degree of temperature change of the substrate 14; as the temperature continues to rise, the height of the support column 21 gradually decreases, which can ensure that the substrate 14 can reach the preset temperature quickly. Therefore, the time of plasma ashing treatment of photoresist is shortened.
  • the heating rate of the substrate 14 is 5°C/sec-20°C/sec.
  • the degree of diffusion of oxygen atoms can be reduced, and the oxide layer 15 can be completely removed.
  • the height of the support column 21 in the direction perpendicular to the upper surface of the chuck 22 may be 3 mm ⁇ 20 mm.
  • the substrate 14 can have a suitable heating rate, thereby reducing the diffusion rate of oxygen atoms in the oxide layer 15 and reasonably controlling the plasma ashing treatment time.
  • the height of the support column may also remain unchanged.
  • the distances from the plurality of support columns 21 to the central axis of the chuck 22 may be equal. In this way, after the base 14 is placed on the support column 21 , the base 14 can be subjected to a relatively uniform force, thereby improving the stability of the base 14 .
  • the support column 21 may be composed of a plurality of sleeve rods nested in sequence; when the sleeve rod is stretched, the height of the support column 21 increases; when the sleeve rod shrinks, the height of the support column 21 decreases.
  • a top rod may also be provided inside the support column, and the expansion and contraction of the top rod can control the rise or fall of the support column.
  • the material of the support column 21 is ceramic.
  • the thermal conductivity of the ceramic is small, which can prevent the chuck 22 from rapidly transferring heat to the substrate 14 through the support column 21, so that the heating rate of the substrate 14 can be reduced to reduce the diffusion rate of oxygen atoms, thereby avoiding increasing the first metal layer. 11 resistors.
  • the material of the support post can also be a metal with low thermal conductivity.
  • the manufacturing equipment of the semiconductor structure in this embodiment includes a chuck 22 and a plurality of support columns 21 located on the chuck 22 .
  • the plurality of support columns 21 can support the substrate 14 to avoid the separation between the substrate 14 and the chuck 22 . Direct contact, thereby reducing the degree of heating of the substrate 14 and reducing the degree of diffusion of impurity atoms such as oxygen atoms on the substrate 14, thereby ensuring that the semiconductor structure has good electrical properties.

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Abstract

本申请实施例提供一种半导体结构的制造方法及半导体结构的制造设备，半导体结构的制造方法，包括：提供基底；在所述基底上形成图形化的光刻胶层，以所述图形化的光刻胶层为掩膜刻蚀所述基底；刻蚀所述基底后，采用等离子体灰化机对所述图形化的光刻胶层和刻蚀产生的残留物进行等离子体灰化处理；所述等离子体灰化处理的过程在无氧环境中进行。本申请实施例能够去除半导体结构上的残留物，且不产生新的残留物，进而能提高半导体结构的电性能。

Description

半导体结构的制造方法和半导体结构的制造设备
交叉引用
本申请基于申请号为202110043371.8、申请日为2021年01月13日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构的制造方法和半导体结构的制造设备。
背景技术
刻蚀是在半导体结构的制造方法中常用的工艺技术。刻蚀是与光刻相联系的图形化处理的一种主要工艺。光刻腐蚀是指先通过光刻将光刻胶进行光刻曝光处理，然后通过其它方式腐蚀所需除去的部分。
在刻蚀之后，通常使用干法工艺和湿法工艺的组合来去除光刻胶和氧化层等残留物。例如，首先使用氧等离子体灰化，然后在高温下使用有机溶剂进行湿化学清洁。然而在现有的去除工艺中，残留物不易得到彻底的去除，且还易产生新的残留物，从而影响半导体结构的性能。
发明内容
本申请实施例提供一种半导体结构的制造方法和半导体结构的 制造设备，以保证将残留物彻底去除，且不产生新的残留物，从而提高半导体结构的性能。
为解决上述问题，本申请实施例提供一种半导体结构的制造方法，包括：提供基底；在所述基底上形成图形化的光刻胶层，以所述图形化的光刻胶层为掩膜刻蚀所述基底；刻蚀所述基底后，采用等离子体灰化机对所述图形化的光刻胶层和刻蚀产生的残留物进行等离子体灰化处理；所述等离子体灰化处理的过程在无氧环境中进行。
本申请实施例还提供一种半导体结构的制造设备，适于对半导体结构上的残留物进行等离子体灰化处理，所述半导体结构包括基底，包括：卡盘和至少三个支撑柱；所述卡盘用于提供热源；所述支撑柱位于所述卡盘上，所述支撑柱位于所述卡盘上，所述支撑柱用于承载所述基底，并使所述基底与所述卡盘脱离。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：本实施例中，在无氧环境下对光刻胶以及残留的杂质进行灰化处理，能够使得氧化层得到较为彻底的去除，且不会产生新的氧化物杂质。
另外，支撑柱用于承载所述基底，并使所述基底与所述卡盘脱离。即支撑柱能够避免卡盘与基底的直接接触，从而降低基底的升温速率，降低金属层表面的氧化能力，避免生成额外的氧化层进而阻绝金属导电能力，且降低氧化层中的氧原子朝向第一金属层扩散的程度，使得半导体结构的具有良好的电性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说 明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1-图3为一种半导体结构的制造方法中各步骤对应的结构示意图。
图4-图6为本申请第一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图。
图7为本申请第一实施例提供的等离子体灰化处理的示意图。
图8为本申请第一实施例提供的卡盘和支撑柱的结构示意图。
具体实施方式
由背景技术可知，在去除刻蚀产生的残留物的工艺中，残留物不易得到彻底的去除，且还易产生新的残留物，从而影响半导体结构的质量。
图1-图3为一种半导体结构制造方法中各步骤的结构示意图。具体地，参考图1，提供基底44，基底44包括第一介质层42、位于相邻第一介质层42之间的第一金属层41，以及位于第一金属层41和第一介质层42上的第二介质层43；在第二介质层43上形成图形化的光刻胶层46。参考图2，以图形化的光刻胶层46(参考图1)为掩膜刻蚀第二介质层43，形成位于第二介质层43内的通孔47；在刻蚀的过程中，由于温度、刻蚀试剂以及腔室气氛等因素的影响，第一金属层41的表面容易产生第一氧化层48a。参考图3，去除图形化的光刻胶层46；在去除图形化的光刻胶层46的过程中，通常使用氧等 离子体灰化技术，而氧气会进一步加剧氧化反应，第一氧化层48a不仅得不到彻底的去除，还会进一步增厚，从而转化为第二氧化层48；另外，氧气还会氧化光刻胶中不可灰化的残留物，从而形成更难去除的杂质层45，杂质层45会对半导体结构的性能造成不良影响；去除图形化的光刻胶层46(参考图1)后，形成填充通孔47(参考图2)的第二金属层49，由于第二氧化层48具有较大的电阻，这会导致第一金属层41与第二金属层49的串联电阻增大。电阻增大会导致半导体结构的运行速率变慢、电性能降低。
为解决上述问题，本申请实施例提供一种半导体结构的制造方法，包括：刻蚀基底后，采用等离子体灰化机对图形化的光刻胶和刻蚀产生的残留物进行等离子体灰化处理；等离子体灰化处理的过程在无氧环境中进行。在无氧环境中，等离子体灰化处理不仅可以去除原有氧化层，还能避免产生新的残留物，从而能够保证半导体结构具有良好的电性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图4-图8为本申请一实施例提供的半导体结构的制造方法，以下将结合附图进行具体说明。
参考图4，提供基底14。基底14中可以包括隔离层和导电层，隔离结构用于隔离多个导电层。本实施例中，基底14包括第一金属层11、第一介质层12和第二介质层13，第一金属层11位于第一介质层12内；第二介质层13位于第一介质层12上，并将第一金属层11覆盖。第一介质层12和第二介质层13为隔离层，用于限定第一金属层11以及后续形成的第二金属层。
在一实施例中，第一介质层12的材料为绝缘材料，例如二氧化硅。在其他实施例中，第一介质层的材料还可以为氮化硅、氮碳化硅或氮氧化硅。
在一实施例中，第一金属层11的材料具有较低的电阻率，例如铜。在其他实施例中，第一金属层的材料还可以为钨、钽或钛。
在一实施例中，第二介质层13的材料为绝缘材料，例如二氧化硅。在其他实施例中，第二介质层的材料还可以为氮化硅、氮碳化硅或氮氧化硅。
在基底14上形成图形化的光刻胶层16。具体的，在基底14上涂敷一层光刻胶层，对光刻胶层进行曝光处理。可以采用溶剂对曝光处理后的光刻胶层进行处理，从而去除部分光刻胶，以形成图形化的光刻胶层16。
参考图5，以图形化的光刻胶层16为掩膜刻蚀基底14。
具体地，本实施例中，以图形化的光刻胶层16为掩膜刻蚀第二介质层13，形成位于第二介质层13内的通孔17，以露出第一金属层11。
在一实施例中，采用干法刻蚀去除部分第二介质层13，刻蚀气体可以为四氟化碳、三氟甲烷以及氧气。由于上述刻蚀气体具有氧化性，可能会在第一金属层11上产生氧化层15等残留物。在其他实施例中，也可以采用湿法刻蚀去除部分第二介质层。
结合参考图6-图8，采用等离子体灰化机对图形化的光刻胶层16(参考图5)和刻蚀产生的残留物进行等离子体灰化处理，等离子体灰化处理的过程在无氧环境中进行。
无氧环境下的等离子体灰化处理能够避免氧化层15(参考图5)进一步增厚，还能够将氧化层15彻底去除，从而保证半导体结构具有较低的电阻。另外，在无氧环境下，光刻胶中难以灰化的物质也不会被氧化，通过后续的清洗工艺，这些难以灰化的物质可以被彻底去除。
在进行等离子体灰化处理的过程中，通入反应气体23，反应气体23包括H 2N 2或NH 3。H 2N 2或NH 3具有一定的还原性，能够进一步去除第一金属层11上残留的氧化物，还能够避免第一金属层11上产生新的氧化物。另外，H 2N 2或NH 3的腐蚀性较小，不会对第一介质层12以及第二介质层13造成较大的损伤。
在一实施例中，H 2N 2的流量为3000sccm～10000sccm，例如可以为4000sccm、5000sccm或8000sccm。H 2N 2的流量在上述范围内，可以在一定程度上缩短工艺时间，还能够避免对半导体结构造成损伤。
在又一实施例中，NH 3的流量为1000sccm～10000sccm。例如可以为2000sccm、4000sccm或7000sccm。NH 3的流量在上述范围内，可以 在一定程度上缩短工艺时间，还能够避免对半导体结构造成损伤。
在一实施例中，在进行等离子体灰化处理的过程中，反应气体23还包括氮气。氮气作为不活泼气体，在一定程度上可以提高半导体结构的硬度和耐磨性。另外，氮气产生的等离子体对半导体结构表面的轰击力度较大，因此氮气还可以提高灰化的效果，从而增加半导体结构的清洁度。
在进行等离子体灰化处理的过程中，腔室温度较低，且在50°～250°范围内，比如可以为100℃、110℃、120℃、150℃或200℃。可以理解的是，若腔室温度较高，氧化层15(参考图5)中的氧原子具有较大的活性，在未将氧化层15灰化完全之前，氧化层15中的氧原子可能朝向第一金属层11中扩散。若第一金属层11中的氧原子含量增加，则会增大第一金属层11的电阻，进而降低半导体结构的运行速率。若腔室温度过低，则可能会增加等离子体灰化处理的时间。而腔室温度在上述范围内，可以降低氧化层15中氧原子扩散的概率，还能够使等离子体灰化处理的时间保持在合理范围内。
在一实施例中，在进行等离子体灰化处理的过程中，腔室压力在50～2000mtorr范围内。比如可以为100mtorr、500mtorr、1000mtorr。腔室压力在上述范围内，可以提高灰化处理的效率，越低压环境下，越能避免金属表面被氧化。
在一实施例中，在进行等离子体灰化处理的过程中，射频功率为1000W～5000W，比如可以为2000W、3000W或4000W。射频功率在上述范围内，可以增大等离子体的能量，从而提高对光刻胶以及氧化物 的灰化程度。
图7为等离子体灰化处理的示意图，图8为卡盘和支撑柱的结构示意图，图8(a)为卡盘和支撑柱的俯视图，图8(b)为支撑柱的俯视图，图8(c)为支撑柱的正视图。结合参考图7和图8，等离子体灰化机包括卡盘22和至少三个支撑柱21；卡盘22用于提供热源，支撑柱21用于承载基底14，并使基底14与卡盘22脱离。
即支撑柱21将基底14顶起，能够避免基底14与卡盘22的直接接触，从而能够降低基底14的加热速度。较低的升温速度能够降低氧化层15(参考图5)中氧原子的扩散程度，从而避免对第一金属层11(参考图5)的导电性产生较大的影响。
在卡盘22提供热源的过程中，基底14的温度变化过程包括升温阶段和恒温阶段。值得注意的是，在升温阶段会同时对氧化层15(参考图5)以及图形化的光刻胶层16(参考图5)进行灰化处理，且在升温阶段结束时，大部分的氧化层15被去除；在恒温阶段，主要对剩余的图形化的光刻胶层16进行灰化处理。
分阶段控制氧化层15(参考图5)以及图形化的光刻胶层16(参考图5)的去除过程的主要原因在于：在较低的温度下，氧化层15中的氧原子的扩散速度较慢，对第一金属层11的电阻影响较小；在升温阶段时，基底14的温度较低，因此，在该阶段内将大部分的氧化层15去除，能够避免后续恒温阶段时，氧原子发生剧烈扩散。在恒温阶段，基底14的温度较高，如此可以加快图形化的光刻胶层16的去除速度，进而缩短工艺时间。
支撑柱21在升温阶段的高度大于在恒温阶段的高度。可以理解的是，支撑柱21在升温阶段的高度较高，则可以降低基底14所接受的热量，进而降低氧原子扩散的几率；支撑柱21在恒温阶段的高度较低，则可以增大基底14所接受到的热量，从而保证基底14具有较高的温度，以加快图形化的光刻胶层16的灰化过程，提高效率，降低成本。
在一实施例中，在升温阶段，支撑柱21在垂直于卡盘22上表面的方向上的高度逐渐降低；在恒温阶段，支撑柱21在垂直于卡盘22上表面的方向上的高度保持不变。主要原因在于：在升温阶段初期，即卡盘22刚开始提供热源时，基底14的温度变化程度较大；随着卡盘22不断供热，基底14的温度变化程度慢慢减小；因此，在升温阶段初期，支撑柱21具有较高的高度，能够减小基底14的温度变化程度；随时温度不断升高，支撑柱21的高度逐渐降低，能够保证基底14能够较快地达到预设温度下，进而缩短光刻胶的等离子体灰化处理的时间。
在升温阶段，基底14的升温速率为5℃/秒-20℃/秒，具体可以为8℃/秒、12℃/秒或18℃/秒。升温速率在上述范围内，可以降低氧原子的扩散程度，并保证氧化层15能够较为彻底的去除。
此外，支撑柱21在垂直于卡盘22上表面的方向上的高度可以为3mm～20mm，具体可以为8mm、12mm或18mm。支撑柱21的高度在上述范围内，可以保证基底14能够具有较合适的加热速度，从而能够降低氧化层15中氧原子的扩散速率，也能够合理的控制等离子体灰 化处理的时间。
在其他实施例中，支撑柱的高度也可以保持不变。
在一实施例中，具有四个支撑柱21，四个支撑柱21能够提高基底14放置的稳定性。在其他实施例中，还可以具有三个或四个以上的支撑柱。
在一实施例中，多个支撑柱21到卡盘22中心轴线的距离可以相等。如此，将基底14放置在支撑柱21上后，基底14能够受到较为均匀的作用力，从而提高基底14的稳定性。
在一实施例中，支撑柱21可以由多个依次嵌套的套杆组成；套杆拉伸，则支撑柱21的高度提高；套杆收缩，则支撑柱21的高度降低。在其他实施例中，也可以在支撑柱的内部设置顶杆，顶杆的伸缩可以控制支撑柱的升高或降低。
在一实施例中，支撑柱21的材料为陶瓷。陶瓷的导热系数较小，能够避免卡盘22通过支撑柱21将热量迅速传递给基底14，如此，能够降低基底14的升温速率，以降低氧原子的扩散速率，从而避免增大第一金属层11的电阻。在其他实施例中，支撑柱的材料还可以为导热率较低的金属。
参考图6，在进行等离子体灰化处理后，通入SO 3气体对基底14进行处理。SO 3气体具有较强的氧化性，能够进一步去除有机物等杂质。
SO 3气体为无水气体，且在通气的过程中，腔室的温度较低。低温下的无水SO 3气体很难氧化第一金属层11，因此，上述处理过程不 会产生新的氧化物杂质，也不会对的第一金属层11的电性能造成不良影响。
采用稀释的过氧化硫和氢氟酸的混合溶液(DSP，dilute sulfuric-peroxide-HF)，以及稀释的氢氟酸溶液(DHF，dilute HF)对半导体结构进行清洗。上述溶液能够进一步去除氧化物和无机物等杂质。
在DSP溶液中，H 2O 2的质量浓度为1～5wt％；H 2SO 4的质量浓度为1～10wt％；HF的质量浓度为0.01～0.08wt％。各组分浓度在上述范围内，可以使得杂质能够被彻底的去除，还能够避免对半导体结构造成损伤。
在DHF溶液中，HF:H 2O＝1:100～1:2000。各组分浓度在上述范围内，可以提高半导体结构的清洁度，还能够避免对半导体结构造成损伤。
值得注意的是，由于本实施例中不采用氢氧化铵和过氧化氢的混合溶液(APM，Ammonia Peroxide Mix)，因此，不会对第一金属层11和第二金属层19造成损伤。
在第一金属层11上形成第二金属层19，第二金属层19还填充满通孔17(参考图5)。
由于第一金属层11表面的氧化层15去除的较为彻底，因此第一金属层11与第二金属层19具有较低的串联电阻，半导体结构的电性能较好。
第一金属层11的材料包括铜、钨、钛、金、钽或银等低电阻金 属，从而能降低半导体结构的电阻，提高半导体结构的运行效率。
综上所述，本实施例中，在无氧环境下对图形化的光刻胶层16以及残留的氧化层15等杂质进行灰化处理，能够使得氧化层15得到较为彻底的去除，且不产生新的残留物。另外，采用支撑柱21将基底14顶起，能够避免卡盘22与基底14的直接接触，从而降低基底14的升温速率，避免氧化层15中的氧原子朝向第一金属层11中扩散，进而影响半导体结构的电性能。
本申请另一实施例提供一种半导体结构的制造设备，半导体结构的制造设备适于对半导体结构上的残留物进行等离子体灰化处理。图7-图8为本实施例提供的示意图，参考图7-图8，半导体结构包括基底14，半导体结构的制造设备包括：卡盘22和至少三个支撑柱21；卡盘22用于提供热源，支撑柱21用于承载基底14，并使基底14与卡盘22脱离。
本实施例与第一实施例相同或相似的部分，请参考第一实施例，在此不再赘述。
参考图7-图8，即支撑柱21将基底14顶起，能够避免基底14与卡盘22的直接接触，从而能够降低基底14的加热速度。较低的升温速度能够降低氧化层15(参考图5)中氧原子的扩散程度，从而避免对第一金属层11(参考图5)的导电性产生较大的影响。
在一实施例中，在卡盘22提供热源的过程中，基底14的温度变化过程包括升温阶段和恒温阶段。值得注意的是，在升温阶段会同时对氧化层15以及图形化的光刻胶层16(参考图5)进行灰化处理， 且在升温阶段结束时，氧化层15会得到较为彻底的去除；在恒温阶段，主要对剩余的图形化的光刻胶层16进行灰化。
分阶段控制氧化层15以及图形化的光刻胶层16的去除过程的主要原因在于：在较低的温度下，氧化层15中的氧原子的扩散速度较慢，对第一金属层11的电阻影响较小；在升温阶段时，基底14的温度较低，因此，在该阶段内将氧化层15完全去除，能够避免后续恒温阶段时，氧原子发生剧烈扩散。在恒温阶段，基底14的温度较高，如此可以加快图形化的光刻胶层16的去除速度，进而缩短工艺时间。
支撑柱21在升温阶段的高度大于在恒温阶段的高度。可以理解的是，支撑柱21在升温阶段的高度较高，则可以降低基底14所接受的热量，进而降低氧原子扩散的几率；支撑柱21在恒温阶段的高度较低，则可以增大基底14所接受到的热量，从而保证基底14具有较高的温度，以加快图形化的光刻胶层16的灰化过程。
在一实施例中，在升温阶段，支撑柱21在垂直于卡盘22上表面的方向上的高度逐渐降低；在恒温阶段，支撑柱21在垂直于卡盘22上表面的方向上的高度保持不变。主要原因在于：在升温阶段初期，即卡盘22刚开始提供热源时，基底14的温度变化程度较大；随着卡盘22不断供热，基底14的温度变化程度慢慢减小；因此，在升温阶段初期，支撑柱21具有较高的高度，能够减小基底14的温度变化程度；随时温度不断升高，支撑柱21的高度逐渐降低，能够保证基底14能够较快地达到预设温度下，进而缩短光刻胶的等离子体灰化处理的时间。
在升温阶段，基底14的升温速率为5℃/秒-20℃/秒。升温速率在上述范围内，可以降低氧原子的扩散程度，并保证氧化层15能够较为彻底的去除。
此外，支撑柱21在垂直于卡盘22上表面的方向上的高度可以为3mm～20mm。支撑柱21的高度在上述范围内，可以保证基底14能够具有较合适的加热速度，从而能够降低氧化层15中氧原子的扩散速率，也能够合理的控制等离子体灰化处理的时间。
在又一实施例中，支撑柱的高度也可以保持不变。
在一实施例中，具有四个支撑柱21，四个支撑柱21能够提高基底14放置的稳定性。在其他实施例中，还可以具有三个或四个以上的支撑柱。
另外，多个支撑柱21到卡盘22中心轴线的距离可以相等。如此，将基底14放置在支撑柱21上后，基底14能够受到较为均匀的作用力，从而提高基底14的稳定性。
在一实施例中，支撑柱21可以由多个依次嵌套的套杆组成；套杆拉伸，则支撑柱21的高度提高；套杆收缩，则支撑柱21的高度降低。在其他实施例中，也可以在支撑柱的内部设置顶杆，顶杆的伸缩可以控制支撑柱的升高或降低。
在一实施例中，支撑柱21的材料为陶瓷。陶瓷的导热系数较小，能够避免卡盘22通过支撑柱21将热量迅速传递给基底14，如此，能够降低基底14的升温速率，以降低氧原子的扩散速率，从而避免增大第一金属层11的电阻。在其他实施例中，支撑柱的材料还可以 为导热率较低的金属。
综上所述，本实施例中半导体结构的制造设备包括卡盘22以及位于卡盘22上的多个支撑柱21，多个支撑柱21可以支撑基底14，以避免基底14与卡盘22的直接接触，从而降低基底14的受热程度，降低基底14上氧原子等杂质原子的扩散程度，从而保证半导体结构具有良好的电性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种半导体结构的制造方法，包括：
    提供基底；
    在所述基底上形成图形化的光刻胶层，以所述图形化的光刻胶层为掩膜刻蚀所述基底；
    刻蚀所述基底后，采用等离子体灰化机对所述图形化的光刻胶层和刻蚀产生的残留物进行等离子体灰化处理；
    所述等离子体灰化处理的过程在无氧环境中进行。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，所述等离子体灰化机包括卡盘和至少三个支撑柱；所述卡盘用于提供热源；所述支撑柱位于所述卡盘上，所述支撑柱用于承载所述基底，并使所述基底与所述卡盘脱离。
  3. 根据权利要求2所述的半导体结构的制造方法，其中，在进行所述等离子体灰化处理的过程中，通入反应气体，所述反应气体包括H 2N 2或NH 3。
  4. 根据权利要求3所述的半导体结构的制造方法，其中，H 2N 2的流量为3000sccm～10000sccm；NH 3的流量为1000sccm～10000sccm。
  5. 根据权利要求3所述的半导体结构的制造方法，其中，所述反应气体还包括N 2。
  6. 根据权利要求2所述的半导体结构的制造方法，其中，在进行所述等离子体灰化处理的过程中，腔室温度在50°～250°范围内。
  7. 根据权利要求2所述的半导体结构的制造方法，其中，在进行所述等离子体灰化处理的过程中，腔室压力在50mtorr～2000mtorr范围内。
  8. 根据权利要求2所述的半导体结构的制造方法，其中，在所述卡盘提供热源的过程中，所述基底的温度变化过程包括升温阶段和恒温阶段；在所述升温阶段，所述支撑柱在垂直于所述卡盘上表面的方向上的高度逐渐降低；在所述恒温阶段，所述支撑柱在垂直于所述卡盘上表面的方向上的高度保持不变；且所述支撑柱在所述升温阶段的 高度大于在所述恒温阶段的高度。
  9. 根据权利要求8所述的半导体结构的制造方法，其中，在所述升温阶段，所述基底的升温速率为5℃/秒-20℃/秒。
  10. 根据权利要求2所述的半导体结构的制造方法，其中，所述支撑柱在垂直于所述卡盘上表面的方向上的高度为3mm～20mm。
  11. 根据权利要求2所述的半导体结构的制造方法，其中，多个所述支撑柱到所述卡盘中心轴线的距离相等。
  12. 根据权利要求2所述的半导体结构的制造方法，其中，所述支撑柱的材料包括陶瓷。
  13. 根据权利要求2所述的半导体结构的制造方法，其中，在进行所述等离子体灰化处理后，通入SO 3气体对所述基底进行处理。
  14. 根据权利要求2所述的半导体结构的制造方法，其中，所述基底包括第一金属层、第一介质层和第二介质层，所述第一金属层位于所述第一介质层内；所述第二介质层位于所述第一介质层上，并将所述第一金属层覆盖；以所述图形化的光刻胶层为掩膜刻蚀所述基底，具体包括：以所述图形化的光刻胶层为掩膜刻蚀所述第二介质层，以露出所述第一金属层；在进行所述等离子体灰化处理后，还包括：在所述第一金属层上形成第二金属层。
  15. 一种半导体结构的制造设备，适于对半导体结构上的残留物进行等离子体灰化处理，所述半导体结构包括基底，包括：卡盘和至少三个支撑柱；所述卡盘用于提供热源；所述支撑柱位于所述卡盘上，所述支撑柱用于承载所述基底，并使所述基底与所述卡盘脱离。
PCT/CN2021/110077 2021-01-13 2021-08-02 半导体结构的制造方法和半导体结构的制造设备 WO2022151714A1 (zh)

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JP2004047513A (ja) * 2002-07-08 2004-02-12 Tokyo Electron Ltd 静電吸着構造および静電吸着方法ならびにプラズマ処理装置およびプラズマ処理方法
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