WO2022151674A1 - 自刷新频率的检测方法 - Google Patents

自刷新频率的检测方法 Download PDF

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Publication number
WO2022151674A1
WO2022151674A1 PCT/CN2021/104923 CN2021104923W WO2022151674A1 WO 2022151674 A1 WO2022151674 A1 WO 2022151674A1 CN 2021104923 W CN2021104923 W CN 2021104923W WO 2022151674 A1 WO2022151674 A1 WO 2022151674A1
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Prior art keywords
self
read
refresh
duration
refresh frequency
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PCT/CN2021/104923
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English (en)
French (fr)
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杨波
王伟洲
刘欢欢
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长鑫存储技术有限公司
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Priority claimed from CN202110055134.3A external-priority patent/CN114765039B/zh
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/504,875 priority Critical patent/US20220230677A1/en
Publication of WO2022151674A1 publication Critical patent/WO2022151674A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a self-refresh detection method.
  • DRAM dynamic random access memory
  • DRAM digital random access memory
  • bit binary bit
  • the transistor will have natural leakage or leakage due to the hammer effect, resulting in that the amount of charge stored on the capacitor is not enough to correctly identify the data, that is, data loss or damage. Therefore, in the process of using DRAM , it is necessary to periodically refresh each memory cell to prevent data loss.
  • the self-refresh frequency of DRAM is very important for DRAM.
  • An embodiment of the present application provides a method for detecting a self-refresh frequency, including: writing data into at least one word line in a memory; performing a self-refresh operation on the memory; after a clock enable signal becomes a low level, setting determining the duration of the low level; performing a read operation on the memory at the positive transition point of the clock enable signal; obtaining multiple read results corresponding to the durations of the low level;
  • the self-refresh frequency of the memory is obtained according to a plurality of durations of the low level and a plurality of the read results.
  • the self-refresh frequency is detected by the principle that effective reading cannot be performed during the execution of the self-refresh operation.
  • the read time of the read operation enters the execution time period of the self-refresh operation or exceeds the execution of the self-refresh operation.
  • the read result corresponding to the read time will change accordingly.
  • the self-refresh cycle and self-refresh frequency of the self-refresh operation can be obtained. Due to the detection principle of the above detection method It is common in different memory particles, so the detection method can be applied to the detection of different memory particles.
  • the production line tester does not need to know the special test mode for outputting the self-refresh frequency corresponding to different memory particles when testing, which is beneficial to improve the self-refresh rate. Ease of refresh rate detection.
  • the preset time is greater than the sum of one self-refresh cycle and the duration of one self-refresh operation, which is beneficial to ensure that the read operation is delayed through the first second type of read transition time and the second The second type of read transition time obtains the self-refresh period and self-refresh frequency.
  • FIG. 1 is a schematic flowchart of a method for detecting a self-refresh frequency according to an embodiment of the present application
  • FIG. 2 is a schematic logical diagram of a method for detecting a self-refresh frequency according to an embodiment of the present application.
  • the test objects may include different types of memory particles from the same manufacturer, or different types of memory particles from different manufacturers. Without knowing the specific circuit design of memory particles, it is usually necessary to enter the The special test mode for outputting the self-refresh frequency corresponding to the memory particle can obtain the self-refresh frequency of the memory particle.
  • production line testers usually cannot accurately grasp the special test mode corresponding to each memory particle.
  • an embodiment of the present application provides a method for detecting a self-refresh frequency.
  • the self-refresh frequency is detected by the principle that a read operation cannot be performed during the execution of the self-refresh operation.
  • the read time of the read operation enters the self-refresh rate.
  • the execution time period of the operation is within or exceeds the execution time period of the self-refresh operation, the read result corresponding to the read time will change accordingly, and the read time corresponding to the changed read result can be obtained.
  • Refresh cycle and self-refresh frequency since the detection principle of the above detection method is common in different memory particles, the detection method can be applied to the detection of different memory particles, and production line testers do not need to know the corresponding functions of different memory particles when testing.
  • the special test mode for outputting self-refresh frequency is beneficial to improve the simplicity of self-refresh frequency detection.
  • FIG. 1 is a schematic flowchart of a method for detecting a self-refresh frequency according to an embodiment of the present application. Specifically, the detection method of the self-refresh frequency includes the following steps:
  • Step 101 Write data into at least one word line in the memory.
  • a memory usually includes multiple sets of banks, and each bank includes multiple word lines.
  • each bank in the memory is opened, and all word lines in each bank are sequentially written until the entire memory is filled with preset data ;
  • data writing is performed on only one word line in a certain memory bank.
  • the specific steps of writing data to all word lines in each memory bank may be as follows: select a memory bank and open one of the word lines, and write preset data in the entire word line; After the preset data is full, close the current word line and open another word line, and write the preset data again until it is full; repeat the above operation until all the word lines in one bank in the memory are full; at this time, select another One memory bank is opened and one of the word lines is opened for data writing until the word line is filled; the above operations are repeated until all the word lines in the memory banks in the memory are filled with preset data.
  • the writing sequence of the memory banks in the memory and the writing sequence of the word lines in the memory are random; secondly, the preset data can be a binary bit "1", in this way, when the subsequent reading result is 0 or not obtained When a valid read result is obtained, the read result can be considered as a failure.
  • Step 102 Perform a self-refresh operation on the memory.
  • Performing a self-refresh operation on the memory is equivalent to sending an activate command to the memory so that the self-refresh operation occurs after the clock enable signal goes low.
  • the clock enable signal (CKE signal) is a low-level active signal.
  • the clock enable signal is at a low level, the memory bank, or the self-refresh operation of the memory or memory particles can be performed normally, that is, the clock
  • the low level of the enable signal is used to trigger the self-refresh operation of the memory bank.
  • a refresh operation which is precisely an automatic refresh operation, is performed on at least one word line in which data is written, so as to ensure the storage in the capacitor connected to each word line. Having a sufficient number of charges is beneficial to avoid data loss caused by leakage during the self-refresh frequency detection process, and to ensure the accuracy of the reading results.
  • Step 103 Set the duration of the low level and perform a read operation.
  • a duration definition operation is performed to define the duration of the low level, that is, the low level of the clock enable signal is maintained after the "duration". Becomes a high level, and at the same time, makes the self-refresh operation for the duration in the execution state.
  • the clock enable signal has a "positive transition point", the "positive transition point” is a time point at which it transitions from a low level to a high level, and the level of the "positive transition point” is a high level. It should be noted that although the level of the "positive trip point” is high, since the jump has just been completed, the self-refresh operation is still in an executable state at the "positive trip point", that is, at the "positive trip point”. “At this point, the read operation may not be valid, and after the "positive trip point", the read operation may be valid.
  • the read operation cannot be performed efficiently. Specifically, when the capacitor connected to the word line is in the refresh stage, the read operation can only read the word line, but since the word line cannot be opened, the read operation cannot be effectively completed due to an error, and it can be considered that The read result of the read operation is failure; further, when the read result of the read operation at the previous moment is success, and the read result of the read operation at the next moment is failure, it can be considered that the next moment is a self-refresh operation 10 At this time, the refresh operation 10 starts or is in progress; when the read result of the read operation at the current moment is failure, and the read result of the read operation at the next moment is successful, it can be considered that the next moment It is the end time point of the self-refresh operation 10, and the self-refresh operation 10 has ended at this time.
  • the read operation includes a plurality of read operations performed in sequence, and the read operation is continuously performed on at least one word line during at least the duration of the low level. Specifically, when only one word line is written with data, the read operation continues to read the data of this word line; when the data is written to all word lines in all memory banks, the read operation can perform random reading , that is, random access to memory banks in the memory, and random access to word lines in the memory body, can also read each memory bank in the memory in sequence, and read each word line in the memory body in sequence.
  • the continuous read operation is used to read the data of different word lines, which is beneficial to avoid the damage of the data in a single word line due to continuous reading, that is, the amount of charge caused by the continuous discharge of the capacitor is not enough to correctly identify the data. , thereby ensuring that the read result can effectively represent whether the self-refresh operation 10 is in progress. It should be noted that even reading data of different word lines needs to be completed within a reasonable time, otherwise the capacitor may have insufficient charge due to natural leakage.
  • the same word line can be effectively continuously read within a reasonable time, beyond which a write-back is required to ensure data accuracy.
  • the read operation includes multiple read actions performed in sequence, but one read operation only corresponds to one read time and one read result.
  • the read result of any read action is a failure
  • the read operation The read result of the fetch operation is failure.
  • the read time corresponding to the read operation is set to the duration set by the duration definition operation, and the read operation is read at the positive transition point of the clock enable signal, so that the read result can effectively represent the positive state. Whether the jump point is within the time period occupied by the self-refresh operation ensures the validity of the corresponding relationship between the read time and the read result.
  • the read time of the read operation is set to 1800ns
  • the set read time is the positive signal of the clock enable signal. jump point.
  • the time of 1700ns is within the execution time period of the self-refresh operation 10
  • the time of 1800ns is between the execution time periods of the adjacent self-refresh operation 10
  • the read result of the read operation will be If it is successful, the corresponding relationship between the reading time and the reading result can be obtained - 1800ns corresponds to a successful reading, and this correspondence is correct; and if the reading is actually started at 1700ns, the reading result is a failure, that is, the actual reading is obtained.
  • the corresponding relationship between the reading time and the reading result is that the reading fails at the moment of 1800ns, and the corresponding relationship is wrong. Therefore, in order to ensure the correct correspondence between the read time and the read result, the actual start time point of the read operation should be as close as possible to the positive transition point of the clock enable signal.
  • the self-refresh operation 10 Since the time point after the positive transition point is high, the self-refresh operation 10 will not be triggered, and the read result of the read operation must be successful. Therefore, the read result of the read operation performed at the positive transition point will not be triggered. It all depends on whether the positive trip point is within the execution time period of the self-refresh operation 10 . That is to say, the number of read actions included in the read operation starting at the positive transition point, whether it includes only one read action or multiple read actions, will not affect the read operation of the read operation. result.
  • the read result of the read operation since the read result of the read operation only depends on the read result of the read operation performed by the positive transition point, and has nothing to do with other read operations, the read result corresponding to the read operation is not affected by adjacent ones.
  • the effect of the time interval of the read action time the time interval between adjacent read actions can be equal or unequal.
  • the time interval between adjacent read actions is related to the manner in which the read actions are performed. For example, a burst of continuous reads will result in different time intervals between adjacent read actions.
  • the self-refresh operation 10 has a self-refresh cycle
  • the inverse of the self-refresh cycle is the self-refresh frequency
  • the self-refresh operation 10 has a refresh duration, which is the duration required for the memory bank to complete the refresh.
  • Step 104 Acquire multiple read results corresponding to multiple low-level durations.
  • the duration definition operation and the read operation need to be alternately performed.
  • the duration set by the later duration definition operation is greater than the duration of the previous duration definition operation, and the durations of the low levels set by the adjacent duration definition operations may be separated by 50ns to 150ns.
  • the duration definition operation may be repeated multiple times until the duration set by the duration definition operation is greater than the preset duration.
  • the preset duration can be set to be longer than one self-refresh cycle to obtain the starting time points of the first two self-refresh operations 10 that are triggered first, and then the self-refresh cycle and self-refresh frequency can be obtained; in practical situations , the preset duration can be set to be greater than the sum of a self-refresh cycle and a refresh duration, to ensure that when there is a delay in the read operation, the end time points of the first two self-refresh operations 10 that are triggered can be obtained, and then get Self-refresh period and self-refresh frequency.
  • the refresh duration of the self-refresh operation 10 is 600 ns
  • the self-refresh period is 7 ⁇ s
  • the time point when the clock enable signal becomes a low level is taken as the zero point of the time axis
  • the start of the first triggered self-refresh operation 10 The time point is 1100ns.
  • the time period of 1100ns to 1700ns is the execution time period of the self-refresh operation 10, and the read operation cannot be performed during this time period; further, since the self-refresh period is 7 ⁇ s, the second The starting time point of the triggered self-refresh operation 10 is 8100 ns, and the execution time period of the second self-refresh operation 10 is 8100 ns to 8700 ns, and the read operation cannot be performed during this time period.
  • the read results of 10 read operations performed within 100ns to 1000ns are successful, and the 7 read operations performed within 1100ns to 1700ns are successful.
  • the read result of 63 read operations within 1800ns ⁇ 8000ns is successful, the read result of 7 read operations performed within 8100ns ⁇ 8700ns is failure, and the read result of 8800ns The read result of the fetch operation is successful.
  • the read transition time from successful read to read failure is the first type of read transition time.
  • the first type of read transition time corresponds to the start time of self-refresh operation 10, such as 1100ns and 8100ns;
  • the read time when the failed conversion becomes the read success is the second type of read conversion time, and the second type of read conversion time corresponds to the end time point of the self-refresh operation 10 , for example, 1800ns and 8800ns.
  • the duration of the low level of the clock enable signal is longer than one self-refresh period, and the self-refresh period and self-refresh frequency of the memory bank are obtained according to the time of the adjacent first-type read transition time; in other embodiments , the start time of the read operation is delayed relative to the time when the clock enable signal becomes low. This delay may be caused by the delay in the issuance of the read signal or the existence of the duration-defining operation, resulting in the actual read operation.
  • the start time is within the execution time period of the first self-refresh operation 10, for example, within the above-mentioned 1100ns to 1700ns, which results in that some read operations are actually performed after the clock enable signal becomes high, making some low power
  • the read result corresponding to the flat duration must be successful, even if the positive transition point is within the execution time period of the first self-refresh operation 10 .
  • the first read transition time of the first type is invalid, and the actually effective first read transition time is
  • the first second type of read transition time at this time, the self-refresh cycle and self-refresh frequency of the memory bank can be obtained according to the adjacent second type of read transition time; correspondingly, the duration of the low level at this time should be greater than The sum of one self-refresh cycle and the refresh duration of one self-refresh operation, to ensure that two adjacent second-type read transition moments are within the duration of the low level.
  • the refresh duration of the self-refresh operation can also be other values, such as 500ns, and the self-refresh period can also be other values, such as 3.9 ⁇ s, and the duration The difference can also be other values in the range of 50-150ns, such as 60ns, 80ns, 120ns or 140ns.
  • Step 105 Obtain the self-refresh frequency of the memory according to the durations of the multiple low levels and the multiple read results.
  • the self-refresh frequency is detected based on the principle that the read operation cannot be performed during the execution of the self-refresh operation.
  • the read time of the read operation enters the execution time period of the self-refresh operation or exceeds the execution of the self-refresh operation During the time period, the read result corresponding to the read time will change accordingly.
  • the self-refresh cycle and self-refresh frequency of the self-refresh operation can be obtained. Due to the detection principle of the above detection method It is common in different memory particles, so the detection method can be applied to the detection of different memory particles.
  • the production line tester does not need to know the special test mode for outputting the self-refresh frequency corresponding to different memory particles when testing, which is beneficial to improve the self-refresh rate. Ease of refresh rate detection.

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Abstract

一种自刷新频率的检测方法，包括：向存储器中至少一条字线内写入数据；对所述存储器进行自刷新操作；在时钟使能信号变为低电平之后，设定所述低电平的持续时长；在所述时钟使能信号的正跳变点对所述存储器进行读取操作；获取多个所述低电平的持续时长对应的多个读取结果；根据多个所述低电平的持续时长和多个所述读取结果得到所述存储器的自刷新频率。该方法有利于提高自刷新频率检测的简便性。

Description

自刷新频率的检测方法
交叉引用
本申请基于申请号为202110055134.3、申请日为2021年01月15日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种自刷新的检测方法。
背景技术
动态随机存取存储器(dynamic random access memory，DRAM)由于集成度高，成本低等优点，目前普遍地适用于各种计算机系统中，作为存储数据的介质。
DRAM的作用原理是利用电容内存储电荷的状态来代表一个二进制比特位(bit)是1还是0。由于在现实中，晶体管会发生自然漏电或因行锤效应而发生漏电，导致电容上所存储的电荷数量并不足以正确地判别数据，即导致数据丢失或损毁，因此，在使用DRAM的过程中，需要周期性地对每个存储器单元进行刷新操作，以防止数据丢失。
DRAM的自刷新频率对于DRAM至关重要。
发明内容
本申请实施例提供一种自刷新频率的检测方法，包括：向存储器中至少一条字线内写入数据；对所述存储器进行自刷新操作；在时钟 使能信号变为低电平之后，设定所述低电平的持续时长；在所述时钟使能信号的正跳变点对所述存储器进行读取操作；获取多个所述低电平的持续时长对应的多个读取结果；根据多个所述低电平的持续时长和多个所述读取结果得到所述存储器的自刷新频率。
本申请实施例提供的技术方案具有以下优点：
上述技术方案中，通过自刷新操作执行期间无法进行有效读取的原理进行自刷新频率的检测，当读取操作的读取时间进入自刷新操作的执行时间段内时或者超过自刷新操作的执行时间段时，读取时间对应的读取结果会发生相应改变，根据发生改变的读取结果对应的读取时间可得到自刷新操作的自刷新周期和自刷新频率，由于上述检测方法的检测原理在不同内存颗粒中通用，因此检测方法可适用于不同内存颗粒的检测，产线测试人员在进行检测时无需知晓不同内存颗粒所对应的用于输出自刷新频率的特殊测试模式，有利于提高自刷新频率检测的简便性。
另外，预设时间大于一个自刷新周期与一次自刷新操作的时长之和，有利于在保证读取操作存在延迟的情况下，可通过第一个第二类读取转换时刻和第二个第二类读取转换时刻获取自刷新周期和自刷新频率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附 图中的图不构成比例限制。
图1为本申请实施例提供的自刷新频率的检测方法的流程示意图；
图2为本申请一实施例提供的自刷新频率的检测方法的逻辑示意图。
具体实施方式
当前在进行内存颗粒的检测时，测试对象可能包括同一厂商的不同类别的内存颗粒，也可能包括不同厂商的不同类别的内存颗粒，在不了解内存颗粒的具体电路设计的情况下，通常需要进入内存颗粒对应的用于输出自刷新频率的特殊测试模式，才能获取内存颗粒的自刷新频率。但在实际测试场景下，产线测试人员通常无法准确掌握每一内存颗粒对应的特殊测试模式。
为解决上述问题，本申请实施例提供一种自刷新频率的检测方法，通过自刷新操作执行期间无法进行读取操作的原理进行自刷新频率的检测，当读取操作的读取时间进入自刷新操作的执行时间段内时或者超过自刷新操作的执行时间段时，读取时间对应的读取结果会发生相应改变，根据发生改变的读取结果对应的读取时间可得到自刷新操作的自刷新周期和自刷新频率，由于上述检测方法的检测原理在不同内存颗粒中通用，因此检测方法可适用于不同内存颗粒的检测，产线测试人员在进行检测时无需知晓不同内存颗粒所对应的用于输出自刷新频率的特殊测试模式，有利于提高自刷新频率检测的简便性。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请实施例提供的自刷新频率的检测方法的流程示意图。具体地，自刷新频率的检测方法包括以下步骤：
步骤101：向存储器中至少一条字线内写入数据。
存储器中通常包括多组存储体，每一存储体中包含多条字线。本实施例中，在写入数据以供进行后续读写时，打开存储器内每一存储体，并对每一存储体内的所有字线进行依次写入，直至整个存储器都被写满预设数据；在其他实施例中，仅对某一存储体中的一条字线进行数据写入。
具体地，对每一存储体内的所有字线进行数据写入的具体步骤可如下所示：选中一存储体并打开其中的一条字线，在整条字线内写入预设数据；在写满预设数据之后，关闭当前字线并打开另一字线，再次写入预设数据直至写满；重复上述操作，直至存储器中一存储体内的所有字线被写满；此时再选中另一存储体并打开其中的一条字线进行数据写入，直至写满该条字线；重复上述操作，直至存储器内所有存储体中的字线都被写满预设数据。
其中，存储器内存储体的写入顺序和存储体内字线的写入顺序都 是随机的；其次，预设数据可以为二进制比特“1”，如此，当后续的读取结果为0或者未获得有效的读取结果时，可认为读取结果为失败。
步骤102：对存储器进行自刷新操作。
对存储器进行自刷新操作相当于向存储器发送激活命令，以使自刷新操作在时钟使能信号变为低电平之后进行。其中，时钟使能信号(CKE信号)为低电平有效信号，在时钟使能信号处于低电平的情况下，存储体，或者说存储器或内存颗粒的自刷新操作才能够正常进行，即时钟使能信号的低电平用于触发存储体的自刷新操作。
本实施例中，在进行后续的时长定义操作和读取操作之前，对写入数据的至少一条字线进行刷新操作，准确来说是自动刷新操作，以保证每一字线连接的电容内存储有足够的电荷数量，有利于避免自刷新频率检测过程中漏电导致的数据丢失，保证读取结果的准确性。
步骤103：设定低电平的持续时长并进行读取操作。
本实施中，在存储体的时钟使能信号变为低电平之后，进行时长定义操作，以定义低电平的持续时长，即使得时钟使能信号的低电平在维持“持续时长”后变为高电平，同时，使得处于持续时长内的自刷新操作处于执行状态。
时钟使能信号具有“正跳变点”，“正跳变点”为从低电平跳转为高电平的时间点，“正跳变点”的电平为高电平。需要说明的是，虽然“正跳变点”的电平为高电平，但由于刚刚完成跳转，自刷新操作在“正跳变点”依旧处于可执行状态，即在“正跳变点”这一时刻， 读取操作可能无法有效进行，而在“正跳变点”之后，读取操作可有效执行。
在自刷新操作10执行时间段内，读取操作无法有效进行。具体来说，在字线连接的电容处于刷新阶段时，读取操作仅仅能够对字线作出读取动作，但由于无法打开字线，读取操作会因为发生错误而无法有效完成，即可认为读取操作的读取结果为失败；进一步地，当前一时刻读取操作的读取结果为成功，后一时刻读取操作的读取结果为失败时，可认为后一时刻为自刷新操作10的起始时间点，此时自刷新操作10开始进行或者正在进行；当前一时刻读取操作的读取结果为失败，后一时刻读取操作的读取结果为成功时，可认为后一时刻为自刷新操作10的结束时间点，此时自刷新操作10已经结束。
本实施例中，读取操作中包含多个依次进行的读取动作，至少在低电平的持续时间内，对至少一条字线持续执行读取动作。具体地，当仅有一条字线被写入数据时，读取动作持续读取该条字线的数据；当数据写满所有存储体中的所有字线时，读取动作可以进行随机读取，即随机读取存储器内的存储体，以及随机读取存储体内的字线，也可以依次读取存储器内的每一存储体，以及依次读取存储体内的每一字线。
其中，持续进行的读取动作用于读取不同字线的数据，有利于避免单条字线内的数据因持续读取而发生损毁，即电容持续放电而导致电荷数量并不足以正确地判别数据，进而保证读取结果可有效表征自刷新操作10是否正在进行。需要说明的是，即便是读取不同字线的 数据，也需要在合理时间内完成，否则电容可能因为自然漏电而存在电荷数量不足的情况。
此外，在合理时间内可对同一字线进行有效地持续读取，超出该时间，则需要写回，以保证数据准确性。
本实施例中，读取操作中包含多个依次进行的读取动作，但是一次读取操作仅对应一个读取时间和一个读取结果，当任一读取动作的读取结果为失败时读取操作的读取结果为失败。进一步地，将读取操作对应的读取时间设定为时长定义操作设定的持续时长，读取操作在时钟使能信号的正跳变点进行读取，如此，读取结果可有效表征正跳变点是否位于自刷新操作所占时间段内，即保证读取时间与读取结果的对应关系的有效性。
举例来说，当低电平持续时长为1800ns时，低电平持续时间段为0～1800ns，读取操作的读取时间设定为1800ns，设定的读取时间为时钟使能信号的正跳变点。当1700ns时刻处于自刷新操作10的执行时间段内，而1800ns时刻处于相邻自刷新操作10的执行时间段之间时，如果在1800ns时刻开始进行读取操作，那么读取操作的读取结果为成功，即可得到读取时间和读取结果的对应关系——1800ns时刻对应读取成功，这一对应关系正确；而如果实际在1700ns开始读取，那么读取结果为失败，即实际得到的读取时间和读取结果的对应关系为1800ns时刻对应读取失败，对应关系发生了错误。因此，为保证读取时间与读取结果的正确对应关系，读取操作的实际起始时间点应当尽量靠近时钟使能信号的正跳变点。
由于正跳变点之后的时间点为高电平，自刷新操作10不会被触发，读取操作的读取结果一定为成功，因此，在正跳变点进行的读取操作的读取结果完全取决于正跳变点是否位于自刷新操作10的执行时间段内。也就是说，在正跳变点开始进行的读取操作所包含的读取动作的数量，无论是只包括一次读取动作，还是包括多次读取动作，不会影响读取操作的读取结果。
进一步的，由于读取操作的读取结果仅取决于正跳变点进行的读取动作的读取结果，而与其他读取动作无关，因此，读取操作对应的读取结果不受相邻读取动作时间的时间间隔的影响，相邻读取动作之间的时间间隔可以相等或不等。相邻读取动作之间的时间间隔与读取动作的执行方式有关，例如突发连续读取就会导致相邻读取动作之间的时间间隔不同。
参考图2，自刷新操作10具有自刷新周期，自刷新周期的倒数为自刷新频率，自刷新操作10具有刷新占用时长，刷新占用时长为存储体完成刷新所需的时长。为获取自刷新周期，需要获取相邻自刷新操作10的起始时间点或结束时间点，从而根据起始时间点或结束时间点之差得到自刷新操作10的刷新时间间隔，进而获取自刷新频率。
步骤104：获取多个低电平的持续时长对应的多个读取结果。
为获取多个读取结果，需要交替进行时长定义操作和读取操作。具体地，后一次时长定义操作设定的持续时长大于前一次时长定义操作的持续时长，且相邻时长定义操作设定的低电平的持续时长可相隔 50ns～150ns。
进一步地，可重复进行多次时长定义操作，直至时长定义操作设定的持续时长大于预设时长。在理想状态下，可以设定预设时长大于一个自刷新周期，以获取最先被触发的两次自刷新操作10的起始时间点，进而得到自刷新周期和自刷新频率；在实际情况下，可以设定预设时长大于一个自刷新周期和一个刷新占用时长之和，以保证当读取操作存在延迟时，可以获取最先被触发的两次自刷新操作10的结束时间点，进而得到自刷新周期和自刷新频率。
以下将代入具体数值进行示例性说明。其中，假设自刷新操作10的刷新占用时长为600ns，自刷新周期为7μs，以时钟使能信号变为低电平的时间点作为时间轴零点，第一被触发的自刷新操作10的起始时间点为1100ns。
由于刷新占用时长为600ns，因此1100ns～1700ns这一时间段为自刷新操作10的执行时间段，在这一时间段内无法进行读取操作；进一步地，由于自刷新周期为7μs，第二个被触发的自刷新操作10的起始时间点为8100ns，第二次进行的自刷新操作10的执行时间段为8100ns～8700ns，在该时间段内同样无法进行读取操作。
假设相邻时长定义操作设定的低电平的持续时长相隔100ns，那么在100ns～1000ns内进行的10次读取操作的读取结果为成功，在1100ns～1700ns内进行的7次读取操作的读取结果为失败，在1800ns～8000ns内进行的63次读取操作的读取结果为成功，在8100ns～8700ns内进行的7次读取操作的读取结果为失败，第8800ns 进行的读取操作的读取结果为成功。
记从读取成功转换为读取失败的读取时刻为第一类读取转换时刻，第一类读取转换时刻对应自刷新操作10的起始时间点，例如1100ns和8100ns；记从读取失败转换为读取成功的读取时刻为第二类读取转换时刻，第二类读取转换时刻对应自刷新操作10的结束时间点，例如1800ns和8800ns。
本实施例中，时钟使能信号的低电平持续时长大于一个自刷新周期，根据相邻第一类读取转换时刻的时间得到存储体的自刷新周期和自刷新频率；在其他实施例中，读取操作的起始时刻相对于时钟使能信号变为低电平的时刻有延迟，这一延迟可能由读取信号的下发延迟或时长定义操作的存在引起，导致读取操作的实际开始时刻位于第一次自刷新操作10的执行时间段内，例如上述的1100ns～1700ns内，这就导致部分读取操作在时钟使能信号变为高电平之后才实际进行，使得部分低电平的持续时长对应的读取结果一定为成功，即便正跳变点位于第一次自刷新操作10的执行时间段内。
换句话说，当读取操作的实际开始时刻位于第一次自刷新操作10的执行时间段内时，第一个第一类读取转换时刻无效，实际有效地第一个读取转换时刻为第一个第二类读取转换时刻，此时，可根据相邻第二类读取转换时刻得到存储体的自刷新周期和自刷新频率；相应地，此时低电平的持续时长应当大于一个自刷新周期和一次自刷新操作的刷新占用时长之和，以保证相邻两次第二类读取转换时刻位于低电平的持续时间段内。
需要说明的是，上述数值仅为示例性说明；在其他实施例中，自刷新操作的刷新占用时长还可以为其他数值，例如500ns，自刷新周期还可以为其他数值，例如3.9μs，持续时长之差还可以为50～150ns中的其他值，例如60ns、80ns、120ns或140ns。
步骤105：根据多个低电平的持续时长和多个读取结果得到存储器的自刷新频率。
本实施例中，通过进行多次时长定义操作和多次读取操作，获取多次读取操作对应的多个读取时间和多个读取结果，进而得到存储体的自刷新周期和自刷新频率。
本实施例中，通过自刷新操作执行期间无法进行读取操作的原理进行自刷新频率的检测，当读取操作的读取时间进入自刷新操作的执行时间段内时或者超过自刷新操作的执行时间段时，读取时间对应的读取结果会发生相应改变，根据发生改变的读取结果对应的读取时间可得到自刷新操作的自刷新周期和自刷新频率，由于上述检测方法的检测原理在不同内存颗粒中通用，因此检测方法可适用于不同内存颗粒的检测，产线测试人员在进行检测时无需知晓不同内存颗粒所对应的用于输出自刷新频率的特殊测试模式，有利于提高自刷新频率检测的简便性。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保 护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种自刷新频率的检测方法，包括：
    向存储器中至少一条字线内写入数据；
    对所述存储器进行自刷新操作；
    在时钟使能信号变为低电平之后，设定所述低电平的持续时长；
    在所述时钟使能信号的正跳变点对所述存储器进行读取操作；
    获取多个所述低电平的持续时长对应的多个读取结果；
    根据多个所述低电平的持续时长和多个所述读取结果得到所述存储器的自刷新频率。
  2. 根据权利要求1所述的自刷新频率的检测方法，其中，交替进行所述低电平的持续时长的设定和所述读取操作。
  3. 根据权利要求1所述的自刷新频率的检测方法，其中，所述读取操作包括多个依次进行的读取动作，任一所述读取动作的读取结果为失败时所述读取操作的读取结果为失败。
  4. 根据权利要求1所述的自刷新频率的检测方法，其中，所述低电平持续时长的设定包括后一次所述低电平的持续时长大于前一次所述低电平的持续时长。
  5. 根据权利要求4所述的自刷新频率的检测方法，其中，任意相邻两次所述低电平的持续时长之差相等。
  6. 根据权利要求5所述的自刷新频率的检测方法，其中，所述持续时长之差为50ns～150ns。
  7. 根据权利要求4所述的自刷新频率的检测方法，其中，持续设 定所述低电平的持续时长，直至所述低电平的持续时长大于预设时长。
  8. 根据权利要求7所述的自刷新频率的检测方法，其中，所述预设时长大于一个自刷新周期，所述自刷新周期为所述自刷新频率的倒数。
  9. 根据权利要求1或8所述的自刷新频率的检测方法，其中，所述读取结果包括第一类读取转换时刻，所述第一类读取转换时刻为从读取成功转换为读取失败的读取时刻；根据相邻两个所述第一类读取转换时刻得到所述存储器的自刷新频率。
  10. 根据权利要求9所述的自刷新频率的检测方法，其中，所述自刷新周期包括7μs或3.9μs。
  11. 根据权利要求7所述的自刷新频率的检测方法，其中，所述预设时间大于一个自刷新周期与一次所述自刷新操作的时长之和，所述自刷新周期为所述自刷新频率的倒数。
  12. 根据权利要求1或11所述的自刷新频率的检测方法，其中，所述读取结果中包括第二类读取转换时刻，所述第二类读取转换时刻为从读取失败转换为读取成功的读取时刻；根据相邻两个所述第二类读取转换时刻得到所述存储器的自刷新频率。
  13. 根据权利要求12所述的自刷新频率的检测方法，其中，所述自刷新操作的时长包括600ns。
  14. 根据权利要求1所述的自刷新频率的检测方法，其中，在设定所述低电平的持续时长之前，对所有字线进行依次写入；所述读取 操作用于对所述存储器中的所有字线进行依次读取。
  15. 根据权利要求1或14所述的自刷新频率的检测方法，其中，在设定所述低电平的持续时长之前，对所有存储体进行依次写入；所述读取操作用于对所有所述存储体进行依次读取。
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