WO2022142579A1 - 一种消除带隙基准电路简并亚稳态的混合信号控制电路 - Google Patents

一种消除带隙基准电路简并亚稳态的混合信号控制电路 Download PDF

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WO2022142579A1
WO2022142579A1 PCT/CN2021/123264 CN2021123264W WO2022142579A1 WO 2022142579 A1 WO2022142579 A1 WO 2022142579A1 CN 2021123264 W CN2021123264 W CN 2021123264W WO 2022142579 A1 WO2022142579 A1 WO 2022142579A1
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circuit
delay
bandgap reference
digital
signal
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PCT/CN2021/123264
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English (en)
French (fr)
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吴边
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卓捷创芯科技（深圳）有限公司
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Priority to US17/925,302 priority Critical patent/US11892865B2/en
Publication of WO2022142579A1 publication Critical patent/WO2022142579A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay

Definitions

  • the invention belongs to the technical field of analog integrated circuits, and in particular relates to a digital and analog mixed signal control circuit for eliminating the degenerate metastability of a self-biased bandgap reference circuit in the ultra-low power consumption application field of passive radio frequency identification tags.
  • the bandgap reference circuit is widely used in the analog circuit part of semiconductor integrated circuit chips. It provides a stable and accurate reference voltage within the semiconductor integrated circuit chip that hardly changes with temperature.
  • the reference voltage is often used as a semiconductor integrated circuit chip.
  • the reference input signal of the power management module in the middle so as to generate the stable power supply voltage required by the system.
  • the bandgap reference circuit is often the first module to start up in all circuit modules, rather than being controlled by a bias control signal other than the bandgap reference circuit module, because At this time, the system has not yet generated a stable power supply, so the logic control signal determined by the logic level cannot be specified; the bandgap reference circuit often adopts a self-starting method, that is, the self-starting circuit sub-module inside the bandgap reference circuit is used in the semiconductor.
  • the self-starting method that is, the self-starting circuit sub-module inside the bandgap reference circuit is used in the semiconductor.
  • bandgap reference circuit module In a more complex system architecture of semiconductor integrated circuit chips, there may be more than one bandgap reference circuit module, which may be due to the need for multiple reference voltages of different voltages in the system architecture, or due to Different reference voltage modules need to achieve different performance indicators (such as different power supply voltage domains, different power consumption, and different temperature points to achieve the optimal zero temperature coefficient, etc.), or due to the integrated A circuit subsystem, such as a circuit IP module integrated as a black box after external procurement, has a reference voltage module itself, and so on.
  • This type of bandgap reference circuit module which exists in a semiconductor integrated circuit system with other bandgap reference modules, may also be controlled by control signals from outside its own circuit module on the basis of its own startup capability. Activate and enter the normal working state.
  • the bandgap reference circuit can generate a stable and accurate reference voltage that does not change with temperature changes is through the function of the feedback loop; in terms of topology, most of the bandgap reference circuits contain two feedback loops, which will have A physical quantity with a positive temperature coefficient, such as the voltage at a node, and a physical quantity with a negative temperature coefficient, such as the voltage at another node, are added at the intersection of the two feedback loops to obtain a positive temperature coefficient and a negative temperature coefficient.
  • the physical quantity for which the temperature coefficient almost completely cancels namely the voltage at the output node of the bandgap reference circuit.
  • the feedback loop described above has the effect of error correction. Due to the existence of the error correction function, the voltage of each node on the feedback loop in the bandgap reference circuit is accurately limited to the pre-designed DC operating point, and does not change with the temperature drift and the change of the working state of the external circuit, so the bandgap The output voltage of the reference circuit will also be stable and accurate.
  • the error correction function that is, the addition operation performed on the aforementioned topology, is provided by a differential amplifier with a dual-port input.
  • the differential pair tube composed of a pair of PMOS transistors or a pair of NMOS transistors under the bias of the bias current source, the input point voltage of the positive feedback loop and the negative feedback
  • the difference between the input point voltages of the loop is amplified, and its typical gain multiple is 60dB (ie, 1000 times), and the amplified difference signal is output to the intersection of the above two feedback loops through the output load of the differential pair tube.
  • the voltage at this point is controlled by a negative feedback loop. Because this junction is the node in the feedback system that controls the output of the bandgap reference voltage, the bandgap reference output voltage is therefore a stable and precise value.
  • the input range of the common mode voltage of the differential pair tube composed of PMOS transistors or NMOS transistors is limited.
  • the common-mode input voltage is defined as half the sum of the node voltage at the positive input terminal and the node voltage at the negative input terminal.
  • the reason for the limited common-mode input voltage range is that the current source MOS transistors that provide bias current to the differential pair transistors require a certain overdrive voltage margin to satisfy the condition that they work in a saturated state. Only when working in the saturation state, the bias current becomes a stable DC current that does not change with the input voltage of the differential pair tube. In other words, the output impedance of the DC current source is relatively large (ideally, the output impedance of the current source is gigantic).
  • the current source MOS transistors on which the input differential pair transistors depend will never be in the saturation region.
  • the working state becomes the working state in the linear region (also called the amplification region).
  • the direct consequence is that the bias current of the differential pair tube deviates from the pre-designed DC operating point value, and changes with the change of the common mode voltage of the input signal, so the amplification gain provided by the differential pair tube changes,
  • the unity-gain bandwidth of the differential amplifier has also changed, that is, both the error correction capability and the error correction response time have changed.
  • radio frequency identification tags are passive during operation, their energy comes from the direct current converted from the alternating current rectified by the radio frequency electromagnetic field after being coupled by the antenna.
  • the obtained energy is inversely proportional to the cube of the communication distance, so in order to obtain the farthest possible communication distance, the circuit inside the chip should consume as little power as possible.
  • This factor limits many complex circuit processing structures. For example, the rail-to-rail dual-input differential pair tube structure with both PMOS and NMOS transistors, which is commonly used in the industry with the ability to extend the common-mode input range, cannot be used in RFID tag chips. use.
  • the bandgap reference circuit may face the problem of metastable degeneracy point because the differential amplifier is limited and restricted by various factors. .
  • the so-called degenerate point refers to a working state of the circuit, which is significantly different from the complete rest state in which all node voltages of the circuit are zero and all branch currents are zero, and is also significantly different from the node voltage and branch current. They are all in the normal working state of the pre-designed DC operating point, but the voltage of some circuit nodes is stable in a working state that the designer does not expect.
  • the state of the circuit at the degenerate point is often not a very stable state, so it is called metastable state.
  • a circuit that is in a metastable state may go through a very long transient transition process to reach a steady state, such as returning to an off state, or entering a normal operating state.
  • a circuit system where the startup sequence of each module or the startup time of each module is critical, even if the circuit at the metastable degenerate point can finally enter the normal startup state, it will be abnormally exceeded due to the startup time. long with unintended consequences.
  • the RFID tag chips necessary for animal identification and high-end livestock breeding in today's animal husbandry are regulated by ISO11784/11785 technical standards, and the packaged products are passive passive electronic ear tags, or passive passive glass tube injection electronic tags
  • the form plays a basic electronic identification function.
  • the higher-end market demand of animal husbandry is to monitor the health status of animals at the same time on the basis of electronic identification, such as key biological health indicators such as the body temperature of livestock. This requires the integration of passive temperature sensor functions on the basis of passive passive RFID tag chips.
  • the passive RFID tag chip with integrated temperature sensor has several important characteristics of the problems faced by the aforementioned bandgap reference circuit: 1) the chip system architecture contains more than one bandgap reference circuit module; 2) the temperature sensor subsystem in the The bandgap reference circuit module not only has a self-starting circuit, but also can be activated and started by an external mode conversion control signal, for example, the radio frequency identification circuit part sends a temperature measurement enable signal to the bandgap reference circuit module in the temperature sensor; 3 ) Because this product is a passive chip product, it strives to achieve low complexity and low power consumption in terms of circuit structure and power consumption. It can be predicted that the band gap reference in the temperature sensor subsystem The amplifiers required by the circuit are also subject to several constraints that have been described earlier.
  • the bandgap reference circuit if in the above-mentioned passive passive RFID tag chip temperature sensor subsystem integrated with temperature sensor, if the bandgap reference circuit has a metastable degeneracy point, it will obviously affect the advanced temperature measurement.
  • the execution time of the instruction will affect the timing and response speed of the signal processing of the entire chip system, and even eventually cannot switch to the temperature measurement mode and the temperature measurement fails.
  • the response time with uncertain delay factor will lead to the unsmooth response of the electronic tag and the insensitive user experience of communication, and even lead to the failure of product promotion. From the point of view of power consumption, if the system experiences metastable state for too long, the bandgap reference circuit will often appear in a state of high current, thus consuming more power consumption, which is unfavorable for passive RFID tags.
  • one of the methods to solve the metastable degeneracy point that the bandgap reference circuit may encounter during the startup process is to increase the bandwidth of the feedback loop and increase the loop gain, such as reference [1] : Yeong-Tsair Lin, Wen-Yaw Chung, Dong-Shiu Wu, Ho-Cheng Lin, and Robert Lin, A Low Voltage CMOS Bandgap Reference, Proceedings of The 3rd International IEEE-NEWCAS Conference, 2005, DOI: 10.1109/NEWCAS.
  • the same error correction capability of the feedback loop can make the startup process avoid falling into the metastable degenerate point.
  • this method is not a method to directly repair the common-mode input voltage range of the differential amplifier in the loop, and it will consume a large amount of power; on the basis of consuming a certain current power consumption, the bandwidth and gain of the feedback loop will still be affected by the power supply voltage.
  • the rail-to-rail dual differential input structure can reach the maximum common-mode input range from the power supply voltage to the ground wire, such as reference [3]: William Redman-White, A High Band width Constant gm and Slew-Rate Rail-to-Rail CMOS Input Circuit and its Application to Analog Cells for Low Voltage VLSI Systems, IEEE Journal of Solid-State Circuits, Vol.32, No.5, May 1997, pp701-712.
  • This technology itself requires additional bias current to be supplied to the composite differential pair tube composed of PMOS tube and NMOS tube, which is equivalent to increasing power consumption for passive passive RFID tag chip systems.
  • the dual-input differential structure has different differential amplification gains in different common-mode input ranges, that is, the high input range near the power supply voltage and the low input range near the zero-voltage ground.
  • the difference of this loop gain in different input ranges will be affected by the influence of the power supply voltage, the influence of temperature drift, and the influence of the fluctuation of the processing parameters of the semiconductor chip; in the passive passive RFID tag chip system, such a technology It also affects the use efficiency of energy, and also causes the deviation of the output voltage of the bandgap reference, so it also has certain limitations.
  • this application proposes a method to eliminate the degeneracy and metastability of the bandgap reference circuit.
  • a state-of-the-art mixed-signal control circuit that utilizes a low-power, precision-customizable digital-to-analogue converter module (DAC), a delay switch, and a non-volatile memory cell for the band
  • DAC digital-to-analogue converter module
  • the circuit node in the degenerate metastable state in the gap reference circuit module is directly controlled and clamped, and the clamping control mechanism is released after a certain delay, which can effectively inhibit the self-biased bandgap reference circuit with an operational amplifier from entering the simple circuit.
  • metastable which enhances the robustness of the circuit, so that the reference circuit can start normally in various situations.
  • This technique is a general and general technical scheme that is widely used to eliminate various metastable degenerate points.
  • the technical solution adopted by the present invention is: a mixed-signal control circuit for eliminating the degenerate metastability of the bandgap reference circuit, comprising a start-up circuit, a mirror current unit, and a self-biased bandgap reference temperature compensation loop. circuit, output circuit and degeneracy elimination circuit,
  • the degeneracy elimination circuit includes a non-volatile storage unit, a digital-to-analog conversion module and a delay switch unit, and the non-volatile storage unit stores preset binary data, which corresponds to the self-biased bandgap reference temperature The voltage value set by a key node in the compensation loop circuit,
  • the input end of the digital-to-analog conversion module is connected to the clock signal module and the non-volatile storage unit, and is used to convert the binary data stored in the non-volatile storage unit into an analog signal, which is output and connected as a transmission signal through the delay switch unit
  • the output identification signal output by the digital-to-analog conversion module is connected to the delay signal input end of the delay switch unit, and the output identification signal is in the digital signal.
  • the analog conversion maintains a low level state before completing the conversion from binary data to an analog voltage signal, and is set to a logic high level when the digital-to-analog conversion module completes the digital-to-analog conversion;
  • the initial state of the delay switch is an on state.
  • the switch When the output identification signal of the digital-to-analog conversion module reaches the control gate of the switch after a certain delay, the switch is turned off; when the circuit is started, the delay switch is in the initial conduction state.
  • the system In the ON state, the system reads the data in the non-volatile storage unit, generates the clamping voltage value through the digital-to-analog conversion module, and connects to the clamped node in the self-biased bandgap reference circuit to compensate the temperature of the biased bandgap reference.
  • the differential amplifier in the loop circuit directly enters the DC operating point required by the design, and establishes a feedback loop with effective error correction capability; after the establishment process is completed, the delay switch is turned off.
  • the degeneracy elimination circuit completes its task and no longer affects the bandgap reference circuit, thereby avoiding the bandgap reference circuit falling into a degenerate metastable state due to the limitation of loop bandwidth and loop gain during startup.
  • the technical solution to achieve the object of the present invention further includes that the degenerate metastable elimination circuit includes a non-volatile storage unit, a digital-to-analog conversion module and a delay switch unit,
  • the non-volatile storage unit After the non-volatile storage unit reads the binary data stored therein, the data is input to a digital-to-analog conversion module, and the digital-to-analog conversion module converts the digital input signal into an analog signal and inputs it to the delay switch unit;
  • the delay switch unit is composed of a delay generation circuit, an inverter and a transmission gate circuit, wherein the two control gates of the transmission gate are respectively controlled by the output signal of the delay generation circuit and its inverted output signal , the delay signal input terminal of the delay switch unit is connected to the output identification signal output terminal of the digital-to-analog conversion module.
  • the beneficial effect of the present invention is that the problem of metastable degeneracy point faced by the bandgap reference circuit is completely solved.
  • the bandgap reference circuit is integrated into a main system, this feature can make the system integration task completely eliminate the band gap.
  • the gap reference falls into the concern of the metastable degenerate point; without the above concerns, the bandgap reference circuit itself can adopt the most optimized low-power and low-voltage design technology to improve the competitiveness of the product; on the other hand, due to the The digital information in the non-volatile storage unit is written in the wafer inspection or chip cost inspection stage. This technology can greatly reduce the direct correlation with the bandgap reference module caused by the deviation or fluctuation of the semiconductor manufacturing process. scrap rate.
  • FIG. 1 is a structural diagram of a bandgap reference circuit with constant Gm bias in the prior art
  • FIG. 2 is a structural diagram of a bandgap reference circuit with a loop amplifier in the prior art
  • FIG. 3 is a structural diagram of a bandgap reference circuit with a constant Gm bias of a start-up circuit in the prior art
  • FIG. 4 is a structural diagram of a loop amplifier bandgap reference circuit with a start-up circuit in the prior art
  • FIG. 5 is a structural diagram of a first embodiment of a self-biased bandgap reference circuit with a degenerate state elimination circuit according to the present invention
  • Embodiment 6 is a structural diagram of Embodiment 2 of a self-biased bandgap reference circuit with a degenerate state elimination circuit according to the present invention
  • Embodiment 7 is a structural diagram of Embodiment 3 of a self-biased bandgap reference circuit with a degenerate state elimination circuit according to the present invention.
  • FIG. 8 is a structural diagram of a delay generation circuit composed of an analog circuit in the degeneracy elimination circuit of the present invention.
  • Embodiment 9 is a structural diagram of Embodiment 1 of a delay generation circuit formed by a digital circuit in the degeneracy elimination circuit of the present invention.
  • FIG. 10 is a structural diagram of Embodiment 2 of a delay generation circuit composed of digital circuits in the degeneracy elimination circuit of the present invention.
  • Embodiment 11 is a structural diagram of Embodiment 3 of a delay generation circuit composed of digital circuits in the degeneracy elimination circuit of the present invention
  • FIG. 12 is a structural diagram of Embodiment 4 of the delay generation circuit composed of digital circuits in the degeneracy elimination circuit of the present invention.
  • a mixed-signal control circuit for eliminating the degenerate metastability of the bandgap reference circuit includes a start-up circuit, a mirror current unit, a self-biased bandgap reference temperature compensation loop circuit, an output circuit and a degenerate state eliminate the circuit,
  • the degeneracy elimination circuit includes a non-volatile storage unit, a digital-to-analog conversion module and a delay switch unit, and the non-volatile storage unit stores preset binary data, which corresponds to the self-biased bandgap reference temperature
  • the voltage value set by a key node in the compensation loop circuit that is, the node that is clamped by the voltage
  • the input end of the digital-to-analog conversion module is connected to the clock signal module and the non-volatile storage unit, and is used to convert the binary data stored in the non-volatile storage unit into an analog signal, which is output and connected as a transmission signal through the delay switch unit
  • the output identification signal output by the digital-to-analog conversion module is connected to the delay signal input end of the delay switch unit, and the output identification signal is in the digital signal.
  • the analog conversion maintains a low level state before completing the conversion from binary data to an analog voltage signal, and is set to a logic high level when the digital-to-analog conversion module completes the digital-to-analog conversion;
  • the initial state of the delay switch is an on state.
  • the switch When the output identification signal of the digital-to-analog conversion module reaches the control gate of the switch after a certain delay, the switch is turned off; when the circuit is started, the delay switch is in the initial conduction state.
  • the system In the ON state, the system reads the data in the non-volatile storage unit, generates the clamping voltage value through the digital-to-analog conversion module, and connects to the clamped node in the self-biased bandgap reference circuit to compensate the temperature of the biased bandgap reference.
  • the differential amplifier in the loop circuit directly enters the DC operating point required by the design, and establishes a feedback loop with effective error correction capability; after the establishment process is completed, the delay switch is turned off.
  • the degeneracy elimination circuit completes its task and no longer affects the bandgap reference circuit, thereby avoiding the bandgap reference circuit falling into a degenerate metastable state due to the limitation of loop bandwidth and loop gain during startup.
  • the bandgap reference circuit when the bandgap reference circuit starts up, due to the limitation of the bandwidth of the bandgap reference loop and the limitation of the loop gain, the two input ends of the amplifier cannot enter the optimal state at first.
  • the DC operating point cannot quickly rely on the feedback loop for error correction to reach the desired DC operating point. At this time, it will face this degenerate metastable state, and may eventually fail to complete the startup and keep falling into this degenerate metastable state.
  • the amplifier Due to the function of the auxiliary start-up circuit composed of the non-volatile memory cell array, the digital-to-analog converter DAC module and the delay switch in this technology, the amplifier is driven by the output voltage of the degeneracy elimination circuit for a period of time, so that it can directly enter the
  • the design requires the DC operating point to be reached, and a feedback loop with effective error correction capability is established. After the establishment process is completed, the delay switch is turned off, and the degeneracy elimination circuit completes its task without affecting the bandgap reference circuit.
  • the feedback loop loses error correction because the differential amplifier loses most of its differential amplification outside its common-mode input range, and in turn, getting into the proper common-mode input range depends on The role of the feedback loop, these two contradictory factors that influence each other lead to the existence of degenerate metastable states.
  • This technology is equivalent to introducing external factors to the clamped point in the bandgap reference voltage circuit. With the help of external factors, it is completely impossible for the entire bandgap reference self-starting process to enter a degenerate state.
  • the clamped node When the clamped node is the input common-mode point Vgp of the differential amplifier shown in Figure 5, its function is to directly introduce the differential amplifier into a suitable common-mode input range, so as to ensure that the differential amplifier has a sufficiently large input range.
  • the gain of the bandgap reference voltage that is, the temperature compensation loop of the bandgap reference voltage has sufficient feedback and error correction capabilities. Under such conditions, the bandgap reference voltage circuit can reliably establish the expected DC operating point, as shown in Figure 5.
  • Example 1 the output end of the digital-to-analog conversion module is output to the common mode point, Vgp, of the self-biased bandgap reference temperature compensation loop circuit through a delay switch unit, which is used to pass a preset value during the startup process.
  • the analog voltage value performs a voltage clamping operation on the common-mode voltage point, and relies on the output driving capability of the digital-to-analog conversion module to force the current bias of the differential amplifier and the bias current of the error correction loop to be established correctly, so that the bandgap
  • the reference module enters the correct DC operating point, thereby eliminating the possibility of the bandgap reference circuit entering degenerate metastability.
  • the differential amplifier can still reliably establish a balance that is consistent with the expected design.
  • the DC operating point as in the second embodiment of FIG.
  • the output terminal of the digital-to-analog conversion module is output to the positive input terminal, Va of the self-biased bandgap reference temperature compensation loop circuit through the delay switch unit;
  • the output terminal of the digital-to-analog conversion module shown in the third embodiment of FIG. 7 is output to the negative input terminal, Vb, of the self-biased bandgap reference temperature compensation loop circuit through the delay switch unit.
  • connection point no matter whether the output point of the delay switch is connected to Va, Vb, or the common mode point Vgp (hereinafter collectively referred to as the connection point), the principle can be summarized as, during the start-up process, through a preset analog
  • the voltage value performs voltage clamping operations on the above connection points (positive input terminal, negative input terminal and common mode point) respectively, and relies on the output driving capability of the DAC module to force the voltage of the above connection points to stabilize at the preset analog voltage value. This very reliably eliminates the possibility of the bandgap reference circuit entering a degenerate metastable state.
  • the pre-set analog voltage value clamped is approximately equal to the voltage value obtained by calculating and measuring the DC operating point of the bandgap reference circuit under normal working conditions, that is, these connection points are after the start-up process.
  • the voltage value that must then eventually settle to, so this clamping operation will not have any negative impact on the operation of the circuit.
  • the action of the delay switch ensures that the voltage clamping operation remains active for a certain period of time, especially when the start-up process is not completed; because of the feedback loop, the junction that is clamped to the correct voltage value affects the bandgap Other nodes in the reference circuit can stabilize to the correct DC operating point voltage faster, and play a role in assisting the completion of the self-starting process.
  • the degeneracy elimination circuit includes a non-volatile storage unit, a digital-to-analog conversion module and a delay switch unit,
  • the non-volatile storage unit After the non-volatile storage unit reads the binary data stored therein, the data is input to a digital-to-analog conversion module, and the digital-to-analog conversion module converts the digital input signal into an analog signal and inputs it to the delay switch unit;
  • the delay switch unit is composed of a delay generation circuit, an inverter and a transmission gate circuit, wherein the two control gates of the transmission gate are respectively controlled by the output signal of the delay generation circuit and its inverted output signal , the delay signal input terminal of the delay switch unit is connected to the output identification signal output terminal of the digital-to-analog conversion module.
  • non-volatile storage unit described in this technology is typically a storage medium array (cell array), an address decoding circuit (decoder), a data reading circuit ( read circuit) and logic control (logic control) circuit.
  • Non-volatile storage media refers to storage media that can still retain data under the condition of no external power supply.
  • Typical non-volatile storage media built into chips can be EEPROM storage (Electrically Erasable Programmable Read Only Memory). Read memory) and Flash storage (also known as flash memory) can play a role in maintaining data in passive passive RFID systems. When the passive RFID tag is in a completely non-working state, its pre-written data can be maintained for up to 10 years without lapse or change.
  • the N-bit digital information stored in the non-volatile unit such as 4 bits, 6 bits, or even 8 bits (which can be determined by the adjustment step size of the input range to be adjusted in this technology), when the system is working (very Obviously, what this technology considers is that the bandgap reference module is not the first module in this system to be powered on and enter the working state, but a bandgap reference module embedded in a subsystem embedded in a larger system that first enters the working state ), N-bit data is input into an N-bit digital-to-analog converter DAC module, and the analog voltage value obtained by the conversion of the DAC module is simultaneously connected to the two input ends of the OPA amplifier in the figure through a delay switch, which causes The state of the common mode input.
  • the delay switch is turned off after a preset delay time, so that the voltages of the two input terminals of the differential amplifier are determined by the feedback loop of the bandgap reference.
  • the preset delay time can be determined by an external clock signal or an analog delay network composed of resistors and capacitors.
  • the digital information in the non-volatile memory cell array can be determined according to the process inspection after the chip production is completed. For example, when the process deviation is large, a digital value suitable for the large process deviation can be written. Under normal process conditions, it is also possible to write a digital value that is very close to the DC operating point of its final design. In short, this technology can greatly reduce the bandgap reference module caused by process deviations. The bad ratio improves the adaptability of the product, that is, the yield.
  • the non-volatile storage unit may be a module with a non-volatile storage function in various forms existing in the industry, which will not be described here.
  • the non-volatile storage unit reads the binary data stored therein, the data is input to a digital-to-analog conversion module, and the digital-to-analog conversion module converts the digital input signal into an analog signal and inputs it to the delay switch unit.
  • the digital-to-analog conversion module described in this technology can be various existing circuit modules with analog-to-digital conversion function in the industry without losing the essence of simple structure and ultra-low power consumption.
  • the static performance or dynamic performance of the indicator so that a very simple design can be used to save costs, and the conversion accuracy can be the simplest 2 bits, or a slightly higher accuracy to improve the fineness of the input voltage adjustment of the differential amplifier in the bandgap reference circuit
  • its specific value can be derived from the allowable difference between the voltage value that the clamped node needs to reach and the preset ideal analog voltage value, or it can be derived from the voltage of the clamped node deviates from the known degenerate point voltage value It is derived from the degree of deviation of , and will not be described here.
  • the voltage driving capability of the digital-to-analog conversion module to the clamped node needs to ensure that before the delay switch is turned off, the voltage of the clamped node can be fully stabilized to the analog voltage value converted by the digital-to-analog converter, and there is no obvious voltage fluctuation. Or the transient change of voltage; while the digital-to-analog conversion module converts the binary data into analog voltage and outputs it to the transmission signal input terminal of the delay switch, the output identification signal of the digital-to-analog conversion module is also output to the delay signal input terminal of the delay switch.
  • the delay switch unit described in this technology is composed of a delay generation circuit, an inverter and a transmission gate circuit, wherein the two control gates of the transmission gate are respectively the output signal DAC_Complete_Delayed of the delay generation circuit and its inversion.
  • the delayed signal can be generated by an analog circuit, that is, the output identification signal of the digital-to-analog conversion module is connected to a low-pass filter, wherein the cut-off frequency of the low-pass filter determines the delay time experienced by the delayed signal, also known as asynchronous. Delay; the delay signal can also be realized by digital implementation.
  • the delay signal is The achieved delay time should be roughly not less than the response time of the temperature compensation loop of the entire bandgap reference circuit. The bandwidth limitation is ignored by the loop.
  • the delay switch is in a conducting state when the bandgap reference circuit starts up, and is turned off after a delay. After the shutdown, the effect of the start-up degeneracy elimination circuit on the bandgap reference circuit is terminated, and at this time the bandgap reference circuit has reliably completed startup without entering a degenerate metastable state.
  • the delay generation circuit includes a second resistor R2 and a first capacitor C1, the second resistor R2 and the first capacitor C1 constitutes a low-pass filter, and the output end of the low-pass filter is connected to the first control gate of the transmission gate circuit composed of the fifth P-type MOS transistor PM5 and the second N-type MOS transistor NM2, and the low-pass filter
  • the output end of the transmission gate circuit is also connected to the second control gate of the transmission gate circuit through the first inverter INV, the input end of the transmission gate circuit is connected to the output end of the digital-to-analog conversion module, and the output end of the transmission gate circuit is connected to to the voltage-clamped node in the bandgap reference circuit.
  • the above delay generation circuit is an analog RC low-pass filter to generate delay, and the input signal of the filter is the output identification signal DAC_Complete controlled by the DAC, that is, when the DAC digital-to-analog conversion is completed, the DAC_Complete signal is given to go through the RC delay to form Delay signal DAC_Complete_Delayed.
  • One channel of the delay signal DAC_Complete_Delayed is directly input to the first control gate of the transmission gate circuit, and the other channel of delay signal is formed after passing through the inverter Input to the second control gate of the transmission gate circuit.
  • the input signal of the delay part is the clock signal
  • the D flip-flop generates a divide-by-two delay or a divide-by-four delay in the middle.
  • the divide-by-two delay or divide-by-four delay The frequency delay is logically ANDed with the output identification signal DAC_Complete of the digital-to-analog conversion module to form a delay signal DAC_Complete_Delayed.
  • One channel of the delay signal DAC_Complete_Delayed is directly input to the first control gate of the transmission gate circuit, and the other channel of delay signal is formed after passing through the inverter Input to the second control gate of the transmission gate circuit, as shown in Figure 9 and Figure 10; or through a JK flip-flop to generate a divide-by-2 or divide-by-four delay, the divide-by-two delay or divide-by-four delay and the digital-to-analog conversion module
  • the output identification signal DAC_Complete is logically ANDed, and the delay signal DAC_Complete_Delayed and Input to the first and second control gates of the transmission gate circuit, respectively, as shown in Figure 11 and Figure 12.
  • the beneficial effect of the present invention is that the problem of metastable degeneracy point faced by the bandgap reference circuit is completely solved.
  • the bandgap reference circuit is integrated into a main system, this feature can make the system integration task completely eliminate the band gap.
  • the gap reference falls into the concern of the metastable degenerate point; without the above concerns, the bandgap reference circuit itself can adopt the most optimized low-power and low-voltage design technology to improve the competitiveness of the product; on the other hand, due to the The digital information in the non-volatile storage unit is written in the wafer inspection or chip cost inspection stage. This technology can greatly reduce the direct correlation with the bandgap reference module caused by the deviation or fluctuation of the semiconductor manufacturing process. scrap rate.

Abstract

一种消除自偏置带隙基准电路简并亚稳态的数字与模拟混合信号控制电路，利用一个低功耗、精度可根据需要灵活定制的数字-模拟转换器模块，一个延迟开关和非挥发性存储单元，对带隙基准电路模块中处于简并亚稳态的电路节点进行直接的控制和钳位，并经过一定延迟之后释放钳位控制机制，可以有效地抑制带运算放大器的自偏置带隙基准电路进入简并亚稳态，增强了电路的鲁棒性，使基准电路能够在各种情况下正常的启动，提高产品的性能及良品率。

Description

一种消除带隙基准电路简并亚稳态的混合信号控制电路 技术领域
本发明属于模拟集成电路技术领域，具体涉及在无源射频识别标签的超低功耗应用领域内，一种消除自偏置带隙基准电路简并亚稳态的数字与模拟混合信号控制电路。
背景技术
带隙基准电路广泛的应用于半导体集成电路芯片的模拟电路部分中，它为半导体集成电路芯片内部提供一个几乎不随温度变化的稳定、精准的参考电压，该参考电压常常被用作半导体集成电路芯片中电源管理模块的参考输入信号，从而产生系统所需要的稳定电源电压。因此，在一般的半导体集成电路芯片的系统架构中，带隙基准电路往往是所有电路模块中首先启动的一个模块，而不是由带隙基准电路模块之外的偏置控制信号所控制的，因为此时系统尚未产生稳定的电源，所以无法规定逻辑电平确定的逻辑控制信号；带隙基准电路往往采取一种自启动的方式，即由带隙基准电路内部的自启动电路子模块，在半导体集成电路芯片的电源上电过程中，从完全关断的初始状态，进入预先设计好的直流工作点的正常工作状态，从而完成自启动过程。当带隙基准电路工作在正常的直流工作点时，每一个电路节点的直流电压和每一个电路支路的直流电流，都是预先设计好的数值。
在更为复杂的半导体集成电路芯片的系统架构中，有可能存在多于一个带隙基准电路模块的情况，这可能是由于系统架构中需要多个不同电压的基准电 压的情况，也可能是由于不同的基准电压模块所需要达到的性能指标不完全相同的情况(比如电源电压域不同、功耗大小不同、和达到最优的零温度系数的温度点不同等)，或者是由于被集成进来的电路子系统，如经外部采购之后作为黑盒子集成进来的某个电路IP模块，本身就带有一个基准电压模块的情况等等。这一类与其他的带隙基准模块同存在于一个半导体集成电路系统中的带隙基准电路模块，有可能在具有自身启动的能力基础上，也会被来自自身电路模块之外的控制信号所激活而进入正常的工作状态。
带隙基准电路之所以可以产生不随温度变化而变化的稳定、精准的参考电压，是借助了反馈环路的作用；在拓扑结构上，带隙基准电路大都包含两条反馈环路，分别将具有正温度系数的物理量，如某个节点的电压，和具有负温度系数的物理量，如另一个节点的电压，在两个反馈环路的交汇点进行相加运算，从而得到一个正温度系数和负温度系数几乎完全抵消的物理量，即带隙基准电路输出节点的电压。
和模拟电路中所有的反馈环路原理一样，上述反馈环路具有纠错的作用。由于纠错功能的存在，带隙基准电路中反馈环路上的各个节点的电压都被精准的限制在预先设计的直流工作点，而不随温度漂移、外部电路工作状态的变化而变化，于是带隙基准电路的输出电压也会稳定而精准。在业界公知的电路实践中，其纠错作用，也就是前述拓扑结构上进行的相加运算，是由具有双端口输入的差分放大器所提供的。以最简单的单级差分放大器为例，由一对PMOS晶体管或者一对NMOS晶体管所组成的差分对管在偏置电流源的偏置作用下，对正反馈环路的输入点电压和负反馈环路的输入点电压的差值进行放大，其典型的增益倍数为60dB(即1000倍)，被放大的差值信号经过差分对管的输出负载而 输出到上述两个反馈环路的交汇点，实现由负反馈环路对该点电压的控制。因为该交汇点是反馈系统中控制带隙基准电压输出的节点，带隙基准输出电压因此成为稳定和精准的数值。
然而，在半导体集成电路芯片设计领域，差分放大器的实现受制于各种因素的影响。
首先，无论由PMOS晶体管还是NMOS晶体管所组成的差分对管，其共模电压输入范围都是有限的。在此，共模输入电压定义为正输入端节点电压和负输入端节点电压之和的一半。共模输入电压范围受限的原因是给差分对管提供偏置电流的电流源MOS管需要一定的过驱动电压裕度空间才能满足其工作在饱和态的条件。只有工作在饱和态，其偏置电流才成为一个稳定的、不随差分对管输入电压变化而变化的直流电流，换言之，该直流电流源的输出阻抗较大(理想情况是电流源的输出阻抗为无穷大)。当差分对管的输入共模电压过低(对于NMOS差分对管而言)或者过高(对于PMOS差分对管而言)时，输入差分对管所依赖的电流源MOS管都会从处于饱和区工作的状态变成处于线性区(也称为放大区)工作的状态。其直接的后果就是差分对管的偏置电流偏离了预先设计好的直流工作点数值，并且随输入信号的共模电压高低变化而变化，于是，差分对管所提供的放大增益发生了变化，该差分放大器的单位增益带宽也发生了变化，即纠错能力和纠错响应时间都发生了改变。
其次，本发明所关注的射频识别标签芯片领域，因为射频识别标签工作时是无源的，其能量来源于射频电磁场经天线耦合之后得到的交流电流整流之后转换而成的直流电流，天线耦合所得到的能量与通讯距离的立方成反比，故而为了得到尽可能远的通讯距离，芯片内部的电路应该消耗尽可能少的电能。这 个因素限制了很多复杂的电路处理结构，比如业界通常采用的具有扩展共模输入范围能力的轨到轨兼有PMOS和NMOS两种晶体管的双输入差分对管结构，无法在射频识别标签芯片中使用。
带隙基准电路，无论是由自启动电路启动，还是受外部控制信号使能而启动，都有可能面临因为其中的差分放大器受各种因素限制和制约而存在的亚稳态简并点的问题。所谓的简并点，是指电路存在的一个工作状态，其既明显不同于电路所有节点电压为零，并且所有支路电流也为零的完全休止状态，也明显不同于节点电压和支路电流均处于预先设计好的直流工作点的正常工作状态，而是某些电路节点电压稳定在设计人员意想不到的一个工作状态。电路处于简并点的状态往往不是一个非常稳定的状态，故此被称作亚稳态。处于亚稳态的电路或许会经过一个非常长时间的瞬态转变过程而到达一个稳态，比如其回归关断状态，或者进入正常的工作状态。在一个各模块启动的顺序、或者各模块启动的时间较为关键的电路系统中，即便是处于亚稳态简并点的电路最终能进入正常的启动状态的话，也会因为启动时间不正常地超长而带来意想不到的后果。
作为上述问题的一个详细阐述，现举一个产业实例来做说明。现今的畜牧业中动物识别和高端牲畜养殖领域所必需的射频识别标签芯片以ISO11784/11785技术标准规范，其包装后的成品以无源被动式电子耳标，或者无源被动式玻璃管注入式电子标签的形式起到了基本的电子标识的功能。然而，畜牧业更高端的市场需求是在电子标识的基础上能够同时监测动物的健康状况，比如牲畜的体温等关键生物健康指标。这就需要在无源被动式射频识别标签芯片的基础上集成无源温度传感器的功能。集成了温度传感器的无源射频识 别标签芯片具有前述的带隙基准电路所面临问题的几个重要特征：1)芯片系统架构中包含不止一个带隙基准电路模块；2)温度传感器子系统中的带隙基准电路模块既具有自启动电路，也可以被外部模式转换控制信号所激活并启动，比如，由射频识别电路部分发出测温使能信号给到温度传感器中的带隙基准电路模块；3)该产品因为是无源被动式的芯片产品，所以在电路结构方面和电能功率消耗方面都力求要求做到低复杂度和低功耗，由此可以预见，在温度传感器子系统中的带隙基准电路所需要用到的放大器也面临前面已经阐述的几种制约因素的影响。更进一步的，如果在上述集成了温度传感器的无源被动式射频识别标签芯片的温度传感器子系统中，带隙基准电路如果因为存在亚稳态的简并点，会很显然地影响到温度测量高级指令的执行时间，从而影响整个芯片系统的信号处理的时序和响应速度，甚至最终无法切换到测温的模式而测温失败。在无源被动式射频识别标签芯片的典型的应答操作中，具有不确定延迟因素的响应时间会导致电子标签的应答不顺畅和通讯不灵敏的用户使用体验，甚至导致产品推广的失败。从功耗的角度，如果系统经历亚稳态的时间过长，带隙基准电路往往会出现大电流的状态，从而消耗更多的功耗，对于无源被动式射频识别标签来说是不利的。
在现有技术中，解决带隙基准电路在启动过程中可能遇到的亚稳态简并点的方法之一就是增大反馈环路的带宽和增大环路增益，如参考文献【1】：Yeong-Tsair Lin,Wen-Yaw Chung,Dong-Shiu Wu,Ho-Cheng Lin,and Robert Lin，A Low Voltage CMOS Bandgap Reference,Proceedings of The 3rd International IEEE-NEWCAS Conference,2005,DOI:10.1109/NEWCAS.2005.1496749,ISBN:0-7803-8934-4；和参考文献【2】：Hande Vinayak Gopal,and Maryam Shojaei Baghini,Trimless,PVT Insensitive Voltage Reference using Compensation of Beta  and Thermal Voltage，2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems,pp528-533,DOI:10.1109/VLSID.2014.98。这些技术的目的是增强反馈环路的纠错能力，即当带隙基准电路模块偏离其预先设计好的直流工作点时，反馈环路可以迅速并准确无误地将带隙基准电路的各个节点拉回直流工作点并稳定下来。在启动过程中，同样的这个反馈环路的纠错能力可以使得启动过程避免陷入亚稳态简并点。但是这个方法不是直接修复环路中差分放大器共模输入电压范围的方法，会消耗较大的功耗；在耗费一定的电流功耗的基础上，反馈环路的带宽和增益仍然会受电源电压高低的影响、温度漂移的影响、和半导体芯片加工工艺参数波动的影响；在无源被动式射频识别标签芯片系统中，这样的技术影响了能量的使用效率，也会造成带隙基准输出电压的偏差，因此具有一定的局限性。
另一种方法是直接扩展反馈环路中的差分放大器的共模输入范围。在业界公知的电路结构中，轨到轨的双差分输入结构可以达到从电源电压到地线的最大共模输入范围，如参考文献【3】：William Redman-White,A High Band width Constant gm and Slew-Rate Rail-to-Rail CMOS Input Circuit and its Application to Analog Cells for Low Voltage VLSI Systems,IEEE Journal of Solid-State Circuits,Vol.32,No.5,May 1997,pp701-712。这个技术自身需要额外的偏置电流给到分别是由PMOS管和NMOS管构成的复合差分对管，对无源被动式射频识别标签芯片系统来说等同于增加了功耗。除此之外，双输入差分结构在不同的共模输入范围，即分别靠近电源电压的高输入范围区间，和靠近零电压地线的低输入范围区间，具有不同的差分放大增益。这个环路增益在不同输入范围所具有的差异性会受电源电压高低的影响、温度漂移的影响、和半导体芯片加工工艺参数 波动的影响；在无源被动式射频识别标签芯片系统中，这样的技术同样影响了能量的使用效率，也会造成带隙基准输出电压的偏差，因此也具有一定的局限性。
发明内容
本申请针对带隙基准电路中因为其内部的差分放大器有限的共模输入电压范围，造成反馈环路存在若干个亚稳态简并点的问题，提出一种消除带隙基准电路简并亚稳态的混合信号控制电路，利用一个低功耗、精度可根据需要灵活定制的数字-模拟转换器模块(Digital-to-Analogue Converter，DAC)，一个延迟开关，和非挥发性存储单元，对带隙基准电路模块中处于简并亚稳态的电路节点进行直接的控制和钳位，并经过一定延迟之后释放钳位控制机制，可以有效地抑制带运算放大器的自偏置带隙基准电路进入简并亚稳态，增强了电路的鲁棒性，使基准电路能够在各种情况下正常的启动。该技术是一种广泛适用于消除各种亚稳态简并点的一般性通用技术方案。
为实现上述技术目的，本发明所采取的技术方案为：一种消除带隙基准电路简并亚稳态的混合信号控制电路,包括启动电路，镜像电流单元，自偏置带隙基准温度补偿环路电路，输出电路和简并态消除电路，
所述简并态消除电路包括非挥发性存储单元、数模转换模块及延迟开关单元，所述非挥发性存储单元中保存有预先设置好的二进制数据，其对应于自偏置带隙基准温度补偿环路电路中某一关键节点所被设定的电压值，
所述数模转换模块输入端连接至时钟信号模块和非挥发性存储单元，用于将非挥发性存储单元中所保存的二进制数据转换为模拟信号，并经延迟开关单 元作为传输信号输出并连接至所述自偏置带隙基准温度补偿环路电路中需要被电压钳位的节点，同时，数模转换模块输出的输出标识信号接至延迟开关单元的延迟信号输入端，输出标识信号在数模转换完成从二进制数据到模拟电压信号的转换之前保持低电平状态，在数模转换模块完成数模转换的时候被置成逻辑高电平；
所述延迟开关初始态为导通状态，当数模转换模块的输出标识信号经过一定的延迟而到达该开关的控制栅极时，该开关被关断；在电路启动时，延迟开关处于初始导通状态，系统读入非挥发性存储单元中的数据，经过数模转换模块产生钳位电压值，并连入自偏置带隙基准电路中的被钳位节点，偏置带隙基准温度补偿环路电路中的差分放大器在被钳位节点的电压驱动下，直接进入设计要求达到的直流工作点，而建立起具有有效纠错能力的反馈环路；当这个建立过程完成之后，延迟开关断开，简并态消除电路完成其任务而不再影响带隙基准电路，由此避免了带隙基准电路在启动过程中因环路带宽和环路增益的限制而陷入简并亚稳态中。
实现本发明目的的技术方案还进一步的包括，所述简并亚稳态消除电路包括非挥发性存储单元、数模转换模块和延迟开关单元，
所述非挥发性存储单元读取到其中所保存的二进制数据后，输入该数据至数模转换模块，数模转换模块将数字输入信号转换为模拟信号，并输入至所述延迟开关单元；
所述延迟开关单元，由一个延迟产生电路、反相器和一个传输门电路所构成，其中传输门的两个控制栅极分别由延迟产生电路的输出信号及其反相后的输出信号所控制，延迟开关单元的延迟信号输入端接到数模转换模块的输出标 识信号输出端。
本发明的有益效果在于彻底解决了带隙基准电路所面临的亚稳态简并点的问题，在带隙基准电路被集成到一个主系统中的时候，该特征可以让系统集成任务完全消除带隙基准陷入亚稳态简并点的顾虑；在没有上述顾虑的前提下，带隙基准电路本身可以采取最为优化的低功耗低电压设计技术从而提高产品的竞争能力；在另一个方面，由于非挥发性存储单元内的数字信息是在晶圆检测或者芯片成本检测阶段才写入的，该项技术可以极大程度的降低因半导体制造工艺偏差或者波动而导致的与带隙基准模块直接相关的废品率。
附图说明
图1为现有技术中恒定Gm偏置的带隙基准电路结构图；
图2为现有技术中带环路放大器的带隙基准电路结构图；
图3为现有技术中带启动电路的恒定Gm偏置的带隙基准电路结构图；
图4为现有技术中带启动电路的环路放大器带隙基准电路结构图；
图5为本发明的带简并态消除电路的自偏置带隙基准电路实施例一结构图；
图6为本发明的带简并态消除电路的自偏置带隙基准电路实施例二结构图；
图7为本发明的带简并态消除电路的自偏置带隙基准电路实施例三结构图；
图8为本发明简并态消除电路中由模拟电路构成的延迟产生电路结构图；
图9为本发明简并态消除电路中由数字电路构成的延迟产生电路实施例一结构图；
图10为本发明简并态消除电路中由数字电路构成的延迟产生电路实施例二结构图；
图11为本发明简并态消除电路中由数字电路构成的延迟产生电路实施例三结构图；
图12为本发明简并态消除电路中由数字电路构成的延迟产生电路实施例四结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图5所示，一种消除带隙基准电路简并亚稳态的混合信号控制电路,包括启动电路，镜像电流单元，自偏置带隙基准温度补偿环路电路，输出电路和简并态消除电路，
所述简并态消除电路包括非挥发性存储单元、数模转换模块及延迟开关单元，所述非挥发性存储单元中保存有预先设置好的二进制数据，其对应于自偏置带隙基准温度补偿环路电路中某一关键节点(即被电压钳位的节点)所被设定的电压值，
所述数模转换模块输入端连接至时钟信号模块和非挥发性存储单元，用于将非挥发性存储单元中所保存的二进制数据转换为模拟信号，并经延迟开关单元作为传输信号输出并连接至所述自偏置带隙基准温度补偿环路电路中需要被电压钳位的节点，同时，数模转换模块输出的输出标识信号接至延迟开关单元的延迟信号输入端,输出标识信号在数模转换完成从二进制数据到模拟电压信 号的转换之前保持低电平状态，在数模转换模块完成数模转换的时候被置成逻辑高电平；
所述延迟开关初始态为导通状态，当数模转换模块的输出标识信号经过一定的延迟而到达该开关的控制栅极时，该开关被关断；在电路启动时，延迟开关处于初始导通状态，系统读入非挥发性存储单元中的数据，经过数模转换模块产生钳位电压值，并连入自偏置带隙基准电路中的被钳位节点，偏置带隙基准温度补偿环路电路中的差分放大器在被钳位节点的电压驱动下，直接进入设计要求达到的直流工作点，而建立起具有有效纠错能力的反馈环路；当这个建立过程完成之后，延迟开关断开，简并态消除电路完成其任务而不再影响带隙基准电路，由此避免了带隙基准电路在启动过程中因环路带宽和环路增益的限制而陷入简并亚稳态中。
在本技术所考虑的应用范围内，当带隙基准电路启动的过程中，由于带隙基准环路带宽的限制，和环路增益的限制，放大器的两个输入端一开始无法进入最理想的直流工作点，也不能很快的依靠反馈环路进行纠错从而达到我们希望的直流工作点，这时候，其便面临这一个简并亚稳态的情况，有可能最终无法完成启动而一直陷入这个简并亚稳态中。由于本技术中由非挥发性存储单元阵列、数模转换器DAC模块和延迟开关所组成的辅助启动电路的作用，放大器在一段时间内受到简并态消除电路输出电压的驱动，从而可以直接进入设计要求达到的直流工作点，而建立起具有有效纠错能力的反馈环路，当这个建立过程完成之后，延迟开关断开，简并态消除电路完成其任务而不再影响带隙基准电路。
如前所述，因为差分放大器在其共模输入范围之外丧失了绝大部分的差分 放大能力而导致反馈环路丧失了纠错能力，而反过来，进入适当的共模输入范围又依赖于反馈环路的作用，这两个互为影响的矛盾因素导致了简并亚稳态的存在。本技术相当于在带隙基准电压电路中被钳位点引入了外部因素，在外部因素的帮助下，整个带隙基准自启动过程是完全不可能进入简并态的。
当所述被钳位的节点为图5所示的差分放大器的输入共模点Vgp时，其作用是直接地把差分放大器引入了一个合适的共模输入范围，从而能够保证差分放大器具有足够大的增益，即带隙基准电压的温度补偿环路具有足够的反馈和纠错能力，在这样的条件下，带隙基准电压电路可以很可靠的建立起预期的直流工作点，如图5的实施实例一，所述数模转换模块的输出端经延迟开关单元输出至所述自偏置带隙基准温度补偿环路电路的共模点，Vgp，用于在启动过程中，通过一个预先设置的模拟电压值对所述共模电压点进行电压钳位操作，依靠数模转换模块的输出驱动能力强制所述差分放大器的电流偏置以及纠错环路的偏置电流得以正确建立，使带隙基准电压模块进入正确的直流工作点，从而消除带隙基准电路进入简并亚稳态的可能性。
当所述被钳位的节点为差分放大器的某一个差模输入点时，即便是差分输入的另一点的电压在启动过程中与被钳位点的电压不一致，由于差分放大器偏离了简并点而处于差分增益足够大的工作区域，在钳位操作结束之后，即延迟开关关断之后，在反馈环路的纠错作用下，差分放大器仍然可以很可靠地建立起与预期设计一致的平衡的直流工作点，如图6的实施例二，所述数模转换模块的输出端经延迟开关单元输出至所述自偏置带隙基准温度补偿环路电路的正输入端,Va；或者是如图7的实施例三所示的数模转换模块的输出端经延迟开关单元输出至所述自偏置带隙基准温度补偿环路电路的负输入端，Vb。
在上述所有的实施实例中无论延迟开关的输出点连接至Va、Vb、还是共模点Vgp(以下统称为连接点)，其原理均可以归纳为在启动的过程中，通过一个预先设置的模拟电压值分别对上述连接点(正输入端、负输入端及共模点)进行电压钳位的操作，依靠DAC模块的输出驱动能力强制上述连接点的电压稳定在预先设置好的模拟电压值，从而非常可靠地消除了带隙基准电路进入简并亚稳态的可能性。所述钳位到的预先设置好的模拟电压值，近似地等于通过计算和测量带隙基准电路在正常的工作状态下的直流工作点而得到的电压值，也即这些连接点在经过启动过程之后最终必须稳定到的电压值，所以该钳位操作不会对电路的运作产生任何的负面影响。而延迟开关的作用确保了电压钳位操作在一定时间内，特别是在启动过程未完成的时间内维持有效；因为反馈环路的作用，被钳位到正确电压值的连接点会影响带隙基准电路中其他节点，使其能够更快地稳定到正确的直流工作点电压上，起到了辅助完成自启动过程的作用。
所述简并态消除电路包括非挥发性存储单元、数模转换模块和延迟开关单元，
所述非挥发性存储单元读取到其中所保存的二进制数据后，输入该数据至数模转换模块，数模转换模块将数字输入信号转换为模拟信号，并输入至所述延迟开关单元；
所述延迟开关单元，由一个延迟产生电路、反相器和一个传输门电路所构成，其中传输门的两个控制栅极分别由延迟产生电路的输出信号及其反相后的输出信号所控制，延迟开关单元的延迟信号输入端接到数模转换模块的输出标识信号输出端。
其中，本技术中所述非挥发性存储单元,典型地以bit(位)或者Byte(字节)为单位的存储介质阵列(cell array)、地址译码电路(decoder)、数据读取电路(read circuit)和逻辑控制(logic control)电路所构成。非挥发性存储介质是指在无外加电源的条件下仍然可以保持数据的存储介质，典型的芯片内置的非挥发性存储介质可以是EEPROM存储(Electrically Erasable Programmable Read Only Memory，带电可擦可编程只读存储器)和Flash存储(又称闪存)，在无源被动式RFID系统中可以起到保持数据的作用，当无源RFID标签处于完全不工作的状态时，其预先写入的数据可以保持达10年的时间而不会失效或者发生改变。非挥发性单元中所存储的N比特数字信息，比如4比特、6比特、甚至8比特(其具体可以由本技术中所要调节的输入范围的调整步长而定)，在系统工作的时候(很显然，本技术所考虑的是带隙基准模块不是本系统中第一个上电进入工作状态的模块，而是一个首先进入工作状态的更大系统中嵌入的一个子系统中的带隙基准模块)，N比特的数据输入到一个N比特的数模转换器DAC模块中，DAC模块经过转换而得到的模拟电压值通过一个延迟开关而同时连接到图中OPA放大器的两个输入端，即造成共模输入的状态。该延时开关经过一个预设的延迟时间之后而断开，从而由带隙基准的反馈回路来决定差分放大器两个输入端的电压。预设的延迟时间可以由外部时钟信号来决定，也可以由电阻和电容组成的模拟延迟网络来决定，其延迟的时间应该大体相当于带隙基准反馈环路的时间常数，即等于(1/f，其中f＝环路带宽)。
非挥发性存储单元阵列中的数字信息可以根据芯片生产完成之后进行的工艺检测而决定，比如当工艺偏差较大的时候，可以写入一个适合该大幅度工艺偏差的数字值，反之，经检测在正常的工艺条件下，也可以写入一个非常接近 其最终设计的直流工作点所对应的数字值，总之，该技术可以在极大程度上降低因工艺偏差而带来的带隙基准模块的不良比率，提高了产品可适应性，即良率。
本技术中非挥发性存储单元可以是业界现有各种形式的具有非挥发性存储功能的模块，此处不加以展开叙述。所述非挥发性存储单元读取到其中所保存的二进制数据后，输入该数据至数模转换模块，数模转换模块将数字输入信号转换为模拟信号，并输入至所述延迟开关单元。
其中，本技术中所述数模转换模块，在不失结构简洁和超低功耗的精髓的基础上，可以是业界现有的各种具有模拟到数字转换功能的电路模块，不需要特别高指标的静态性能或者动态性能，从而可以采用非常简单的设计节省成本，其转换精度可以为最简单的2比特，也可以稍高一点精度以提高带隙基准电路中差分放大器输入电压调整的精细程度，其具体数值可以从被钳位节点所需要达到的电压值与预设理想的模拟电压值的允许差值推导而得到，也可以从被钳位节点的电压偏离已知的简并点电压值的偏离程度推导而得到，此处不再加以展开叙述。该数模转换模块对被钳位节点的电压驱动能力需要保证在延迟开关关断以前，被钳位节点的电压得以充分稳定到数模转换器所转换的模拟电压值，而没有明显的电压波动或者电压的瞬态变化；在数模转换模块将二进制数据转换为模拟电压输出到延迟开关的传输信号输入端的同时，数模转换模块的输出标识信号也输出到延迟开关的延迟信号输入端。
其中，本技术中所述延迟开关单元，由一个延迟产生电路、反相器和一个 传输门电路所构成，其中传输门的两个控制栅极分别由延迟产生电路的输出信号DAC_Complete_Delayed及其反相后的输出信号
Figure PCTCN2021123264-appb-000001
所控制。延迟信号可以由模拟电路的方式产生，即将数模转换模块的输出标识信号接入一个低通滤波器，其中低通滤波器的截止频率决定了延迟信号所经历的延迟时间，也称为异步的延迟；延迟信号也可以通过数字实现的方式实现，将系统时钟信号经过分频电路分频后与输出标识信号进行逻辑“与”(AND)运算而输出而得到一种同步的延迟；延迟信号所达到的延迟时间，应该大致不小于整个带隙基准电路温度补偿环路的响应时间，换言之，延迟时间大致与所述环路的时间常数可比，那么该钳位操作的作用就不会因为环路带宽的局限而被环路所忽略。无论是模拟方式实现的异步延迟还是数字逻辑方式实现的同步延迟，延迟开关在带隙基准电路启动的一开始都是处于导通状态，经过延迟之后关断。关断之后，启动简并态消除电路对带隙基准电路的影响终止，而此时带隙基准电路已经可靠地完成了启动而不会进入简并亚稳态。
当所述延迟信号由模拟电路的方式产生时，其具体的电路结构如图8所示，所述延迟产生电路包括第二电阻R2及第一电容C1，所述第二电阻R2和第一电容C1组成低通滤波器，所述低通滤波器的输出端连接至由第五P型MOS管PM5和第二N型MOS管NM2组成的传输门电路的第一控制栅极，低通滤波器的输出端还通过第一反相器INV连接至所述传输门电路的第二控制栅极，所述传输门电路的输入端连接至数模转换模块的输出端，传输门电路的输出端连接至带隙基准电路中被电压钳位的节点。
上述延迟产生电路是以模拟的RC低通滤波器产生延迟，滤波器的输入信号是由DAC控制的输出标识信号DAC_Complete，即当DAC数模转换完成后，给出 DAC_Complete信号去经过RC延迟，形成延迟信号DAC_Complete_Delayed。所述延迟信号DAC_Complete_Delayed一路直接输入至传输门电路的第一控制栅极，另一路延迟信号经过反相器后形成
Figure PCTCN2021123264-appb-000002
输入至传输门电路的第二控制栅极。
同样的，当以数字方式产生与时钟信号同步的延迟时，延迟部分的输入信号为时钟信号，中间经过D触发器产生二分频延迟或者四分频延迟，所述二分频延迟或者四分频延迟与数模转换模块的输出标识信号DAC_Complete进行逻辑“与”运算，形成延迟信号DAC_Complete_Delayed。所述延迟信号DAC_Complete_Delayed一路直接输入至传输门电路的第一控制栅极，另一路延迟信号经过反相器后形成
Figure PCTCN2021123264-appb-000003
输入至传输门电路的第二控制栅极，如图9和图10；或者经过JK触发器产生二分频或者四分频延迟，所述二分频延迟或者四分频延迟与数模转换模块的输出标识信号DAC_Complete进行逻辑“与”运算，延迟信号DAC_Complete_Delayed和
Figure PCTCN2021123264-appb-000004
分别输入至传输门电路的第一和第二控制栅极，如图11和图12。
本发明的有益效果在于彻底解决了带隙基准电路所面临的亚稳态简并点的问题，在带隙基准电路被集成到一个主系统中的时候，该特征可以让系统集成任务完全消除带隙基准陷入亚稳态简并点的顾虑；在没有上述顾虑的前提下，带隙基准电路本身可以采取最为优化的低功耗低电压设计技术从而提高产品的竞争能力；在另一个方面，由于非挥发性存储单元内的数字信息是在晶圆检测或者芯片成本检测阶段才写入的，该项技术可以极大程度的降低因半导体制造工艺偏差或者波动而导致的与带隙基准模块直接相关的废品率。

Claims (8)

  1. 一种消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:包括启动电路，镜像电流单元，自偏置带隙基准温度补偿环路电路，输出电路和简并态消除电路，
    所述简并态消除电路包括非挥发性存储单元、数模转换模块及延迟开关单元，所述非挥发性存储单元中保存有预先设置好的二进制数据，其对应于自偏置带隙基准温度补偿环路电路中某一关键节点所被设定的电压值，
    所述数模转换模块输入端连接至时钟信号模块和非挥发性存储单元，用于将非挥发性存储单元中所保存的二进制数据转换为模拟信号，并经延迟开关单元作为传输信号输出并连接至所述自偏置带隙基准温度补偿环路电路中需要被电压钳位的节点，同时，数模转换模块输出的输出标识信号接至延迟开关单元的延迟信号输入端，输出标识信号在数模转换完成从二进制数据到模拟电压信号的转换之前保持低电平状态，在数模转换模块完成数模转换的时候被置成逻辑高电平；
    所述延迟开关初始态为导通状态，当数模转换模块的输出标识信号经过一定的延迟而到达该开关的控制栅极时，该开关被关断；在电路启动时，延迟开关处于初始导通状态，系统读入非挥发性存储单元中的数据，经过数模转换模块产生钳位电压值，并连入自偏置带隙基准电路中的被钳位节点，偏置带隙基准温度补偿环路电路中的差分放大器在被钳位节点的电压驱动下，直接进入设计要求达到的直流工作点，而建立起具有有效纠错能力的反馈环路；当这个建立过程完成之后，延迟开关断开，简并态消除电路完成其任务而不再影响带隙基准电路，由此避免了带隙基准电路在启动过程中因环路带宽和环路增益的限制而陷入简并亚稳态中。
  2. 如权利要求1所述的消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:所述数模转换模块的输出端经延迟开关单元输出至所述自偏置带隙基准温度补偿环路电路的共模点，用于在启动过程中，通过一个预先设置的模拟电压值对所述共模电压点进行电压钳位操作，依靠数模转换模块的输出驱动能力强制所述差分放大器的电流偏置以及纠错环路的偏置电流得以正确建立，使带隙基准电压模块进入正确的直流工作点，从而消除带隙基准电路进入简并亚稳态的可能性。
  3. 如权利要求1所述的消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:所述数模转换模块的输出端经延迟开关单元输出至所述自偏置带隙基准温度补偿环路电路的正输入端，用于在启动过程中，通过一个预先设置的模拟电压值对所述正输入端进行电压钳位操作，依靠数模转换模块的输出驱动能力强制所述正输入端的电压稳定在预先设置好的模拟电压值，从而消除带隙基准电路进入简并亚稳态的可能性。
  4. 如权利要求1所述的消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:所述数模转换模块的输出端经延迟开关单元输出至所述自偏置带隙基准温度补偿环路电路的负输入端，用于在启动过程中，通过一个预先设置的模拟电压值对所述负输入端进行电压钳位操作，依靠数模转换模块的输出驱动能力强制所述负输入端的电压稳定在预先设置好的模拟电压值，从而消除带隙基准电路进入简并亚稳态的可能性。
  5. 如权利要求1所述的消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:所述简并态消除电路包括非挥发性存储单元、数模转换模块和延迟开关单元，
    所述非挥发性存储单元读取到其中所保存的二进制数据后，输入该数据至数模转换模块，数模转换模块将数字输入信号转换为模拟信号，并输入至所述延迟开关单元；
    所述延迟开关单元，由一个延迟产生电路、反相器和一个传输门电路所构成，其中传输门的两个控制栅极分别由延迟产生电路的输出信号及其反相后的输出信号所控制，延迟开关单元的延迟信号输入端接到数模转换模块的输出标识信号输出端。
  6. 如权利要求5所述的消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:当所述延迟产生电路为模拟电路时，所述延迟产生电路包括第二电阻R2及第一电容C1，所述第二电阻R2和第一电容C1组成低通滤波器，所述低通滤波器的输出端连接至由第五P型MOS管PM5和第二N型MOS管NM2组成的传输门电路的第一控制栅极，低通滤波器的输出端还通过第一反相器INV连接至所述传输门电路的第二控制栅极，所述传输门电路的输入端连接至数模转换模块的输出端，传输门电路的输出端连接至带隙基准电路中被电压钳位的节点。
  7. 如权利要求5所述的消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:当所述延迟产生电路为数字电路时，延迟部分的输入信号为时钟信号，中间经过D触发器产生二分频延迟或者四分频延迟，所述二分频延迟或者四分频延迟与数模转换模块的输出标识信号进行逻辑与运算，形成延迟信号。
  8. 如权利要求5所述的消除带隙基准电路简并亚稳态的混合信号控制电路,其特征在于:当所述延迟产生电路为数字电路时，延迟部分的输入信号为时钟信号，中间经过JK触发器产生二分频延迟或者四分频延迟，所述二分频延迟或者四分频延迟与数模转换模块的输出标识信号进行逻辑与运算，形成延迟信号。
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