WO2022142357A1 - 密封环结构及其制备方法 - Google Patents

密封环结构及其制备方法 Download PDF

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Publication number
WO2022142357A1
WO2022142357A1 PCT/CN2021/112134 CN2021112134W WO2022142357A1 WO 2022142357 A1 WO2022142357 A1 WO 2022142357A1 CN 2021112134 W CN2021112134 W CN 2021112134W WO 2022142357 A1 WO2022142357 A1 WO 2022142357A1
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WIPO (PCT)
Prior art keywords
diode group
electrode
high electron
electron mobility
mobility transistor
Prior art date
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PCT/CN2021/112134
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English (en)
French (fr)
Inventor
林科闯
徐宁
刘成
何俊蕾
林育赐
赵杰
叶念慈
Original Assignee
厦门市三安集成电路有限公司
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Application filed by 厦门市三安集成电路有限公司 filed Critical 厦门市三安集成电路有限公司
Publication of WO2022142357A1 publication Critical patent/WO2022142357A1/zh
Priority to US18/342,560 priority Critical patent/US20230361056A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605—Resistors with PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to the technical field of integrated circuits, in particular, to a semiconductor device, and relates to a sealing ring structure and a preparation method thereof.
  • Electro-Static discharge is a phenomenon of charge release and transfer between integrated circuit chips and external objects. Since a large amount of charge is released in a short period of time, the energy generated by ESD is much higher than the chip's ability to withstand, so it is likely to cause temporary failure or even permanent damage to the function of the chip. Therefore, in order to avoid damage to integrated circuits by static electricity as much as possible, electrostatic discharge protection design is very important in improving product reliability and yield.
  • an integrated circuit is provided with an electrostatic protection structure alone, so as to protect the integrated circuit when static electricity occurs.
  • the separately provided electrostatic protection structure will occupy a certain chip area of the integrated circuit, thereby increasing the chip area of the device, which is not conducive to the miniaturization of the device.
  • the purpose of the present invention is to provide a sealing ring structure and a preparation method thereof, which can utilize the sealing ring area to realize the electrostatic protection function, thereby saving the area of the device.
  • a seal ring structure in one aspect of the present invention, includes an enhancement mode high electron mobility transistor, a diode group and a resistor fabricated by a semiconductor epitaxial layer, and the enhancement mode high electron mobility transistor is used to surround the semiconductor
  • the diode group and the resistor are used to be arranged on the periphery of the device area; the anode of the diode group is used for metal connection with the first electrode of the semiconductor device, and the cathode of the diode group is connected with the first metal terminal of the resistor.
  • the second metal terminal is used for metal connection to the second electrode of the semiconductor device; the gate of the enhancement mode high electron mobility transistor is connected to the cathode metal of the diode group, and the drain of the enhancement mode high electron mobility transistor is used to connect with the first electrode metal Connection, the source of the enhancement mode high electron mobility transistor is used for metal connection with the second electrode of the semiconductor device.
  • the sealing ring structure can utilize the sealing ring area to realize the electrostatic protection function, thereby saving the area of the device.
  • the first electrode is the gate electrode of the semiconductor device, and the second electrode is the source electrode of the semiconductor device; or, the first electrode is the source electrode of the semiconductor device, and the second electrode is the gate electrode of the semiconductor device.
  • the diode group includes 3 to 7 diodes connected in series in sequence.
  • the diode group includes a vertical diode group and/or a lateral diode group, the lateral diode group is distributed on the lateral side of the device area, and the vertical diode group is distributed on the vertical side of the device area; when the diode group includes a vertical diode group and a horizontal diode group.
  • the vertical diode group and the horizontal diode group are connected in series, and the anode of the vertical diode group is connected to the first electrode metal, and the cathode of the horizontal diode group is connected to the first metal terminal metal.
  • the resistors and vertical diode groups are distributed on opposite sides of the device region; the vertical diode group includes at least one diode; and the lateral diode group includes at least one diode.
  • the vertical diode group includes two diodes connected in series
  • the lateral diode group includes four diodes connected in series.
  • the vertical diode group and the lateral diode group respectively comprise three diodes connected in series in sequence.
  • the length of the gate of the enhancement mode high electron mobility transistor along the first direction is between 0.5 ⁇ m and 1.0 ⁇ m; the source electrode of the enhancement mode high electron mobility transistor and the gate electrode of the enhancement mode high electron mobility transistor The distance along the first direction is between 0.5 ⁇ m and 1.5 ⁇ m.
  • the distance between the anode of the diode and the cathode of the diode along the first direction is between 1.5 ⁇ m and 3.0 ⁇ m, and the gate of the enhancement mode high electron mobility transistor and the drain of the enhancement mode high electron mobility transistor are along the first direction.
  • the distance of the directions is between 1.5 ⁇ m and 3.0 ⁇ m.
  • the semiconductor epitaxial layer includes a substrate, a buffer layer, a channel layer, a potential barrier layer and a P-type nitride layer stacked in sequence;
  • the enhancement mode high electron mobility transistor includes a source electrode and a drain electrode arranged on the potential barrier layer, The gate is arranged on the P-type nitride layer;
  • the diode group includes an anode arranged on the P-type nitride layer and a cathode arranged on the barrier layer; the resistance is arranged on the first metal terminal and the second metal on the barrier layer Terminals; enhanced high electron mobility transistors, diode groups, and resistors are isolated by isolation regions.
  • Another aspect of the present invention provides a method for preparing a seal ring structure, the method comprising: sequentially forming a buffer layer, a channel layer, a barrier layer and a P-type nitride layer on a substrate; and etching the P-type nitride layer to define the P-type nitride layer in the enhancement mode high electron mobility transistor region, the P-type nitride layer in the diode group region, and remove the P-type nitride layer in the resistance region, wherein the enhancement mode high electron mobility transistor
  • the area ring is arranged on the periphery of the device area of the semiconductor device, and the diode group area and the resistance area are arranged on the periphery of the device area; the source and drain electrodes of the enhancement mode high electron mobility transistor, the cathode of the diode group, and the first electrode of the resistor are prepared respectively.
  • the metal terminal and the second metal terminal; the active region of the enhancement mode high electron mobility transistor, the active region of the diode group and the active region of the resistance are defined by ion implantation; the enhancement mode high electron mobility transistor is separately prepared
  • the gate of the diode group and the anode of the diode group respectively connect the anode of the diode group to the first electrode metal of the semiconductor device, connect the cathode of the diode group to the metal of the first metal end of the resistor, and the second metal end of the resistor to the metal of the semiconductor device.
  • the second electrode metal is connected; the gate of the enhancement mode high electron mobility transistor is connected to the cathode metal of the diode group, the drain of the enhancement mode high electron mobility transistor is connected to the first electrode metal, and the source of the enhancement mode high electron mobility transistor
  • the electrode is metallically connected to the second electrode of the semiconductor device.
  • separately preparing the source and drain of the enhancement mode high electron mobility transistor, the cathode of the diode group, and the first metal end and the second metal end of the resistor include: preparing separately by means of evaporation or sputtering.
  • the source and drain of the enhancement mode high electron mobility transistor, the cathode of the diode bank, and the first and second metal terminals of the resistor include: preparing separately by means of evaporation or sputtering.
  • This embodiment provides a sealing ring structure, the sealing ring structure includes an enhancement mode high electron mobility transistor, a diode group and a resistor fabricated by a semiconductor epitaxial layer, and the enhancement mode high electron mobility transistor is used for a device surrounding a semiconductor device
  • the diode group and the resistor are used to be arranged on the periphery of the device area
  • the anode of the diode group is used for metal connection with the first electrode of the semiconductor device
  • the cathode of the diode group is connected with the first metal end of the resistor, and the second metal of the resistor
  • the terminal is used for metal connection to the second electrode of the semiconductor device
  • the gate of the enhancement mode high electron mobility transistor is connected to the cathode metal of the diode group, and the drain of the enhancement mode high electron mobility transistor is used to connect with the first electrode metal
  • the enhancement mode The source of the high electron mobility transistor is used for metal connection with the second electrode of the semiconductor device.
  • the enhancement mode high electron mobility transistor annularly arranged on the periphery of the device region of the semiconductor device can realize the mechanical protection of the device region, avoid the damage of the device region by stress or impurities during the cutting process, and when the first part of the semiconductor device is
  • the sealing ring structure will conduct the positive charge under the action of the diode group and the enhanced high electron mobility transistor to realize electrostatic discharge;
  • the sealing ring structure will conduct the negative charges away through the enhancement mode high electron mobility transistor, thereby realizing electrostatic discharge.
  • the sealing ring structure of the present application can realize both mechanical protection of the semiconductor device and electrostatic protection of the semiconductor device, so that the semiconductor device does not need to be provided with a separate electrostatic protection structure and saves the area of the device.
  • FIG. 1 is a schematic diagram of a layout structure of a sealing ring structure provided by an embodiment of the present invention
  • FIG. 2 is an equivalent circuit diagram of a sealing ring structure provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an enhancement mode high electron mobility transistor with a seal ring structure according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a diode provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a resistor provided by an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a method for preparing a sealing ring structure according to an embodiment of the present invention.
  • Icons 10 - Enhancement Mode High Electron Mobility Transistor; 11 - Enhancement Mode High Electron Mobility Transistor Source; 12 - Enhancement Mode High Electron Mobility Transistor Gate; 13 - Enhancement Mode High Electron Mobility Transistor Drain 20-diode group; 21-vertical diode group; 22-transverse diode group; 23-diode; 231-diode anode; 232-diode cathode; 30-resistor; 31-first metal terminal; 32-second metal 40-device region; 41-gate of semiconductor device; 42-source of semiconductor device; a-first direction; 50-non-functional region; 51-substrate; 52-buffer layer; 53-channel layer 54-barrier layer; 55-P-type nitride layer.
  • horizontal does not imply that a component is required to be absolutely horizontal or overhang, but rather may be slightly inclined.
  • horizontal only means that its direction is more horizontal than “vertical”, it does not mean that the structure must be completely horizontal, but can be slightly inclined.
  • the terms “arranged”, “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection, It can also be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or the internal communication between the two components.
  • the specific meanings of the above terms in the present invention can be understood in specific situations.
  • dicing lanes are formed between the chips formed on the wafer, and the wafer is cut through the dicing lanes to divide the wafer into a plurality of chips.
  • stress and impurities will be generated, which may cause damage to the chip.
  • a surrounding area between the dicing road and the chip will be formed.
  • the chip is provided with a stress protection ring, that is, a sealing ring structure.
  • the seal ring structure is a very important part in the back-end process of semiconductor manufacturing.
  • the existing sealing ring structure only has a mechanical stress protection function, and does not have electrostatic discharge (Electro-Static discharge, ESD) protection function.
  • ESD Electro-Static discharge
  • a corresponding electrostatic protection structure needs to be provided separately.
  • the electrostatic protection structure provided separately will occupy the area of the device. Therefore, the present application improves the existing sealing ring structure, so that the The sealing ring structure has an electrostatic protection function, so that the sealing ring structure can use the sealing ring area to realize the electrostatic protection function, thereby saving the area of the device.
  • the sealing ring area is located at the outer periphery of the device area, and the sealing ring structure provided in the present application hereinafter is provided in the sealing ring area.
  • the present embodiment provides a seal ring structure including an enhancement mode high electron mobility transistor 10 , a diode group 20 and a resistor 30 fabricated by a semiconductor epitaxial layer.
  • the enhancement mode high electron mobility transistor 10 The diode group 20 and the resistor 30 are used to be arranged around the periphery of the device area 40 of the semiconductor device (also the chip area of the semiconductor device), and the diode group 20 and the resistor 30 are used to be arranged around the periphery of the device area 40; the anode of the diode group 20 is used to connect with the first electrode of the semiconductor device.
  • the cathode of the diode group 20 is metally connected to the first metal terminal 31 of the resistor 30, and the second metal terminal 32 of the resistor 30 is used for metal connection to the second electrode of the semiconductor device;
  • the gate 12 of the enhancement mode high electron mobility transistor It is connected with the cathode metal of the diode group 20, the drain electrode 13 of the enhancement mode high electron mobility transistor is used for connecting with the first electrode metal, and the source electrode 11 of the enhancement mode high electron mobility transistor is used for connecting with the second electrode metal of the semiconductor device. connect.
  • the sealing ring structure can utilize the sealing ring area to realize the electrostatic protection function, thereby saving the area of the device.
  • the above-mentioned enhancement mode high electron mobility transistor 10 is used to surround the outer periphery of the device region 40 of the semiconductor device, that is, the enhancement mode high electron mobility transistor 10 of this embodiment is in a closed ring shape, as shown in FIG. 1 .
  • the enhanced high electron mobility transistor 10 can be arranged around the outer periphery of the device region 40, and the device region 40 can be fully sealed and protected, so as to avoid the stress generated during the cutting process of the wafer self-cutting road Or the impurities cause damage to the device region 40 .
  • the first metal end 31 of the resistor 30 is the positive electrode of the resistor 30
  • the second metal end 32 of the resistor 30 is the negative electrode of the resistor 30 .
  • the diode group 20 and the resistor 30 are respectively used to be arranged between the enhancement mode high electron mobility transistor 10 and the device region 40; of course, the enhancement mode high electron mobility transistor 10 can also be used to arrange the periphery of the device region 40, and the diode group 20 and the resistor 30 are respectively disposed on the periphery of the enhancement mode high electron mobility transistor 10 , in other words, the enhancement mode high electron mobility transistor 10 is disposed between the diode group 20 and the resistor 30 and the device region 40 .
  • the diode group 20 may be formed by connecting a plurality of diodes 23 in series. Specifically, the number of diodes 23 in the diode group 20 can be determined by those skilled in the art according to the actual situation. In this embodiment, optionally, the diode group 20 includes 3 to 7 diodes 23 connected in series in sequence. For example, The diode group 20 may include five diodes 23 connected in series; alternatively, the diode group 20 may include six diodes 23 connected in series.
  • the plurality of diodes 23 and the resistors 30 in the diode group 20 can also be sequentially connected in series and then arranged around the periphery of the device region 40 , in other words, the distance between each diode 23 and the device region 40 are equal, and the distance between each diode 23 and the device region 40 and the distance between the resistor 30 and the device region 40 are also the same (please refer to FIG. 1, FIG. 1 is that the resistor 30 and each diode 23 are arranged around the device region 40, so that the device Zone 40 is protected on three sides).
  • each diode 23 and resistor 30 can also be wound around the outer periphery of the device region 40 , so as to achieve the sealing protection of the device region 40 to a certain extent.
  • the above-mentioned resistors 30 and the plurality of diodes 23 may be uniformly distributed on the periphery of the device area 40 (which can achieve all-round protection of the four sides of the device area 40 ), or may be randomly distributed on the periphery of the device area 40 . Therefore, those skilled in the art can decide according to actual needs.
  • each diode 23 and the resistor 30 are arranged along the outer periphery of the device region 40 , which can further reduce the influence of the cutting process on the device region 40 .
  • the sealing ring structure provided in this embodiment may also have a certain distance from the device region 40 (specifically, the diode group 20 and the resistor 30 respectively There is a certain distance from the device region 40 ), for example, it can be 10 ⁇ m or the like.
  • FIG. 2 is an equivalent circuit structure of the sealing ring structure.
  • the anode of the diode group 20 is used for metal connection with the first electrode of the semiconductor device, and the cathode of the diode group 20 is connected to the first electrode of the resistor 30 .
  • the metal terminal 31 is metal-connected, and the second metal terminal 32 of the resistor 30 is used for metal connection with the second electrode of the semiconductor device.
  • the gate 12 of the enhancement mode high electron mobility transistor is connected to the cathode metal of the diode group 20, the drain electrode 13 of the enhancement mode high electron mobility transistor is used to connect to the first electrode metal, and the source electrode of the enhancement mode high electron mobility transistor 11 is used for metal connection with the second electrode of the semiconductor device.
  • the diode group 20 is turned on and passes through the diode The current of group 20 flows through resistor 30 to discharge the charge. In addition, after the current flows through the diode group 20, a high voltage is generated at point B relative to the ground. If the high voltage is greater than the threshold voltage of the enhancement mode high electron mobility transistor 10 (the threshold voltage is 1V to 2V), then the enhancement mode high electron mobility transistor 10.
  • the electron mobility transistor 10 will also be turned on, further conducting away the charges accumulated at point A, thereby realizing electrostatic discharge; when the first electrode of the semiconductor device accumulates negative charges, and a negative voltage is generated at point A relative to the second electrode, Due to the reverse conduction characteristic of the enhancement mode high electron mobility transistor 10, the enhancement mode high electron mobility transistor 10 is turned on in the reverse direction, and negative charges are conducted through the enhancement mode high electron mobility transistor 10, thereby realizing electrostatic discharge.
  • the first electrode is the gate electrode 41 of the semiconductor device
  • the second electrode is the source electrode 42 of the semiconductor device.
  • the seal ring structure can realize electrostatic discharge protection for the gate electrode 41 of the semiconductor device.
  • the first electrode may also be the source electrode 42 of the semiconductor device, and the second electrode may be the gate electrode 41 of the semiconductor device.
  • the anode of the diode group 20 is connected to the source electrode 42 of the semiconductor device, and the source electrode 11 of the enhancement mode high electron mobility transistor is connected to the gate electrode 41 of the semiconductor device.
  • Pole 42 implements electrostatic discharge protection. Since the sealing ring structure realizes electrostatic protection for the source electrode 42 of the semiconductor device and realizes electrostatic protection for the gate electrode 41 of the semiconductor device in the same principle, both can refer to the previous description of the electrostatic protection of the first electrode, and will not be repeated here. .
  • the present embodiment provides a seal ring structure, the seal ring structure includes an enhancement mode high electron mobility transistor 10, a diode group 20 and a resistor 30 fabricated through a semiconductor epitaxial layer, the enhancement mode high electron mobility transistor 10
  • the diode group 20 and the resistor 30 are used to be arranged around the periphery of the device area 40 of the semiconductor device, and the diode group 20 and the resistor 30 are used to be arranged on the periphery of the device area 40;
  • the anode of the diode group 20 is used to connect with the first electrode metal of the semiconductor device, and the cathode of the diode group 20
  • the first metal terminal 31 of the resistor 30 is metally connected, and the second metal terminal 32 of the resistor 30 is used for metal connection to the second electrode of the semiconductor device;
  • the gate 12 of the enhancement mode high electron mobility transistor is metally connected to the cathode of the diode group 20 , the drain 13 of the enhancement mode high electron mobility transistor is used for connecting with the first
  • the enhancement mode high electron mobility transistor 10 annularly arranged on the periphery of the device region 40 can realize the mechanical protection of the device region 40, avoid the device region 40 from being damaged by stress or impurities during the cutting process, and when the first part of the semiconductor device is When a high voltage is generated on one electrode relative to the second electrode due to the accumulation of positive charges, the sealing ring structure will conduct the positive charges under the action of the diode group 20 and the enhancement mode high electron mobility transistor 10 to realize electrostatic discharge; when the semiconductor device When the negative voltage is generated relative to the second electrode due to the accumulation of negative charges on the first electrode, the sealing ring structure will conduct the negative charges away through the enhancement mode high electron mobility transistor 10 to realize electrostatic discharge.
  • the sealing ring structure of the present application can realize not only mechanical protection for the device region 40 but also electrostatic protection for the device region 40 , so that the semiconductor device does not need to be provided with a separate electrostatic protection structure and saves the area of the device.
  • the diode group 20 includes a vertical diode group 21 and/or a horizontal diode group 22, the horizontal diode group 22 is distributed on the lateral side of the device region 40, and the vertical diode group 21 is distributed on the vertical side of the device region 40; when the diode group 20 When the vertical diode group 21 and the horizontal diode group 22 are included, the vertical diode group 21 and the horizontal diode group 22 are connected in series, the anode of the vertical diode group 21 is connected to the first electrode metal, and the cathode of the horizontal diode group 22 is connected to the first metal of the resistor 30. Terminal 31 metal connection.
  • the vertical diode groups 21 and the lateral diode groups 22 are distributed on adjacent two sides of the device region 40 .
  • the vertical diode group 21 is formed by connecting the diodes 23 on the left side of the device region 40 in series
  • the lateral diode group 22 is formed by connecting the diodes 23 on the upper side of the device region 40 in series. of. Distributing the diode groups 20 on two adjacent sides of the device region 40 facilitates the electrical connection between the vertical diode group 21 and the lateral diode group 22 , and further improves the stress protection effect on the device region 40 .
  • the orientations involved in this embodiment are all provided on the basis of the accompanying drawings in the description, so as to facilitate understanding, and should not be regarded as a specific limitation to the present application.
  • the above-mentioned diode group 20 may also only include the vertical diode group 21 or the lateral diode group 22 .
  • the resistor 30 and the vertical diode group 21 are distributed on opposite sides of the device region 40, the vertical diode group 21 includes at least one diode 23, and the lateral diode group 22 includes at least one diode 23. In this way, the vertical diode group 21, the lateral diode group The resistors 22 and the resistors 30 can be distributed on three sides of the device region 40 , so as to realize multi-directional protection of the device region 40 .
  • the vertical diode group 21 includes two diodes 23 connected in series, and the lateral diode group 22 includes four diodes 23 connected in series.
  • the vertical diode group 21 is distributed on the short side of the device area 40, and the lateral diode group 22 is distributed on the long side of the device area 40. In this way, the uniform distribution of the diodes 23 can be achieved to a certain extent, and the protection effect of the semiconductor device is better. .
  • the vertical diode group 21 and the lateral diode group 22 respectively include three diodes 23 connected in series. In this way, it can be applied to the case where the adjacent two sides of the device region 40 have the same length, for example, when the cross-section of the device region 40 is square.
  • the specific distribution of the diode groups 20 can be determined by those skilled in the art according to the actual situation. The above two methods are only two examples of the present application and should not be considered as limitations of the present application.
  • each diode 23 is fabricated based on the enhancement mode high electron mobility transistor 10 during fabrication, that is, the enhancement mode high electron mobility transistor 10 is fabricated first
  • the enhancement mode high electron mobility transistor 10 is prepared from the region of the diode group 10 and the region of the diode group 20, and then the gate 12 of the enhancement mode high electron mobility transistor and the source of the enhancement mode high electron mobility transistor in the region of the diode group 20 are connected.
  • the poles 11 are interconnected by metal to form the anode 231 of the diode.
  • the distance between the gate electrode 12 of the enhancement mode high electron mobility transistor and the source electrode 11 of the enhancement mode high electron mobility transistor along the first direction a is between 0.5 ⁇ m and 1.5 ⁇ m.
  • the above-mentioned first direction a can be referred to as shown in FIG. 3 to FIG. 5 .
  • the length of the gate 12 of the enhancement mode high electron mobility transistor along the first direction a is between 0.5 ⁇ m and 1.0 ⁇ m.
  • the distance between the gate 12 of the enhancement mode high electron mobility transistor and the drain 13 of the enhancement mode high electron mobility transistor along the first direction a is between 1.5 ⁇ m and 3.0 ⁇ m.
  • the width of the gate 12 of the enhancement mode high electron mobility transistor along the second direction is between 10000 ⁇ m and 20000 ⁇ m, wherein the second direction is perpendicular to the first direction a.
  • the size of the diode 23 in the first direction a is the same as that of the enhancement mode high electron mobility transistor 10, but optionally, in the pre-fabrication process of the diode 23, its gate (before the metal interconnection of the diode 23 has not yet formed an anode, but has a gate at this time) and the gate 12 of the enhancement mode high electron mobility transistor may have a different width in the second direction.
  • the gate of the diode 23 may have a width of 400 ⁇ m in the second direction. to 1000 ⁇ m.
  • the gate of diode 23 (the diode 23 has no anode before the metal interconnection and has a gate at this time) and the source of diode 23 (the diode 23 has no anode before the metal interconnection and has a source electrode at this time) ) along the first direction a is between 0.5 ⁇ m and 1.5 ⁇ m
  • the length of the gate of the diode 23 along the first direction a is between 0.5 ⁇ m and 1.0 ⁇ m
  • the anode 231 of the diode and the cathode 232 of the diode are along the first direction a.
  • the distance of the direction a may be between 1.5 ⁇ m and 3.0 ⁇ m.
  • the length of the resistor 30 may be between 3.0 ⁇ m and 4.0 ⁇ m, and the width of the resistor 30 may be between 2000 ⁇ m and 2500 ⁇ m.
  • the above-mentioned semiconductor epitaxial layer includes a substrate 51 , a buffer layer 52 , a channel layer 53 , a barrier layer 54 and a P-type nitride layer 55 that are stacked in sequence.
  • the enhancement mode high electron mobility transistor 10 includes a source electrode and a drain electrode provided on the barrier layer 54, a gate electrode provided on the P-type nitride layer 55; the diode group 20 includes an anode electrode provided on the P-type nitride layer 55 And set the cathode on the barrier layer 54 ; the resistor 30 is set on the first metal terminal 31 and the second metal terminal 32 on the barrier layer 54 .
  • the enhancement mode high electron mobility transistor 10, the diode group 20, and the resistor 30 are isolated by an isolation region.
  • FIG. 6 another aspect of the present invention provides a method for preparing a sealing ring structure, the method comprising:
  • a buffer layer 52 a buffer layer 52 , a channel layer 53 , a barrier layer 54 and a P-type nitride layer 55 are sequentially formed on the substrate 51 .
  • the barrier layer 54 may be an AlGaN barrier layer, and its thickness may be between 1 nm and 50 nm.
  • the channel layer 53 may be a GaN channel layer
  • the P-type nitride layer 55 may be a P-GGaN layer.
  • the thickness of the P-type nitride layer 55 can be between 50 nm and 300 nm, and the doping concentration is between 1017-1021 cm-3.
  • sealing ring of the present invention is used to seal and protect the device region 40 in all directions, so as to avoid damage to the device region 40 caused by stress or impurities generated in the process of cutting the wafer self-dicing line.
  • the P-type nitride layer 55 is etched to define the P-type nitride layer in the enhancement mode high electron mobility transistor 10 region, the P-type nitride layer in the diode group 20 region, and the P-type nitrogen in the resistor 30 region is removed
  • the compound layer 55 is formed, wherein the enhancement mode high electron mobility transistor 10 is arranged on the periphery of the device region 40 of the semiconductor device, and the diode group 20 region and the resistor 30 region are arranged on the periphery of the device region 40 .
  • the P-type nitride layer 55 formed in the above step S100 is etched to define the P-type nitride layer 55 of the enhancement mode high electron mobility transistor 10 region and the diode group 20 region respectively, and all the resistors 30 are etched away. P-type nitride layer 55 in the region.
  • the above-mentioned etching process may adopt ICP etching.
  • a P-type nitride layer 55 should be defined in the corresponding region of each diode 23 .
  • the source 11 of the enhancement mode high electron mobility transistor, the drain electrode 13 of the enhancement mode high electron mobility transistor, the cathode of the diode group 20, and the first metal terminal 31 of the resistor 30 ie the resistor 30
  • the positive electrode of the resistor 30 and the second metal terminal 32 ie, the negative electrode of the resistor 30
  • the device region 40 can be formed on the periphery of the device region 40 and arranged around the device region 40
  • a ring-shaped enhancement type high electron mobility transistor 10 is formed, and a diode group 20 and a resistor 30 can be formed between the enhancement type high electron mobility transistor 10 and the device region 40 .
  • step S300 respectively preparing the source 11 and the drain of the enhancement mode high electron mobility transistor, the cathode of the diode group 20, and the first metal terminal 31 and the second metal terminal 32 of the resistor 30, you can for:
  • the source electrode 11 and the drain electrode of the enhancement mode high electron mobility transistor, the cathode electrode of the diode group 20 , and the first metal terminal 31 and the second metal terminal 32 of the resistor 30 are respectively prepared by evaporation or sputtering.
  • the metal systems used in the above-mentioned electrodes may be Ti (titanium), Al (aluminum), Ni (nickel), Au (gold), Ta (tantalum), etc., and alloys and compounds containing the above metal systems.
  • the respective active regions can be formed by ionizing the enhancement mode high electron mobility transistor 10 , the diode group and the resistor 30 respectively. In this way, an isolation region is formed in the region where ion implantation is not performed between the enhancement mode high electron mobility transistor 10, the diode group and the resistor 30, so that the enhancement mode high electron mobility transistor 10, the diode group and the resistor 30 are isolated from each other. .
  • the gate electrode 12 of the enhancement mode high electron mobility transistor and the anode electrode of the diode group 20 can be prepared by means of evaporation or sputtering.
  • the metal system used in the gate 12 of the enhancement mode high electron mobility transistor may be Ti, Ni, Pd (palladium), Au, etc., and alloys and compounds thereof including the metal system.
  • the enhancement mode high electron mobility transistor 10 the diode group 20 and the resistor 30, and thereby improve the fabrication efficiency, the enhancement mode high electron mobility transistor 10, the diode group 20 and the resistor 30 can be fabricated simultaneously.
  • the diode group 20 may be fabricated based on the enhancement mode high electron mobility transistor 10 , that is, the enhancement mode high electron mobility is fabricated in the region of the enhancement mode high electron mobility transistor 10 and the region of the diode group 20 respectively.
  • the transistor 10 is formed, thereby forming the enhancement mode high electron mobility transistor 10 in the region of the enhancement mode high electron mobility transistor 10 and the enhancement mode high electron mobility transistor 10 in the region of the diode group 20 .
  • the region of the enhancement mode high electron mobility transistor 10 and the region of the diode group 20 are in different positions on the non-functional region 50 .
  • the gate electrode 12 of the enhancement mode high electron mobility transistor in the diode group 20 region and the source electrode 11 of the enhancement mode high electron mobility transistor in the diode group 20 region can be metal interconnected, thereby The anode of the diode group 20 is formed.
  • S600 Connect the anode of the diode group 20 to the metal of the first electrode of the semiconductor device, respectively connect the cathode of the diode group 20 to the first metal terminal 31 of the resistor 30, and the second metal terminal 32 of the resistor 30 to the first metal terminal of the semiconductor device.
  • the two electrodes are connected to metal; the gate 12 of the enhancement mode high electron mobility transistor is connected to the cathode metal of the diode group 20, the drain 13 of the enhancement mode high electron mobility transistor is connected to the first electrode metal, and the enhancement mode high electron mobility transistor is connected to the first electrode metal.
  • the source electrode 11 of the semiconductor device is metallically connected to the second electrode.
  • This step is to make the diode group 20 , the enhancement mode high electron mobility transistor 10 and the resistor 30 form an electrostatic protection structure through metal interconnection, so as to perform electrostatic discharge protection on the semiconductor device.
  • the specific connection relationship can be combined with the equivalent circuit diagram of FIG. 2 . And refer to the foregoing description about the structure, which will not be repeated here.
  • an insulating layer may be provided in a region other than the corresponding region of the cathode of the diode group 20 and the first metal terminal 31, and other metals are interconnected with each other. The connected place can be obtained in the same way, and will not be repeated in this embodiment.
  • the diode group 20 and the resistor 30 are metal interconnected, a seal ring structure is formed, and then the seal ring structure is interconnected with the semiconductor device to connect the device region 40 of the semiconductor device.
  • the electrostatic protection function of semiconductor devices is realized.

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Abstract

一种密封环结构及其制备方法，涉及集成电路技术领域。该密封环结构包括通过半导体外延层制作的增强型高电子迁移率晶体管、二极管组和电阻，增强型高电子迁移率晶体管用于环设于半导体器件的器件区外周，二极管组和电阻用于设于器件区外周；二极管组的阳极用于与半导体器件的第一电极金属连接、阴极与电阻的第一金属端金属连接，电阻的第二金属端用于金属连接半导体器件的第二电极；增强型高电子迁移率晶体管的栅极与二极管组的阴极金属连接、漏极用于与第一电极金属连接、源极用于与半导体器件的第二电极金属连接。该密封环结构能够利用密封环区域实现静电保护功能，从而节省器件的面积。

Description

密封环结构及其制备方法 技术领域
本发明涉及集成电路技术领域，具体而言，应用于半导体器件，涉及一种密封环结构及其制备方法。
 背景技术
静电放电(Electro-Static discharge，ESD)是集成电路芯片与外部物体之间的电荷释放和转移现象。由于在短时间释放大量电荷，ESD产生的能量远高于芯片的承受能力，因此很可能会导致芯片的功能暂时失效甚至永久损坏。因此，为了尽量避免静电对集成电路的损坏，静电释放防护设计在提高产品的可靠性和良率方面就显得非常重要。
通常，集成电路会单独设置有静电保护结构，从而在出现静电时对集成电路进行保护。然而，单独设置的静电保护结构会占据一定的集成电路的芯片面积，从而导致器件的芯片面积增大，不利于器件小型化。
 技术解决方案
本发明的目的在于提供一种密封环结构及其制备方法，其能够利用密封环区域实现静电保护功能，从而节省器件的面积。
本发明的实施例是这样实现的：
本发明的一方面，提供一种密封环结构，该密封环结构包括通过半导体外延层制作的增强型高电子迁移率晶体管、二极管组以及电阻，增强型高电子迁移率晶体管用于环设于半导体器件的器件区外周，二极管组和电阻用于设于器件区外周；二极管组的阳极用于与半导体器件的第一电极金属连接，二极管组的阴极与电阻的第一金属端金属连接，电阻的第二金属端用于金属连接半导体器件的第二电极；增强型高电子迁移率晶体管的栅极与二极管组的阴极金属连接，增强型高电子迁移率晶体管的漏极用于与第一电极金属连接，增强型高电子迁移率晶体管的源极用于与半导体器件的第二电极金属连接。该密封环结构能够利用密封环区域实现静电保护功能，从而节省器件的面积。
可选地，第一电极为半导体器件的栅极，第二电极为半导体器件的源极；或者，第一电极为半导体器件的源极，第二电极为半导体器件的栅极。
可选地，二极管组包括3个至7个依次串联的二极管。
可选地，二极管组包括纵向二极管组和/或横向二极管组，横向二极管组分布于器件区的横侧，纵向二极管组分布于器件区的纵侧；当二极管组包括纵向二极管组和横向二极管组时，纵向二极管组和横向二极管组串联连接，且纵向二极管组的阳极与第一电极金属连接，横向二极管组的阴极与第一金属端金属连接。
可选地，电阻和纵向二极管组分布于器件区的相对两侧；纵向二极管组包括至少一个二极管；横向二极管组包括至少一个二极管。
可选地，纵向二极管组包括两个依次串联的二极管，横向二极管组包括四个依次串联的二极管。
可选地，纵向二极管组和横向二极管组分别包括三个依次串联的二极管。
可选地，增强型高电子迁移率晶体管的栅极沿第一方向的长度在0.5μm至1.0μm之间；增强型高电子迁移率晶体管的源极和增强型高电子迁移率晶体管的栅极沿第一方向的距离在0.5μm至1.5μm之间。
可选地，二极管的阳极与二极管的阴极沿第一方向的距离在1.5μm至3.0μm之间，增强型高电子迁移率晶体管的栅极与增强型高电子迁移率晶体管的漏极沿第一方向的距离在1.5μm至3.0μm之间。
进一步，半导体外延层包括依次层叠的衬底、缓冲层、沟道层、势垒层以及P型氮化物层；增强型高电子迁移率晶体管包括设置在势垒层上的源极和漏极、设置P型氮化物层上的栅极；二极管组包括设置在P型氮化物层上的阳极和设置在势垒层上的阴极；电阻设置在势垒层上的第一金属端和第二金属端；增强型高电子迁移率晶体管、二极管组、电阻之间通过隔离区隔离。
本发明的另一方面，提供一种密封环结构的制备方法，该方法包括：在衬底上依次形成缓冲层、沟道层、势垒层和P型氮化物层；刻蚀P型氮化物层，以定义出增强型高电子迁移率晶体管区域的P型氮化物层、二极管组区域的P型氮化物层，并去除电阻区域的P型氮化物层，其中，增强型高电子迁移率晶体管区域环设于半导体器件的器件区外周，二极管组区域和电阻区域设于器件区的外周；分别制备增强型高电子迁移率晶体管的源极和漏极、二极管组的阴极，以及电阻的第一金属端和第二金属端；通过离子注入定义出相互隔离的增强型高电子迁移率晶体管的有源区、二极管组的有源区和电阻的有源区；分别制备增强型高电子迁移率晶体管的栅极和二极管组的阳极；分别将二极管组的阳极与半导体器件的第一电极金属连接，将二极管组的阴极与电阻的第一金属端金属连接，电阻的第二金属端与半导体器件的第二电极金属连接；增强型高电子迁移率晶体管的栅极与二极管组的阴极金属连接，增强型高电子迁移率晶体管的漏极与第一电极金属连接，增强型高电子迁移率晶体管的源极与半导体器件的第二电极金属连接。
可选地，分别制备增强型高电子迁移率晶体管的源极和漏极、二极管组的阴极，以及电阻的第一金属端和第二金属端，包括：采用蒸镀或者溅射的方式分别制备增强型高电子迁移率晶体管的源极和漏极、二极管组的阴极，以及电阻的第一金属端和第二金属端。
 有益效果
本发明的有益效果包括：
本实施例提供一种密封环结构，该密封环结构包括通过半导体外延层制作的增强型高电子迁移率晶体管、二极管组以及电阻，增强型高电子迁移率晶体管用于环设于半导体器件的器件区外周，二极管组和电阻用于设于器件区外周；二极管组的阳极用于与半导体器件的第一电极金属连接，二极管组的阴极与电阻的第一金属端金属连接，电阻的第二金属端用于金属连接半导体器件的第二电极；增强型高电子迁移率晶体管的栅极与二极管组的阴极金属连接，增强型高电子迁移率晶体管的漏极用于与第一电极金属连接，增强型高电子迁移率晶体管的源极用于与半导体器件的第二电极金属连接。这样，环形围设于半导体器件的器件区外周的增强型高电子迁移率晶体管可以实现对器件区的机械保护，避免在切割过程中器件区受到应力或者杂质的损伤，并且当半导体器件的第一电极因正电荷积累，而产生相对半导体器件的第二电极的高压时，密封环结构会在二极管组和增强型高电子迁移率晶体管的作用下导走正电荷从而实现静电释放；当半导体器件的第一电极因负电荷积累，而产生相对半导体器件的第二电极的负压时，密封环结构会通过增强型高电子迁移率晶体管将负电荷导走，从而实现静电释放。如此一来，本申请的密封环结构既可以实现对半导体器件的机械保护，还可以实现对半导体器件的静电保护，从而使得半导体器件无需单独设置静电保护结构，节省了器件的面积。
 附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本发明实施例提供的密封环结构的布局结构示意图；
图2为本发明实施例提供的密封环结构的等效电路图；
图3为本发明实施例提供的密封环结构的增强型高电子迁移率晶体管的结构示意图；
图4为本发明实施例提供的二极管的结构示意图；
图5为本发明实施例提供的电阻的结构示意图；
图6为本发明实施例提供的密封环结构的制备方法的流程示意图。
图标：10-增强型高电子迁移率晶体管；11-增强型高电子迁移率晶体管的源极；12-增强型高电子迁移率晶体管的栅极；13-增强型高电子迁移率晶体管的漏极；20-二极管组；21-纵向二极管组；22-横向二极管组；23-二极管；231-二极管的阳极；232-二极管的阴极；30-电阻；31-第一金属端；32-第二金属端；40-器件区；41-半导体器件的栅极；42-半导体器件的源极；a-第一方向；50-非功能区；51-衬底；52-缓冲层；53-沟道层；54-势垒层；55-P型氮化物层。
 本发明的实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
此外，术语“水平”、“竖直”等术语并不表示要求部件绝对水平或悬垂，而是可以稍微倾斜。如“水平”仅仅是指其方向相对“竖直”而言更加水平，并不是表示该结构一定要完全水平，而是可以稍微倾斜。
在本发明的描述中，还需要说明的是，除非另有明确的规定和限定，术语“设置”、“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
通常在晶圆上形成的芯片之间会形成切割道，通过切割道对晶圆进行切割从而将晶圆划分为多个芯片。但是在对晶圆进行切割的过程中，会产生应力以及杂质等，从而很可能导致芯片发生损伤，通常为了能够避免芯片受到来自于切割道区域的损伤威胁，会在切割道和芯片之间围绕芯片设置应力保护环，也就是密封环结构。密封环结构在半导体制造的后端制程当中是相当重要的部分。然而，现有密封环结构只具备一个机械应力的保护功能，不具备静电放电(Electro-Static discharge，ESD)保护功能。若要实现芯片的静电保护，则需要单独设置对应的静电保护结构，然而，单独设置的静电保护结构会占用器件的面积，为此，本申请对现有的密封环结构进行了改进，从而使得密封环结构具备静电保护功能，以使得密封环结构能够利用密封环区域实现静电保护功能，从而节省器件的面积。下文将对本申请做出的改进以示例的方式进行详细说明。
需要说明的是，密封环区域位于器件区的外周，下文中本申请提供的密封环结构设于密封环区域。请参照图1，本实施例提供一种密封环结构，该密封环结构包括通过半导体外延层制作的增强型高电子迁移率晶体管10、二极管组20以及电阻30，增强型高电子迁移率晶体管10用于环设于半导体器件的器件区40（也是半导体器件的芯片区域）外周，二极管组20和电阻30用于设于器件区40外周；二极管组20的阳极用于与半导体器件的第一电极金属连接，二极管组20的阴极与电阻30的第一金属端31金属连接，电阻30的第二金属端32用于金属连接半导体器件的第二电极；增强型高电子迁移率晶体管的栅极12与二极管组20的阴极金属连接，增强型高电子迁移率晶体管的漏极13用于与第一电极金属连接，增强型高电子迁移率晶体管的源极11用于与半导体器件的第二电极金属连接。该密封环结构能够利用密封环区域实现静电保护功能，从而节省器件的面积。
需要说明的是，上述增强型高电子迁移率晶体管10用于环设于半导体器件的器件区40的外周，即本实施例的增强型高电子迁移率晶体管10呈封闭环形，如图1所示，这样，增强型高电子迁移率晶体管10便可以围设于器件区40的外周，对器件区40进行全方位的密封保护，从而可以避免在对晶圆自切割道进行切割过程中产生的应力或者杂质对器件区40造成损伤。
另外，需要说明的是，上述电阻30的第一金属端31即为电阻30的正极，上述电阻30的第二金属端32即为电阻30的负极。
二极管组20和电阻30分别用于设置于增强型高电子迁移率晶体管10与器件区40之间；当然，增强型高电子迁移率晶体管10也可以用于设置器件区40的外周，且二极管组20和电阻30分别设于增强型高电子迁移率晶体管10的外周，换言之，增强型高电子迁移率晶体管10设于二极管组20和电阻30与器件区40之间。
其中，需要说明的是，二极管组20可以由多个二极管23相互串联连接形成。具体地二极管组20中的二极管23的数量本领域技术人员可根据实际情况而定，在本实施例中，可选地，二极管组20包括3个至7个依次串联的二极管23，示例地，二极管组20可以包括5个依次串联的二极管23；或者，二极管组20可以包括6个依次串联的二极管23。
另外，在本实施例中，上述二极管组20中的多个二极管23以及电阻30也可以依次串联连接后沿器件区40的外周环绕设置，换言之，每个二极管23与器件区40之间的距离相等，且每个二极管23与器件区40的距离和电阻30与器件区40的距离也相等（请参见图1，图1即为电阻30和每个二极管23绕器件区40设置，从而对器件区40进行三个侧面的保护）。这样，每个二极管23和电阻30也可以绕设于器件区40的外周，从而在一定程度上实现对器件区40的密封保护。应理解，上述电阻30和多个二极管23可以是均布于器件区40的外周（可实现器件区40的四个侧面全方位的保护），也可以是随机分布于器件区40的外周，对此，本领域技术人员可根据实际需求而定。
本实施例将每一个二极管23和电阻30沿器件区40外周绕设，可以进一步降低切割过程对器件区40造成的影响。为了使得密封环结构对器件区40的保护功能更佳，在本实施例中，本实施例提供的密封环结构还可以与器件区40之间具有一定距离（具体为二极管组20和电阻30分别和器件区40之间具有一定距离），例如可以为10μm等。
还有，请结合参照图2，图2为密封环结构的等效电路结构，上述二极管组20的阳极用于和半导体器件的第一电极金属连接，二极管组20的阴极与电阻30的第一金属端31金属连接，电阻30的第二金属端32用于和半导体器件的第二电极金属连接。增强型高电子迁移率晶体管的栅极12与二极管组20的阴极金属连接，增强型高电子迁移率晶体管的漏极13用于与第一电极金属连接，增强型高电子迁移率晶体管的源极11用于与半导体器件的第二电极金属连接。这样，当半导体器件的第一电极因正电荷积累，而在A点产生相对于第二电极的高压时（即正的高压，例如该高压大于6V），此时，二极管组20开启，经过二极管组20的电流流经电阻30将电荷进行释放。另外，电流流经二极管组20后在B点处产生相对于地的高压，若该高压大于增强型高电子迁移率晶体管10的阈值电压（该阈值电压为1V至2V），这时增强型高电子迁移率晶体管10也会开启，进一步导走A点积累的电荷，从而实现静电释放；当半导体器件的第一电极因负电荷积累，而在A点产生相对于第二电极的负压时，由于增强型高电子迁移率晶体管10的反向导通特性，增强型高电子迁移率反向开启，负电荷会通过增强型高电子迁移率晶体管10导走，从而实现静电释放。
可选地，在一种实施例中，如图1和图2所示，上述第一电极为半导体器件的栅极41，第二电极为半导体器件的源极42。这样，密封环结构可以实现对半导体器件的栅极41的静电释放保护。
当然，在另一种实施例中，可选地，第一电极还可以为半导体器件的源极42，第二电极为半导体器件的栅极41。这时，则二极管组20的阳极与半导体器件的源极42金属连接，增强型高电子迁移率晶体管的源极11和半导体器件的栅极41金属连接，从而实现密封环结构对半导体器件的源极42实现静电释放保护。由于密封环结构对半导体器件的源极42实现静电保护和对半导体器件的栅极41实现静电保护的原理相同，故均可参见前文对第一电极实现静电保护的相关描述，在此不再赘述。
综上所述，本实施例提供一种密封环结构，该密封环结构包括通过半导体外延层制作的增强型高电子迁移率晶体管10、二极管组20以及电阻30，增强型高电子迁移率晶体管10用于环设于半导体器件的器件区40外周，二极管组20和电阻30用于设于器件区40外周；二极管组20的阳极用于与半导体器件的第一电极金属连接，二极管组20的阴极与电阻30的第一金属端31金属连接，电阻30的第二金属端32用于金属连接半导体器件的第二电极；增强型高电子迁移率晶体管的栅极12与二极管组20的阴极金属连接，增强型高电子迁移率晶体管的漏极13用于与第一电极金属连接，增强型高电子迁移率晶体管的源极11用于与半导体器件的第二电极金属连接。这样，环形围设于器件区40外周的增强型高电子迁移率晶体管10可以实现对器件区40的机械保护，避免器件区40在切割过程中受到应力或者杂质的损伤，并且当半导体器件的第一电极因正电荷积累，而产生相对于第二电极的高压时，密封环结构会在二极管组20和增强型高电子迁移率晶体管10的作用下导走正电荷从而实现静电释放；当半导体器件的第一电极因负电荷积累，而产生相对于第二电极的负压时，密封环结构会通过增强型高电子迁移率晶体管10将负电荷导走，从而实现静电释放。如此一来，本申请的密封环结构既可以实现对器件区40的机械保护，还可以实现对器件区40的静电保护，从而使得半导体器件无需单独设置静电保护结构，节省了器件的面积。
可选地，二极管组20包括纵向二极管组21和/或横向二极管组22，横向二极管组22分布于器件区40的横侧，纵向二极管组21分布于器件区40的纵侧；当二极管组20包括纵向二极管组21和横向二极管组22时，纵向二极管组21和横向二极管组22串联连接，纵向二极管组21的阳极与第一电极金属连接，横向二极管组22的阴极与电阻30的第一金属端31金属连接。纵向二极管组21和横向二极管组22分布于器件区40的相邻两侧。
可参见图1所示，纵向二极管组21即为由分布于器件区40的左侧的二极管23串联连接形成的，横向二极管组22即为由分布于器件区40的上侧的二极管23串联形成的。将二极管组20分布于器件区40的相邻两边一来便于纵向二极管组21和横向二极管组22之间的电性连接，二来可进一步提高对器件区40的应力保护效果。应理解，本实施例所涉及的方位均是以说明书附图为基础提出的，以便于帮助理解，不应当被认定为对本申请的具体限制。当然，在本实施例中，上述二极管组20也可以只包括纵向二极管组21或横向二极管组22。
进一步地，电阻30和纵向二极管组21分布于器件区40的相对两侧，纵向二极管组21包括至少一个二极管23，横向二极管组22包括至少一个二极管23，这样，纵向二极管组21、横向二极管组22和电阻30可以分布于器件区40的三个侧边，从而实现对器件区40的多方位保护。
示例地，在一种实施例中，请参见图1所示，可选地，纵向二极管组21包括两个依次串联的二极管23，横向二极管组22包括四个依次串联的二极管23。其中，纵向二极管组21分布于器件区40的短边，横向二极管组22分布于器件区40的长边，这样，可在一定程度上实现二极管23的均匀分布，对半导体器件的保护效果更佳。
在另一种实施例中，可选地，纵向二极管组21和横向二极管组22分别包括三个依次串联的二极管23。这样，可适用于器件区40的相邻两边长度相当的情况，例如器件区40的横截面为正方形的情况下。具体二极管组20的分布情况本领域技术人员可根据实际情况而定，上述两种方式仅为本申请的两种示例，不应当认为是对本申请的限制。
可选地，请再结合参照图3至图5，在本实施例中，每个二极管23在制备时，是基于增强型高电子迁移率晶体管10进行制备的，即先在增强型高电子迁移率晶体管10的区域和二极管组20的区域制备增强型高电子迁移率晶体管10，再将二极管组20的区域的增强型高电子迁移率晶体管的栅极12和增强型高电子迁移率晶体管的源极11通过金属互连以形成二极管的阳极231。
增强型高电子迁移率晶体管的栅极12与增强型高电子迁移率晶体管的源极11沿第一方向a的距离在0.5μm至1.5μm之间。其中，上述第一方向a可参见图3至图5所示。增强型高电子迁移率晶体管的栅极12沿第一方向a长度在0.5μm至1.0μm之间。增强型高电子迁移率晶体管的栅极12与增强型高电子迁移率晶体管的漏极13沿第一方向a的距离在1.5μm至3.0μm之间。增强型高电子迁移率晶体管的栅极12沿第二方向的宽度为10000μm至20000μm之间，其中，第二方向与第一方向a垂直。
其中，二极管23在第一方向a上的尺寸与增强型高电子迁移率晶体管10的尺寸范围相同，但可选地，二极管23的在前期制备过程中，其栅极（在金属互连之前二极管23还未形成阳极，此时具有栅极）与增强型高电子迁移率晶体管的栅极12在第二方向的宽度范围可以不同，例如，二极管23的栅极沿第二方向的宽度可以为400μm至1000μm之间。
例如，二极管23的栅极（在金属互连之前二极管23还未形成阳极，此时具有栅极）和二极管23的源极（在金属互连之前二极管23还未形成阳极，此时具有源极）沿第一方向a的距离在0.5μm至1.5μm之间，二极管23的栅极沿第一方向a的长度在0.5μm至1.0μm之间，二极管的阳极231与二极管的阴极232沿第一方向a的距离可以为1.5μm至3.0μm之间。
另外，在本实施例中，可选地，电阻30的长度可以为3.0μm至4.0μm之间，电阻30的宽度可以为2000μm至2500μm之间。
可选地，在本实施例中，上述半导体外延层包括依次层叠的衬底51、缓冲层52、沟道层53、势垒层54以及P型氮化物层55。增强型高电子迁移率晶体管10包括设置在势垒层54上的源极和漏极、设置P型氮化物层55上形成的栅极；二极管组20包括设置在P型氮化物层55的阳极和设置势垒层54上的阴极；电阻30设置在势垒层54上的第一金属端31和第二金属端32。增强型高电子迁移率晶体管10、二极管组20、电阻30之间通过隔离区隔离。
请再结合参照图6，本发明的另一方面，提供一种密封环结构的制备方法，该方法包括：
S100、在衬底51上依次形成缓冲层52、沟道层53、势垒层54和P型氮化物层55。
其中，势垒层54可以为AlGaN势垒层，其厚度可以在1nm至50nm之间。沟道层53可以为GaN沟道层，P型氮化物层55可以为P-GGaN层。P型氮化物层55的厚度可以为50nm至300nm之间，掺杂浓度在1017-1021cm-3之间。
需要说明的是，本发明密封环是为了对器件区40进行全方位的密封保护，从而可以避免在对晶圆自切割道进行切割过程中产生的应力或者杂质对器件区40造成损伤。
S200、刻蚀P型氮化物层55，以定义出增强型高电子迁移率晶体管10区域的P型氮化物层、二极管组20区域的P型氮化物层，并去除电阻30区域的P型氮化物层55，其中，增强型高电子迁移率晶体管10区域环设于半导体器件的器件区40外周，二极管组20区域和电阻30区域设于器件区40的外周。
即对上述步骤S100形成的P型氮化物层55进行刻蚀，以分别定义出增强型高电子迁移率晶体管10区域、二极管组20区域的P型氮化物层55，并且全部刻蚀掉电阻30区域的P型氮化物层55。其中，上述刻蚀工艺可采用ICP刻蚀。
另外，当二极管组20包括多个二极管23时，则应该分别在各个二极管23的对应区域定义出P型氮化物层55。
S300、分别制备增强型高电子迁移率晶体管的源极11和漏极、二极管组20的阴极，以及电阻30的第一金属端31和第二金属端32。
需要说明的是，上述制备增强型高电子迁移率晶体管的源极11和增强型高电子迁移率晶体管的漏极13，二极管组20的阴极，以及电阻30的第一金属端31（即电阻30的正极）和第二金属端32（即电阻30的负极）可以是同时进行的，也可以是分别独立进行的，在此不作限制，只要能使得在器件区40的外周形成围绕器件区40设置的环形增强型高电子迁移率晶体管10，并且在增强型高电子迁移率晶体管10与器件区40之间形成二极管组20和电阻30即可。
其中，可选地，上述步骤S300、分别制备增强型高电子迁移率晶体管的源极11和漏极、二极管组20的阴极，以及电阻30的第一金属端31和第二金属端32，可以为：
采用蒸镀或者溅射的方式分别制备增强型高电子迁移率晶体管的源极11和漏极、二极管组20的阴极，以及电阻30的第一金属端31和第二金属端32。
另外，上述各电极所采用的金属体系可以为Ti（钛）、Al（铝）、Ni（镍）、Au（金）、Ta（钽）等及其包含上述金属体系在内的合金及化合物。
S400、通过离子注入定义出相互隔离的增强型高电子迁移率晶体管10的有源区、二极管组20的有源区和电阻30的有源区。
需要说明的是，通过分别对增强型高电子迁移率晶体管10、二极管组和电阻30进行离子可形成各自的有源区。这样在增强型高电子迁移率晶体管10、二极管组和电阻30之间未进行离子注入的区域则形成隔离区，使得增强型高电子迁移率晶体管10、二极管组和电阻30两两之间相互隔离。
S500、分别制备增强型高电子迁移率晶体管的栅极12和二极管组20的阳极。
其中，可以采用蒸镀或者溅射的方式制备增强型高电子迁移率晶体管的栅极12和二极管组20的阳极。上述增强型高电子迁移率晶体管的栅极12所采用的金属体系可以为Ti、Ni、Pd（钯）、Au等及其包含上述金属体系在内的合金及化合物。
为了使得在制备增强型高电子迁移率晶体管10、二极管组20和电阻30时简化制备工序，进而提高制备效率，上述增强型高电子迁移率晶体管10、二极管组20和电阻30可以同时进行制备。
在本实施例中，二极管组20可以是基于增强型高电子迁移率晶体管10进行制备的，即分别在增强型高电子迁移率晶体管10的区域和二极管组20的区域制备增强型高电子迁移率晶体管10，从而形成位于增强型高电子迁移率晶体管10区域的增强型高电子迁移率晶体管10和位于二极管组20区域的增强型高电子迁移率晶体管10。需注意，增强型高电子迁移率晶体管10区域和二极管组20的区域在非功能区50上处于不同的位置。
这样，在形成二极管组20时，可以将二极管组20区域的增强型高电子迁移率晶体管的栅极12和二极管组20区域的增强型高电子迁移率晶体管的源极11进行金属互连，从而形成二极管组20的阳极。
S600、分别将二极管组20的阳极与半导体器件的第一电极金属连接，将二极管组20的阴极与电阻30的第一金属端31金属连接，电阻30的第二金属端32与半导体器件的第二电极金属连接；增强型高电子迁移率晶体管的栅极12与二极管组20的阴极金属连接，增强型高电子迁移率晶体管的漏极13与第一电极金属连接，增强型高电子迁移率晶体管的源极11与半导体器件的第二电极金属连接。
该步骤是为了使得二极管组20、增强型高电子迁移率晶体管10以及电阻30通过金属互连形成静电保护结构，从而对半导体器件进行静电释放保护，具体地连接关系可结合图2的等效电路图以及参见前文关于结构处的描述，在此不再赘述。
另外，在进行各个电极之间的金属互连时，应当注意与其他电极之间进行绝缘隔离以避免与其他电极之间发生短路。例如，将二极管组20的阴极和电阻30的第一金属端31金属互联时，可以在除了二极管组20的阴极和第一金属端31之外对应的区域以外的区域设置绝缘层，其他金属互连的地方同理可得，本实施例不再赘述。
本申请将增强型高电子迁移率晶体管10、二极管组20以及电阻30进行金属互连之后，形成密封环结构，然后将密封环结构与半导体器件进行互连便可以在对半导体器件的器件区40进行机械保护的基础上实现了半导体器件的静电保护功能。
以上所述仅为本发明的可选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本发明对各种可能的组合方式不再另行说明。

Claims (10)

  1. 一种密封环结构，其特征在于，包括通过半导体外延层制作的增强型高电子迁移率晶体管、二极管组以及电阻，所述增强型高电子迁移率晶体管用于环设于半导体器件的器件区外周，所述二极管组和所述电阻用于设于所述器件区外周；所述二极管组的阳极用于与所述半导体器件的第一电极金属连接，所述二极管组的阴极与所述电阻的第一金属端金属连接，所述电阻的第二金属端用于金属连接所述半导体器件的第二电极；所述增强型高电子迁移率晶体管的栅极与所述二极管组的阴极金属连接，所述增强型高电子迁移率晶体管的漏极用于与所述第一电极金属连接，所述增强型高电子迁移率晶体管的源极用于与所述半导体器件的第二电极金属连接。
  2. 根据权利要求1所述的密封环结构，其特征在于，所述二极管组包括3个至7个依次串联的二极管。
  3. 根据权利要求1所述的密封环结构，其特征在于，所述二极管组包括纵向二极管组和/或横向二极管组，所述横向二极管组分布于所述器件区的横侧，所述纵向二极管组分布于所述器件区的纵侧；当所述二极管组包括纵向二极管组和横向二极管组时，所述纵向二极管组和所述横向二极管组串联连接，且所述纵向二极管组的阳极与所述第一电极金属连接，所述横向二极管组的阴极与所述第一金属端金属连接。
  4. 根据权利要求3所述的密封环结构，其特征在于，所述电阻和所述纵向二极管组分布于所述器件区的相对两侧；所述纵向二极管组包括至少一个二极管；所述横向二极管组包括至少一个二极管。
  5. 根据权利要求1所述的密封环结构，其特征在于，所述第一电极为半导体器件的栅极，所述第二电极为半导体器件的源极；或者，所述第一电极为半导体器件的源极，所述第二电极为半导体器件的栅极。
  6. 根据权利要求2所述的密封环结构，其特征在于，所述增强型高电子迁移率晶体管的栅极沿第一方向的长度在0.5μm至1.0μm之间；所述增强型高电子迁移率晶体管的源极和所述增强型高电子迁移率晶体管的栅极沿所述第一方向的距离在0.5μm至1.5μm之间。
  7. 根据权利要求6所述的密封环结构，其特征在于，所述二极管的阳极与所述二极管的阴极沿所述第一方向的距离在1.5μm至3.0μm之间，所述增强型高电子迁移率晶体管的栅极与所述增强型高电子迁移率晶体管的漏极沿所述第一方向的距离在1.5μm至3.0μm之间。
  8. 根据权利要求1所述的密封环结构，其特征在于，所述半导体外延层包括依次层叠的衬底、缓冲层、沟道层、势垒层以及P型氮化物层；所述增强型高电子迁移率晶体管包括设置在势垒层上的源极和漏极、设置P型氮化物层上的栅极；所述二极管组包括设置在P型氮化物层上的阳极和设置在所述势垒层上的阴极；所述电阻包括设置在势垒层上的第一金属端和第二金属端；所述增强型高电子迁移率晶体管、二极管组、电阻之间通过隔离区隔离。
  9. 一种密封环结构的制备方法，其特征在于，包括：
    在衬底上依次形成缓冲层、沟道层、势垒层和P型氮化物层；
    刻蚀所述P型氮化物层，以定义出增强型高电子迁移率晶体管区域的P型氮化物层、二极管组区域的P型氮化物层，并去除电阻区域的P型氮化物层，其中，所述增强型高电子迁移率晶体管区域环设于半导体器件的器件区外周，所述二极管组区域和所述电阻区域设于所述器件区的外周；
    分别制备所述增强型高电子迁移率晶体管的源极和漏极、所述二极管组的阴极，以及所述电阻的第一金属端和第二金属端；
    通过离子注入定义出相互隔离的所述增强型高电子迁移率晶体管的有源区、所述二极管组的有源区和所述电阻的有源区；
    分别制备所述增强型高电子迁移率晶体管的栅极和所述二极管组的阳极；
    分别将所述二极管组的阳极与所述半导体器件的第一电极金属连接，将所述二极管组的阴极与所述电阻的第一金属端金属连接，所述电阻的第二金属端与所述半导体器件的第二电极金属连接；所述增强型高电子迁移率晶体管的栅极与所述二极管组的阴极金属连接，所述增强型高电子迁移率晶体管的漏极与所述第一电极金属连接，所述增强型高电子迁移率晶体管的源极与所述半导体器件的第二电极金属连接。
  10. 根据权利要求9所述的密封环结构的制备方法，其特征在于，所述分别制备所述增强型高电子迁移率晶体管的源极和漏极、所述二极管组的阴极，以及所述电阻的第一金属端和第二金属端，包括：
    采用蒸镀或者溅射的方式分别制备所述增强型高电子迁移率晶体管的源极和漏极、所述二极管组的阴极，以及所述电阻的第一金属端和第二金属端。
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