WO2022141206A1 - 一种数字信号的调制方法及装置、开关电源控制方法及开关电源 - Google Patents

一种数字信号的调制方法及装置、开关电源控制方法及开关电源 Download PDF

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WO2022141206A1
WO2022141206A1 PCT/CN2020/141431 CN2020141431W WO2022141206A1 WO 2022141206 A1 WO2022141206 A1 WO 2022141206A1 CN 2020141431 W CN2020141431 W CN 2020141431W WO 2022141206 A1 WO2022141206 A1 WO 2022141206A1
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Prior art keywords
value
comparator
modulation
pwm signal
counter
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PCT/CN2020/141431
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English (en)
French (fr)
Inventor
潘丽雯
冯辉
王德源
金新宇
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华为技术有限公司
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Priority to CN202080004269.0A priority Critical patent/CN112771456B/zh
Priority to EP20967547.9A priority patent/EP4254751A4/en
Priority to PCT/CN2020/141431 priority patent/WO2022141206A1/zh
Publication of WO2022141206A1 publication Critical patent/WO2022141206A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33584—Bidirectional converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/30—Nc systems
    • G05B2219/42—Servomotor, servo controller kind till VSS
    • G05B2219/42237—Pwm pulse width modulation, pulse to position modulation ppm
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present application relates to the technical field of digital coding, and in particular, to a digital signal modulation method and device, a switching power supply control method, and a switching power supply.
  • SiC switches or GaN switches have better switching characteristics, and can achieve a switching frequency of hundreds of KHz (kilohertz), and the switching frequency of GaN switches can even reach higher. Higher switching frequency can significantly reduce the volume of the inductor-capacitor transformer in the switching power supply, which is the key to improving the power density of the whole machine.
  • analog chips can be used to generate analog PWM signals to control the operation of switching power supplies; in medium and high-power application scenarios, programmable controllers can be used to generate digital PWM signals to control switching power supplies work.
  • the analog PWM signal is a continuously changing signal, once calibrated, there is no problem of accuracy.
  • the digital PWM signal simulates a continuously changing signal through discrete values.
  • the clock of the commonly used digital PWM generator does not exceed 200MHz. Therefore, when the switching frequency is high, the discrete value is too high, which will affect the accuracy of the digital PWM signal.
  • the digital PWM generator generates the corresponding PWM signal by setting the value of the counter (Counter) and the value of the comparator (Compare), and the ratio of the value of the comparator and the value of the counter can be obtained. duty cycle.
  • the modulation methods of the PWM signal can be divided into two types: Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM).
  • PWM Pulse Width Modulation
  • PFM Pulse Frequency Modulation
  • the pulse width can be changed by modifying the value of the comparator to change the duty cycle.
  • the value of the counter can be modified by modifying the value of the counter or the value of the counter and the comparator at the same time. Change the pulse frequency to change the duty cycle.
  • pulse frequency modulation usually causes the pulse frequency to jitter in a wide range.
  • the actual adjustable duty cycle range of pulse frequency modulation It is not large, and the scope of application is relatively small, for example, it is usually used in LLC resonant circuits.
  • the existing single chip microcomputer can configure the PWM signal output as a dither mode.
  • the accuracy of the average duty cycle can be improved.
  • the value of the counter of the PWM signal is 10
  • an average duty cycle of 4.25/10 can be achieved.
  • a single-chip microcomputer can be configured with a jitter of up to 4 bits. The disadvantage of the jitter mode is that it needs time to change the accuracy.
  • the jitter value is increased by 2 bits, it will take 4 cycles to achieve the duty cycle accuracy of 4.75/10. If the jitter value is increased by 4 bits , when a duty cycle of 4.75/10 is achieved, it takes 16 cycles to achieve.
  • the 4-bit dither mode is used, which greatly reduces the response speed of the output.
  • the dither mode will also increase the difficulty of filtering the output, and the duty cycle of the output PWM signal is only the accuracy of the average value. higher, while the duty cycle accuracy per cycle is still lower.
  • the jitter of the duty cycle of the PWM signal will cause the jitter of the output voltage and current, and it is easy to cause the switching frequency of the switching power supply to be lower than the oscillation ripple frequency.
  • the present application provides a digital signal modulation method and device, a switching power supply control method and a switching power supply.
  • the duty cycle accuracy of the PWM signal of 1 cycle in order to output a higher precision PWM signal.
  • a first aspect of the present application provides a method for modulating a digital signal, including:
  • the PWM signal of each period in the periodic PWM signal is subjected to pulse frequency modulation according to the correction value.
  • the PWM technology is used to generate a periodic PWM signal according to the modulation value of the comparator and the initial value of the counter, and then the PFM technology is used to perform pulse frequency modulation on the PWM signal of each cycle according to the correction value, By appropriately changing the frequency, the duty cycle accuracy of the PWM signal in each cycle is improved, and a higher-precision PWM signal can be achieved without increasing the hardware cost.
  • the acquiring the modulation value of the comparator according to the target duty cycle and the initial value of the counter includes:
  • the precise value of the comparator is calculated and obtained, and the modulation value of the comparator is obtained by rounding the precise value of the comparator.
  • the accurate value of the comparator can be obtained by multiplication calculation, and when the accurate value of the comparator has decimal places, the modulation value of the comparator is obtained by rounding.
  • the comparison is performed according to the target duty cycle, the initial value of the counter, and the comparison.
  • the modulation value of the controller is obtained, and the correction value obtained includes:
  • the duty cycle of the PWM signal is less than 0.5
  • the modulation value of the comparator is calculated.
  • a precision value, and the first correction value is obtained by rounding the first precision value.
  • the duty cycle of the PWM signal is less than 0.5
  • select the corresponding calculation method to calculate the correction value wherein, when the duty cycle of the PWM signal is less than 0.5, according to the modulation value of the comparator and the comparator
  • the difference between the exact values, the modulation value of the comparator, and the initial value of the counter are calculated to obtain the first precision value.
  • the first precision value has decimal places
  • the first correction value is rounded to obtain the first correction value
  • the first correction value is used to pair the
  • the initial value of the counter is modulated to realize frequency modulation of the generated PWM signal of each cycle, thereby further improving the duty cycle accuracy of the PWM signal of each cycle.
  • the PWM of each period in the periodic PWM signal is performed according to the correction value.
  • Signals subjected to pulse frequency modulation include:
  • the initial value of the counter of each period of the periodic PWM signal is modulated according to the first correction value.
  • pulse frequency modulation includes high-level fixed-length pulse frequency modulation and low-level fixed-length pulse frequency modulation, of which high-level fixed-length pulse frequency modulation means that the high-level pulse width does not change, and only modulates the initial value of the counter.
  • the low-level fixed-length pulse frequency modulation means that the low-level pulse width does not change, and the modulation value of the comparator and the initial value of the counter need to be modulated at the same time.
  • a high-level fixed-length pulse frequency modulation can be selected to modulate the initial value of the counter, thereby improving the duty cycle accuracy of the final output PWM signal.
  • the initial value of the counter of the PWM signal of each period in the periodic PWM signal is modulated by addition according to the first correction value.
  • the pulse frequency modulation with high level and fixed length is selected, that is, the initial value of the counter needs to be modulated according to the first correction value.
  • the modulation direction is the same as the rounding direction.
  • the initial value of the counter also needs to be subtracted and modulated, and the modulation amount is The calculated first correction value, in the same way, if the exact value of the comparator is rounded up, that is, the modulation value of the comparator is greater than the exact value of the comparator, if you want to further improve the precision value of the duty cycle, you also need to The initial value of is additively modulated.
  • the method further includes:
  • the duty cycle of the PWM signal is greater than or equal to 0.5
  • the difference between the modulation value of the comparator and the precise value of the comparator is calculated to obtain the second precision value, and the second correction value is obtained by rounding the second precision value.
  • the duty cycle of the PWM signal is greater than or equal to 0.5, according to the difference between the modulation value of the comparator and the precise value of the comparator, the difference between the modulation value of the comparator and the initial value of the counter, and the value of the counter.
  • the initial value is calculated to obtain a second precision value, and when the second precision value has decimal places, rounding is performed to obtain a second correction value.
  • the second correction value is used to modulate the initial value of the counter and the modulation value of the comparator to realize frequency modulation of the generated PWM signal of each cycle, thereby further improving the duty cycle accuracy of the PWM signal of each cycle.
  • PWM signal for pulse frequency modulation includes:
  • the initial value of the counter and the modulation value of the comparator of the PWM signal of each period in the periodic PWM signal are modulated according to the second correction value.
  • pulse frequency modulation includes high-level fixed-length pulse frequency modulation and low-level fixed-length pulse frequency modulation, of which high-level fixed-length pulse frequency modulation means that the high-level pulse width does not change, and only modulates the initial value of the counter.
  • the low-level fixed-length pulse frequency modulation means that the low-level pulse width does not change, and the modulation value of the comparator and the initial value of the counter need to be modulated at the same time.
  • a low-level fixed-length pulse frequency modulation can be selected to modulate the modulation value of the comparator and the initial value of the counter, thereby improving the final output PWM The duty cycle accuracy of the signal.
  • the initial value of the counter of the PWM signal of each period in the periodic PWM signal and the value of the comparator are calculated according to the second correction value.
  • the modulation value is additively modulated
  • the duty cycle of the generated PWM signal is greater than or equal to 0.5
  • select the low-level fixed-length pulse frequency modulation that is, the modulation value of the comparator and the initial value of the counter need to be modulated according to the second correction value.
  • the modulation direction is opposite to the rounding direction, that is, when the exact value of the comparator is rounded down, the initial value of the counter and the modulation value of the comparator are added and modulated.
  • the exact value of the comparator is rounded up, the The initial value of the counter and the modulation value of the comparator are subtracted and modulated, thereby improving the duty cycle accuracy of the PWM signal in each cycle.
  • the rounding includes:
  • the rounding is performed by taking the nearest integer value.
  • the rounding method can be used to obtain the nearest integer value, thereby modulating the PWM signal closest to the target duty cycle.
  • a digital signal modulation device comprising:
  • a calculation unit configured to obtain the modulation value of the comparator according to the target duty cycle and the initial value of the counter; obtain the correction value according to the target duty cycle, the initial value of the counter and the modulation value of the comparator;
  • a pulse width modulation unit configured to generate a periodic PWM signal according to the modulation value of the comparator and the initial value of the counter
  • a pulse frequency modulation unit configured to perform pulse frequency modulation on the PWM signal of each period in the periodic PWM signal according to the correction value.
  • the acquiring the modulation value of the comparator according to the target duty cycle and the initial value of the counter includes:
  • the precise value of the comparator is calculated and obtained, and the modulation value of the comparator is obtained by rounding the precise value of the comparator.
  • the comparison is performed according to the target duty cycle, the initial value of the counter, and the comparison.
  • the modulation value of the controller is obtained, and the correction value obtained includes:
  • the first precision value is calculated according to the difference between the modulation value of the comparator and the precise value of the comparator, the modulation value of the comparator and the initial value of the counter.
  • the first correction value is obtained by rounding the first precision value.
  • the PWM signal of each period in the periodic PWM signal is determined according to the correction value.
  • Performing pulse frequency modulation involves:
  • the initial value of the counter of each period of the periodic PWM signal is modulated according to the first correction value.
  • the initial value of the counter of the PWM signal of each period in the periodic PWM signal is modulated by addition according to the first correction value.
  • a fifth possible implementation manner of the apparatus for modulating a digital signal further comprising:
  • the PWM signal of each period in the periodic PWM signal is determined according to the correction value.
  • Performing pulse frequency modulation involves:
  • the initial value of the counter and the modulation value of the comparator of the PWM signal of each period in the periodic PWM signal are modulated according to the second correction value.
  • the initial value of the counter of the PWM signal of each period in the periodic PWM signal and the value of the comparator are calculated according to the second correction value.
  • the modulation value is additively modulated
  • the rounding includes:
  • the rounding is performed by taking the nearest integer value.
  • a switching power supply control method including:
  • the modulation method of the digital signal in the modulation method of the digital signal is performed according to the target duty ratio, and the switching power supply is controlled using the output PWM signal.
  • a switching power supply comprising:
  • a switch circuit, the PWM signal of the switch circuit is provided by any one of the digital signal modulation devices.
  • a fifth aspect of the present application provides a computing device, including:
  • At least one memory connected to the bus and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform a modulation method of the digital signal or a switching power supply control method any of the methods described in .
  • a sixth aspect of the present application provides a computer-readable storage medium on which program instructions are stored, the program instructions, when executed by a computer, cause the computer to execute a modulation method or switch of the digital signal.
  • a seventh aspect of the present application provides a computer program product, which includes program instructions that, when executed by a computer, cause the computer to execute a modulation method or a switching power supply control method for the digital signal. any of the methods described in .
  • FIG. 1 shows a schematic diagram of an existing digital PWM signal generation method
  • FIG. 2 shows a schematic diagram of modulating the duty cycle using a dither mode
  • Fig. 3 shows the contrast schematic diagram of the duty cycle dispersion of pulse width modulation and pulse frequency modulation
  • FIG. 4 shows a schematic diagram of a modulation method of a digital signal provided by an embodiment of the present application
  • FIG. 5 shows a schematic diagram of a PWM/FPM hybrid modulation according to an embodiment of the present application
  • FIG. 6 shows a schematic diagram of a PWM/PFM hybrid modulation method provided by an embodiment of the present application
  • FIG. 7 shows a circuit diagram of a high-frequency miniaturized DAB converter provided by an embodiment of the present application.
  • FIG. 8 shows a schematic diagram of the power transmission characteristics of the DAB change period provided by an embodiment of the present application.
  • FIG. 9 shows an architecture diagram of a digital signal modulation device provided by an embodiment of the present application.
  • FIG. 10 shows an architecture diagram of a computing device provided by an embodiment of the present application.
  • PWM Pulse width modulation, pulse width modulation.
  • PFM Pulse frequency modulation, pulse frequency modulation.
  • PWM duty cycle refers to the proportion of high level in a pulse period.
  • PWM resolution refers to the number of stages that the duty cycle of PWM can be adjusted.
  • Duty cycle dispersion refers to the variation of the duty cycle between two adjacent periods of output during pulse width modulation or pulse frequency modulation. The smaller the duty cycle dispersion, the higher the adjustable precision of the duty cycle. .
  • the value of the counter (Counter) is set to n, and the value of the comparator (Compare) is set to k.
  • the polarity of the PWM signal output by the single-chip microcomputer is reversed and configured. , when the value of the counter is less than or equal to the value of the comparator, a high-level PWM signal is output, and when the value of the counter > the value of the comparator, a low-level PWM signal is output, and the duty cycle of the PWM signal can be obtained as k/n.
  • Pulse frequency modulation includes two modulation modes: high-level fixed-length and low-level fixed-length, among which,
  • the duty cycle dispersion is:
  • the duty cycle dispersion is:
  • the duty cycle dispersion under pulse width modulation and pulse frequency modulation is plotted, as shown in FIG. 3 , by comparing the duty cycle dispersion of pulse width modulation and pulse frequency modulation, it can be found that The duty cycle dispersion under pulse frequency modulation is always smaller than that under pulse width modulation.
  • Fig. 3 it can be further concluded that when k ⁇ n/2, that is, when the duty cycle is less than 0.5, the dispersion of the duty cycle under the high-level fixed-length pulse frequency modulation is smaller, that is, the duty cycle is less than When the value is 0.5, high-level fixed-length pulse frequency modulation can be used to achieve modulation with higher duty cycle accuracy.
  • the dispersion of the duty cycle under the low-level fixed-length pulse frequency modulation is smaller, that is, when the duty cycle is greater than or equal to 0.5, the low-level fixed-length is selected.
  • the pulse frequency modulation of 100°C can achieve modulation with higher duty cycle precision.
  • the pulse frequency modulation will be jittered in a wide range, which will cause certain difficulties in the design of the magnetic components or filter components of the circuit.
  • an embodiment of the present application provides a method for modulating a digital signal.
  • pulse width modulation is used to generate a periodic PWM signal
  • pulse frequency modulation is used to generate a periodic PWM signal.
  • the frequency modulation of the PWM signal of one cycle can not only avoid the problem that the pulse frequency of the output PWM signal changes greatly, but also greatly improve the duty cycle accuracy of the output PWM signal. The application is described in detail below.
  • the method includes:
  • S402 Obtain a correction value according to the target duty cycle, the initial value of the counter, and the modulation value of the comparator;
  • S403 Generate a periodic PWM signal according to the modulation value of the comparator and the initial value of the counter;
  • S404 Perform pulse frequency modulation on the PWM signal of each period in the periodic PWM signal according to the correction value.
  • the target duty cycle is the most accurate duty cycle to achieve the working output target.
  • the target required to accurately output the working voltage can be determined according to the working voltage and rated voltage that the switching power supply needs to output. duty cycle.
  • the modulation value and the correction value of the comparator that need to achieve the target duty cycle can be calculated respectively.
  • the modulation value of the comparator refers to the value that the comparator needs to set
  • the correction value refers to the value required for addition and subtraction modulation when the PWM signal is pulse frequency modulated.
  • the modulation value and correction value of the comparator are modulated integer values under the premise of satisfying the modulation accuracy. Specifically, the calculation includes:
  • an accurate comparator value is calculated.
  • the accurate comparator value is defined as the If the exact value of the comparator is a numerical value with decimal places, the exact value of the comparator needs to be rounded to obtain the modulation value of the comparator used for pulse width modulation;
  • the ratio of the initial value of the counter and the target duty cycle must have a certain deviation, and the deviation value is smaller than the duty cycle dispersion generated by one pulse width modulation.
  • Further calculations can be performed based on the exact value of the comparator, the modulation value of the comparator and the initial value of the counter, resulting in a correction value for the pulse frequency modulation.
  • the calculation process of the correction value needs to refer to the size of the duty cycle of the PWM signal, and the calculation process is performed based on the principle of obtaining a maximum correction value.
  • the modulation value of the comparator is used as the denominator to calculate, according to the modulation value of the comparator
  • the difference between the value and the precise value of the comparator, the modulation value of the comparator and the initial value of the counter are calculated to obtain the first precision value.
  • the first precision value is a numerical value with decimal places
  • the first precision value needs to be Carry out rounding to obtain the first correction value for pulse frequency modulation; when the duty cycle of the PWM signal is greater than or equal to 0.5, that is, the modulation value of the comparator is greater than or equal to half of the initial value of the counter, at this time the initial value of the counter is
  • the difference between the value and the modulation value of the comparator is calculated as the denominator, according to the difference between the modulation value of the comparator and the exact value of the comparator, the difference between the modulation value of the comparator and the initial value of the counter and the initial value of the counter.
  • the second precision value is calculated to obtain the second precision value. If the second precision value is a numerical value with decimal places, the second precision value needs to be rounded to obtain the second correction value for pulse frequency modulation.
  • the exact value of the comparator, the closest integer value of the first precision value and the second precision value can be obtained by rounding, thereby realizing more accurate pulse width modulation and pulse frequency modulation.
  • pulse width modulation and pulse frequency modulation can be performed. specific,
  • pulse width modulation is performed, and the digital PWM generator is set according to the modulation value of the comparator and the initial value of the counter to generate a periodic PWM signal.
  • the duty cycle of the PWM signal in each cycle is the ratio of the modulation value of the comparator to the initial value of the counter.
  • the initial value of the counter of the PWM signal of each cycle is subjected to addition modulation or subtraction modulation according to the first correction value, so that the duty cycle of the modulated PWM signal is adjusted.
  • the duty cycle is closer to the target duty cycle;
  • the initial value of the counter and the modulation value of the comparator of the PWM signal of each cycle are subjected to addition modulation or subtraction modulation according to the second correction value.
  • the initial value of the counter of the PWM signal of each period is adjusted according to the first correction value.
  • the value is subjected to one or more subtraction modulation, that is, the initial value of the counter is subtracted by the first correction value to obtain the final value of the counter; if the duty cycle of the PWM signal is greater than or equal to 0.5, then according to the second correction value
  • the initial value of the counter and the modulation value of the comparator of the PWM signal of each cycle are subjected to one or more addition modulation, that is, the modulation value of the comparator and the initial value of the counter are respectively added with a second correction value to obtain The final comparator value and counter value.
  • the initial value of the counter of the PWM signal of each period is calculated according to the first correction value.
  • One or more addition modulations are performed, that is, the initial value of the counter is added with the first correction value to obtain the final counter value; if the duty cycle of the PWM signal is greater than or equal to 0.5, then the second correction value is used for
  • the initial value of the counter and the modulation value of the comparator of the PWM signal of each cycle are subjected to one or more subtraction modulation, that is, the modulation value of the comparator and the initial value of the counter are respectively subtracted by the second correction value to obtain the final The comparator value and the counter value.
  • the number of times of performing the pulse frequency modulation is determined by the maximum precision of the pulse frequency modulation. For example, when the maximum precision value of the pulse frequency modulation is smaller than the first correction value or the second correction value, only one modulation is performed at this time. If the first correction value or the second correction value cannot be reached, multiple modulations are required.
  • the pulse width modulation is used to generate a periodic PWM signal, and then the PWM signal of each period in the periodic PWM signal is generated. Carry out further pulse frequency modulation, and after the pulse frequency modulation of the PWM signal of a single cycle is over, restore the modulation value of the comparator and the initial value of the counter, so that the initial duty cycle of the PWM signal in the next cycle is still the pulse width. Modulates the duty cycle of the resulting PWM signal.
  • the following formula explains the precision of the modulation method in the embodiment of the present application.
  • the duty cycle of the PWM signal generated by the pulse width modulation be k/n
  • k is the modulation value of the comparator
  • n is the initial value of the counter.
  • the integer part k and the fractional part ⁇ k can be obtained, and the floor function is a rounding down function
  • the pulse width modulation can be realized, and the PWM signal with a duty ratio of k/n is output.
  • the duty cycle accuracy is too low, and the difference from the target duty cycle set in the PI regulator is large.
  • the embodiment of the present application adopts the hybrid modulation method of PWM/PFM.
  • the PWM signal of each cycle is modulated to generate the PWM signal.
  • the duty ratio is k/n.
  • further pulse frequency modulation needs to be performed on the PWM signal of each cycle.
  • the modulation mode of high-level fixed-length PFM is selected.
  • the integer part k and the fractional part ⁇ k are obtained according to the rounding, and the initial value n of the timer is calculated to calculate the correction value a,
  • a high-level and fixed-length pulse frequency modulation is performed to modulate the PWM signal of each cycle, and the duty ratio of the modulated output is k/(n-a).
  • a high-level and fixed-length pulse frequency modulation is performed to modulate the PWM signal of each cycle, and the duty ratio of the modulated output is (k+b)/(n+b).
  • the duty cycle k/(n-a) or (k+b)/(n+b) output after the pulse frequency modulation is compared with the modulation value k of the comparator and the initial value n of the counter according to the rounding.
  • the duty cycle k/n of the generated PWM signal is more accurate.
  • the rounding algorithm is not limited to the rounding down function, and a rounding method of rounding can also be used, and round up or round down according to the calculated exact value, so as to obtain Integer value closest to this exact value, further improving the modulated duty cycle accuracy.
  • the DAB (Dual Active Full-Bridge) converter is designed with silicon carbide (SiC) switching tubes, and specifically includes: The primary side filter circuit composed of inductor L1 and capacitors C1 and C2, the high-frequency transformer primary full bridge circuit composed of SiC switch tubes S1-S4, the high-frequency inductor L, the high-frequency transformer circuit, and the SiC switch tubes Q1-Q4 are composed of Secondary side filter circuit composed of high frequency transformer secondary side full bridge circuit, inductor L2 and capacitors C3 and C4.
  • the switching frequency of the DAB converter is set to 100KHz.
  • the DAB converter can be controlled by a single phase shift (Single phase shift, SPS), as shown in Figure 8, in this SPS control mode, due to the special power transfer equation of the DAB converter, the phase shift angle cannot exceed 90°, and, in order to retain a 30% margin, the phase shift angle of its rated operation is usually set not to exceed 45°.
  • SPS single phase shift
  • a digital chip is used as a PWM generator to generate a PWM signal to control the DAB converter
  • the digital chip may be a chip of the STM32G4 series.
  • the clock frequency of the PWM signal generated by the digital chip is 170MHz.
  • the value k of the phase shift register determines the size of the duty cycle k/n of the PWM signal generated by the digital chip, that is, determines the size of the power transmission of the DAB converter.
  • the duty ratio k/n of the PWM signal needs to be modulated to improve the duty ratio precision of the PWM signal.
  • the embodiment of the present application adopts the PWM/PFM hybrid modulation method to calculate the phase-shift duty cycle required by the DAB in each working state, and determines the values of k and n that are closest to the phase-shift duty cycle.
  • Width modulation generates a PWM signal
  • pulse frequency modulation is used to modulate the PWM signal of each cycle to output a PWM signal with higher phase shift accuracy.
  • the phase shift angle output to the DAB converter is 45°, correspondingly, the phase shift angle output to the DAB converter is 45°.
  • the PWM signal generated by the pulse width modulation is subjected to subtraction modulation according to the correction value a, and the modulated phase-shifted duty cycle can be obtained as,
  • the deviation of the phase-shift duty cycle after pulse frequency modulation and the phase-shift duty cycle required by the DAB converter in the rated working state is 0, and the phase-shift angle deviation is 0°. It can be concluded that the duty cycle accuracy of the single-cycle PWM signal after pulse frequency modulation is significantly higher than the duty cycle accuracy before pulse frequency modulation is not performed. At this time, the switching frequency of the DAB converter (the frequency of the PWM signal) is 100KHz*1700/1696 ⁇ 100.24KHz.
  • the phase shift angle output to the DAB converter is 4.5°
  • the PWM signal generated by the pulse width modulation is subjected to subtraction modulation according to the correction value a, and the modulated phase-shifted duty cycle can be obtained as,
  • the deviation of the phase-shift duty cycle after pulse frequency modulation and the phase-shift duty cycle required by the DAB converter in the rated working state is 0, and the phase-shift angle deviation is 0°.
  • the switching frequency of the DAB converter (the frequency of the PWM signal) is 100KHz*1700/1680 ⁇ 100.19KHz.
  • the duty cycle accuracy of the PWM signal modulated and output by the PWM/PFM hybrid modulation method provided in the embodiment of the present application is significantly higher than that of the traditional PWM signal output by using only pulse width modulation.
  • the relative deviation of the phase angle is also smaller, and the frequency fluctuation range of the PWM signal caused by the pulse frequency modulation is smaller, which does not increase the design difficulty of the filter circuit, and has no significant impact on the operation of the DAB converter.
  • the present application can improve the duty cycle precision of a single cycle PWM signal without increasing any hardware cost, and can greatly improve the duty cycle resolution of the PWM signal.
  • the digital signal modulation apparatus 900 includes:
  • a calculation unit 901 configured to obtain the modulation value of the comparator according to the target duty cycle and the initial value of the counter; obtain the correction value according to the target duty cycle, the initial value of the counter and the modulation value of the comparator ;
  • a pulse width modulation unit 902 configured to generate a periodic PWM signal according to the modulation value of the comparator and the initial value of the counter;
  • the pulse frequency modulation unit 903 is configured to perform pulse frequency modulation on the PWM signal of each period in the periodic PWM signal according to the correction value.
  • the digital signal modulation device 900 can be applied to any high-frequency power electronic converter or switching power supply that is digitally controlled and uses duty cycle or phase shift angle to control output power, including but not limited to Buck/ Boost (boost and buck) circuits, phase-shifted full-bridge circuits, forward circuits, flyback circuits, inverter circuits, etc.
  • Buck/ Boost boost and buck
  • phase-shifted full-bridge circuits forward circuits, flyback circuits, inverter circuits, etc.
  • the target duty cycle used by the calculation unit 901 is the most accurate duty cycle that achieves the working output target. For example, in a switching power supply, the precise output of the working voltage can be determined according to the working voltage and rated voltage that the switching power supply needs to output. desired target duty cycle.
  • the modulation value and the correction value of the comparator that need to achieve the target duty cycle can be calculated respectively.
  • the modulation value of the comparator refers to the value that the comparator needs to set
  • the correction value refers to the value required for addition and subtraction modulation when the PWM signal is pulse frequency modulated.
  • the modulation value and correction value of the comparator need to be integer values that can be achieved under the premise of satisfying the modulation accuracy.
  • the calculation includes:
  • an accurate comparator value is calculated. If the exact value of the comparator is a numerical value with decimal places, the exact value of the comparator needs to be rounded to obtain the modulation value of the comparator used for pulse width modulation;
  • the ratio between it and the initial value of the counter still has a certain deviation from the target duty cycle.
  • the value performs further calculations to obtain a correction value for the pulse frequency modulation.
  • the calculation process of the correction value needs to refer to the size of the duty cycle of the PWM signal, and the calculation process is performed based on the principle of obtaining a maximum correction value.
  • the modulation value of the comparator is used as the denominator to calculate, according to the modulation value of the comparator
  • the difference between the value and the precise value of the comparator, the modulation value of the comparator and the initial value of the counter are calculated to obtain the first precision value.
  • the first precision value is a numerical value with decimal places
  • the first precision value needs to be Carry out rounding to obtain the first correction value for pulse frequency modulation; when the duty cycle of the PWM signal is greater than or equal to 0.5, that is, the modulation value of the comparator is greater than or equal to half of the initial value of the counter, at this time the initial value of the counter is
  • the difference between the value and the modulation value of the comparator is calculated as the denominator, according to the difference between the modulation value of the comparator and the exact value of the comparator, the difference between the modulation value of the comparator and the initial value of the counter and the initial value of the counter.
  • the second precision value is calculated to obtain the second precision value. If the second precision value is a numerical value with decimal places, the second precision value needs to be rounded to obtain the second correction value for pulse frequency modulation.
  • the exact value of the comparator, the closest integer value of the first precision value and the second precision value can be obtained by rounding, thereby realizing more accurate pulse width modulation and pulse frequency modulation.
  • pulse width modulation and pulse frequency modulation can be performed. specific,
  • pulse width modulation is performed, and the digital PWM generator is set according to the modulation value of the comparator and the initial value of the counter to generate a periodic PWM signal.
  • the duty cycle of the PWM signal in each cycle is the ratio of the modulation value of the comparator to the initial value of the counter.
  • the initial value of the counter of the PWM signal of each cycle is subjected to addition modulation or subtraction modulation according to the first correction value, so that the duty cycle of the modulated PWM signal is adjusted.
  • the duty cycle is closer to the target duty cycle;
  • the initial value of the counter and the modulation value of the comparator of the PWM signal of each cycle are subjected to addition modulation or subtraction modulation according to the second correction value.
  • the initial value of the counter of the PWM signal of each period is adjusted according to the first correction value.
  • the value is subtracted and modulated, that is, the initial value of the counter is subtracted by the first correction value to obtain the final value of the counter; if the duty cycle of the PWM signal is greater than or equal to 0.5, then according to the second correction value for each of the
  • the initial value of the counter and the modulation value of the comparator of the periodic PWM signal are subjected to additive modulation, that is, the modulation value of the comparator and the initial value of the counter are respectively added with a second correction value to obtain the final value of the comparator and the counter value of .
  • the initial value of the counter of the PWM signal of each period is calculated according to the first correction value.
  • Perform additive modulation that is, add the initial value of the counter to the first correction value to obtain the final value of the counter; if the duty cycle of the PWM signal is greater than or equal to 0.5, then according to the second correction value for each cycle
  • the initial value of the counter and the modulation value of the comparator of the PWM signal are subjected to subtraction modulation, that is, the modulation value of the comparator and the initial value of the counter are respectively subtracted by the second correction value to obtain the final value of the comparator and the value of the counter. value.
  • FIG. 10 is a schematic structural diagram of a computing device 1000 provided by an embodiment of the present application.
  • the computing device 1000 includes: a processor 1010 , a memory 1020 , a communication interface 1030 , and a bus 1040 .
  • the communication interface 1030 in the computing device 1000 shown in FIG. 10 can be used to communicate with other devices.
  • the processor 1010 can be connected with the memory 1020 .
  • the memory 1020 may be used to store the program codes and data. Therefore, the memory 1020 may be a storage module inside the processor 1010 , or an external storage module independent from the processor 1010 , or may include a storage module inside the processor 1010 and an external storage module independent from the processor 1010 . part.
  • the computing device 1000 may further include a bus 1040 .
  • the memory 1020 and the communication interface 1030 may be connected to the processor 1010 through the bus 1040 .
  • the bus 1040 may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus or the like.
  • PCI peripheral component interconnect standard
  • EISA Extended Industry Standard Architecture
  • the bus 1040 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one line is shown in FIG. 10, but it does not mean that there is only one bus or one type of bus.
  • the processor 1010 may adopt a central processing unit (central processing unit, CPU).
  • the processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSPs digital signal processors
  • ASICs application specific integrated circuits
  • FPGAs off-the-shelf programmable gate arrays
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the processor 1010 uses one or more integrated circuits to execute related programs, so as to implement the technical solutions provided by the embodiments of the present application.
  • the memory 1020 may include read only memory and random access memory, and provides instructions and data to the processor 1010 .
  • a portion of the processor 1010 may also include non-volatile random access memory.
  • the processor 1010 may also store device type information.
  • the processor 1010 executes the computer-executed instructions in the memory 1020 to execute the operation steps of the above method.
  • the computing device 1000 may correspond to a corresponding subject in executing the methods according to the various embodiments of the present application, and the above-mentioned and other operations and/or functions of each module in the computing device 1000 are for the purpose of realizing the present invention, respectively.
  • the corresponding processes of each method in the embodiment will not be repeated here.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .
  • Embodiments of the present application further provide a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, is used to execute a method for generating diverse problems, and the method includes the methods described in the foregoing embodiments. at least one of the options.
  • the computer storage medium of the embodiments of the present application may adopt any combination of one or more computer-readable media.
  • the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.
  • the computer readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination of the above.
  • a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a propagated data signal in baseband or as part of a carrier wave with computer-readable program code coupled thereto. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device .
  • Program code embodied on a computer readable medium may be transmitted using any suitable medium including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • Computer program code for performing the operations of the present application may be written in one or more programming languages, including object-oriented programming languages—such as Java, Smalltalk, C++, but also conventional Procedural programming language - such as the "C" language or similar programming language.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server.
  • the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or wide area network (WAN), or may be connected to an external computer (eg, through the Internet using an Internet service provider) connect).
  • LAN local area network
  • WAN wide area network
  • Internet service provider an external computer

Abstract

本申请提供了一种数字信号的调制方法，包括：根据目标占空比和计数器的初始值，获取比较器的调制值；根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值；根据所述比较器的调制值和所述计数器的初始值，生成周期性的PWM信号，根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制。本申请在不增加硬件成本的前提下，通过对每个周期的PWM信号进行脉冲频率调制，提高每个周期的PWM信号的占空比精度，以输出更高精度的PWM信号。

Description

一种数字信号的调制方法及装置、开关电源控制方法及开关电源 技术领域
本申请涉及数字编码技术领域，特别涉及一种数字信号的调制方法及装置、开关电源控制方法及开关电源。
背景技术
随着碳化硅(SiC)器件和氮化镓(GaN)器件的制造工艺日趋成熟，越来越多的开关电源采用SiC开关管或GaN开关管来设计。SiC开关管或GaN开关管的开关特性较好，可以实现数百KHz(千赫兹)的开关频率，其中GaN开关管的开关频率甚至可以达到更高。更高的开关频率可以显著减小开关电源中的电感电容变压器的体积，是提升整机功率密度的关键。
针对开关电源的不同应用场景，在小功率应用场景，可以采用模拟芯片生成模拟PWM信号来控制开关电源的工作，在中大功率应用场景，可以采用可编程控制器生成数字PWM信号来控制开关电源的工作。其中，模拟PWM信号为连续变化的信号，一旦校准，不存在精度问题。而数字PWM信号是通过离散值来模拟连续变化的信号，常用的数字PWM发生器的时钟不超过200MHz，因此在开关频率较高时，离散值太高，会影响数字PWM信号的精度。
如图1所示，数字PWM发生器通过设定计数器(Counter)的值和比较器(Compare)的值来生成对应的PWM信号，根据比较器的值和计数器的值的比值可得到PWM信号的占空比。对该PWM信号的调制方式可分为脉冲宽度调制(Pulse width modulation，PWM)和脉冲频率调制(Pulse frequency modulation，PFM)两种。其中，在脉冲宽度调制下，可以通过修改比较器的值来改变脉冲宽度，以改变占空比，在脉冲频率调制下，可以通过修改计数器的值或同时修改计数器的值和比较器的值来改变脉冲频率，以改变占空比。但是脉冲频率调制通常会造成脉冲频率在一个较宽的范围抖动，对于一般的开关电源，其不太可能在一个很宽的频率范围下工作，因此脉冲频率调制的实际可调的占空比范围不大，适用范围也相对较小，例如通常在LLC谐振电路中使用。
采用脉冲宽度调制对PWM信号进行调制时，现有的单片机可配置PWM信号输出为抖动(Dither)模式，通过使比较器的值在一定范围内抖动，实现平均占空比精度的提高。如图2所示，假设该PWM信号的计数器的值为10，通过设定比较器的值在4个周期内有规律的选择4和5之间抖动，可以实现平均占空比为4.25/10、4.5/10、4.75/10的PWM信号。一般单片机最多可配置4bit的抖动。抖动模式的缺陷是需要时间换精度，根据抖动值与时间的指数关系，例如，如果提升2bit的抖动值，在实现4.75/10的占空比精度时，需要4个周期才能实现，如果提升4bit的抖动值，在实现4.75/10的占空比时，则需要16个周期才能实现。对于需要更高精度的场合，采用4bit的抖动模式，大大降低了输出的响应速度，同时，抖动模式还会增大输出的滤波难度，并且其输出的PWM信号的占空比只是平均值的精度更高，而每个周期的占空比精度仍然较低。PWM信号的占空比的抖动，会造成输出电压电流的抖动，容易造成开关 电源的开关频率低于振荡纹波频率。
基于上述缺陷，可通过选用更高主频和性能的单片机，但是其频率和性能也仅比普通单片机高2-3倍，带来的提升有限，但成本会相对增加很多，且发热量较大。
发明内容
有鉴于此，本申请提供了一种数字信号的调制方法及装置、开关电源控制方法及开关电源，在不增加硬件成本的前提下，通过对每个周期的PWM信号进行脉冲频率调制，提高每个周期的PWM信号的占空比精度，以输出更高精度的PWM信号。
为达到上述目的，本申请的第一方面提供一种数字信号的调制方法，包括：
根据目标占空比和计数器的初始值，获取比较器的调制值；
根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值；
根据所述比较器的调制值和所述计数器的初始值生成周期性的PWM信号；
根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制。
由上，通过本方法，首先采用PWM技术，根据比较器的调制值和计数器的初始值生成周期性的PWM信号，然后采用PFM技术，根据修正值对每个周期的PWM信号进行脉冲频率调制，通过适当改变频率的方法提高每个周期的PWM信号的占空比精度，在不增加硬件成本的前提下，实现更高精度的PWM信号。
根据第一方面，在该数字信号的调制方法的第一种可能的实现方式中，所述根据目标占空比和计数器的初始值，获取比较器的调制值包括：
根据所述目标占空比和所述计数器的初始值，计算得到比较器的精确值，对所述比较器的精确值取整得到所述比较器的调制值。
由上，根据目标占空比和计数器的初始值，进行乘法计算即可得到比较器的精确值，该比较器的精确值具有小数位时，进行取整得到比较器的调制值。
根据第一方面的第一种可能的实现方式，在该数字信号的调制方法的第二种可能的实现方式中，所述根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值包括：
所述PWM信号的占空比小于0.5时，根据所述比较器的调制值与所述比较器的精确值的差值、所述比较器的调制值和所述计数器的初始值，计算得到第一精度值，对所述第一精度值取整得到第一修正值。
由上，根据PWM信号的占空比是否小于0.5，选择对应的计算方式计算出修正值，其中，所述PWM信号的占空比小于0.5时，根据所述比较器的调制值与比较器的精确值的差值、比较器的调制值和计数器的初始值，计算得到第一精度值，该第一精度值具有小数位时，进行取整得到第一修正值，利用该第一修正值对计数器的初始值进行调制，以实现对生成的每个周期的PWM信号的频率调制，从而进一步提高每个周期的PWM信号的占空比精度。
根据第一方面的第二种可能的实现方式，在该数字信号调制方法的第三种可能的实现方式中，所述根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行调制。
由上，脉冲频率调制包括高电平定长的脉冲频率调制和低电平定长的脉冲频率调制，其中高电平定长的脉冲频率调制是指高电平脉宽不变，仅调制计数器的初始值，低电平定长的脉冲频率调制是指低电平脉宽不变，需要同时调制比较器的调制值和计数器的初始值。本方法中，当生成的PWM信号的占空比小于0.5时，可选择采用高电平定长的脉冲频率调制，对计数器的初始值进行调制，从而提高最终输出的PWM信号的占空比精度。
根据第一方面的第三种可能的实现方式，在该数字信号的调制方法的第四种可能的实现方式中，
对所述比较器的精确值向下取整时，根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行减法调制；
对所述比较器的精确值向上取整时，根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行加法调制。
由上，当生成的PWM信号的占空比小于0.5时，选择高电平定长的脉冲频率调制，即需要根据第一修正值对计数器的初始值进行调制，此时调制方向与取整方向相同，若比较器的精确值向下取整，即比较器的调制值小于比较器的精确值，若想要进一步提高占空比精度值，也需要对计数器的初始值进行减法调制，调制量为计算得出的第一修正值，同理，若比较器的精确值向上取整，即比较器的调制值大于比较器的精确值，若想要进一步提高占空比精度值，也需要对计数器的初始值进行加法调制。
根据第一方面的第二种可能的实现方式，在该数字信号的调制方法的第五种可能的实现方式中，还包括：
所述PWM信号的占空比大于等于0.5时，根据所述比较器的调制值与比较器的精确值的差值、所述比较器的调制值与所述计数器的初始值的差值和所述计数器的初始值，计算得到第二精度值，对所述第二精度值取整得到第二修正值。
由上，所述PWM信号的占空比大于等于0.5时，根据所述比较器的调制值与比较器的精确值的差值、比较器的调制值与计数器的初始值的差值和计数器的初始值，计算得到第二精度值，该第二精度值具有小数位时，进行取整得到第二修正值。利用该第二修正值对计数器的初始值及比较器的调制值进行调制，以实现对生成的每个周期的PWM信号的频率调制，从而进一步提高每个周期的PWM信号的占空比精度。
根据第一方面的第五种可能的实现方式，在该数字信号的调制方法的第六种可能的实现方式中，所述根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行调制。
由上，脉冲频率调制包括高电平定长的脉冲频率调制和低电平定长的脉冲频率调制，其中高电平定长的脉冲频率调制是指高电平脉宽不变，仅调制计数器的初始值，低电平定长的脉冲频率调制是指低电平脉宽不变，需要同时调制比较器的调制值和计数器的初始值。本方法中，当生成的PWM信号的占空比大于等于0.5时，可选择采 用低电平定长的脉冲频率调制，对比较器的调制值和计数器的初始值进行调制，从而提高最终输出的PWM信号的占空比精度。
根据第一方面的第六种可能的实现方式，在该数字信号的调制方法的第七种可能的实现方式中，
对所述比较器的精确值向下取整时，则根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行加法调制；
对所述比较器的精确值向上取整时，则根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行减法调制。
由上，当生成的PWM信号的占空比大于等于0.5时，选择低电平定长的脉冲频率调制，即需要根据第二修正值对比较器的调制值和计数器的初始值进行调制，此时调制方向与取整方向相反，即比较器的精确值向下取整时，则对计数器的初始值和比较器的调制值进行加法调制，反之，比较器的精确值向上取整时，则对计数器的初始值和比较器的调制值进行减法调制，从而提高每个周期的PWM信号的占空比精度。
根据第一方面的第四种可能或第七种可能的实现方式，在该数字信号的调制方法的第八种可能的实现方式中，所述取整包括：
取最接近的整数值的方式进行所述取整。
由上，对比较器的精确值、第一精度值和第二精度值取整时，可采用四舍五入的方法取最接近的整数值，从而调制得到最接近目标占空比的PWM信号。
为达到上述目的，本申请的第二方面提供一种数字信号的调制装置，包括：
计算单元，用于根据目标占空比和计数器的初始值，获取比较器的调制值；根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值；
脉冲宽度调制单元，用于根据所述比较器的调制值和所述计数器的初始值生成周期性的PWM信号；
脉冲频率调制单元，用于根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制。
根据第二方面，在该数字信号的调制装置的第一种可能的实现方式中，所述根据目标占空比和计数器的初始值，获取比较器的调制值包括：
根据所述目标占空比和所述计数器的初始值，计算得到比较器的精确值，对所述比较器的精确值取整得到所述比较器的调制值。
根据第二方面的第一种可能的实现方式，在该数字信号的调制装置的第二种可能的实现方式中，所述根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值包括：
所述PWM信号的占空比小于0.5时，根据所述比较器的调制值与比较器的精确值的差值、比较器的调制值和计数器的初始值，计算得到第一精度值，对所述第一精度值取整得到所述第一修正值。
根据第二方面的第二种可能的实现方式，在该数字信号的调制装置的第三种可能 的实现方式中，根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行调制。
根据第二方面的第三种可能的实现方式，在该数字信号的调制装置的第四种可能的实现方式中，
对所述比较器的精确值向下取整时，根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行减法调制；
对所述比较器的精确值向上取整时，根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行加法调制。
根据第二方面的第二种可能的实现方式，在该数字信号的调制装置的第五种可能的实现方式中，还包括：
所述PWM信号的占空比大于等于0.5时，根据所述比较器的调制值与所述比较器的精确值的差值、所述比较器的调制值与所述计数器的初始值的差值和所述计数器的初始值，计算得到第二精度值，对所述第二精度值取整得到第二修正值。
根据第二方面的第五种可能的实现方式，在该数字信号的调制装置的第六种可能的实现方式中，根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行调制。
根据第二方面的第六种可能的实现方式，在该数字信号的调制装置的第七种可能的实现方式中，
对所述比较器的精确值向下取整时，则根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行加法调制；
对所述比较器的精确值向上取整时，则根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行减法调制。
根据第二方面的第四种可能或第七种可能的实现方式，在该数字信号的调制装置的第七种可能的实现方式中，所述取整包括：
取最接近的整数值的方式进行所述取整。
为达到上述目的，本申请的第三方面提供一种开关电源控制方法，包括：
根据开关电源的额定电压和目标输出电压，确定目标占空比；
根据所述目标占空比执行所述数字信号的调制方法中的数字信号的调制方法，使用输出的PWM信号控制所述开关电源。
为达到上述目的，本申请的第四方面提供一种开关电源，包括：
开关电路，该开关电路的PWM信号由所述数字信号的调制装置中任意一项所述 的装置提供。
为达到上述目的，本申请的第五方面提供一种计算设备，包括：
总线；
通信接口，其与所述总线连接；
至少一个处理器，其与所述总线连接；以及
至少一个存储器，其与所述总线连接并存储有程序指令，所述程序指令当被所述至少一个处理器执行时使得所述至少一个处理器执行所述数字信号的调制方法或开关电源控制方法中任意一项所述的方法。
为达到上述目的，本申请的第六方面提供一种计算机可读存储介质，其上存储有程序指令，所述程序指令当被计算机执行时使得所述计算机执行所述数字信号的调制方法或开关电源控制方法中任意一项所述的方法。
为达到上述目的，本申请的第七方面提供一种计算机程序产品，其包括有程序指令，所述程序指令当被计算机执行时使得所述计算机执行所述数字信号的调制方法或开关电源控制方法中任意一项所述的方法。
本申请的这些和其它方面在以下(多个)实施例的描述中会更加简明易懂。
附图说明
以下参照附图来进一步说明本申请的各个特征和各个特征之间的联系。附图均为示例性的，一些特征并不以实际比例示出，并且一些附图中可能省略了本申请所涉及领域的惯常的且对于本申请非必要的特征，或是额外示出了对于本申请非必要的特征，附图所示的各个特征的组合并不用以限制本申请。另外，在本说明书全文中，相同的附图标记所指代的内容也是相同的。具体的附图说明如下：
图1示出了现有的数字PWM信号的生成方式示意图；
图2示出了采用抖动模式调制占空比的示意图；
图3示出了脉冲宽度调制和脉冲频率调制的占空比离散度的对比示意图；
图4示出了本申请实施例提供的一种数字信号的调制方法的示意图；
图5示出了本申请实施例的PWM/FPM混合调制的示意图；
图6示出了本申请实施例提供的一种PWM/PFM的混合调制方法的示意图；
图7示出了本申请实施例提供的一种高频小型化的DAB变换器的电路图；
图8示出了本申请实施例提供的DAB变化期功率传输特性的示意图；
图9示出了本申请实施例提供的一种数字信号的调制装置的架构图；
图10示出了本申请实施例提供的一种计算设备的架构图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例 中附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。
说明书和权利要求书中的词语“第一、第二、第三等”或模块A、模块B、模块C等类似用语，仅用于区别类似的对象，不代表针对对象的特定排序，可以理解地，在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本申请实施例能够以除了在这里图示或描述的以外的顺序实施。
在以下的描述中，所涉及的表示步骤的标号，如S110、S120……等，并不表示一定会按此步骤执行，在允许的情况下可以互换前后步骤的顺序，或同时执行。
说明书和权利要求书中使用的术语“包括”不应解释为限制于其后列出的内容；它不排除其它的元件或步骤。因此，其应当诠释为指定所提到的所述特征、整体、步骤或部件的存在，但并不排除存在或添加一个或更多其它特征、整体、步骤或部件及其组群。因此，表述“包括装置A和B的设备”不应局限为仅由部件A和B组成的设备。
本说明书中提到的“一个实施例”或“实施例”意味着与该实施例结合描述的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在本说明书各处出现的用语“在一个实施例中”或“在实施例中”并不一定都指同一实施例，但可以指同一实施例。此外，在一个或多个实施例中，能够以任何适当的方式组合各特定特征、结构或特性，如从本公开对本领域的普通技术人员显而易见的那样。
对本申请具体实施方式进行进一步详细说明之前，对本申请实施例中涉及的技术用语进行说明。除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。如有不一致，以本说明书中所说明的含义或者根据本说明书中记载的内容得出的含义为准。另外，本文中所使用的术语只是为了描述本申请实施例的目的，不是旨在限制本申请。
为了准确地对本申请中的技术内容进行叙述，以及为了准确地理解本申请，在对具体实施方式进行说明之前先对本说明书中所使用的术语给出如下的解释说明或定义。
PWM：Pulse width modulation，脉冲宽度调制。
PFM：Pulse frequency modulation，脉冲频率调制。
PWM占空比：指一个脉冲周期内高电平的所占的比例。
PWM分辨率：指PWM的占空比可调的级数。
占空比离散度：指脉冲宽度调制或脉冲频率调制时，输出的相邻两个周期的占空比的变化量，占空比离散度越小，则说明占空比的可调精度越高。
下面，首先对脉冲宽度调制(PWM)和脉冲频率调制(PFM)的占空比离散度进行对比分析，以比较两种调制模式下，占空比的可调精度。
首先，设置计数器(Counter)的值为n，比较器(Compare)的值为k，为便于计算，本申请实施例及下述实施例中，对单片机输出的PWM信号的极性进行反转配置，配置计数器的值≤比较器的值时，输出高电平PWM信号，计数器的值＞比较器的值时，输出低电平PWM信号，可得PWM信号的占空比为k/n。
则，脉冲宽度调制下，占空比离散度为：
Figure PCTCN2020141431-appb-000001
脉冲频率调制包括高电平定长和低电平定长两种调制模式，其中，
高电平定长的脉冲频率调制下，占空比离散度为：
Figure PCTCN2020141431-appb-000002
或
Figure PCTCN2020141431-appb-000003
低电平定长的脉冲频率调制下，占空比离散度为：
Figure PCTCN2020141431-appb-000004
或
Figure PCTCN2020141431-appb-000005
本申请实施例中，假设将脉冲宽度调制和脉冲频率调制下的占空比离散度进行绘制，如图3所示，通过比较脉冲宽度调制和脉冲频率调制的占空比离散度，可发现在脉冲频率调制下的占空比离散度总是小于脉冲宽度调制下的占空比离散度。并且，根据该图3还可进一步得出，当k＜n/2，即占空比小于0.5时，高电平定长的脉冲频率调制下的占空比离散度更小，即占空比小于0.5时，选用高电平定长的脉冲频率调制可实现更高占空比精度的调制。反之，当k≥n/2，即占空比大于等于0.5时，低电平定长的脉冲频率调制下的占空比离散度更小，即占空比大于等于0.5时，选用低电平定长的脉冲频率调制可实现更高占空比精度的调制。
但是，如果仅采用脉冲频率调制进行调制，会造成脉冲频率在一个较宽范围内抖动，对电路的磁性元件或滤波元件的设计造成一定难度。
基于此，本申请实施例提供了一种数字信号的调制方法，通过结合脉冲宽度调制和脉冲频率调制的优点，首先采用脉冲宽度调制，生成周期性的PWM信号，然后采用脉冲频率调制，对每个周期的PWM信号进行频率调制，既可避免输出的PWM信号的脉冲频率变化较大的问题，还能大幅度提升输出的PWM信号的占空比精度。下面对本申请进行详细介绍。
实施例一
如图4所示，本申请实施例提供的一种数字信号的调制方法中，该方法包括：
S401：根据目标占空比和计数器的初始值，获取比较器的调制值；
S402：根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值；
S403：根据所述比较器的调制值和计数器的初始值，生成周期性的PWM信号；
S404：根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制。
本方法中，目标占空比为达到工作输出目标的最精确占空比，例如在开关电源中，可根据开关电源所需输出的工作电压和额定电压，确定精确输出该工作电压所需的目标占空比。其中，根据该目标占空比和数字PWM发生器的计数器的初始值，可分别计算得出需要达到该目标占空比的比较器的调制值和修正值。其中比较器的调制值指的是比较器所需设定的值，修正值指的是，对PWM信号进行脉冲频率调制时，需要进行加、减调制所需的值，本申请中，基于数字PWM发生器的工作原理，该比较器的调制值和修正值为满足调制精度前提下，可调制的整数值。该计算具体包括：
根据目标占空比和计数器的初始值，计算得到一个精确的比较器的值，为便于后文的描述，本实施例中将该精确的比较器的值定义为比较器的精确值，该比较器的精确值若为具有小数位的数值时，需要对比较器的精确值进行取整得到用于脉冲宽度调制的所述比较器的调制值；
对于所述取整后的比较器的调制值，其和计数器的初始值的比值与目标占空比必定存在一定偏差，该偏差值小于一次脉冲宽度调制所产生的占空比离散度，此时可根据比较器的精确值、比较器的调制值和计数器的初始值执行进一步的计算，得到用于脉冲频率调制的修正值。其中，该修正值的计算过程需要参考PWM信号的占空比的大小，基于得到一个最大修正值的原则执行该计算过程。具体的，所述PWM信号的占空比小于0.5时，即比较器的调制值小于计数器的初始值的一半，此时将该比较器的调制值作为分母进行计算，根据所述比较器的调制值与比较器的精确值的差值、比较器的调制值和计数器的初始值，计算得到第一精度值，该第一精度值若为具有小数位的数值时，需要对该第一精度值进行取整得到用于脉冲频率调制的第一修正值；所述PWM信号的占空比大于等于0.5时，即比较器的调制值大于等于计数器的初始值的一半，此时将该计数器的初始值与比较器的调制值的差值作为分母进行计算，根据所述比较器的调制值与比较器的精确值的差值、比较器的调制值与计数器的初始值的差值和计数器的初始值，计算得到第二精度值，该第二精度值若为具有小数位的数值时，需要对该第二精度值进行取整得到用于脉冲频率调制的第二修正值。
上述取整过程中，可采用四舍五入的方式分别取所述比较器的精确值、第一精度值和第二精度值最接近的整数值，从而实现更为精确的脉冲宽度调制和脉冲频率调制。
基于计算得到的比较器的调制值和第一、第二修正值，可进行脉冲宽度调制和脉冲频率调制。具体的，
首先进行脉冲宽度调制，根据该比较器的调制值和计数器的初始值对数字PWM发生器进行设置，生成周期性的PWM信号，基于上文介绍的，本申请实施例对输出的PWM信号的极性进行反转配置，则每个周期的PWM信号的占空比均为比较器的调制值与计数器的初始值的比值。
下面介绍对每个周期的PWM信号的脉冲频率调制过程，根据图3可知，当k＜n/2，即占空比小于0.5时，高电平定长的脉冲频率调制下的占空比离散度更小。反之，当k≥n/2，即占空比大于等于0.5时，低电平定长的脉冲频率调制下的占空比离散度 更小。因此，根据PWM信号的占空比，对周期性的PWM信号中每个周期的PWM信号进行如下脉冲频率调制：
所述PWM信号的占空比小于0.5时，根据所述第一修正值对所述每个周期的PWM信号的所述计数器的初始值进行加法调制或减法调制，使调制后的PWM信号的占空比更加接近所述目标占空比；
所述PWM信号的占空比大于等于0.5时，根据所述第二修正值对所述每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行加法调制或减法调制。
其中，根据对比较器的精确值向下取整或向上取整，决定执行减法调制或加法调制，具体的，
当对所述比较器的精确值向下取整时，若所述PWM信号的占空比小于0.5，则根据所述第一修正值对所述每个周期的PWM信号的所述计数器的初始值进行一次或多次减法调制，即将计数器的初始值减去第一修正值以得到最终的计数器的值；若所述PWM信号的占空比大于等于0.5，则根据所述第二修正值对所述每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行一次或多次加法调制，即将比较器的调制值和计数器的初始值分别加上第二修正值，以得到最终的比较器的值和计数器的值。
当对所述比较器的精确值向上取整时，若所述PWM信号的占空比小于0.5，则根据所述第一修正值对所述每个周期的PWM信号的所述计数器的初始值进行一次或多次加法调制，即将计数器的初始值加上第一修正值以得到最终的计数器的值；若所述PWM信号的占空比大于等于0.5，则根据所述第二修正值对所述每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行一次或多次减法调制，即将比较器的调制值和计数器的初始值分别减去第二修正值，以得到最终的比较器的值和计数器的值。
本申请实施例中，上述进行脉冲频率调制的次数由脉冲频率调制的最大精度决定，例如当脉冲频率调制的最大精度值小于所述第一修正值或第二修正值，此时仅进行一次调制无法达到该第一修正值或第二修正值，则需要进行多次调制。
如图5所示，本申请实施例通过采用在脉冲宽度调制中插入脉冲频率调制的方式，首先采用脉冲宽度调制生成周期性的PWM信号，然后对周期性的PWM信号中每个周期的PWM信号进行进一步的脉冲频率调制，并在对单个周期的PWM信号的脉冲频率调制结束后，恢复比较器的调制值和计数器的初始值，使下一个周期的PWM信号的初始占空比仍然为脉冲宽度调制生成的PWM信号的占空比。下面对本申请实施例调制方法的精度进行如下公式解释，设脉冲宽度调制生成的PWM信号的占空比为k/n，k为比较器的调制值，n为计数器的初始值，设上述计算得到的第一修正值为a，第二修正值为b，则进行脉冲频率调制后，调制前和调制后的占空比差值小于脉冲宽度调制的占空比离散度，如下：
Figure PCTCN2020141431-appb-000006
或
Figure PCTCN2020141431-appb-000007
或
Figure PCTCN2020141431-appb-000008
或
Figure PCTCN2020141431-appb-000009
因此，可说明本申请实施例通过对每个周期的PWM信号进行脉冲频率调制，相较于仅进行脉冲宽度调制，可进一步提高每个周期的PWM信号的占空比精度，无需增加硬件成本的前提下，最大程度的提供单个周期的PWM信号的占空比分辨率。
实施例二
如图6所示，本申请实施例提供的一种PWM/PFM的混合调制方法中，通过PI调节器(Proportional Integral Controller)设定需要的目标占空比d，根据该目标占空比d和计数器的初始值n，即可得到该目标占空比对应的比较器的精确值K＝d*n。通过将该比较器的精确值K进行向下取整，可得到整数部分k和小数部分Δk，floor函数为向下取整函数，
k＝floor(K)；
Δk＝K-k。
传统的脉冲宽度调制中，根据取整得到的整数部分k以及计数器的初始值n，即可实现脉冲宽度调制，输出占空比为k/n的PWM信号，该脉冲宽度调制输出的PWM信号的占空比精度太低，与PI调节器中设定的目标占空比的差值较大。
因此，本申请实施例采用PWM/PFM的混合调制方法，首先采用与传统脉冲宽度调制相同的方式，根据整数部分k和计数器的初始值n，调制生成每个周期的PWM信号，该PWM信号的占空比为k/n，与传统脉冲宽度调制不同的是，本申请实施例，还需要对每个周期的PWM信号进行进一步的脉冲频率调制。
其中，根据PWM信号的占空比是否大于等于0.5，即k是否大于等于n/2，选择不同的修正值的计算方式及对应的脉冲频率调制，具体的，
当k＜n/2时，选择高电平定长的PFM的调制方式，此时根据取整得到整数部分k和小数部分Δk，以及计时器初始值n，计算修正值a，
a＝floor(Δk*n/k)；
利用该修正值a，进行高电平定长的脉冲频率调制，对每个周期的PWM信号进行调制，调制后输出的占空比为k/(n-a)。
当k≥n/2时，选择低电平不变的脉冲频率调制，此时根据取整得到整数部分k和小数部分Δk，以及计时器初始值n，计算修正值b，
b＝floor(Δk*n/n-k)；
利用该修正值b，进行高电平定长的脉冲频率调制，对每个周期的PWM信号进行调制，调制后输出的占空比为(k+b)/(n+b)。
经过所述脉冲频率调制后输出的占空比k/(n-a)或(k+b)/(n+b)，相较于根据取整的比较器的调制值k和计数器的初始值n所生成的PWM信号的占空比k/n，精度更高。
本申请的一些实施例中，取整算法不局限于向下取整函数，还可以采用四舍五入 的取整方式，根据计算得出的精确值进行向上取整或向下取整，以取整得到最接近该精确值的整数值，从而进一步提高调制后的占空比精度。
实施例三
下面基于图6所述的混合调制方法，结合一具体应用场景进行详细介绍。
如图7所示为本申请实施例提供的一种高频小型化的DAB变换器的电路图，该DAB(双有源全桥)变换器采用碳化硅(SiC)开关管来设计，具体包括：由电感L1和电容C1、C2组成的原边滤波电路、SiC开关管S1-S4组成的高频变压器原边全桥电路、高频电感L、高频变压器电路、SiC开关管Q1-Q4组成的高频变压器副边全桥电路、电感L2和电容C3、C4组成的副边滤波电路。该DAB变换器的开关频率设定为100KHz。
该DAB变换器可以采用单移相(Single phase shift，SPS)控制的方式，如图8所示，在该SPS控制方式下，由于DAB变换器的特殊功率传输方程，导致其移相角不能超过90°，并且，为保留30％的裕量，通常设置其额定工作时的移相角不超过45°。
本申请实施例中，采用数字芯片作为PWM发生器，生成PWM信号对该DAB变换器进行控制，该数字芯片可以为STM32G4系列的芯片。该数字芯片生成的PWM信号的时钟频率为170MHz，基于该DAB变换器额定工作时的移相角不超过45°，可得到，该DAB变换器额定工作时，该数字芯片的周期寄存器(计数器)的值设定为n＝170MHz/100KHz＝1700，移相寄存器(比较器)的值设定为k＝1700*(45°/360°)≈213。其中，该移相寄存器的取值k决定了该数字芯片生成的PWM信号的占空比k/n的大小，即决定了DAB变换器的功率传输的大小，为实现更高精度的功率传输，需要对该PWM信号的占空比k/n进行调制，以提高该PWM信号的占空比精度。
本申请实施例采用PWM/PFM混合调制的方法，对DAB在各个工作状态所需的移相占空比进行计算，确定最接近该移相占空比的k和n的取值，通过先脉冲宽度调制生成PWM信号，再利用脉冲频率调制对每个周期的PWM信号进行调制，以输出更高移相精度的PWM信号。具体的，
当DAB变换器处于全载的额定工作状态时，根据DAB变换器的特殊功率传输方程，输出给该DAB变换器的移相角为45°，对应的，则输出给该DAB变换器的移相占空比为d＝45°/360°＝0.125。根据本方法可得，该移相占空比对应的比较器的精确值为K＝1700*0.125＝212.5，采用向下取整函数对该比较器的精确值取整可得，
k＝floor(K)＝212，
Δk＝K-k＝0.5，
基于取整得到的比较器的调制值k和移相寄存器(比较器)的值n，进行脉冲宽度调制，生成的PWM信号的占空比为212/1700≈0.1247，移相角为0.1247*360°＝44.892°，与移相角45°的偏差为0.11°，相对偏差百分比为0.24％。因此，通过本方法，可对该脉冲宽度调制生成的每个周期的PWM信号进行脉冲频率调制。
由于该占空比d＜0.5，此时根据本申请选用高电平不变的脉冲频率调制，则根据取整得到整数部分k和小数部分Δk，以及移相寄存器(比较器)的值n，计算修正值a，
a＝floor(Δk*n/k)＝floor(0.5*1700/212)＝4，
由于对比较器的精确值采用向下取整的方式，此时根据该修正值a对脉冲宽度调制生成的PWM信号进行减法调制，可得到调制后的移相占空比为，
k/n-a＝212/(1700-4)＝0.125，
可得出，经过脉冲频率调制后的移相占空比与DAB变换器处于额定工作状态所需的移相占空比的偏差为0，移相角偏差为0°。可得出，进行脉冲频率调制后的单个周期的PWM信号的占空比精度明显高于未进行脉冲频率调制前的占空比精度。此时该DAB变换器的开关频率(PWM信号的频率)为100KHz*1700/1696≈100.24KHz。
当DAB变换器处于轻载的工作状态时，输出给该DAB变换器的移相角为4.5°，对应的，则输出给该DAB变换器的移相占空比为d＝4.5°/360°＝0.0125。根据本方法可得，该移相占空比对应的比较器的精确值为K＝1700*0.0125＝21.25，采用向下取整函数对该比较器的精确值取整可得，
k＝floor(K)＝21，
Δk＝K-k＝0.25，
基于取整得到的比较器的调制值k和移相寄存器(比较器)的值n，进行脉冲宽度调制，生成的PWM信号的占空比为21/1700≈0.01235，移相角为0.01235*360°＝4.446°，与移相角4.5°的偏差为0.054°，相对偏差百分比为1.11％。因此，通过本方法，可对该脉冲宽度调制生成的每个周期的PWM信号进行脉冲频率调制。
由于该占空比d＜0.5，此时根据本申请选用高电平不变的脉冲频率调制，则根据取整得到整数部分k和小数部分Δk，以及移相寄存器(比较器)的值n，计算修正值a，
a＝floor(Δk*n/k)＝floor(0.25*1700/21)＝20，
由于对比较器的精确值采用向下取整的方式，此时根据该修正值a对脉冲宽度调制生成的PWM信号进行减法调制，可得到调制后的移相占空比为，
k/n-a＝21/(1700-20)＝0.0125，
可得出，经过脉冲频率调制后的移相占空比与DAB变换器处于额定工作状态所需的移相占空比的偏差为0，移相角偏差为0°。此时该DAB变换器的开关频率(PWM信号的频率)为100KHz*1700/1680≈100.19KHz。
综上所述，本申请实施例提供的PWM/PFM混合调制方法所调制输出的PWM信号的占空比精度明显高于传统的只使用脉冲宽度调制所输出的PWM信号的占空比精度，移相角的相对偏差也更小，同时脉冲频率调制所造成的PWM信号的频率波动范围较小，不会增加滤波电路的设计难度，对DAB变换器的工作无显著影响。本申请在无需增加任何硬件成本的前提下，可以提高单个周期的PWM信号的占空比精度，可极大提高PWM信号的占空比的分辨率。
实施例四
如图9所示为本申请实施例提供的一种数字信号的调制装置的架构图，该数字信号的调制装置900包括：
计算单元901，用于根据目标占空比和计数器的初始值，获取比较器的调制值； 根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值；
脉冲宽度调制单元902，用于根据所述比较器的调制值和所述计数器的初始值生成周期性的PWM信号；
脉冲频率调制单元903，用于根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制。
本申请实施例中，该数字信号的调制装置900可应用到任何数字控制并使用占空比或移相角来控制输出功率的高频电力电子变换器或开关电源中，包括但不限于Buck/Boost(升压和降压)电路、移相全桥电路、正激电路、反激电路、逆变电路等等。
其中，计算单元901所使用的目标占空比为达到工作输出目标的最精确占空比，例如在开关电源中，可根据开关电源所需输出的工作电压和额定电压，确定精确输出该工作电压所需的目标占空比。其中，根据该目标占空比和数字PWM发生器的计数器的初始值，可分别计算得出需要达到该目标占空比的比较器的调制值和修正值。其中比较器的调制值指的是比较器所需设定的值，修正值指的是，对PWM信号进行脉冲频率调制时，需要进行加、减调制所需的值，本申请中，基于数字PWM发生器的工作原理，该比较器的调制值和修正值需要为满足调制精度前提下，可达到的整数值。该计算具体包括：
根据目标占空比和计数器的初始值，计算得到一个精确的比较器的值，为便于后文的区分，本实施例中将该精确的比较器的值定义为比较器的精确值，该比较器的精确值若为具有小数位的数值时，需要对比较器的精确值进行取整得到用于脉冲宽度调制的所述比较器的调制值；
对于所述取整后的比较器的调制值，其和计数器的初始值的比值与目标占空比仍然存在一定偏差，此时可根据比较器的精确值、比较器的调制值和计数器的初始值执行进一步的计算，得到用于脉冲频率调制的修正值。其中，该修正值的计算过程需要参考PWM信号的占空比的大小，基于得到一个最大修正值的原则执行该计算过程。具体的，所述PWM信号的占空比小于0.5时，即比较器的调制值小于计数器的初始值的一半，此时将该比较器的调制值作为分母进行计算，根据所述比较器的调制值与比较器的精确值的差值、比较器的调制值和计数器的初始值，计算得到第一精度值，该第一精度值若为具有小数位的数值时，需要对该第一精度值进行取整得到用于脉冲频率调制的第一修正值；所述PWM信号的占空比大于等于0.5时，即比较器的调制值大于等于计数器的初始值的一半，此时将该计数器的初始值与比较器的调制值的差值作为分母进行计算，根据所述比较器的调制值与比较器的精确值的差值、比较器的调制值与计数器的初始值的差值和计数器的初始值，计算得到第二精度值，该第二精度值若为具有小数位的数值时，需要对该第二精度值进行取整得到用于脉冲频率调制的第二修正值。
上述取整过程中，可采用四舍五入的方式分别取所述比较器的精确值、第一精度值和第二精度值最接近的整数值，从而实现更为精确的脉冲宽度调制和脉冲频率调制。
基于计算得到的比较器的调制值和第一、第二修正值，可进行脉冲宽度调制和脉冲频率调制。具体的，
首先进行脉冲宽度调制，根据该比较器的调制值和计数器的初始值对数字PWM发生器进行设置，生成周期性的PWM信号，基于上文介绍的，本申请实施例对输出的PWM信号的极性进行反转配置，则每个周期的PWM信号的占空比均为比较器的调制值与计数器的初始值的比值。
下面介绍对每个周期的PWM信号的脉冲频率调制过程，根据图3可知，当k＜n/2，即占空比小于0.5时，高电平定长的脉冲频率调制下的占空比离散度更小。反之，当k≥n/2，即占空比大于等于0.5时，低电平定长的脉冲频率调制下的占空比离散度更小。因此，根据PWM信号的占空比，对周期性的PWM信号中每个周期的PWM信号进行如下脉冲频率调制：
所述PWM信号的占空比小于0.5时，根据所述第一修正值对所述每个周期的PWM信号的所述计数器的初始值进行加法调制或减法调制，使调制后的PWM信号的占空比更加接近所述目标占空比；
所述PWM信号的占空比大于等于0.5时，根据所述第二修正值对所述每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行加法调制或减法调制。
其中，根据对比较器的精确值向下取整或向上取整，决定执行减法调制或加法调制，具体的，
当对所述比较器的精确值向下取整时，若所述PWM信号的占空比小于0.5，则根据所述第一修正值对所述每个周期的PWM信号的所述计数器的初始值进行减法调制，即将计数器的初始值减去第一修正值以得到最终的计数器的值；若所述PWM信号的占空比大于等于0.5，则根据所述第二修正值对所述每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行加法调制，即将比较器的调制值和计数器的初始值分别加上第二修正值，以得到最终的比较器的值和计数器的值。
当对所述比较器的精确值向上取整时，若所述PWM信号的占空比小于0.5，则根据所述第一修正值对所述每个周期的PWM信号的所述计数器的初始值进行加法调制，即将计数器的初始值加上第一修正值以得到最终的计数器的值；若所述PWM信号的占空比大于等于0.5，则根据所述第二修正值对所述每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行减法调制，即将比较器的调制值和计数器的初始值分别减去第二修正值，以得到最终的比较器的值和计数器的值。
图10是本申请实施例提供的一种计算设备1000的结构性示意性图。该计算设备1000包括：处理器1010、存储器1020、通信接口1030、总线1040。
应理解，图10所示的计算设备1000中的通信接口1030可以用于与其他设备之间进行通信。
其中，该处理器1010可以与存储器1020连接。该存储器1020可以用于存储该程序代码和数据。因此，该存储器1020可以是处理器1010内部的存储模块，也可以是与处理器1010独立的外部存储模块，还可以是包括处理器1010内部的存储模块和与处理器1010独立的外部存储模块的部件。
其中，计算设备1000还可以包括总线1040。其中，存储器1020、通信接口1030可以通过总线1040与处理器1010连接。总线1040可以是外设部件互连标准(Peripheral  Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线1040可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条线表示，但并不表示仅有一根总线或一种类型的总线。
应理解，在本申请实施例中，该处理器1010可以采用中央处理模块(central processing unit，CPU)。该处理器还可以是其它通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate Array，FPGA)或者其它可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。或者该处理器1010采用一个或多个集成电路，用于执行相关程序，以实现本申请实施例所提供的技术方案。
该存储器1020可以包括只读存储器和随机存取存储器，并向处理器1010提供指令和数据。处理器1010的一部分还可以包括非易失性随机存取存储器。例如，处理器1010还可以存储设备类型的信息。
在计算设备1000运行时，所述处理器1010执行所述存储器1020中的计算机执行指令执行上述方法的操作步骤。
应理解，根据本申请实施例的计算设备1000可以对应于执行根据本申请各实施例的方法中的相应主体，并且计算设备1000中的各个模块的上述和其它操作和/或功能分别为了实现本实施例各方法的相应流程，为了简洁，在此不再赘述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以 存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时用于执行一种多样化问题生成方法，该方法包括上述各个实施例所描述的方案中的至少之一。
本申请实施例的计算机存储介质，可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质例如可以是，但不限于，电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本文件中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中连接了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括、但不限于无线、电线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
注意，上述仅为本申请的较佳实施例及所运用的技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申 请的构思的情况下，还可以包括更多其他等效实施例，均属于本申请的保护范畴。

Claims (23)

  1. 一种数字信号的调制方法，其特征在于，包括：
    根据目标占空比和计数器的初始值，获取比较器的调制值；
    根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值；
    根据所述比较器的调制值和计数器的初始值，生成周期性的脉冲宽度调制PWM信号；
    根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制。
  2. 根据权利要求1所述的方法，其特征在于，所述根据目标占空比和计数器的初始值，获取比较器的调制值包括：
    根据所述目标占空比和所述计数器的初始值，计算得到比较器的精确值，对所述比较器的精确值取整得到所述比较器的调制值。
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值包括：
    所述PWM信号的占空比小于0.5时，根据所述比较器的调制值与所述比较器的精确值的差值、所述比较器的调制值和所述计数器的初始值，计算得到第一精度值，对所述第一精度值取整得到第一修正值。
  4. 根据权利要求3所述的方法，其特征在于，根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
    根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行调制。
  5. 根据权利要求4所述的方法，其特征在于，
    对所述比较器的精确值向下取整时，根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行减法调制；
    对所述比较器的精确值向上取整时，根据所述第一修正值对所述每个周期的PWM信号的所述计数器的初始值进行加法调制。
  6. 根据权利要求3所述的方法，其特征在于，还包括：
    所述PWM信号的占空比大于等于0.5时，根据所述比较器的调制值与所述比较器的精确值的差值、所述比较器的调制值与所述计数器的初始值的差值和所述计数器的初始值，计算得到第二精度值，对所述第二精度值取整得到第二修正值。
  7. 根据权利要求6所述的方法，其特征在于，根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
    根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行调制。
  8. 根据权利要求7所述的方法，其特征在于，
    对所述比较器的精确值向下取整时，根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行加法调制；
    对所述比较器的精确值向上取整时，根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行减法调制。
  9. 根据权利要求5或8所述的方法，其特征在于，所述取整包括：
    取最接近的整数值的方式进行所述取整。
  10. 一种数字信号的调制装置，其特征在于，包括：
    计算单元，用于根据目标占空比和计数器的初始值，获取比较器的调制值；根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值；
    脉冲宽度调制单元，用于根据所述比较器的调制值和所述计数器的初始值，生成周期性的PWM信号；
    脉冲频率调制单元，用于根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制。
  11. 根据权利要求10所述的装置，其特征在于，所述根据目标占空比和计数器的初始值，获取比较器的调制值包括：
    根据所述目标占空比和所述计数器的初始值，计算得到比较器的精确值，对所述比较器的精确值取整得到所述比较器的调制值。
  12. 根据权利要求11所述的装置，其特征在于，所述根据所述目标占空比、所述计数器的初始值和所述比较器的调制值，获取修正值包括：
    所述PWM信号的占空比小于0.5时，根据所述比较器的调制值与所述比较器的精确值的差值、所述比较器的调制值和所述计数器的初始值，计算得到第一精度值，对所述第一精度值取整得到第一修正值。
  13. 根据权利要求12所述的装置，其特征在于，根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
    根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行调制。
  14. 根据权利要求13所述的装置，其特征在于，
    对所述比较器的精确值向下取整时，根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行减法调制；
    对所述比较器的精确值向上取整时，根据所述第一修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值进行加法调制。
  15. 根据权利要求12所述的装置，其特征在于，还包括：
    所述PWM信号的占空比大于等于0.5时，根据所述比较器的调制值与所述比较器的精确值的差值、所述比较器的调制值与所述计数器的初始值的差值和所述计数器的初始值，计算得到第二精度值，对所述第二精度值取整得到第二修正值。
  16. 根据权利要求15所述的装置，其特征在于，根据所述修正值对所述周期性的PWM信号中每个周期的PWM信号进行脉冲频率调制包括：
    根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和比较器的调制值进行调制。
  17. 根据权利要求16所述的装置，其特征在于，
    对所述比较器的精确值向下取整时，则根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行加法调制；
    对所述比较器的精确值向上取整时，则根据所述第二修正值对所述周期性的PWM信号中每个周期的PWM信号的所述计数器的初始值和所述比较器的调制值进行减法调制。
  18. 根据权利要求14或17所述的装置，其特征在于，所述取整包括：
    取最接近的整数值的方式进行所述取整。
  19. 一种开关电源控制方法，其特征在于，包括：
    根据开关电源的额定电压和目标输出电压，确定目标占空比；
    根据所述目标占空比执行权利要求1至9中任意一项所述的数字信号的调制方法，使用输出的PWM信号控制所述开关电源。
  20. 一种开关电源，其特征在于，包括：
    开关电路，该开关电路的PWM信号由权利要求10至18任意一项所述的装置提供。
  21. 一种计算设备，其特征在于，包括：
    总线；
    通信接口，其与所述总线连接；
    至少一个处理器，其与所述总线连接；以及
    至少一个存储器，其与所述总线连接并存储有程序指令，所述程序指令当被所述至少一个处理器执行时使得所述至少一个处理器执行权利要求1至9或权利要求19中任意一项所述的方法。
  22. 一种计算机可读存储介质，其特征在于，其上存储有程序指令，所述程序指令当被计算机执行时使得所述计算机执行权利要求1至9或权利要求19中任意一项所述的方法。
  23. 一种计算机程序产品，其特征在于，其包括有程序指令，所述程序指令当被计算机执行时使得所述计算机执行权利要求1至9或权利要求19中任意一项所述的方法。
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