WO2022137553A1 - Method for manufacturing wiring pattern, and wiring pattern with resist - Google Patents

Method for manufacturing wiring pattern, and wiring pattern with resist Download PDF

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Publication number
WO2022137553A1
WO2022137553A1 PCT/JP2020/048915 JP2020048915W WO2022137553A1 WO 2022137553 A1 WO2022137553 A1 WO 2022137553A1 JP 2020048915 W JP2020048915 W JP 2020048915W WO 2022137553 A1 WO2022137553 A1 WO 2022137553A1
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Prior art keywords
wiring pattern
wiring
pattern
mask
peeling
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Application number
PCT/JP2020/048915
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French (fr)
Japanese (ja)
Inventor
光昭 戸田
良明 成沢
敬之 山本
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株式会社メイコー
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Priority to PCT/JP2020/048915 priority Critical patent/WO2022137553A1/en
Publication of WO2022137553A1 publication Critical patent/WO2022137553A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

Definitions

  • the present invention relates to a wiring pattern manufacturing method and a wiring pattern with a resist.
  • a semi-additive method and an MSAP method are known as disclosed in Patent Document 1.
  • a dry film is provided on the surface of a substrate on which a copper foil is laminated, and the dry film is exposed and developed to form a non-masked portion, and electrolysis is performed on the copper foil exposed in the non-masked portion.
  • electrolysis is performed on the copper foil exposed in the non-masked portion.
  • a wiring pattern having a substantially rectangular cross-sectional shape is formed.
  • the entire surface of the substrate is etched according to the thickness of the copper foil to remove the copper foil in the portion unnecessary for the circuit, thereby creating a thinned wiring pattern. can.
  • the wiring pattern has a smaller wiring width than the desired design width, and the smaller the design width is set, the greater the influence is, and in some cases, the wiring pattern may disappear from the position to be formed. Occurs.
  • an etching resist made of a resin material can be formed only on the upper surface of the wiring pattern, only the copper foil can be etched relatively easily without reducing the wiring width of the wiring pattern.
  • the procedure for forming the etching resist is added to the procedure of the MSAP method. It is thought that it can be incorporated.
  • the wiring pattern formed on the non-masked portion of the dry film is not formed in a perfect rectangular shape, and a slight gap is generated between the side surface of the plated conductor and the inner surface surface of the dry film. Then, since the electrodeposition film formed on the plated conductor is formed from a liquid material, it is cured in a state of entering the gap. At this time, since the electrodeposition film and the dry film are similar components containing a common resin material, the dry film in contact with the electrodeposition film is denatured by the bond between the resins, and the stripping solution for peeling the dry film is used. Since the residue cannot be peeled off, the quality of the wiring pattern may be deteriorated.
  • the present invention has been made in view of such a problem, and an object of the present invention is a wiring pattern manufacturing method capable of suppressing the generation of mask residue while maintaining the wiring width of the wiring pattern as designed. And to provide a wiring pattern with a resist.
  • the wiring pattern manufacturing method of the present invention comprises a mask forming step of forming an insulating mask pattern on an insulating substrate provided with a conductive layer on the surface, and conductor plating on a non-masked portion of the conductive layer.
  • the thickness of the wiring pattern is set to be equal to or larger than the thickness of the mask pattern.
  • the wiring pattern is formed so as to include a main body having a predetermined first wiring width and a head having a second wiring width wider than the first wiring width and provided on the upper surface of the main body. do.
  • the wiring pattern with resist of the present invention includes a main body having a predetermined first wiring width and a head provided on the upper surface of the main body and having a second wiring width wider than the first wiring width.
  • a wiring pattern made of conductor plating in which the main body and the head are integrally formed, and a resist film made of a resin material provided on the upper surface and side surfaces of the head are provided.
  • the present invention it is possible to provide a wiring pattern manufacturing method capable of suppressing the generation of mask residue while maintaining the wiring width of the wiring pattern as designed, and a wiring pattern with a resist.
  • the wiring pattern manufacturing method according to the present invention comprises procedures of a mask forming step, a plating step, an electrodeposition step, a mask peeling step, an etching step, and an electrodeposition film peeling step.
  • a mask forming step a plating step
  • an electrodeposition step a mask peeling step
  • an etching step an etching step
  • an electrodeposition film peeling step a mask peeling step
  • FIG. 1 is a cross-sectional view of a substrate showing a mask forming process according to the present invention.
  • the mask pattern 3 having an insulating property is formed on the insulating substrate 1 provided with the conductive layer 2 on the surface.
  • the insulating substrate 1 is made of a resin material and is, for example, a rigid support substrate, but may be a flexible substrate or a multilayer substrate.
  • the conductive layer 2 is a conductive metal thin film having a thickness of about 5 ⁇ m, and is, for example, a copper foil formed by laminating on the insulating substrate 1 or electroless copper plating formed on the surface of the insulating substrate 1.
  • the mask pattern 3 is an alkaline development type dry film, which is exposed along the wiring formation position and developed with a developer of 1% sodium carbonate (Na 2 CO 3 ) to form a non-mask portion 3a. .. That is, the surface of the conductive layer 2 is exposed in the non-masked portion 3a of the mask pattern 3. At this time, the non-masked portion 3a is set to the first wiring width L1 which is a design value of the wiring width of the wiring pattern 4 to be formed.
  • FIG. 2 is a cross-sectional view of a substrate showing a plating process according to the present invention.
  • the conductive layer 2 as the seed layer is energized in the copper sulfate plating solution to form the wiring pattern 4 as the electrolytic copper plating on the non-masked portion 3a.
  • the thickness of the wiring pattern 4 is controlled according to the energization current and the cumulative current based on the energization time, and is set to be equal to or larger than the thickness of the mask pattern 3 in the present invention.
  • the electrolytic copper plating overflows from the non-masked portion 3a of the mask pattern 3 and is wider than the main body 4a having the above-mentioned predetermined first wiring width L1 and the first wiring width L1. It has a shape such that it has a second wiring width L2 and has a head portion 4b provided on the upper surface of the main body 4a. Since the main body 4a and the head 4b are integrally formed by a series of copper plating, there is no boundary between them.
  • FIG. 3 is a cross-sectional view of a substrate showing an electrodeposition process according to the present invention.
  • the electrodeposition step by energizing the wiring pattern 4 in a liquid containing an electrodeposition material made of a resin material, a thickness of about 1 to 5 ⁇ m is applied to the exposed surface of the wiring pattern 4, that is, the upper surface and the side surface of the head 4b.
  • the electrodeposited film 5 to have is formed.
  • the wiring pattern 4 is filled with the non-masked portion 3a of the mask pattern 3, and is further formed in a shape such that the non-masked portion 3a of the mask pattern 3 is covered with the head 4b described above. .. Therefore, the possibility that a gap G is generated between the inner surface of the non-mask portion 3a in the mask pattern 3 and the side surface of the main body 4a of the wiring pattern 4 is suppressed, and even if a slight gap G is generated, the electrodeposition material is included. It is possible to prevent the solution from infiltrating the gap G.
  • the electrodeposition film 5 is a resin design that does not dissolve in the dry film peeling solution for peeling the mask pattern 3 in a later step, and functions as a resist for etching treatment described later.
  • FIG. 4 is a cross-sectional view of a substrate showing a mask peeling step according to the present invention.
  • the mask pattern 3 used for forming the wiring pattern 4 is removed with a stripping solution containing 3% caustic soda (NaOH).
  • a stripping solution containing 3% caustic soda (NaOH) As a result, the surface of the conductive layer 2 of the substrate is exposed at the portion where the wiring pattern 4 is not formed.
  • a resisted wiring pattern 6 composed of a wiring pattern 4 and an electrodeposition film 5 as an etching resist is formed on the surface of the conductive layer 2.
  • the stripping solution of the mask pattern 3 is composed of a component that dissolves the alkaline development type dry film, it has no dissolving action on the electrodeposition film 5, and both the mask pattern 3 and the electrodeposition film made of a resin material have no dissolving action. Of 5, only the mask pattern 3 can be selectively removed. Further, although the mask pattern 3 and the electrodeposition film 5 are made of a material that easily bonds between resins as described in detail later, in the present invention, the contact area between the two is minimized. Therefore, in the mask peeling step according to the present invention, the mask pattern 3 can be peeled with high accuracy without causing a residue.
  • FIG. 5 is a cross-sectional view of a substrate showing an etching process according to the present invention.
  • the conductive layer 2 is etched with a standard solution such as an aqueous solution of cupric chloride using the electrodeposition film 5 as an etching resist.
  • the conductive layer 2 in the region where the resisted wiring pattern 6 does not exist is removed, and a circuit pattern in which the plurality of wiring patterns 4 are insulated from each other is formed.
  • the wiring pattern 4 is made of copper like the conductive layer 2, since the electrodeposition film 5 serves as an etching resist, surface etching is prevented, and the first wiring width L1 as a desired design value is obtained. Can be maintained.
  • the above-mentioned cupric chloride aqueous solution for etching the conductive layer 2 also dissolves the electrodeposition film 5 in the etching step. It ends up. Therefore, when the electrodeposition film 5 is made of a metal material, a peroxide-based etching solution such as ammonium persulfate that can etch the conductive layer 2 and does not dissolve the electrodeposition film 5 is used.
  • a peroxide-based etching solution such as ammonium persulfate that can etch the conductive layer 2 and does not dissolve the electrodeposition film 5 is used.
  • the method using a peroxide-based etching solution requires a complicated process for reducing the environmental load such as waste liquid treatment of lead contained in solder.
  • the electrodeposition film 5 in the present invention is formed of the resin material as described above, so that even if an aqueous solution of cupric chloride having a low environmental load is used in the etching process, the electrodeposition film 5 is maintained as an etching resist without being dissolved. To.
  • FIG. 6 is a cross-sectional view of a substrate showing the electrodeposition film peeling step according to the present invention.
  • the electrodeposition film 5 can be peeled from the surface of the wiring pattern 4 by, for example, a known organic amine-based stripping liquid. As a result, a fine circuit pattern made of only copper as a conductive material is formed on the upper surface of the insulating substrate 1.
  • the circuit pattern can be used as it is in the fine circuit of the printed wiring board, but it can also be shaped into a rectangular cross section and used by further performing the following shaping step.
  • two types of shaping processes will be described.
  • FIG. 7 is a cross-sectional view of a substrate showing a first shaping step according to the present invention.
  • the wiring pattern 4 is shaped so as to have the same thickness as the mask pattern 3 before peeling. That is, in the first shaping step, the portion of the wiring pattern 4 formed in the plating step described above, which corresponds to the head portion 4b, can be polished to leave the portion of the main body 4a having a rectangular cross section.
  • the upper surface of the wiring is polished by several ⁇ m as a pretreatment for coating the wiring pattern 4 with a solder resist.
  • the polishing can be the first shaping step.
  • the mask pattern 3 is formed so as to be the same as the predetermined design thickness at the stage of the mask forming step described above. By doing so, the thickness of the wiring pattern 4 can be made as designed.
  • FIG. 8 is a cross-sectional view of a substrate showing a second shaping step according to the present invention.
  • the second shaping step after the electrodeposition film peeling step described above, the protruding portion 4c of the wiring pattern 4 protruding in the pattern width direction is etched. That is, in the second shaping step, the protruding portion 4c having a sharp shape is preferentially etched by slightly etching the surface of the wiring pattern 4 formed in the plating step described above.
  • the wiring pattern 4 in the state of FIG. 6 is used as the inner layer pattern of the multilayer wiring board, the upper surface of the wiring is etched by several ⁇ m as a pretreatment for burying the wiring pattern 4 with, for example, an insulating resin layer. Etching can be the second shaping step.
  • the wiring pattern 4 is set to have a predetermined design thickness or more by an etching amount sufficient to remove the protruding portion 4c of the wiring pattern 4.
  • the thickness of the wiring pattern 4 shaped in the second shaping step can be controlled to the thickness as designed.
  • the mask pattern 3 is formed on the insulating substrate 1 provided with the conductive layer 2 on the surface, and the wiring pattern 4 and the electrodeposition film 5 are laminated inside the non-masked portion 3a.
  • FIG. 9 is a cross-sectional view of a substrate showing a plating process according to the prior art.
  • the wiring pattern 4 is formed so as to be thinner than the mask pattern 3, thereby forming a conductor plating having a rectangular cross section.
  • the conductor plating of the wiring pattern 4 is not formed in a completely rectangular shape, and a slight gap G is formed between the inner side surface of the non-masked portion 3a and the side surface of the wiring pattern 4.
  • FIG. 10 is a cross-sectional view of a substrate showing an electrodeposition process according to the prior art.
  • the thickness of the electrodeposition film 5 is only about 1 to 5 ⁇ m, as shown in FIG.
  • the electrodeposition film 5 gets into the gap G between the mask pattern 3 and the wiring pattern 4.
  • the electrodeposition film 5 contains a polymer having the same component as the mask pattern 3 among the resin materials, it exhibits a high bonding force with the adjacent mask pattern 3 at the time of curing, and is one of the mask patterns 3.
  • the part is altered to form the resin-to-resin bonding part 7.
  • FIG. 11 is a cross-sectional view of a substrate showing a mask peeling process according to the prior art.
  • the stripping solution is applied to the mask pattern 3 in the state shown in FIG. 10, most of the mask pattern 3 is peeled off, but the resin-to-resin bonding portion 7 which is not dissolved by the stripping solution remains as a film residue, and the wiring pattern 4 Deteriorates the quality of.
  • the wiring interval between the two wiring patterns 4 becomes narrower as the wiring circuit becomes finer pitch, the film residue between the two wiring patterns 4 is combined and increased.
  • the wiring pattern 4 is formed by conductor plating with the mask pattern 3 formed on the insulating substrate 1, and the electrodeposition film as an etching resist is formed on the exposed surface of the wiring pattern 4. Form 5. Therefore, it is possible to reduce the possibility that the wiring pattern 4 is etched even in the step of etching the conductive layer 2. As a result, the cross-sectional shape of the formed fine wiring pattern 4 can be appropriately managed, and the characteristics when applied to a high-frequency antenna pattern, for example, can be improved.
  • the conductor plating is performed so that the thickness of the wiring pattern 4 is equal to or larger than the thickness of the mask pattern 3 as shown in FIG.
  • the head portion 4b of the wiring pattern 4 serves as a lid for the opening of the non-masked portion 3a. Therefore, the electrodeposition film 5 formed on the exposed surface of the wiring pattern 4 is prevented from invading the non-masked portion 3a, and the contact area with the mask pattern 3 is minimized as shown in FIG. be able to.
  • the mask pattern 3 the deteriorated portion in contact with the electrodeposition film 5 is suppressed to a minimum, and the generation of residue at the time of peeling is also suppressed.
  • the wiring pattern manufacturing method according to the present invention it is possible to suppress the generation of mask residue while maintaining the wiring width of the wiring pattern as designed.
  • the wiring pattern manufacturing method includes a mask forming step of forming an insulating mask pattern on an insulating substrate provided with a conductive layer on the surface, and conductor plating on a non-masked portion of the conductive layer.
  • the etching step of etching the conductive layer and the electrodeposition film peeling step of peeling the electrodeposition film are included, and in the plating step, the thickness of the wiring pattern is set to be equal to or larger than the thickness of the mask pattern.
  • the wiring pattern is formed so as to have a shape including a main body having a predetermined first wiring width and a head having a second wiring width wider than the first wiring width and provided on the upper surface of the main body. ..
  • a wiring pattern is formed by conductor plating with a mask pattern formed on an insulating substrate, and an electrodeposition film as an etching resist is formed on the exposed surface of the wiring pattern.
  • the head of the wiring pattern is formed by setting the thickness of the wiring pattern to be equal to or larger than the thickness of the mask pattern, and the head becomes the lid of the non-masked portion in the mask pattern. Therefore, even if a gap is formed between the inner surface of the non-masked portion in the mask pattern and the side surface of the wiring pattern, the solution for forming the electrodeposition film does not penetrate into the gap in the electrodeposition step. , The contact area between the formed electrodeposition film and the mask pattern can be minimized.
  • the wiring pattern manufacturing method according to the first embodiment it is possible to suppress the generation of mask residue while maintaining the wiring width of the wiring pattern as designed.
  • the wiring pattern manufacturing method in the first embodiment described above, after the electrodeposition film peeling step, the wiring pattern is shaped so as to have the same thickness as the mask pattern before peeling. Includes shaping process.
  • the wiring pattern formed in the plating step is shaped to have the same thickness as the mask pattern, so that the wiring pattern has the same shape as the non-masked portion of the conductive layer. Therefore, the cross-sectional shape of the wiring pattern can be rectangular.
  • the mask pattern manufacturing method in the above-mentioned second embodiment, in the mask forming step, the mask pattern having the same thickness as the predetermined design thickness of the wiring pattern is formed.
  • the mask pattern was formed by the shaping step by forming the mask pattern having the same thickness as the predetermined design thickness required for the wiring pattern at the stage of the mask forming step.
  • the wiring pattern can be made as thick as designed.
  • a shaping step of etching the protruding portion of the wiring pattern protruding in the pattern width direction is performed.
  • the cross-sectional shape of the wiring pattern can be made rectangular by etching the protruding portion protruding in the pattern width direction with respect to the wiring pattern formed in the plating step. ..
  • the wiring pattern in the fourth embodiment described above, in the plating step, has a predetermined design thickness or more.
  • the wiring pattern formed by the shaping process is made as designed by setting the thickness of the wiring pattern to be equal to or more than the required predetermined design thickness at the stage of the plating process. Can be thick.
  • the wiring pattern with resist according to the sixth embodiment includes a main body having a predetermined first wiring width and a head having a second wiring width wider than the first wiring width and provided on the upper surface of the main body. It comprises a wiring pattern composed of conductor plating including, and integrally formed with the main body and the head, and an electrodeposition film made of a resin material provided on the upper surface and the side surface of the head.
  • the electrodeposition film is provided on the upper surface and the side surface of the head in the wiring pattern, even when etching is performed around the wiring pattern, for example. It is possible to reduce the possibility that the wiring pattern itself is reduced or reduced. Further, in the wiring pattern with resist, the contact area between the mask pattern used at the time of forming the wiring pattern and the electrodeposition film is minimized, so that even if the mask pattern is altered by the electrodeposition film in the vicinity. , It is possible to reduce the possibility that the altered portion remains on the electrodeposited film. Therefore, according to the wiring pattern with resist according to the sixth embodiment, it is possible to suppress the generation of mask residue while maintaining the wiring width of the wiring pattern as designed.
  • Insulated substrate 1 Insulated substrate 2 Conductive layer 3 Mask pattern 3a Non-masked part 4 Wiring pattern 4a Main body 4b Head 4c Protruding part 5 Electroplated film 6 Resistive wiring pattern 7 Resin-to-resin coupling part L1 First wiring width L1 L2 2nd wiring width L2 G gap

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

Provided is a method for manufacturing a wiring pattern, the method including: a mask forming step for forming an insulating mask pattern (3) on an insulating substrate (1) having a conductive layer (2) provided on a surface thereof; a plating step for forming a wiring pattern (4) with a conductor plating on a non-mask section (3a) of the conductive layer (2); an electro-deposition step for forming an electro-deposition film (5) composed of a resin material on an exposed surface of the wiring pattern (4); a mask peeling step for peeling off the mask pattern (3); an etching step for etching the conductive layer (2) using the electro-deposition film (5) as an etching resist; and an electro-deposition film peeling step for peeling off the electro-deposition film (5), wherein in the plating step, the thickness of the mask pattern (3) is made to be equal to or greater than the thickness of the wiring pattern (4), whereby the wiring pattern (4) is formed so as to assume a shape that includes a main body (4a) that has a predetermined first wiring width (L1) and a head section (4b) that has a second wiring width (L2) that is greater than the first wiring width (L1) and is provided on an upper surface of the main body (4a).

Description

配線パターン製造方法、及びレジスト付き配線パターンWiring pattern manufacturing method and wiring pattern with resist
　本発明は、配線パターン製造方法、及びレジスト付き配線パターンに関する。 The present invention relates to a wiring pattern manufacturing method and a wiring pattern with a resist.
　電気・電子機器の小型化及び高機能化に伴い、プリント配線板における配線パターンを細線化するための研究開発が進められている。配線パターンは、細線化される程その断面形状を設計通りに形成することが困難となるため、細線化と形状制御とを両立する技術が求められている。 With the miniaturization and higher functionality of electrical and electronic equipment, research and development are underway to make the wiring pattern of printed wiring boards thinner. As the wiring pattern becomes thinner, it becomes more difficult to form the cross-sectional shape as designed. Therefore, there is a demand for a technique that achieves both thinning and shape control.
　ここで、信頼性の高い微細配線を比較的作製し易い技術として、特許文献１に開示されているように、セミアディティブ法やＭＳＡＰ法(Modified Semi Additive Process)が知られている。例えばＭＳＡＰ法は、銅箔がラミネートされた基板の表面にドライフィルムを設け、当該ドライフィルムを露光及び現像することにより非マスク部を形成すると共に、当該非マスク部において露出する銅箔上に電解めっきを形成することで略矩形の断面形状を有する配線パターンを形成する。そして、ドライフィルムを剥離した後、銅箔の厚みに応じた分だけ基板表面全体をエッチングして回路に不要な部分の銅箔を除去することにより、細線化された配線パターンを作成することができる。 Here, as a technique for relatively easily producing highly reliable fine wiring, a semi-additive method and an MSAP method (Modified Semi Additive Process) are known as disclosed in Patent Document 1. For example, in the MSAP method, a dry film is provided on the surface of a substrate on which a copper foil is laminated, and the dry film is exposed and developed to form a non-masked portion, and electrolysis is performed on the copper foil exposed in the non-masked portion. By forming the plating, a wiring pattern having a substantially rectangular cross-sectional shape is formed. Then, after the dry film is peeled off, the entire surface of the substrate is etched according to the thickness of the copper foil to remove the copper foil in the portion unnecessary for the circuit, thereby creating a thinned wiring pattern. can.
　しかし、銅箔の不要部分を除去するエッチングの工程においては、銅箔部分だけでなく電解めっきで形成された配線パターン自体もエッチングされる。このため、配線パターンは、配線幅が所望の設計幅よりも減少してしまい、特に小さい設計幅に設定されている程その影響が大きく、場合によっては形成すべき位置から消失してしまう可能性が生じる。 However, in the etching process for removing unnecessary parts of the copper foil, not only the copper foil part but also the wiring pattern itself formed by electrolytic plating is etched. For this reason, the wiring pattern has a smaller wiring width than the desired design width, and the smaller the design width is set, the greater the influence is, and in some cases, the wiring pattern may disappear from the position to be formed. Occurs.
　ここで、配線パターンの上面だけに樹脂材料からなるエッチングレジストを形成することができれば、配線パターンの配線幅を減少させることなく比較的容易に銅箔だけをエッチングすることができる。このとき、例えば特許文献２に記載された方法のように、パターニングされたドライフィルムの非マスク部において配線パターン及び電着膜を順に積層することにより、ＭＳＡＰ法の手順にエッチングレジストの形成手順を組み入れることができると考えられる。 Here, if an etching resist made of a resin material can be formed only on the upper surface of the wiring pattern, only the copper foil can be etched relatively easily without reducing the wiring width of the wiring pattern. At this time, for example, as in the method described in Patent Document 2, by laminating the wiring pattern and the electrodeposited film in order in the non-masked portion of the patterned dry film, the procedure for forming the etching resist is added to the procedure of the MSAP method. It is thought that it can be incorporated.
特開２０２０－８８０６２号公報Japanese Unexamined Patent Publication No. 2020-88062 特開平１０－２７９５３号公報Japanese Unexamined Patent Publication No. 10-27953
　しかしながら、ドライフィルムの非マスク部に形成される配線パターンは、完全な矩形形状で形成される訳ではなく、めっき導体の側面とドライフィルムの内側面との間に僅かな隙間が生じる。そして、めっき導体上に形成される電着膜が液状の材料から形成されるため当該隙間に入り込んだ状態で硬化する。このとき、電着膜とドライフィルムとが共通の樹脂材料を含む類似の成分であることから、電着膜と接するドライフィルムが樹脂間結合により変質し、ドライフィルムを剥離するための剥離液では剥離できずに残渣が生じるため、配線パターンの品質を低下させる虞が生じる。 However, the wiring pattern formed on the non-masked portion of the dry film is not formed in a perfect rectangular shape, and a slight gap is generated between the side surface of the plated conductor and the inner surface surface of the dry film. Then, since the electrodeposition film formed on the plated conductor is formed from a liquid material, it is cured in a state of entering the gap. At this time, since the electrodeposition film and the dry film are similar components containing a common resin material, the dry film in contact with the electrodeposition film is denatured by the bond between the resins, and the stripping solution for peeling the dry film is used. Since the residue cannot be peeled off, the quality of the wiring pattern may be deteriorated.
　本発明はこのような課題に鑑みてなされたものであり、その目的とするところは、配線パターンの配線幅を設計通りに維持しつつマスク残渣の発生を抑制することができる配線パターン製造方法、及びレジスト付き配線パターンを提供することにある。 The present invention has been made in view of such a problem, and an object of the present invention is a wiring pattern manufacturing method capable of suppressing the generation of mask residue while maintaining the wiring width of the wiring pattern as designed. And to provide a wiring pattern with a resist.
　上記目的を達成するため、本発明の配線パターン製造方法は、表面に導電層が設けられた絶縁基板に絶縁性のマスクパターンを形成するマスク形成工程と、前記導電層の非マスク部に導体めっきで配線パターンを形成するめっき工程と、前記配線パターンの露出表面に樹脂材料からなる電着膜を形成する電着工程と、前記マスクパターンを剥離するマスク剥離工程と、前記電着膜をエッチングレジストとして前記導電層をエッチングするエッチング工程と、前記電着膜を剥離する電着膜剥離工程と、を含み、前記めっき工程においては、前記配線パターンの厚みを前記マスクパターンの厚み以上とすることにより、所定の第１配線幅を有する本体と、前記第１配線幅よりも広い第２配線幅を有し前記本体の上面に設けられる頭部と、を含む形状となるように前記配線パターンを形成する。 In order to achieve the above object, the wiring pattern manufacturing method of the present invention comprises a mask forming step of forming an insulating mask pattern on an insulating substrate provided with a conductive layer on the surface, and conductor plating on a non-masked portion of the conductive layer. A plating step of forming a wiring pattern, an electrodeposition step of forming an electrodeposition film made of a resin material on an exposed surface of the wiring pattern, a mask peeling step of peeling off the mask pattern, and an etching resist for the electrodeposition film. In the plating step, the thickness of the wiring pattern is set to be equal to or larger than the thickness of the mask pattern. The wiring pattern is formed so as to include a main body having a predetermined first wiring width and a head having a second wiring width wider than the first wiring width and provided on the upper surface of the main body. do.
　また、本発明のレジスト付き配線パターンは、所定の第１配線幅を有する本体と、前記本体の上面に設けられると共に前記第１配線幅よりも広い第２配線幅を有する頭部と、を含み、前記本体と前記頭部とが一体的に形成される導体めっきからなる配線パターンと、前記頭部の上面及び側面に設けられた樹脂材料からなるレジスト膜と、を備える。 Further, the wiring pattern with resist of the present invention includes a main body having a predetermined first wiring width and a head provided on the upper surface of the main body and having a second wiring width wider than the first wiring width. A wiring pattern made of conductor plating in which the main body and the head are integrally formed, and a resist film made of a resin material provided on the upper surface and side surfaces of the head are provided.
　本発明によれば、配線パターンの配線幅を設計通りに維持しつつマスク残渣の発生を抑制することができる配線パターン製造方法、及びレジスト付き配線パターンを提供することができる。 According to the present invention, it is possible to provide a wiring pattern manufacturing method capable of suppressing the generation of mask residue while maintaining the wiring width of the wiring pattern as designed, and a wiring pattern with a resist.
本発明に係るマスク形成工程を示す基板断面図である。It is a cross-sectional view of a substrate which shows the mask forming process which concerns on this invention. 本発明に係るめっき工程を示す基板断面図である。It is sectional drawing of the substrate which shows the plating process which concerns on this invention. 本発明に係る電着工程を示す基板断面図である。It is sectional drawing of the substrate which shows the electrodeposition process which concerns on this invention. 本発明に係るマスク剥離工程を示す基板断面図である。It is a cross-sectional view of a substrate which shows the mask peeling process which concerns on this invention. 本発明に係るエッチング工程を示す基板断面図である。It is sectional drawing of the substrate which shows the etching process which concerns on this invention. 本発明に係る電着膜剥離工程を示す基板断面図である。It is sectional drawing of the substrate which shows the electrodeposition film peeling process which concerns on this invention. 本発明に係る第１の整形工程を示す基板断面図である。It is a cross-sectional view of a substrate which shows the 1st shaping process which concerns on this invention. 本発明に係る第２の整形工程を示す基板断面図である。It is a cross-sectional view of a substrate which shows the 2nd shaping process which concerns on this invention. 従来技術に係るめっき工程を示す基板断面図である。It is a substrate sectional view which shows the plating process which concerns on the prior art. 従来技術に係る電着工程を示す基板断面図である。It is a substrate sectional view which shows the electrodeposition process which concerns on a prior art. 従来技術に係るマスク剥離工程を示す基板断面図である。It is a cross-sectional view of a substrate which shows the mask peeling process which concerns on the prior art.
　以下、図面を参照しつつ発明の実施形態について詳細に説明する。尚、本発明は、以下に説明する内容に限定されるものではなく、その要旨を変更しない範囲において任意に変更して実施することが可能である。また、実施の形態の説明に用いる図面は、いずれも構成部材を模式的に示すものであって、理解を深めるべく部分的な強調、拡大、縮小、又は省略などを行っており、構成部材の縮尺や形状等を正確に表すものとはなっていない場合がある。 Hereinafter, embodiments of the invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described below, and can be arbitrarily modified and implemented without changing the gist thereof. In addition, the drawings used for explaining the embodiments are all schematically showing the constituent members, and are partially emphasized, enlarged, reduced, or omitted in order to deepen the understanding of the constituent members. It may not accurately represent the scale or shape.
　本発明に係る配線パターン製造方法は、マスク形成工程、めっき工程、電着工程、マスク剥離工程、エッチング工程、及び電着膜剥離工程の手順からなる。以下において、配線パターン製造方法のそれぞれの手順について、図１乃至図６を参照しつつ詳細に説明する。 The wiring pattern manufacturing method according to the present invention comprises procedures of a mask forming step, a plating step, an electrodeposition step, a mask peeling step, an etching step, and an electrodeposition film peeling step. Hereinafter, each procedure of the wiring pattern manufacturing method will be described in detail with reference to FIGS. 1 to 6.
　まず、後述する配線パターン４を形成するための準備として、マスク形成工程が行われる。図１は、本発明に係るマスク形成工程を示す基板断面図である。マスク形成工程においては、表面に導電層２が設けられた絶縁基板１に絶縁性を有するマスクパターン３が形成される。絶縁基板１は、樹脂材料からなり、例えば剛性を有する支持基板であるが、フレキシブル基板であってもよく、又は多層基板であってもよい。導電層２は、５μｍ程度の厚みを有する導電性の金属薄膜であり、例えば絶縁基板１にラミネートして形成される銅箔、又は絶縁基板１の表面に形成される無電解銅めっきである。 First, a mask forming step is performed as a preparation for forming the wiring pattern 4 described later. FIG. 1 is a cross-sectional view of a substrate showing a mask forming process according to the present invention. In the mask forming step, the mask pattern 3 having an insulating property is formed on the insulating substrate 1 provided with the conductive layer 2 on the surface. The insulating substrate 1 is made of a resin material and is, for example, a rigid support substrate, but may be a flexible substrate or a multilayer substrate. The conductive layer 2 is a conductive metal thin film having a thickness of about 5 μm, and is, for example, a copper foil formed by laminating on the insulating substrate 1 or electroless copper plating formed on the surface of the insulating substrate 1.
　マスクパターン３は、アルカリ現像タイプのドライフィルムであり、配線形成位置に沿って露光され、炭酸ソーダ(Ｎａ２ＣＯ３)１％の現像液で現像されることにより非マスク部３ａが形成される。すなわち、導電層２は、マスクパターン３の非マスク部３ａにおいて表面が露出している。このとき、非マスク部３ａは、形成する配線パターン４の配線幅の設計値である第１配線幅Ｌ１に設定される。 The mask pattern 3 is an alkaline development type dry film, which is exposed along the wiring formation position and developed with a developer of 1% sodium carbonate (Na 2 CO 3 ) to form a non-mask portion 3a. .. That is, the surface of the conductive layer 2 is exposed in the non-masked portion 3a of the mask pattern 3. At this time, the non-masked portion 3a is set to the first wiring width L1 which is a design value of the wiring width of the wiring pattern 4 to be formed.
　マスク形成工程によりマスク付きの基板が形成されると、当該基板にめっき加工を施すことにより配線パターン４を形成するめっき工程が行われる。図２は、本発明に係るめっき工程を示す基板断面図である。めっき工程においては、硫酸銅めっき液中においてシード層としての導電層２が通電されることにより、非マスク部３ａに電解銅めっきとしての配線パターン４が形成される。 When a substrate with a mask is formed by the mask forming step, a plating step of forming a wiring pattern 4 is performed by plating the substrate. FIG. 2 is a cross-sectional view of a substrate showing a plating process according to the present invention. In the plating step, the conductive layer 2 as the seed layer is energized in the copper sulfate plating solution to form the wiring pattern 4 as the electrolytic copper plating on the non-masked portion 3a.
　ここで、配線パターン４の厚みは、通電電流及び通電時間に基づく累積電流に応じて制御され、本発明においてはマスクパターン３の厚み以上に設定される。これにより、電解銅めっきは、図２に示されるように、マスクパターン３の非マスク部３ａから溢れ、上記した所定の第１配線幅Ｌ１を有する本体４ａと、第１配線幅Ｌ１よりも広い第２配線幅Ｌ２を有し本体４ａの上面に設けられる頭部４ｂと、を有するような形状となる。尚、本体４ａ及び頭部４ｂは、一連の銅めっきにより一体的に形成されるため両者の境界は存在しない。 Here, the thickness of the wiring pattern 4 is controlled according to the energization current and the cumulative current based on the energization time, and is set to be equal to or larger than the thickness of the mask pattern 3 in the present invention. As a result, as shown in FIG. 2, the electrolytic copper plating overflows from the non-masked portion 3a of the mask pattern 3 and is wider than the main body 4a having the above-mentioned predetermined first wiring width L1 and the first wiring width L1. It has a shape such that it has a second wiring width L2 and has a head portion 4b provided on the upper surface of the main body 4a. Since the main body 4a and the head 4b are integrally formed by a series of copper plating, there is no boundary between them.
　めっき工程により配線パターン４が形成されると、配線パターン４の表面にエッチングレジストを形成する電着工程が行われる。図３は、本発明に係る電着工程を示す基板断面図である。電着工程においては、樹脂材料からなる電着材料を含む液中において配線パターン４に通電することにより、配線パターン４の露出表面、すなわち頭部４ｂの上面及び側面に１～５μｍ程度の厚みを有する電着膜５が形成される。このとき、配線パターン４は、マスクパターン３の非マスク部３ａを充填しており、更には上記した頭部４ｂによりマスクパターン３の非マスク部３ａに蓋をするような形状に形成されている。そのため、マスクパターン３における非マスク部３ａの内側面と配線パターン４の本体４ａの側面との間に隙間Ｇが生じる虞が抑制され、たとえ僅かに隙間Ｇが生じたとしても電着材料を含む溶液が当該隙間Ｇに浸入することを防止することができる。ここで、電着膜５は、後の工程でマスクパターン３を剥離するためのドライフィルム剥離溶液では溶解しない樹脂設計であり、後述するエッチング処理のレジストとして機能する。 When the wiring pattern 4 is formed by the plating process, an electrodeposition step of forming an etching resist on the surface of the wiring pattern 4 is performed. FIG. 3 is a cross-sectional view of a substrate showing an electrodeposition process according to the present invention. In the electrodeposition step, by energizing the wiring pattern 4 in a liquid containing an electrodeposition material made of a resin material, a thickness of about 1 to 5 μm is applied to the exposed surface of the wiring pattern 4, that is, the upper surface and the side surface of the head 4b. The electrodeposited film 5 to have is formed. At this time, the wiring pattern 4 is filled with the non-masked portion 3a of the mask pattern 3, and is further formed in a shape such that the non-masked portion 3a of the mask pattern 3 is covered with the head 4b described above. .. Therefore, the possibility that a gap G is generated between the inner surface of the non-mask portion 3a in the mask pattern 3 and the side surface of the main body 4a of the wiring pattern 4 is suppressed, and even if a slight gap G is generated, the electrodeposition material is included. It is possible to prevent the solution from infiltrating the gap G. Here, the electrodeposition film 5 is a resin design that does not dissolve in the dry film peeling solution for peeling the mask pattern 3 in a later step, and functions as a resist for etching treatment described later.
　電着工程により電着膜５が形成されると、基板からマスクパターン３を剥離するマスク剥離工程が行われる。図４は、本発明に係るマスク剥離工程を示す基板断面図である。マスク剥離工程においては、配線パターン４の形成に使用したマスクパターン３が苛性ソーダ(ＮａＯＨ)３％の剥離液で除去される。これにより、基板は、配線パターン４が形成されない部分において導電層２の表面が露出することになる。このとき、導電層２の表面において、配線パターン４及びエッチングレジストとしての電着膜５からなるレジスト付き配線パターン６が形成される。 When the electrodeposition film 5 is formed by the electrodeposition step, a mask peeling step of peeling the mask pattern 3 from the substrate is performed. FIG. 4 is a cross-sectional view of a substrate showing a mask peeling step according to the present invention. In the mask peeling step, the mask pattern 3 used for forming the wiring pattern 4 is removed with a stripping solution containing 3% caustic soda (NaOH). As a result, the surface of the conductive layer 2 of the substrate is exposed at the portion where the wiring pattern 4 is not formed. At this time, a resisted wiring pattern 6 composed of a wiring pattern 4 and an electrodeposition film 5 as an etching resist is formed on the surface of the conductive layer 2.
　ここで、マスクパターン３の剥離液は、アルカリ現像タイプのドライフィルムを溶解する成分からなるため、電着膜５に対しては溶解作用がなく、共に樹脂材料からなるマスクパターン３及び電着膜５のうち、マスクパターン３のみを選択的に除去することができる。また、マスクパターン３及び電着膜５は、詳細を後述するように樹脂間結合しやすい材料からなるものの、本発明においては両者の接触面積が最小限に抑えられている。このため、本発明に係るマスク剥離工程では、残渣を生じさせることなく高精度にマスクパターン３を剥離することができる。 Here, since the stripping solution of the mask pattern 3 is composed of a component that dissolves the alkaline development type dry film, it has no dissolving action on the electrodeposition film 5, and both the mask pattern 3 and the electrodeposition film made of a resin material have no dissolving action. Of 5, only the mask pattern 3 can be selectively removed. Further, although the mask pattern 3 and the electrodeposition film 5 are made of a material that easily bonds between resins as described in detail later, in the present invention, the contact area between the two is minimized. Therefore, in the mask peeling step according to the present invention, the mask pattern 3 can be peeled with high accuracy without causing a residue.
　マスク剥離工程によりマスクパターン３が剥離されると、導電層２をエッチングするエッチング工程が行われる。図５は、本発明に係るエッチング工程を示す基板断面図である。エッチング工程においては、電着膜５をエッチングレジストとして、例えば塩化第二銅水溶液等の標準的な溶解液により導電層２がエッチングされる。これにより、レジスト付き配線パターン６が存在しない領域の導電層２が除去され、複数の配線パターン４が互いに絶縁された回路パターンが形成される。このとき、配線パターン４は、導電層２と同じく銅で形成されているものの、電着膜５がエッチングレジストとなるため表面のエッチングが防止され、所望の設計値としての第１配線幅Ｌ１を維持することができる。 When the mask pattern 3 is peeled off by the mask peeling step, an etching step of etching the conductive layer 2 is performed. FIG. 5 is a cross-sectional view of a substrate showing an etching process according to the present invention. In the etching step, the conductive layer 2 is etched with a standard solution such as an aqueous solution of cupric chloride using the electrodeposition film 5 as an etching resist. As a result, the conductive layer 2 in the region where the resisted wiring pattern 6 does not exist is removed, and a circuit pattern in which the plurality of wiring patterns 4 are insulated from each other is formed. At this time, although the wiring pattern 4 is made of copper like the conductive layer 2, since the electrodeposition film 5 serves as an etching resist, surface etching is prevented, and the first wiring width L1 as a desired design value is obtained. Can be maintained.
　尚、電着膜５が仮に半田や錫等の金属材料で形成される場合には、導電層２をエッチングするための上記の塩化第二銅水溶液は、エッチング工程において電着膜５も溶解してしまう。このため、電着膜５が金属材料からなる場合には、導電層２をエッチングでき且つ電着膜５を溶解しない過硫酸アンモニウム等の過酸化物系エッチング液が使用されることになる。しかしながら、過酸化物系エッチング液を使用する方法は、半田に含まれる鉛の廃液処理等のように環境負荷を低減するための複雑な工程を要する。そこで、本発明における電着膜５は、上記したように樹脂材料で形成されることにより、エッチング工程において環境負荷の低い塩化第二銅水溶液が使用されても溶解せずにエッチングレジストとして維持される。 If the electrodeposition film 5 is formed of a metal material such as solder or tin, the above-mentioned cupric chloride aqueous solution for etching the conductive layer 2 also dissolves the electrodeposition film 5 in the etching step. It ends up. Therefore, when the electrodeposition film 5 is made of a metal material, a peroxide-based etching solution such as ammonium persulfate that can etch the conductive layer 2 and does not dissolve the electrodeposition film 5 is used. However, the method using a peroxide-based etching solution requires a complicated process for reducing the environmental load such as waste liquid treatment of lead contained in solder. Therefore, the electrodeposition film 5 in the present invention is formed of the resin material as described above, so that even if an aqueous solution of cupric chloride having a low environmental load is used in the etching process, the electrodeposition film 5 is maintained as an etching resist without being dissolved. To.
　導電層２がエッチングされると、配線パターン４から電着膜５を剥離する電着膜剥離工程が行われる。図６は、本発明に係る電着膜剥離工程を示す基板断面図である。電着膜剥離工程においては、電着膜５は、例えば公知の有機アミン系剥離液により配線パターン４の表面から剥離することができる。これにより、絶縁基板１の上面に導電材料としての銅のみからなる微細な回路パターンが形成されることになる。 When the conductive layer 2 is etched, an electrodeposition film peeling step of peeling the electrodeposition film 5 from the wiring pattern 4 is performed. FIG. 6 is a cross-sectional view of a substrate showing the electrodeposition film peeling step according to the present invention. In the electrodeposition film peeling step, the electrodeposition film 5 can be peeled from the surface of the wiring pattern 4 by, for example, a known organic amine-based stripping liquid. As a result, a fine circuit pattern made of only copper as a conductive material is formed on the upper surface of the insulating substrate 1.
　ところで、当該回路パターンは、プリント配線板の微細回路においてそのまま使用することも可能であるが、次に示す整形工程を更に行うことで矩形形状の断面に整形して使用することもできる。ここでは２通りの整形工程について説明する。 By the way, the circuit pattern can be used as it is in the fine circuit of the printed wiring board, but it can also be shaped into a rectangular cross section and used by further performing the following shaping step. Here, two types of shaping processes will be described.
　図７は、本発明に係る第１の整形工程を示す基板断面図である。第１の整形工程においては、上記した電着膜剥離工程の後に、剥離前のマスクパターン３と同じ厚みになるよう配線パターン４を整形する。すなわち、第１の整形工程では、上記しためっき工程で形成した配線パターン４のうち、頭部４ｂに相当する部分を研磨することで、矩形断面を有する本体４ａの部分を残すことができる。ここで、図６の状態における配線パターン４がプリント配線板の外層パターンとして使用される場合、例えば配線パターン４をソルダーレジストで被膜する前処理として配線上面が数μｍだけ研磨されることになるため、当該研磨を第１の整形工程とすることができる。 FIG. 7 is a cross-sectional view of a substrate showing a first shaping step according to the present invention. In the first shaping step, after the electrodeposition film peeling step described above, the wiring pattern 4 is shaped so as to have the same thickness as the mask pattern 3 before peeling. That is, in the first shaping step, the portion of the wiring pattern 4 formed in the plating step described above, which corresponds to the head portion 4b, can be polished to leave the portion of the main body 4a having a rectangular cross section. Here, when the wiring pattern 4 in the state of FIG. 6 is used as the outer layer pattern of the printed wiring board, for example, the upper surface of the wiring is polished by several μm as a pretreatment for coating the wiring pattern 4 with a solder resist. , The polishing can be the first shaping step.
　また、この場合、配線パターン４に求められる所定の設計厚みが本体４ａの厚みに相当するため、上記したマスク形成工程の段階において、マスクパターン３を当該所定の設計厚みと同じになるように形成することで、配線パターン４の厚みを設計通りにすることができる。 Further, in this case, since the predetermined design thickness required for the wiring pattern 4 corresponds to the thickness of the main body 4a, the mask pattern 3 is formed so as to be the same as the predetermined design thickness at the stage of the mask forming step described above. By doing so, the thickness of the wiring pattern 4 can be made as designed.
　図８は、本発明に係る第２の整形工程を示す基板断面図である。第２の整形工程においては、上記した電着膜剥離工程の後に、パターン幅方向に突出した配線パターン４の突出部４ｃをエッチングしている。すなわち、第２の整形工程では、上記しためっき工程で形成した配線パターン４の表面を僅かにエッチングすることにより、尖った形状を有する突出部４ｃが優先的にエッチングされる。ここで、図６の状態における配線パターン４が多層配線板の内層パターンとして使用される場合、配線パターン４を例えば絶縁樹脂層で埋設する前処理として配線上面が数μｍだけエッチングされるため、当該エッチングを第２の整形工程とすることができる。 FIG. 8 is a cross-sectional view of a substrate showing a second shaping step according to the present invention. In the second shaping step, after the electrodeposition film peeling step described above, the protruding portion 4c of the wiring pattern 4 protruding in the pattern width direction is etched. That is, in the second shaping step, the protruding portion 4c having a sharp shape is preferentially etched by slightly etching the surface of the wiring pattern 4 formed in the plating step described above. Here, when the wiring pattern 4 in the state of FIG. 6 is used as the inner layer pattern of the multilayer wiring board, the upper surface of the wiring is etched by several μm as a pretreatment for burying the wiring pattern 4 with, for example, an insulating resin layer. Etching can be the second shaping step.
　また、この場合、上記しためっき工程の段階において、配線パターン４のうち突出部４ｃを除去できる程度のエッチング量だけ配線パターン４を所定の設計厚み以上とする。これにより、第２の整形工程で整形される配線パターン４の厚みを、設計通りの厚みに制御することができる。 Further, in this case, at the stage of the plating process described above, the wiring pattern 4 is set to have a predetermined design thickness or more by an etching amount sufficient to remove the protruding portion 4c of the wiring pattern 4. Thereby, the thickness of the wiring pattern 4 shaped in the second shaping step can be controlled to the thickness as designed.
　次に、本発明に係る配線パターン製造方法の作用効果について、従来技術を用いた製造方法と比較して説明する。ここで例示する従来技術は、表面に導電層２が設けられた絶縁基板１にマスクパターン３を形成し、非マスク部３ａの内部において配線パターン４及び電着膜５を積層するものとしている。 Next, the operation and effect of the wiring pattern manufacturing method according to the present invention will be described in comparison with the manufacturing method using the prior art. In the prior art illustrated here, the mask pattern 3 is formed on the insulating substrate 1 provided with the conductive layer 2 on the surface, and the wiring pattern 4 and the electrodeposition film 5 are laminated inside the non-masked portion 3a.
　図９は、従来技術に係るめっき工程を示す基板断面図である。図９においては、マスクパターン３よりも配線パターン４の厚みが薄くなるように形成することで、断面が矩形形状の導体めっきを形成しようとするものである。しかしながら、配線パターン４の導体めっきは、完全な矩形形状のまま形成されていく訳ではなく、非マスク部３ａの内側面と配線パターン４の側面との間に僅かな隙間Ｇができてしまう。 FIG. 9 is a cross-sectional view of a substrate showing a plating process according to the prior art. In FIG. 9, the wiring pattern 4 is formed so as to be thinner than the mask pattern 3, thereby forming a conductor plating having a rectangular cross section. However, the conductor plating of the wiring pattern 4 is not formed in a completely rectangular shape, and a slight gap G is formed between the inner side surface of the non-masked portion 3a and the side surface of the wiring pattern 4.
　図１０は、従来技術に係る電着工程を示す基板断面図である。上記のめっき工程の後に、図９に示す状態の配線パターン４の上面に電着膜５を形成すると、電着膜５の厚みが約１～５μｍ程度しかないことにより、図１０に示されるようにマスクパターン３と配線パターン４との隙間Ｇに電着膜５が入り込んでしまう。ここで、電着膜５は、樹脂材料の中でもマスクパターン３と同様の成分の高分子を含むため、硬化時において隣接するマスクパターン３との間で高い結合力を示し、マスクパターン３の一部を変質させて樹脂間結合部７を生成する。 FIG. 10 is a cross-sectional view of a substrate showing an electrodeposition process according to the prior art. When the electrodeposition film 5 is formed on the upper surface of the wiring pattern 4 in the state shown in FIG. 9 after the above plating step, the thickness of the electrodeposition film 5 is only about 1 to 5 μm, as shown in FIG. The electrodeposition film 5 gets into the gap G between the mask pattern 3 and the wiring pattern 4. Here, since the electrodeposition film 5 contains a polymer having the same component as the mask pattern 3 among the resin materials, it exhibits a high bonding force with the adjacent mask pattern 3 at the time of curing, and is one of the mask patterns 3. The part is altered to form the resin-to-resin bonding part 7.
　図１１は、従来技術に係るマスク剥離工程を示す基板断面図である。図１０に示された状態のマスクパターン３に剥離液を適用すると、大部分のマスクパターン３は剥離されるものの、剥離液では溶解しない樹脂間結合部７がフィルム残渣として残ってしまい配線パターン４の品質を低下させてしまう。特に、配線回路のファインピッチ化に伴い２つの配線パターン４の配線間隔が狭くなると、両者の間のフィルム残渣が結合・増大することになる。 FIG. 11 is a cross-sectional view of a substrate showing a mask peeling process according to the prior art. When the stripping solution is applied to the mask pattern 3 in the state shown in FIG. 10, most of the mask pattern 3 is peeled off, but the resin-to-resin bonding portion 7 which is not dissolved by the stripping solution remains as a film residue, and the wiring pattern 4 Deteriorates the quality of. In particular, when the wiring interval between the two wiring patterns 4 becomes narrower as the wiring circuit becomes finer pitch, the film residue between the two wiring patterns 4 is combined and increased.
　これに対し、本発明に係る配線パターン製造方法は、絶縁基板１に形成されたマスクパターン３により導体めっきで配線パターン４を形成すると共に、配線パターン４の露出表面にエッチングレジストとしての電着膜５を形成する。このため、導電層２をエッチングする工程においても配線パターン４がエッチングされる虞を低減することができる。これにより、形成された微細な配線パターン４の断面形状を適切に管理することができ、例えば高周波アンテナパターンに適用する場合の特性を向上させることができる。 On the other hand, in the wiring pattern manufacturing method according to the present invention, the wiring pattern 4 is formed by conductor plating with the mask pattern 3 formed on the insulating substrate 1, and the electrodeposition film as an etching resist is formed on the exposed surface of the wiring pattern 4. Form 5. Therefore, it is possible to reduce the possibility that the wiring pattern 4 is etched even in the step of etching the conductive layer 2. As a result, the cross-sectional shape of the formed fine wiring pattern 4 can be appropriately managed, and the characteristics when applied to a high-frequency antenna pattern, for example, can be improved.
　その上で、本発明に係る配線パターン製造方法は、配線パターン４を形成するめっき工程において、図２に示されるように配線パターン４の厚みがマスクパターン３の厚み以上となるように導体めっきの生成量が制御されることにより、配線パターン４の頭部４ｂが非マスク部３ａの開口に対する蓋となる。このため、配線パターン４の露出表面に形成される電着膜５は、非マスク部３ａに浸入することが回避され、図３に示されるようにマスクパターン３との接触面積を最小限に抑えることができる。これにより、マスクパターン３は、電着膜５と接する変質部分が最小限に抑えられ、剥離時における残渣の発生も抑えられることになる。 Then, in the wiring pattern manufacturing method according to the present invention, in the plating step of forming the wiring pattern 4, the conductor plating is performed so that the thickness of the wiring pattern 4 is equal to or larger than the thickness of the mask pattern 3 as shown in FIG. By controlling the amount of production, the head portion 4b of the wiring pattern 4 serves as a lid for the opening of the non-masked portion 3a. Therefore, the electrodeposition film 5 formed on the exposed surface of the wiring pattern 4 is prevented from invading the non-masked portion 3a, and the contact area with the mask pattern 3 is minimized as shown in FIG. be able to. As a result, in the mask pattern 3, the deteriorated portion in contact with the electrodeposition film 5 is suppressed to a minimum, and the generation of residue at the time of peeling is also suppressed.
　従って、本発明に係る配線パターン製造方法によれば、配線パターンの配線幅を設計通りに維持しつつマスク残渣の発生を抑制することができる。 Therefore, according to the wiring pattern manufacturing method according to the present invention, it is possible to suppress the generation of mask residue while maintaining the wiring width of the wiring pattern as designed.
＜本発明の実施態様＞
　本発明の第１実施態様に係る配線パターン製造方法は、表面に導電層が設けられた絶縁基板に絶縁性のマスクパターンを形成するマスク形成工程と、前記導電層の非マスク部に導体めっきで配線パターンを形成するめっき工程と、前記配線パターンの露出表面に樹脂材料からなる電着膜を形成する電着工程と、前記マスクパターンを剥離するマスク剥離工程と、前記電着膜をエッチングレジストとして前記導電層をエッチングするエッチング工程と、前記電着膜を剥離する電着膜剥離工程と、を含み、前記めっき工程においては、前記配線パターンの厚みを前記マスクパターンの厚み以上とすることにより、所定の第１配線幅を有する本体と、前記第１配線幅よりも広い第２配線幅を有し前記本体の上面に設けられる頭部と、を含む形状となるように前記配線パターンを形成する。 <Embodiment of the present invention>
The wiring pattern manufacturing method according to the first embodiment of the present invention includes a mask forming step of forming an insulating mask pattern on an insulating substrate provided with a conductive layer on the surface, and conductor plating on a non-masked portion of the conductive layer. A plating step for forming a wiring pattern, an electrodeposition step for forming an electrodeposition film made of a resin material on an exposed surface of the wiring pattern, a mask peeling step for peeling off the mask pattern, and the electrodeposition film as an etching resist. The etching step of etching the conductive layer and the electrodeposition film peeling step of peeling the electrodeposition film are included, and in the plating step, the thickness of the wiring pattern is set to be equal to or larger than the thickness of the mask pattern. The wiring pattern is formed so as to have a shape including a main body having a predetermined first wiring width and a head having a second wiring width wider than the first wiring width and provided on the upper surface of the main body. ..
　配線パターン製造方法は、絶縁基板に形成されたマスクパターンにより導体めっきで配線パターンを形成すると共に、当該配線パターンの露出表面にエッチングレジストとしての電着膜を形成する。ここで、めっき工程においては、配線パターンの厚みがマスクパターンの厚み以上とされることで配線パターンの頭部が形成され、当該頭部がマスクパターンにおける非マスク部の蓋となる。このため、たとえマスクパターンにおける非マスク部の内側面と配線パターンの側面との間に隙間が形成されたとしても、電着工程において電着膜を形成するための溶液が当該隙間に浸入せず、形成される電着膜とマスクパターンとの接触面積を最小限に抑えることができる。これにより、マスクパターンは、電着膜と接する変質部分が最小限に抑えられ、剥離時における残渣の発生も抑えられることになる。従って、第１実施態様に係る配線パターン製造方法によれは、配線パターンの配線幅を設計通りに維持しつつマスク残渣の発生を抑制することができる。 In the wiring pattern manufacturing method, a wiring pattern is formed by conductor plating with a mask pattern formed on an insulating substrate, and an electrodeposition film as an etching resist is formed on the exposed surface of the wiring pattern. Here, in the plating step, the head of the wiring pattern is formed by setting the thickness of the wiring pattern to be equal to or larger than the thickness of the mask pattern, and the head becomes the lid of the non-masked portion in the mask pattern. Therefore, even if a gap is formed between the inner surface of the non-masked portion in the mask pattern and the side surface of the wiring pattern, the solution for forming the electrodeposition film does not penetrate into the gap in the electrodeposition step. , The contact area between the formed electrodeposition film and the mask pattern can be minimized. As a result, in the mask pattern, the altered portion in contact with the electrodeposition film is minimized, and the generation of residue at the time of peeling is also suppressed. Therefore, according to the wiring pattern manufacturing method according to the first embodiment, it is possible to suppress the generation of mask residue while maintaining the wiring width of the wiring pattern as designed.
　本発明の第２実施態様に係る配線パターン製造方法は、上記した第１実施態様において、前記電着膜剥離工程の後に、剥離前の前記マスクパターンと同じ厚みになるよう前記配線パターンを整形する整形工程を含む。 In the wiring pattern manufacturing method according to the second embodiment of the present invention, in the first embodiment described above, after the electrodeposition film peeling step, the wiring pattern is shaped so as to have the same thickness as the mask pattern before peeling. Includes shaping process.
　第２実施態様に係る配線パターン製造方法によれば、めっき工程で形成した配線パターンをマスクパターンと同じ厚みになるよう整形することにより、配線パターンが導電層の非マスク部と同一の形状になるため、配線パターンの断面形状を矩形とすることができる。 According to the wiring pattern manufacturing method according to the second embodiment, the wiring pattern formed in the plating step is shaped to have the same thickness as the mask pattern, so that the wiring pattern has the same shape as the non-masked portion of the conductive layer. Therefore, the cross-sectional shape of the wiring pattern can be rectangular.
　本発明の第３実施態様に係る配線パターン製造方法は、上記した第２実施態様において、前記マスク形成工程においては、前記配線パターンの所定の設計厚みと同じ厚みの前記マスクパターンが形成される。 In the wiring pattern manufacturing method according to the third embodiment of the present invention, in the above-mentioned second embodiment, in the mask forming step, the mask pattern having the same thickness as the predetermined design thickness of the wiring pattern is formed.
　第３実施態様に係る配線パターン製造方法によれば、マスク形成工程の段階において、配線パターンに求められる所定の設計厚みと同じ厚みのマスクパターンを形成しておくことにより、整形工程により成形された配線パターンを設計通りの厚みにすることができる。 According to the wiring pattern manufacturing method according to the third embodiment, the mask pattern was formed by the shaping step by forming the mask pattern having the same thickness as the predetermined design thickness required for the wiring pattern at the stage of the mask forming step. The wiring pattern can be made as thick as designed.
　本発明の第４実施態様に係る配線パターン製造方法は、上記した第１実施態様において、前記電着膜剥離工程の後に、パターン幅方向に突出した前記配線パターンの突出部をエッチングする整形工程を含む。 In the wiring pattern manufacturing method according to the fourth embodiment of the present invention, in the first embodiment described above, after the electrodeposition film peeling step, a shaping step of etching the protruding portion of the wiring pattern protruding in the pattern width direction is performed. include.
　第４実施態様に係る配線パターン製造方法によれば、めっき工程で形成した配線パターンに対し、パターン幅方向に突出した突出部をエッチングすることにより、配線パターンの断面形状を矩形とすることができる。 According to the wiring pattern manufacturing method according to the fourth embodiment, the cross-sectional shape of the wiring pattern can be made rectangular by etching the protruding portion protruding in the pattern width direction with respect to the wiring pattern formed in the plating step. ..
　本発明の第５実施態様に係る配線パターン製造方法は、上記した第４実施態様において、前記めっき工程においては、前記配線パターンを所定の設計厚み以上とする。 In the wiring pattern manufacturing method according to the fifth embodiment of the present invention, in the fourth embodiment described above, in the plating step, the wiring pattern has a predetermined design thickness or more.
　第５実施態様に係る配線パターン製造方法によれば、めっき工程の段階において、配線パターンの厚みを要求される所定の設計厚み以上としておくことにより、整形工程により成形された配線パターンを設計通りの厚みにすることができる。 According to the wiring pattern manufacturing method according to the fifth embodiment, the wiring pattern formed by the shaping process is made as designed by setting the thickness of the wiring pattern to be equal to or more than the required predetermined design thickness at the stage of the plating process. Can be thick.
　第６実施態様に係るレジスト付き配線パターンは、所定の第１配線幅を有する本体と、前記第１配線幅よりも広い第２配線幅を有し前記本体の上面に設けられる頭部と、を含む導体めっきからなり、前記本体と前記頭部とが一体的に形成される配線パターンと、前記頭部の上面及び側面に設けられた樹脂材料からなる電着膜と、を備える。 The wiring pattern with resist according to the sixth embodiment includes a main body having a predetermined first wiring width and a head having a second wiring width wider than the first wiring width and provided on the upper surface of the main body. It comprises a wiring pattern composed of conductor plating including, and integrally formed with the main body and the head, and an electrodeposition film made of a resin material provided on the upper surface and the side surface of the head.
　第６実施態様に係るレジスト付き配線パターンによれば、配線パターンにおける頭部の上面及び側面に電着膜が設けられているため、例えば配線パターンの周囲でエッチングが行われる場合であっても、配線パターン自体が減縮される虞を低減することができる。また、レジスト付き配線パターンは、配線パターンの形成時に使用されるマスクパターンと電着膜との接触面積が最小限に抑えられるため、マスクパターンが近接する電着膜により変質する場合であっても、電着膜に変質部分が残存する虞を低減することができる。従って、第６実施態様に係るレジスト付き配線パターンによれば、配線パターンの配線幅を設計通りに維持しつつマスク残渣の発生を抑制することができる。 According to the wiring pattern with resist according to the sixth embodiment, since the electrodeposition film is provided on the upper surface and the side surface of the head in the wiring pattern, even when etching is performed around the wiring pattern, for example. It is possible to reduce the possibility that the wiring pattern itself is reduced or reduced. Further, in the wiring pattern with resist, the contact area between the mask pattern used at the time of forming the wiring pattern and the electrodeposition film is minimized, so that even if the mask pattern is altered by the electrodeposition film in the vicinity. , It is possible to reduce the possibility that the altered portion remains on the electrodeposited film. Therefore, according to the wiring pattern with resist according to the sixth embodiment, it is possible to suppress the generation of mask residue while maintaining the wiring width of the wiring pattern as designed.
　１　絶縁基板
　２　導電層
　３　マスクパターン
　３ａ　非マスク部
　４　配線パターン
　４ａ　本体
　４ｂ　頭部
　４ｃ　突出部
　５　電着膜
　６　レジスト付き配線パターン
　７　樹脂間結合部
　Ｌ１　第１配線幅Ｌ１
　Ｌ２　第２配線幅Ｌ２
　Ｇ　隙間 1 Insulated substrate 2 Conductive layer 3 Mask pattern 3a Non-masked part 4 Wiring pattern 4a Main body 4b Head 4c Protruding part 5 Electroplated film 6 Resistive wiring pattern 7 Resin-to-resin coupling part L1 First wiring width L1
L2 2nd wiring width L2
G gap

Claims (6)

  1. 　表面に導電層が設けられた絶縁基板に絶縁性のマスクパターンを形成するマスク形成工程と、
    　前記導電層の非マスク部に導体めっきで配線パターンを形成するめっき工程と、
    　前記配線パターンの露出表面に樹脂材料からなる電着膜を形成する電着工程と、
    　前記マスクパターンを剥離するマスク剥離工程と、
    　前記電着膜をエッチングレジストとして前記導電層をエッチングするエッチング工程と、
    　前記電着膜を剥離する電着膜剥離工程と、を含み、
    　前記めっき工程においては、前記配線パターンの厚みを前記マスクパターンの厚み以上とすることにより、所定の第１配線幅を有する本体と、前記第１配線幅よりも広い第２配線幅を有し前記本体の上面に設けられる頭部と、を含む形状となるように前記配線パターンを形成する、配線パターン製造方法。     A mask forming step of forming an insulating mask pattern on an insulating substrate provided with a conductive layer on the surface,
    A plating step of forming a wiring pattern by conductor plating on the non-masked portion of the conductive layer,
    An electrodeposition step of forming an electrodeposition film made of a resin material on the exposed surface of the wiring pattern, and
    The mask peeling step of peeling the mask pattern and
    An etching step of etching the conductive layer using the electrodeposition film as an etching resist,
    Including the electrodeposition film peeling step of peeling the electrodeposition film.
    In the plating step, by setting the thickness of the wiring pattern to be equal to or greater than the thickness of the mask pattern, the main body having a predetermined first wiring width and the second wiring width wider than the first wiring width are obtained. A wiring pattern manufacturing method for forming the wiring pattern so as to have a shape including a head provided on the upper surface of the main body.
  2. 　前記電着膜剥離工程の後に、剥離前の前記マスクパターンと同じ厚みになるよう前記配線パターンを整形する整形工程を含む、請求項１に記載の配線パターン製造方法。 The wiring pattern manufacturing method according to claim 1, further comprising a shaping step of shaping the wiring pattern so as to have the same thickness as the mask pattern before peeling after the electrodeposition film peeling step.
  3. 　前記マスク形成工程においては、前記配線パターンの所定の設計厚みと同じ厚みの前記マスクパターンが形成される、請求項２に記載の配線パターン製造方法。 The wiring pattern manufacturing method according to claim 2, wherein in the mask forming step, the mask pattern having the same thickness as the predetermined design thickness of the wiring pattern is formed.
  4. 　前記電着膜剥離工程の後に、パターン幅方向に突出した前記配線パターンの突出部をエッチングする整形工程を含む、請求項１に記載の配線パターン製造方法。 The wiring pattern manufacturing method according to claim 1, further comprising a shaping step of etching the protruding portion of the wiring pattern protruding in the pattern width direction after the electrodeposition film peeling step.
  5. 　前記めっき工程においては、前記配線パターンを所定の設計厚み以上とする、請求項４に記載の配線パターン製造方法。 The wiring pattern manufacturing method according to claim 4, wherein in the plating step, the wiring pattern has a predetermined design thickness or more.
  6. 　所定の第１配線幅を有する本体と、前記第１配線幅よりも広い第２配線幅を有し前記本体の上面に設けられる頭部と、を含む導体めっきからなり、前記本体と前記頭部とが一体的に形成される配線パターンと、
    　前記頭部の上面及び側面に設けられた樹脂材料からなる電着膜と、を備えるレジスト付き配線パターン。     It is composed of conductor plating including a main body having a predetermined first wiring width and a head having a second wiring width wider than the first wiring width and provided on the upper surface of the main body, and the main body and the head. And the wiring pattern that is integrally formed with
    A wiring pattern with a resist comprising an electrodeposition film made of a resin material provided on the upper surface and the side surface of the head.
PCT/JP2020/048915 2020-12-25 2020-12-25 Method for manufacturing wiring pattern, and wiring pattern with resist WO2022137553A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044605A (en) * 1999-07-29 2001-02-16 Ngk Spark Plug Co Ltd Manufacture of wiring board with thin film
JP2003338676A (en) * 2002-05-20 2003-11-28 Mec Kk Method of manufacturing copper wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044605A (en) * 1999-07-29 2001-02-16 Ngk Spark Plug Co Ltd Manufacture of wiring board with thin film
JP2003338676A (en) * 2002-05-20 2003-11-28 Mec Kk Method of manufacturing copper wiring board

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