WO2022134440A1 - 采样器、显示驱动芯片和显示装置 - Google Patents

采样器、显示驱动芯片和显示装置 Download PDF

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Publication number
WO2022134440A1
WO2022134440A1 PCT/CN2021/094645 CN2021094645W WO2022134440A1 WO 2022134440 A1 WO2022134440 A1 WO 2022134440A1 CN 2021094645 W CN2021094645 W CN 2021094645W WO 2022134440 A1 WO2022134440 A1 WO 2022134440A1
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Prior art keywords
sampling
sampling control
nth
clock signal
flip
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PCT/CN2021/094645
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English (en)
French (fr)
Inventor
白东勋
李东明
南帐镇
花正贝
范昊
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北京奕斯伟计算技术有限公司
合肥奕斯伟集成电路有限公司
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Publication of WO2022134440A1 publication Critical patent/WO2022134440A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of signal sampling, and in particular, to a sampler, a display driving chip and a display device.
  • the clock signal generating circuit extracts the clock from the high-speed serial data, and generates a reference clock signal to operate the display driving logic.
  • the process of converting serial data to parallel data one high-speed serial data will be converted into multi-bit low-speed parallel data, so the load of the data buffer is generally relatively large, and the size of the data buffer is usually increased to ensure its normal operation. .
  • the main purpose of the present disclosure is to provide a sampler, a display driving chip and a display device.
  • the present disclosure provides a sampler including a first sampling control circuit for converting serial input data into N pieces of first serial data; a second sampling control circuit including N second sampling control units, each The second sampling control unit includes M second sampling control unit circuits, N and M are positive integers, N is greater than 1, and/or, M is greater than 1, the mth in the nth second sampling control unit.
  • the two-sampling control unit circuit is used to convert the nth first serial data into corresponding second serial data under the control of the corresponding sampling control signal, where n is a positive integer less than or equal to N;
  • the sampling circuit is electrically connected to the second sampling control unit circuit, and is used for converting the second serial data into corresponding parallel data under the control of the sampling control clock signal.
  • the first sampling control circuit includes N first sampling control unit circuits, and the nth first sampling control unit circuit is configured to convert the serial input data into the nth first serial data.
  • the nth first sampling control unit circuit includes an nth first control inverter and an nth second control inverter;
  • the input terminal of the nth first control inverter is connected to the serial input data, and the output terminal of the nth first control inverter is connected to the output terminal of the nth second control inverter.
  • the input terminal is electrically connected;
  • the output terminal of the nth second control inverter is used for outputting the nth first serial data.
  • the nth first sampling control unit circuit includes the nth control NAND gate and the nth control inverter;
  • the first input terminal of the nth control NAND gate is connected to the serial input data
  • the second input terminal of the nth control NAND gate is connected to the nth input control signal
  • the nth control NAND gate is connected to the nth input control signal.
  • the output end of the control NAND gate is electrically connected with the input end of the nth control inverter;
  • the output terminal of the nth control inverter is used for outputting the nth first serial data.
  • the mth second sampling control unit circuit in the nth second sampling control unit includes a sampling NAND gate and a sampling inverter;
  • the first input terminal of the sampling NAND gate is connected to the nth first serial data
  • the second input terminal of the sampling NAND gate is connected to the corresponding sampling control signal
  • the sampling NAND gate is connected to the corresponding sampling control signal.
  • the output terminal of the gate is electrically connected to the input terminal of the sampling inverter
  • the output terminal of the sampling inverter is electrically connected to the sampling circuit
  • the sampling inverter is used for outputting the corresponding output terminal through its output terminal.
  • the sampling circuit includes multiple D flip-flops
  • the input end of the D flip-flop is connected to the second serial data, the control end of the D flip-flop is connected to the corresponding sampling control clock signal, and the output end of the D flip-flop is used to output the corresponding parallel data .
  • the present disclosure also provides a display driving chip, including the above-mentioned sampler.
  • the display driver chip described in the embodiment of the present disclosure further includes:
  • a clock signal generator for extracting clock edge information in the original serial input data to generate a corresponding input clock signal
  • a delay circuit configured to control the original serial input data to delay a predetermined time to obtain serial input data, and provide the serial input data to the sampler;
  • a delay-locked loop for converting the input clock signal into a plurality of sampling control clock signals and providing the sampling control clock signals to the sampler.
  • the display device includes the above-mentioned display driving chip.
  • FIG. 1 is a block diagram of a sampler according to an example embodiment
  • FIG. 2 is a structural diagram of a display driver chip according to an example embodiment
  • FIG. 3 is a timing diagram of a clock signal employed in a display driver chip according to an example embodiment
  • FIG. 4 is a block diagram of a sampler according to another example embodiment
  • FIG. 5 is a circuit diagram of a sampler according to yet another example embodiment
  • FIG. 6 is a working timing diagram of the embodiment of the sampler shown in FIG. 5 of the present disclosure.
  • FIG. 7 is a circuit diagram of a sampler according to another example embodiment.
  • FIG. 8 is an operation timing diagram of the sampler shown in FIG. 7 according to an example embodiment
  • FIG. 9 is a block diagram of a sampler according to another example embodiment.
  • FIG. 10 is a circuit diagram of a sampler according to yet another example embodiment
  • FIG. 11 is a working timing diagram of the embodiment of the sampler shown in FIG. 10 of the present disclosure.
  • FIG. 12 is a circuit diagram of a sampler according to another example embodiment
  • FIG. 13 is an operation timing diagram of the sampler shown in FIG. 12 according to an example embodiment
  • FIG. 14 shows the current I1 consumed by the data buffer in the conventional sampler, the current I2 consumed by the data buffer in the embodiment of the sampler shown in FIG. 7 , and the embodiment of the sampler shown in FIG. 12 .
  • the sampler includes a first sampling control circuit 11 , a second sampling control circuit 12 and a sampling circuit 13 , wherein the second sampling control circuit 12 includes N second sampling circuits control unit; the second sampling control unit includes M second sampling control unit circuits; the first sampling control circuit 11 is used to convert the serial input data into N first serial data, and N and M are positive Integer; N is greater than 1, and/or, M is greater than 1;
  • the mth second sampling control unit circuit in the nth second sampling control unit is used to convert the nth first serial data into corresponding second serial data under the control of the corresponding sampling control signal;
  • the sampling circuit 13 is electrically connected to the second sampling control unit circuit, and is used for converting the second serial data into corresponding parallel data under the control of the sampling control clock signal;
  • n is a positive integer less than or equal to N.
  • the sampler described in the embodiments of the present disclosure can convert serial input data into N pieces of first serial data through the first sampling control circuit, and the mth second sampling control unit circuit in the nth second control unit uses Under the control of the corresponding sampling control signal, the nth first serial data is converted into the corresponding second serial data, and the sampling circuit, under the control of the sampling control clock signal, converts the second serial data to the corresponding second serial data. The data is converted to the corresponding parallel data.
  • each sampling control unit are controlled by corresponding sampling control signals to perform data conversion, so that when the sampler is working, each sampling included in the working period of the sampler can be made During the time period, the signal output by at least one of the second sampling control unit circuits remains unchanged, so that power consumption can be saved, the peak current and average current of the circuit can be reduced, and the anti-electromagnetic interference performance can be improved.
  • the first sampling control circuit 11 and the second sampling circuit 12 form a data buffer.
  • the sampler described in the embodiment of the present disclosure is included in the display driver chip described in the embodiment of the present disclosure.
  • the display driver chip described in the embodiment of the present disclosure may include a sampler 20 , a clock signal generator 21 , delay circuit 23 and delay-locked loop 24, wherein,
  • the clock signal generator 21 is used to extract the clock edge information in the original serial input data DIN to generate the corresponding input clock signal RCLK;
  • the delay circuit 23 is configured to control the original serial input data DIN to delay a predetermined time to obtain serial input data RDAT, and provide the serial input data RDAT to the sampler 20;
  • the delay locked loop 24 converts the input clock signal RCLK into a plurality of sampling control clock signals and provides the sampling control clock signals to the sampler 20 .
  • the original serial input data DIN may be clock-embedded serial data
  • the clock signal generator 21 extracts clock edge information in DIN to generate a corresponding input clock signal RCLK; for example , when one of the original serial input data DIN has 24 rising edges, the input clock signal RCLK may also have 24 rising edges;
  • the delay-locked loop 24 converts the input clock signal RCLK into a plurality of sampling control clock signals, and each rising edge of the sampling control clock signal corresponds to a rising edge of RCLK;
  • the delay circuit 23 is used to control the original serial input data DIN to delay a predetermined time to obtain the serial input data RDAT; the predetermined time can be selected according to the actual situation, so that the middle part of one data of RDAT is the same as the other one.
  • the sampling control clock signal corresponds to the rising edge, so that the sampler can accurately convert the serial input data RDAT into corresponding parallel data.
  • the delay-locked loop 24 outputs 24 sampling control clock signals
  • the first sampling control clock signal is labeled CLK1
  • the fourth sampling control clock signal is labeled CLK4
  • the fifth sampling control clock signal is labeled CLK5
  • the eighth sampling control clock signal is labeled CLK8.
  • the clock signal, labeled CLK9 is the ninth sampling control clock signal
  • labeled CLK12 is the twelfth sampling control clock signal
  • labeled CLK13 is the thirteenth sampling control clock signal
  • labeled CLK16 is the sixteenth sampling control clock signal
  • the control clock signal, labeled CLK17 is the seventeenth sampling control clock signal
  • labeled CLK20 is the twentieth sampling control clock signal
  • labeled CLK21 is the twenty-first sampling control clock signal
  • labeled CLK24 is the first sampling control clock signal. Twenty-four sampling control clock signal;
  • D1 is the first data carried by RDAT
  • D4 is the fourth data carried by RDAT
  • D5 is the fifth data carried by RDAT
  • D8 is the eighth data carried by RDAT
  • labeled D9 is the ninth data carried by RDAT
  • labeled D12 is the twelfth data carried by RDAT
  • labeled D13 is the thirteenth data carried by RDAT
  • labeled D16 is carried by RDAT
  • the sixteenth data the seventeenth data that is labeled D17 is carried by RDAT
  • the data that is labeled D20 is the twentieth data carried by RDAT
  • the data that is labeled D21 is the twenty-first data carried by RDAT
  • Labeled D24 is the twenty-fourth data carried by RDAT.
  • the middle section of D1 carried by RDAT corresponds to the rising edge of CLK1
  • the middle section of D4 carried by RDAT corresponds to the rising edge of CLK4
  • the middle section of D5 carried by RDAT corresponds to the rising edge of CLK5
  • the middle section of D8 carried by RDAT corresponds to the rising edge of CLK5.
  • the middle section corresponds to the rising edge of CLK8,
  • the middle section of D9 carried by RDAT corresponds to the rising edge of CLK9
  • the middle section of D12 carried by RDAT corresponds to the rising edge of CLK12
  • the middle section of D13 carried by RDAT corresponds to the rising edge of CLK13
  • the middle section of D13 carried by RDAT corresponds to the rising edge of CLK13.
  • the middle section of D16 corresponds to the rising edge of CLK16
  • the middle section of D17 carried by RDAT corresponds to the rising edge of CLK17
  • the middle section of D20 carried by RDAT corresponds to the rising edge of CLK20
  • the middle section of D21 carried by RDAT corresponds to the rising edge of CLK21
  • RDAT The mid-section of the carried D24 corresponds to the rising edge of CLK24.
  • the first sampling control circuit may include N first sampling control unit circuits, and the nth first sampling control unit circuit is used to convert the serial input data into the nth first serial data. .
  • the first sampling control circuit may include N first sampling control unit circuits, and each first sampling control unit circuit outputs one piece of the first serial data.
  • the nth first sampling control unit circuit includes an nth first control inverter and an nth second control inverter;
  • the input terminal of the nth first control inverter is connected to the serial input data, and the output terminal of the nth first control inverter is connected to the output terminal of the nth second control inverter.
  • the input terminal is electrically connected;
  • the output terminal of the nth second control inverter is used for outputting the nth first serial data.
  • the first sampling control unit circuit may include two control inverters, but is not limited thereto.
  • the nth first sampling control unit circuit includes an nth control NAND gate and an nth control inverter
  • the first input terminal of the nth control NAND gate is connected to the serial input data
  • the second input terminal of the nth control NAND gate is connected to the nth input control signal
  • the nth control NAND gate is connected to the nth input control signal.
  • the output end of the control NAND gate is electrically connected with the input end of the nth control inverter;
  • the output terminal of the nth control inverter is used for outputting the nth first serial data.
  • the nth first sampling control unit circuit may include an nth control NAND gate and an nth control inverter, and the second input terminal of the nth control NAND gate is connected to The nth input control signal, when the potential of the nth input control signal is a low voltage, no matter whether the serial input data is a high voltage or a low voltage, the nth control NAND gate outputs a high voltage, thus Power consumption can be saved, and peak and average currents can be reduced.
  • the m-th second sampling control unit circuit in the n-th second sampling control unit can include a sampling NAND gate and a sampling inverter;
  • the first input terminal of the sampling NAND gate is connected to the nth first serial data
  • the second input terminal of the sampling NAND gate is connected to the corresponding sampling control signal
  • the sampling NAND gate is connected to the corresponding sampling control signal.
  • the output terminal of the gate is electrically connected to the input terminal of the sampling inverter
  • the output terminal of the sampling inverter is electrically connected to the sampling circuit
  • the sampling inverter is used for outputting the corresponding output terminal through its output terminal.
  • the second input end of the sampling NAND gate is connected to a corresponding sampling control signal, so that when the potential of the sampling control signal is a low voltage, the output of the sampling NAND gate is all high voltage, the sampling inverters all output low voltage, so that power consumption can be saved.
  • the sampling circuit may include a plurality of D flip-flops
  • the input end of the D flip-flop is connected to the second serial data, the control end of the D flip-flop is connected to the corresponding sampling control clock signal, and the output end of the D flip-flop is used to output the corresponding parallel data .
  • N is equal to 1, and M is equal to 3;
  • the first sampling control circuit 11 is used for converting serial input data into first serial data
  • the second sampling control circuit includes a second sampling control unit
  • the second sampling control unit includes a first second sampling control unit circuit 121, a second second sampling control unit circuit 122 and a third second sampling control unit circuit 123;
  • the first second sampling control unit circuit 121 is configured to convert the first serial data into the first second serial data under the control of the first sampling control signal
  • the second second sampling control unit circuit 122 is configured to convert the first serial data into the second second serial data under the control of the second sampling control signal
  • the third second sampling control unit circuit 123 is used to convert the first serial data into the third second serial data under the control of the third sampling control signal;
  • the sampling circuit 13 is respectively electrically connected to the first second sampling control unit circuit 121 , the second second sampling control unit circuit 122 and the third second sampling control unit circuit 123 for Under the control of the sampling control clock signal, the first second serial data, the second second serial data and the third second serial data are converted into corresponding parallel data.
  • the first sampling control circuit 11 includes a first inverter F1 and a second inverter F2;
  • the first second sampling control unit circuit 121 includes a first NAND gate AF1 and a third inverter F3;
  • the second second sampling control unit circuit 122 includes a second NAND gate AF2 and a fourth inverter F4;
  • the third second sampling control unit circuit 123 includes a third NAND gate AF3 and a fifth inverter F5;
  • the input terminal of F1 is connected to the serial input data RDAT, and the output terminal of F1 is electrically connected to the input terminal of F2;
  • the first input terminal of AF1 is electrically connected to the output terminal of F2; the second input terminal of AF1 is connected to the first enable clock signal EN1, the output terminal of AF1 is electrically connected to the input terminal of F3, and the output terminal of F3 is used to output the first enable clock signal EN1.
  • the first input terminal of AF2 is electrically connected to the output terminal of F2, the second input terminal of AF2 is connected to the second enable clock signal EN2, the output terminal of AF2 is electrically connected to the input terminal of F4, and the output terminal of F4 is used to output the second enabling clock signal EN2.
  • the first input terminal of AF3 is electrically connected to the output terminal of F2, the second input terminal of AF3 is connected to the third enable clock signal EN3, the output terminal of AF3 is electrically connected to the input terminal of F5, and the output terminal of F5 is used to output the third enable clock signal EN3.
  • the sampling circuit 13 is respectively electrically connected to the output end of F3, the output end of F4 and the output end of F5, and is used for, under the control of the sampling control clock signal, the first second serial data, the first second serial data, the first second serial data and the second serial data.
  • the two second serial data and the third second serial data are converted into corresponding parallel data.
  • EN1, EN2 and EN3 are sampling control signals.
  • the first load capacitor is labeled C1
  • the second load capacitor is labeled C2
  • the third load capacitor is labeled C3 .
  • the sampling period includes a first sampling period S1 , a second sampling period S2 and a third sampling period S3 which are set in sequence;
  • the first second sampling control unit circuit 121 works to output the first second serial data RDAT1 through the output terminal of F3 ;
  • the second second sampling control unit circuit 122 works to output the second second serial data RDAT2 through the output terminal of F4 ;
  • EN3 is high voltage
  • EN1 and EN2 are low voltage
  • the third second sampling control unit circuit 123 works to output the third second serial data RDAT3 through the output terminal of F5 .
  • the sampling circuit includes a first sampling unit 61 , a second sampling unit 62 and a third sampling unit 63 ;
  • the first sampling unit 61 includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop and the eighth D flip-flop;
  • the input terminal of the first D flip-flop is connected to RDAT1, the output terminal of the first D flip-flop is electrically connected to the first parallel data output terminal; the control terminal of the first D flip-flop is connected to the first sampling control terminal clock signal;
  • the input terminal of the second D flip-flop is connected to RDAT1, the output terminal of the second D flip-flop is electrically connected to the second parallel data output terminal; the control terminal of the second D flip-flop is connected to the second sampling control terminal clock signal;
  • the input terminal of the third D flip-flop is connected to RDAT1, the output terminal of the third D flip-flop is electrically connected to the third parallel data output terminal; the control terminal of the third D flip-flop is connected to the third sampling control terminal clock signal;
  • the input terminal of the fourth D flip-flop is connected to RDAT1, the output terminal of the fourth D flip-flop is electrically connected to the fourth parallel data output terminal; the control terminal of the fourth D flip-flop is connected to the fourth sampling control terminal clock signal;
  • the input end of the fifth D flip-flop is connected to RDAT1, the output end of the fifth D flip-flop is electrically connected to the fifth parallel data output end; the control end of the fifth D flip-flop is connected to the fifth sampling control clock signal;
  • the input end of the sixth D flip-flop is connected to RDAT1, the output end of the sixth D flip-flop is electrically connected to the sixth parallel data output end; the control end of the sixth D flip-flop is connected to the sixth sampling control clock signal;
  • the input terminal of the seventh D flip-flop is connected to RDAT1, the output terminal of the seventh D flip-flop is electrically connected to the seventh parallel data output terminal; the control terminal of the seventh D flip-flop is connected to the seventh sampling control terminal clock signal;
  • the input end of the eighth D flip-flop is connected to RDAT1, the output end of the eighth D flip-flop is electrically connected to the eighth parallel data output end; the control end of the eighth D flip-flop is connected to the eighth sampling control clock signal;
  • the second sampling unit 62 includes a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop, a twelfth D flip-flop, a thirteenth D flip-flop, a fourteenth D flip-flop, and a tenth D flip-flop. Five D flip-flops and sixteenth D flip-flops;
  • the input end of the ninth D flip-flop is connected to RDAT2, the output end of the ninth D flip-flop is electrically connected to the ninth parallel data output end; the control end of the ninth D flip-flop is connected to the ninth sampling control clock signal;
  • the input terminal of the tenth D flip-flop is connected to RDAT2, the output terminal of the tenth D flip-flop is electrically connected to the tenth parallel data output terminal; the control terminal of the tenth D flip-flop is connected to the tenth sampling control terminal. clock signal;
  • the input end of the eleventh D flip-flop is connected to RDAT2, the output end of the eleventh D flip-flop is electrically connected to the eleventh parallel data output end; the control end of the eleventh D flip-flop is connected to The eleventh sampling control clock signal;
  • the input end of the twelfth D flip-flop is connected to RDAT2, the output end of the twelfth D flip-flop is electrically connected to the twelfth parallel data output end; the control end of the twelfth D flip-flop is connected to The twelfth sampling control clock signal;
  • the input end of the thirteenth D flip-flop is connected to RDAT2, the output end of the thirteenth D flip-flop is electrically connected to the thirteenth parallel data output end; the control end of the thirteenth D flip-flop is connected to The thirteenth sampling control clock signal;
  • the input end of the fourteenth D flip-flop is connected to RDAT2, the output end of the fourteenth D flip-flop is electrically connected to the fourteenth parallel data output end; the control end of the fourteenth D flip-flop is connected to The fourteenth sampling control clock signal;
  • the input end of the fifteenth D flip-flop is connected to RDAT2, the output end of the fifteenth D flip-flop is electrically connected to the fifteenth parallel data output end; the control end of the fifteenth D flip-flop is connected to The fifteenth sampling control clock signal;
  • the input end of the sixteenth D flip-flop is connected to RDAT2, the output end of the sixteenth D flip-flop is electrically connected to the sixteenth parallel data output end; the control end of the sixteenth D flip-flop is connected to The sixteenth sampling control clock signal;
  • the third sampling unit 63 includes a seventeenth D flip-flop, an eighteenth D flip-flop, a nineteenth D flip-flop, a twentieth D flip-flop, a twenty-first D flip-flop, and a twenty-second D flip-flop. , the twenty-third D flip-flop and the twenty-fourth D flip-flop;
  • the input end of the seventeenth D flip-flop is connected to RDAT3, the output end of the seventeenth D flip-flop is electrically connected to the seventeenth parallel data output end; the control end of the seventeenth D flip-flop is connected to The seventeenth sampling control clock signal;
  • the input end of the eighteenth D flip-flop is connected to RDAT3, the output end of the eighteenth D flip-flop is electrically connected to the eighteenth parallel data output end; the control end of the eighteenth D flip-flop is connected to The eighteenth sampling control clock signal;
  • the input end of the nineteenth D flip-flop is connected to RDAT3, the output end of the nineteenth D flip-flop is electrically connected to the nineteenth parallel data output end; the control end of the nineteenth D flip-flop is connected to The nineteenth sampling control clock signal;
  • the input end of the twentieth D flip-flop is connected to RDAT3, the output end of the twentieth D flip-flop is electrically connected to the twentieth parallel data output end; the control end of the twentieth D flip-flop is connected to The twentieth sampling control clock signal;
  • the input terminal of the twenty-first D flip-flop is connected to RDAT3, and the output terminal of the twenty-first D flip-flop is electrically connected to the twenty-first parallel data output terminal;
  • the control terminal is connected to the twenty-first sampling control clock signal;
  • the input end of the 22nd D flip-flop is connected to RDAT3, and the output end of the 22nd D flip-flop is electrically connected to the 22nd parallel data output end;
  • the control terminal is connected to the twenty-second sampling control clock signal;
  • the input terminal of the twenty-third D flip-flop is connected to RDAT3, and the output terminal of the twenty-third D flip-flop is electrically connected to the twenty-third parallel data output terminal; the control of the twenty-third flip-flop The terminal is connected to the twenty-third sampling control clock signal;
  • the input terminal of the twenty-fourth D flip-flop is connected to RDAT3, and the output terminal of the twenty-fourth D flip-flop is electrically connected to the twenty-fourth parallel data output terminal;
  • the control terminal is connected to the twenty-fourth sampling control clock signal.
  • DOUT[1:8] is the first set of parallel data output terminals
  • the first set of parallel data output terminals includes: a first parallel data output terminal, a second parallel data output terminal, a third parallel data output terminal a parallel data output terminal, a fourth parallel data output terminal, a fifth parallel data output terminal, a sixth parallel data output terminal, a seventh parallel data output terminal and an eighth parallel data output terminal;
  • Labeled CLK[1:8] is a first clock signal set, the first clock signal set includes: a first sampling control clock signal, a second sampling control clock signal, a third sampling control clock signal, and a fourth sampling control clock signal a clock signal, a fifth sampling control clock signal, a sixth sampling control clock signal, a seventh sampling control clock signal, and an eighth sampling control clock signal;
  • Labeled DOUT[9:16] is a second set of parallel data output terminals, the second set of parallel data output terminals includes: a ninth parallel data output terminal, a tenth parallel data output terminal, and an eleventh parallel data output terminal , the twelfth parallel data output terminal, the thirteenth parallel data output terminal, the fourteenth parallel data output terminal, the fifteenth parallel data output terminal and the sixteenth parallel data output terminal;
  • Labeled CLK[9:16] is the second clock signal set, the second clock signal set includes: the ninth sampling control clock signal, the tenth sampling control clock signal, the eleventh sampling control clock signal, the twelfth sampling control clock signal sampling control clock signal, thirteenth sampling control clock signal, fourteenth sampling control clock signal, fifteenth sampling control clock signal, sixteenth sampling control clock signal;
  • Labeled DOUT[17:24] is the third parallel data output terminal set
  • the third parallel data output terminal set includes: the seventeenth parallel data output terminal, the eighteenth parallel data output terminal, the nineteenth parallel data output terminal an output terminal, a twentieth parallel data output terminal, a twenty-first parallel data output terminal, a twenty-second parallel data output terminal, a twenty-third parallel data output terminal, and a twenty-fourth parallel data output terminal;
  • Labeled CLK[17:24] is the third clock signal set
  • the third clock signal set includes: the seventeenth sampling control clock signal, the eighteenth sampling control clock signal, the nineteenth sampling control clock signal, the Twenty sampling control clock signal, twenty-first sampling control clock signal, twenty-second sampling control clock signal, twenty-third sampling control clock signal, twenty-fourth sampling control clock signal.
  • FIG. 8 is an operation timing chart of the sampler shown in FIG. 7 .
  • the first sampling control clock signal labeled CLK1, the fourth sampling control clock signal labeled CLK4, the fifth sampling control clock signal labeled CLK5, and the eighth sampling control clock signal labeled CLK8 The control clock signal, labeled CLK9 is the ninth sampling control clock signal, labeled CLK12 is the twelfth sampling control clock signal, labeled CLK13 is the thirteenth sampling control clock signal, labeled CLK16 is the sixteenth sampling control clock signal
  • the sampling control clock signal, the seventeenth sampling control clock signal labeled CLK17, the twentieth sampling control clock signal labeled CLK20, the twenty-first sampling control clock signal labeled CLK21, and the CLK24 sampling control clock signal The twenty-fourth sampling control clock signal;
  • D1 is the first data carried by RDAT
  • D4 is the fourth data carried by RDAT
  • D5 is the fifth data carried by RDAT
  • D8 is the eighth data carried by RDAT
  • labeled D9 is the ninth data carried by RDAT
  • labeled D12 is the twelfth data carried by RDAT
  • labeled D13 is the thirteenth data carried by RDAT
  • labeled D16 is carried by RDAT
  • the sixteenth data the seventeenth data that is labeled D17 is carried by RDAT
  • the data that is labeled D20 is the twentieth data carried by RDAT
  • the data that is labeled D21 is the twenty-first data carried by RDAT
  • the twenty-fourth data carried by RDAT is labeled D24;
  • the reference numeral S1 is the first sampling time period
  • the reference numeral S2 is the second sampling time period
  • the reference numeral S3 is the third sampling time period.
  • N is equal to 3
  • M is equal to 2;
  • the first sampling control circuit includes a first first sampling control unit circuit 81, a second first sampling control unit circuit 82 and a third first sampling control unit circuit 83;
  • the second sampling control circuit includes a first second sampling control unit, a second second sampling control unit and a third second sampling control unit;
  • the first second sampling control unit includes a first second sampling control unit circuit 121 and a second second sampling control unit circuit 122;
  • the second second sampling control unit includes a third second sampling control unit circuit 123 and a fourth second sampling control unit circuit 124;
  • the third second sampling control unit includes a fifth second sampling control unit circuit 125 and a sixth second sampling control unit circuit 126;
  • the first second sampling control unit circuit 121 is configured to convert the first first serial data into the first second serial data under the control of the first sampling control signal;
  • the second second sampling control unit circuit 122 is configured to convert the first first serial data into the second second serial data under the control of the second sampling control signal;
  • the third second sampling control unit circuit 123 is used to convert the second first serial data into the third second serial data under the control of the third sampling control signal;
  • the fourth second sampling control unit circuit 124 is configured to convert the second first serial data into fourth second serial data under the control of the fourth sampling control signal;
  • the fifth second sampling control unit circuit 125 is configured to convert the third first serial data into the fifth second serial data under the control of the fifth sampling control signal;
  • the sixth second sampling control unit circuit 126 is configured to convert the third first serial data into the sixth second serial data under the control of the sixth sampling control signal;
  • the sampling circuit 13 is respectively connected with the first second sampling control unit circuit 121 , the second second sampling control unit circuit 122 , the third second sampling control unit circuit 123 , the fourth The second sampling control unit circuit 124, the fifth second sampling control unit circuit 125 and the sixth second sampling control unit circuit 126 are electrically connected to the first second serial data, the second second serial data, the third second serial data, the fourth second serial data, the fifth second serial data Serial data, the sixth second serial data are converted into corresponding parallel data.
  • the first first sampling control unit circuit 81 includes a first NAND gate AF1 and a first inverter F1;
  • the second first sampling control unit circuit 82 includes a second NAND gate AF2 and a second inverter F2;
  • the third first sampling control unit circuit 83 includes a third NAND gate AF3 and a third inverter F3;
  • the first second sampling control unit circuit 121 includes a fourth NAND gate AF4 and a fourth inverter F4;
  • the second second sampling control unit circuit 122 includes a fifth NAND gate AF5 and a fifth inverter F4;
  • the third second sampling control unit circuit 123 includes a sixth NAND gate AF6 and a sixth inverter F6;
  • the fourth second sampling control unit circuit 124 includes a seventh NAND gate AF7 and a seventh inverter F7;
  • the fifth second sampling control unit circuit 125 includes an eighth NAND gate AF8 and an eighth inverter F8;
  • the sixth second sampling control unit circuit 126 includes a ninth NAND gate AF9 and a ninth inverter F9;
  • the first input end of AF1 is connected to RDAT, the second input end of AF1 is connected to the first enable clock signal EN1, and the output end of AF1 is electrically connected to the input end of F1;
  • the first input end of AF2 is connected to RDAT, the second input end of AF2 is connected to the second enable clock signal EN2, and the output end of AF2 is electrically connected to the input end of F2;
  • the first input end of AF3 is connected to RDAT, the second input end of AF3 is connected to the third enable clock signal EN3, and the output end of AF3 is electrically connected to the input end of F3;
  • the first input terminal of AF4 is electrically connected to the output terminal of F1
  • the second input terminal of AF4 is connected to the fourth enable clock signal EN1.1
  • the output terminal of AF4 is electrically connected to the input terminal of F4
  • the output terminal of F4 is used for Output the first second serial data RDAT1;
  • the first input terminal of AF5 is electrically connected to the output terminal of F1
  • the second input terminal of AF5 is connected to the fifth enable clock signal EN1.2
  • the output terminal of AF5 is electrically connected to the input terminal of F5
  • the output terminal of F5 is used for Output the second second serial data RDAT2;
  • the first input terminal of AF6 is electrically connected to the output terminal of F2, the second input terminal of AF4 is connected to the sixth enable clock signal EN2.1, the output terminal of AF6 is electrically connected to the input terminal of F6, and the output terminal of F6 is used for Output the third second serial data RDAT3;
  • the first input terminal of AF7 is electrically connected to the output terminal of F2, the second input terminal of AF7 is connected to the seventh enable clock signal EN2.2, the output terminal of AF7 is electrically connected to the input terminal of F7, and the output terminal of F7 is used for Output the fourth second serial data RDAT4;
  • the first input terminal of AF8 is electrically connected to the output terminal of F3, the second input terminal of AF8 is connected to the eighth enable clock signal EN3.1, the output terminal of AF8 is electrically connected to the input terminal of F8, and the output terminal of F8 is used for Output the fifth second serial data RDAT5;
  • the first input terminal of AF9 is electrically connected to the output terminal of F3, the second input terminal of AF9 is connected to the ninth enable clock signal EN3.2, the output terminal of AF9 is electrically connected to the input terminal of F9, and the output terminal of F9 is used for The sixth second serial data RDAT4 is output.
  • EN1, EN2 and EN3 are input control signals, and EN1.1, EN1.2, EN2.1, EN2.2, EN3.1 and EN3.2 are sampling control signals.
  • the first load capacitor is labeled C1
  • the second load capacitor is labeled C2
  • the third load capacitor is labeled C3
  • the fourth load capacitor is labeled C4.
  • C5 is the fifth load capacitance
  • C6 is the sixth load capacitance.
  • the sampling period includes a first sampling period S1 , a second sampling period S2 , a third sampling period S3 , a first sampling period S1 , a second sampling period S2 , a third sampling period S3 , the fourth sampling period S4, the fifth sampling period S5 and the sixth sampling period S6;
  • EN1 is high voltage
  • EN2 and EN3 are low voltage
  • EN1.1 is high voltage
  • EN1.2, EN2.1, EN2.2, EN3.1 and EN3.2 are all low voltage
  • the first first sampling control unit circuit 81 and the first second sampling control unit circuit 121 work to output the first second serial data RDAT1 through the output terminal of F4;
  • EN1 is high voltage
  • EN2 and EN3 are low voltage
  • EN1.2 is high voltage
  • EN1.1, EN2.1, EN2.2, EN3.1 and EN3.2 are all low voltage
  • the first first sampling control unit circuit 81 and the second second sampling control unit circuit 122 work to output the second second serial data RDAT2 through the output terminal of F5;
  • EN2 is high voltage
  • EN1 and EN3 are low voltage
  • EN2.1 is high voltage
  • EN1.1, EN1.2, EN2.2, EN3.1 and EN3.2 are all low voltage
  • the second first sampling control unit circuit 82 and the third second sampling control unit circuit 123 work to output the third second serial data RDAT3 through the output terminal of F6;
  • EN2 is high voltage
  • EN1 and EN3 are low voltage
  • EN2.2 is high voltage
  • EN1.1, EN1.2, EN2.1, EN3.1 and EN3.2 are all low voltage
  • the second first sampling control unit circuit 81 and the fourth second sampling control unit circuit 124 work to output the fourth second serial data RDAT4 through the output terminal of F7;
  • EN3 is high voltage
  • EN1 and EN2 are low voltage
  • EN3.1 is high voltage
  • EN1.1, EN1.2, EN2.1, EN2.2 and EN3.2 are all low voltage
  • the third first sampling control unit circuit 83 and the fifth second sampling control unit circuit 125 work to output the fifth second serial data RDAT5 through the output end of F8;
  • EN3 is high voltage
  • EN1 and EN2 are low voltage
  • EN3.2 is high voltage
  • EN1.1, EN2.1, EN2.1, EN2.2 and EN3.1 are all low voltage
  • the third first sampling control unit circuit 83 and the sixth second sampling control unit circuit 126 work to output the sixth second serial data RDAT6 through the output terminal of F9.
  • the sampling circuit includes a first sampling unit 61 , a second sampling unit 62 , a third sampling unit 63 , and a fourth sampling unit 64, the fifth sampling unit 65 and the sixth sampling unit 66;
  • the first sampling unit 61 includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the first sampling unit 62 includes a fifth D flip-flop and a sixth D flip-flop , the seventh D flip-flop and the eighth D flip-flop;
  • the input terminal of the first D flip-flop is connected to RDAT1, the output terminal of the first D flip-flop is electrically connected to the first parallel data output terminal; the control terminal of the first D flip-flop is connected to the first sampling control terminal clock signal;
  • the input terminal of the second D flip-flop is connected to RDAT1, the output terminal of the second D flip-flop is electrically connected to the second parallel data output terminal; the control terminal of the second D flip-flop is connected to the second sampling control terminal clock signal;
  • the input terminal of the third D flip-flop is connected to RDAT1, the output terminal of the third D flip-flop is electrically connected to the third parallel data output terminal; the control terminal of the third D flip-flop is connected to the third sampling control terminal clock signal;
  • the input terminal of the fourth D flip-flop is connected to RDAT1, the output terminal of the fourth D flip-flop is electrically connected to the fourth parallel data output terminal; the control terminal of the fourth D flip-flop is connected to the fourth sampling control terminal clock signal;
  • the input end of the fifth D flip-flop is connected to RDAT2, the output end of the fifth D flip-flop is electrically connected to the fifth parallel data output end; the control end of the fifth D flip-flop is connected to the fifth sampling control clock signal;
  • the input end of the sixth D flip-flop is connected to RDAT2, the output end of the sixth D flip-flop is electrically connected to the sixth parallel data output end; the control end of the sixth D flip-flop is connected to the sixth sampling control clock signal;
  • the input end of the seventh D flip-flop is connected to RDAT2, the output end of the seventh D flip-flop is electrically connected to the seventh parallel data output end; the control end of the seventh D flip-flop is connected to the seventh sampling control clock signal;
  • the input end of the eighth D flip-flop is connected to RDAT2, the output end of the eighth D flip-flop is electrically connected to the eighth parallel data output end; the control end of the eighth D flip-flop is connected to the eighth sampling control clock signal;
  • the third sampling unit 63 includes a ninth D flip-flop, a tenth D flip-flop, an eleventh D flip-flop and a twelfth D flip-flop, and the fourth sampling unit 64 includes a thirteenth D flip-flop, a Fourteen D flip-flops, fifteenth D flip-flops and sixteenth D flip-flops;
  • the input end of the ninth D flip-flop is connected to RDAT3, the output end of the ninth D flip-flop is electrically connected to the ninth parallel data output end; the control end of the ninth D flip-flop is connected to the ninth sampling control clock signal;
  • the input terminal of the tenth D flip-flop is connected to RDAT3, the output terminal of the tenth D flip-flop is electrically connected to the tenth parallel data output terminal; the control terminal of the tenth D flip-flop is connected to the tenth sampling control terminal clock signal;
  • the input end of the eleventh D flip-flop is connected to RDAT3, the output end of the eleventh D flip-flop is electrically connected to the eleventh parallel data output end; the control end of the eleventh D flip-flop is connected to The eleventh sampling control clock signal;
  • the input end of the twelfth D flip-flop is connected to RDAT3, the output end of the twelfth D flip-flop is electrically connected to the twelfth parallel data output end; the control end of the twelfth D flip-flop is connected to The twelfth sampling control clock signal;
  • the input end of the thirteenth D flip-flop is connected to RDAT4, the output end of the thirteenth D flip-flop is electrically connected to the thirteenth parallel data output end; the control end of the thirteenth D flip-flop is connected to The thirteenth sampling control clock signal;
  • the input end of the fourteenth D flip-flop is connected to RDAT4, the output end of the fourteenth D flip-flop is electrically connected to the fourteenth parallel data output end; the control end of the fourteenth D flip-flop is connected to The fourteenth sampling control clock signal;
  • the input end of the fifteenth D flip-flop is connected to RDAT4, the output end of the fifteenth D flip-flop is electrically connected to the fifteenth parallel data output end; the control end of the fifteenth D flip-flop is connected to The fifteenth sampling control clock signal;
  • the input end of the sixteenth D flip-flop is connected to RDAT4, the output end of the sixteenth D flip-flop is electrically connected to the sixteenth parallel data output end; the control end of the sixteenth D flip-flop is connected to The sixteenth sampling control clock signal;
  • the fifth sampling unit 65 includes a seventeenth D flip-flop, an eighteenth D flip-flop, a nineteenth D flip-flop and a twentieth D flip-flop; the fifth sampling unit 66 includes a twenty-first D flip-flop device, the twenty-second D flip-flop, the twenty-third D flip-flop, and the twenty-fourth D flip-flop;
  • the input end of the seventeenth D flip-flop is connected to RDAT5, the output end of the seventeenth D flip-flop is electrically connected to the seventeenth parallel data output end; the control end of the seventeenth D flip-flop is connected to The seventeenth sampling control clock signal;
  • the input end of the eighteenth D flip-flop is connected to RDAT5, the output end of the eighteenth D flip-flop is electrically connected to the eighteenth parallel data output end; the control end of the eighteenth D flip-flop is connected to The eighteenth sampling control clock signal;
  • the input end of the nineteenth D flip-flop is connected to RDAT5, the output end of the nineteenth D flip-flop is electrically connected to the nineteenth parallel data output end; the control end of the nineteenth D flip-flop is connected to The nineteenth sampling control clock signal;
  • the input end of the twentieth D flip-flop is connected to RDAT5, the output end of the twentieth D flip-flop is electrically connected to the twentieth parallel data output end; the control end of the twentieth D flip-flop is connected to The twentieth sampling control clock signal;
  • the input end of the twenty-first D flip-flop is connected to RDAT6, and the output end of the twenty-first D flip-flop is electrically connected to the twenty-first parallel data output end;
  • the control terminal is connected to the twenty-first sampling control clock signal;
  • the input end of the 22nd D flip-flop is connected to RDAT6, and the output end of the 22nd D flip-flop is electrically connected to the 22nd parallel data output end;
  • the control terminal is connected to the twenty-second sampling control clock signal;
  • the input terminal of the twenty-third D flip-flop is connected to RDAT6, and the output terminal of the twenty-third D flip-flop is electrically connected to the twenty-third parallel data output terminal; the output terminal of the twenty-third D flip-flop is electrically connected to the twenty-third parallel data output terminal;
  • the control terminal is connected to the twenty-third sampling control clock signal;
  • the input end of the twenty-fourth D flip-flop is connected to RDAT6, and the output end of the twenty-fourth D flip-flop is electrically connected to the twenty-fourth parallel data output end;
  • the control terminal is connected to the twenty-fourth sampling control clock signal.
  • DOUT[1:4] is the first set of parallel data output terminals
  • the first set of parallel data output terminals includes: a first parallel data output terminal, a second parallel data output terminal, a third parallel data output terminal a parallel data output terminal and a fourth parallel data output terminal;
  • Labeled DOUT[5:8] is a second set of parallel data output terminals, the second set of parallel data output terminals includes: a fifth parallel data output terminal, a sixth parallel data output terminal, a seventh parallel data output terminal, and the eighth parallel data output terminal;
  • Labeled CLK[1:4] is a first clock signal set, the first clock signal set includes: a first sampling control clock signal, a second sampling control clock signal, a third sampling control clock signal, and a fourth sampling control clock signal clock signal;
  • Labeled CLK[5:6] is a second clock signal set, the second clock signal set includes: a fifth sampling control clock signal, a sixth sampling control clock signal, a seventh sampling control clock signal, and an eighth sampling control clock signal clock signal;
  • Labeled DOUT[9:12] is a third set of parallel data output terminals, the third set of parallel data output terminals includes: a ninth parallel data output terminal, a tenth parallel data output terminal, and an eleventh parallel data output terminal and the twelfth parallel data output;
  • Labeled DOUT[13:16] is the fourth set of parallel data output terminals
  • the fourth set of parallel data output terminals includes: the thirteenth parallel data output terminal, the fourteenth parallel data output terminal, and the fifteenth parallel data output terminal.
  • Labeled CLK[9:12] is the third clock signal set, the third clock signal set includes: the ninth sampling control clock signal, the tenth sampling control clock signal, the eleventh sampling control clock signal and the twelfth sampling control clock signal Sampling control clock signal;
  • Labeled CLK[13:16] is the fourth clock signal set, the fourth clock signal set includes: the thirteenth sampling control clock signal, the fourteenth sampling control clock signal, the fifteenth sampling control clock signal, the thirteenth sampling control clock signal, the Sixteen sampling control clock signals;
  • Labeled DOUT[17:20] is the fifth parallel data output terminal set, and the fifth parallel data output terminal set includes: the seventeenth parallel data output terminal, the eighteenth parallel data output terminal, and the nineteenth parallel data output terminal. an output terminal and a twentieth parallel data output terminal;
  • Labeled DOUT[21:24] is the sixth parallel data output terminal set
  • the sixth parallel data output terminal set includes: the twenty-first parallel data output terminal, the twenty-second parallel data output terminal, the twenty-second parallel data output terminal three parallel data output terminals and twenty-four parallel data output terminals;
  • Labeled CLK[17:20] is the fifth clock signal set, the fifth clock signal set includes: the seventeenth sampling control clock signal, the eighteenth sampling control clock signal, the nineteenth sampling control clock signal and the eighteenth sampling control clock signal Twenty sampling control clock signal;
  • Labeled CLK[21:24] is the sixth clock signal set
  • the sixth clock signal set includes: the twenty-first sampling control clock signal, the twenty-second sampling control clock signal, and the twenty-third sampling control clock signal, the twenty-fourth sampling control clock signal.
  • FIG. 13 is an operation timing chart of the sampler shown in FIG. 12 .
  • the first sampling control clock signal labeled CLK1, the fourth sampling control clock signal labeled CLK4, the fifth sampling control clock signal labeled CLK5, and the eighth sampling control clock signal labeled CLK8 The control clock signal, labeled CLK9 is the ninth sampling control clock signal, labeled CLK12 is the twelfth sampling control clock signal, labeled CLK13 is the thirteenth sampling control clock signal, labeled CLK16 is the sixteenth sampling control clock signal
  • the sampling control clock signal, the seventeenth sampling control clock signal labeled CLK17, the twentieth sampling control clock signal labeled CLK20, the twenty-first sampling control clock signal labeled CLK21, and the CLK24 sampling control clock signal The twenty-fourth sampling control clock signal;
  • D1 is the first data carried by RDAT
  • D4 is the fourth data carried by RDAT
  • D5 is the fifth data carried by RDAT
  • D8 is the eighth data carried by RDAT
  • labeled D9 is the ninth data carried by RDAT
  • labeled D12 is the twelfth data carried by RDAT
  • labeled D13 is the thirteenth data carried by RDAT
  • labeled D16 is carried by RDAT
  • the sixteenth data the seventeenth data that is labeled D17 is carried by RDAT
  • the data that is labeled D20 is the twentieth data carried by RDAT
  • the data that is labeled D21 is the twenty-first data carried by RDAT
  • the twenty-fourth data carried by RDAT is labeled D24;
  • the display driving chip according to the embodiment of the present disclosure includes the above-mentioned sampler.
  • the display driver chip may further include a clock signal generator, a delay circuit and a delay-locked loop, wherein,
  • the clock signal generator is used for extracting clock edge information in the original serial input data to generate a corresponding input clock signal
  • the delay circuit is configured to control the original serial input data to delay a predetermined time to obtain serial input data, and provide the serial input data to the sampler;
  • the delay locked loop converts the input clock signal into a plurality of sampling control clock signals and provides the sampling control clock signals to the sampler.
  • the display device includes the above-mentioned display driving chip.

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Abstract

一种采样器、显示驱动芯片和显示装置。采样器包括第一采样控制电路（11），用于将串行输入数据转换为N个第一串行数据；第二采样控制电路（12），包括N个第二采样控制单元，每个第二采样控制单元包括M个第二采样控制单元电路，N和M 为正整数，N大于1，和/或，M大于1，第n个第二采样控制单元中的第m个第二采样控制单元电路在采样控制信号的控制下，将第n个第一串行数据转换为第二串行数据，n为小于或等于N的正整数；采样电路（13），与第二采样控制单元电连接，用于在采样控制时钟信号的控制下，将第二串行数据转换为相应的并行数据。

Description

采样器、显示驱动芯片和显示装置 技术领域
本公开涉及信号采样技术领域，尤其涉及一种采样器、显示驱动芯片和显示装置。
背景技术
在显示驱动芯片电路中，时钟信号生成电路从高速的串行数据中提取时钟，生成参考时钟信号，以操作显示驱动逻辑。在串行数据转并行数据过程中，一位高速串行数据会转成多位低速并行数据，所以数据缓冲器的负载一般会比较大，通常会增大数据缓冲器的尺寸来保证其正常工作。
发明内容
本公开的主要目的在于提供一种采样器、显示驱动芯片和显示装置。
本公开提供了一种采样器，包括第一采样控制电路，用于将串行输入数据转换为N个第一串行数据；第二采样控制电路，包括N个第二采样控制单元，每个所述第二采样控制单元包括M个第二采样控制单元电路，N和M为正整数，N大于1，和/或，M大于1，第n个第二采样控制单元中的第m个第二采样控制单元电路用于在相应的采样控制信号的控制下，将第n个第一串行数据转换为相应的第二串行数据，n为小于或等于N的正整数；
所述采样电路，与所述第二采样控制单元电路电连接，用于在采样控制时钟信号的控制下，将所述第二串行数据转换为相应的并行数据。
可选的，所述第一采样控制电路包括N个第一采样控制单元电路，第n个第一采样控制单元电路用于将所述串行输入数据转换为第n个第一串行数据。
可选的，所述第n个第一采样控制单元电路包括第n个第一控制反相器和第n个第二控制反相器；
所述第n个第一控制反相器的输入端接入所述串行输入数据，所述第n个第一控制反相器的输出端与所述第n个第二控制反相器的输入端电连接；
所述第n个第二控制反相器的输出端用于输出所述第n个第一串行数据。
可选的，所述第n个第一采样控制单元电路包括第n个控制与非门和第n个控制反相器；
所述第n个控制与非门的第一输入端接入所述串行输入数据，所述第n个控制与非门的第二输入端接入第n输入控制信号，所述第n个控制与非门的输出端与所述第n个控制反相器的输入端电连接；
所述第n个控制反相器的输出端用于输出所述第n个第一串行数据。
可选的，第n个第二采样控制单元中的第m个第二采样控制单元电路包括采样与非门和采样反相器；
所述采样与非门的第一输入端接入所述第n个第一串行数据，所述采样与非门的第二输入端接入所述相应的采样控制信号，所述采样与非门的输出端与所述采样反相器的输入端电连接，所述采样反相器的输出端与所述采样电路电连接，所述采样反相器用于通过其输出端输出所述相应的第二串行数据至所述采样电路。
可选的，所述采样电路包括多个D触发器；
所述D触发器的输入端接入所述第二串行数据，所述D触发器的控制端接入相应的采样控制时钟信号，所述D触发器的输出端用于输出相应的并行数据。
本公开还提供了一种显示驱动芯片，包括上述的采样器。
可选的，本公开实施例所述的显示驱动芯片还包括：
时钟信号生成器，用于提取原始串行输入数据中的时钟边沿信息，以产生响应的输入时钟信号；
延迟电路，用于控制所述原始串行输入数据延时预定时间，以得到串行输入数据，并将所述串行输入数据提供至所述采样器；
延迟锁相环，用于将所述输入时钟信号转换为多个采样控制时钟信号，并将所述采样控制时钟信号提供至所述采样器。
本公开实施例所述的显示装置包括上述的显示驱动芯片。
附图说明
图1是根据示例实施例的采样器的结构图；
图2是根据示例实施例的显示驱动芯片的结构图；
图3是根据示例实施例的显示驱动芯片中采用的时钟信号的时序图；
图4是根据另一示例实施例的采样器的结构图；
图5是根据又一示例实施例的采样器的电路图；
图6是本公开图5所示的采样器的实施例的工作时序图；
图7是根据另一示例实施例的采样器的电路图；
图8是根据示例实施例的图7所示的采样器的工作时序图；
图9是根据另一示例实施例的采样器的结构图；
图10是根据又一示例实施例的采样器的电路图；
图11是本公开图10所示的采样器的实施例的工作时序图；
图12是根据另一示例实施例的采样器的电路图；
图13是根据示例实施例的图12所示的采样器的工作时序图；
图14是现有的采样器中的数据缓冲器耗费的电流I1、图7所示的采样器的实施例中的数据缓冲器耗费的电流I2，以及，图12所示的采样器的实施例中的数据缓冲器耗费的电流I3的时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开实施例所述的采样器包括第一采样控制电路11、第二采样控制电路12和采样电路13，其中，所述第二采样控制电路12包括N个第二采样控制单元；所述第二采样控制单元包括M个第二采样控制单元电路；所述第一采样控制电路11用于将串行输入数据转换为N个第一串行数据，N和M为正整数；N大于1，和/或，M大于1；
第n个第二采样控制单元中的第m个第二采样控制单元电路用于在相应的采样控制信号的控制下，将第n个第一串行数据转换为相应的第二串行数据；
所述采样电路13与所述第二采样控制单元电路电连接，用于在采样控制时钟信号的控制下，将所述第二串行数据转换为相应的并行数据；
n为小于或等于N的正整数。
本公开实施例所述的采样器可以通过第一采样控制电路将串行输入数据转换为N个第一串行数据，第n个第二控制单元中的第m个第二采样控制单元电路用于在相应的采样控制信号的控制下，将第n个第一串行数据转换为相应的第二串行数据，所述采样电路在采样控制时钟信号的控制下，将所述第二串行数据转换为相应的并行数据。在本公开实施例中，各采样控制单元的电路相应的采样控制信号的控制下，以进行数据转换，从而可以在所述采样器工作时，使得在所述采样器的工作时段包括的各个采样时间段，至少一个所述第二采样控制单元电路输出的信号不变，从而能够节省功耗，降低电路的峰值电流和平均电流，提升抗电磁干扰性能。
在本公开实施例中，所述第一采样控制电路11和所述第二采样电路12组成数据缓冲器。
本公开实施例所述的采样器包含于本公开实施例所述的显示驱动芯片，如图2所示，本公开实施例所述的显示驱动芯片可以包括采样器20、时钟信号生成器21、延迟电路23和延迟锁相环24，其中，
所述时钟信号生成器21用于提取原始串行输入数据DIN中的时钟边沿信息，以产生相应的输入时钟信号RCLK；
所述延迟电路23用于控制所述原始串行输入数据DIN延时预定时间，以得到串行输入数据RDAT，并将所述串行输入数据RDAT提供至所述采样器20；
所述延迟锁相环24将所述输入时钟信号RCLK转换为多个采样控制时钟信号，并将所述采样控制时钟信号提供至所述采样器20。
在本公开实施例中，所述原始串行输入数据DIN可以为时钟嵌入式的串行数据，所述时钟信号生成器21提取DIN中的时钟边沿信息，以产生相应的输入时钟信号RCLK；例如，当一个所述原始串行输入数据DIN具有24个上 升沿时，所述输入时钟信号RCLK也可以具有24个上升沿；
所述延迟锁相环24将所述输入时钟信号RCLK转换为多个采样控制时钟信号，每个所述采样控制时钟信号的上升沿对应于RCLK的一个上升沿；
所述延迟电路23用于控制所述原始串行输入数据DIN延时预定时间，以得到串行输入数据RDAT；所述预定时间可以根据实际情况选定，以使得RDAT的一个数据的中段与一个采样控制时钟信号的上升沿对应，以使得采样器能够准确的将串行输入数据RDAT转换为相应的并行数据。
如图3所示，假设一个所述原始串行输入数据DIN具有24个上升沿，则延迟锁相环24输出24个采样控制时钟信号；
在图3中，标号为CLK1的为第一采样控制时钟信号，标号为CLK4的为第四采样控制时钟信号，标号为CLK5的为第五采样控制时钟信号，标号为CLK8的为第八采样控制时钟信号，标号为CLK9的为第九采样控制时钟信号，标号为CLK12的为第十二采样控制时钟信号，标号为CLK13的为第十三采样控制时钟信号，标号为CLK16的为第十六采样控制时钟信号，标号为CLK17的为第十七采样控制时钟信号，标号为CLK20的为第二十采样控制时钟信号，标号为CLK21的为第二十一采样控制时钟信号，标号为CLK24的为第二十四采样控制时钟信号；
标号为D1的为RDAT携带的第一个数据，标号为D4的为RDAT携带的第四个数据，标号为D5的为RDAT携带的第五个数据，标号为D8的为RDAT携带的第八个数据，标号为D9的为RDAT携带的第九个数据，标号为D12的为RDAT携带的第十二个数据，标号为D13的为RDAT携带的第十三个数据，标号为D16的为RDAT携带的第十六个数据，标号为D17的为RDAT携带的第十七个数据，标号为D20的为RDAT携带的第二十个数据，标号为D21的为RDAT携带的第二十一个数据，标号为D24的为RDAT携带的第二十四个数据。
如图3所示，RDAT携带的D1的中段与CLK1的上升沿对应，RDAT携带的D4的中段与CLK4的上升沿对应，RDAT携带的D5的中段与CLK5的上升沿对应，RDAT携带的D8的中段与CLK8的上升沿对应，RDAT携带的D9的中段与CLK9的上升沿对应，RDAT携带的D12的中段与CLK12的上升 沿对应，RDAT携带的D13的中段与CLK13的上升沿对应，RDAT携带的D16的中段与CLK16的上升沿对应，RDAT携带的D17的中段与CLK17的上升沿对应，RDAT携带的D20的中段与CLK20的上升沿对应，RDAT携带的D21的中段与CLK21的上升沿对应，RDAT携带的D24的中段与CLK24的上升沿对应。
可选的，所述第一采样控制电路可以包括N个第一采样控制单元电路，第n个第一采样控制单元电路用于将所述串行输入数据转换为第n个第一串行数据。
在具体实施时，所述第一采样控制电路可以包括N个第一采样控制单元电路，每个第一采样控制单元电路输出一个所述第一串行数据。
根据一种具体实施方式，所述第n个第一采样控制单元电路包括第n个第一控制反相器和第n个第二控制反相器；
所述第n个第一控制反相器的输入端接入所述串行输入数据，所述第n个第一控制反相器的输出端与所述第n个第二控制反相器的输入端电连接；
所述第n个第二控制反相器的输出端用于输出所述第n个第一串行数据。
在本公开实施例中，所述第一采样控制单元电路可以包括两个控制反相器，但不以此为限。
根据另一种具体实施方式，所述第n个第一采样控制单元电路包括第n个控制与非门和第n个控制反相器；
所述第n个控制与非门的第一输入端接入所述串行输入数据，所述第n个控制与非门的第二输入端接入第n输入控制信号，所述第n个控制与非门的输出端与所述第n个控制反相器的输入端电连接；
所述第n个控制反相器的输出端用于输出所述第n个第一串行数据。
在具体实施时，所述第n个第一采样控制单元电路可以包括第n个控制与非门和第n个控制反相器，所述第n个控制与非门的第二输入端接入第n输入控制信号，当所述第n输入控制信号的电位为低电压时，无论所述串行输入数据为高电压还是低电压，所述第n个控制与非门都输出高电压，从而可以节省功耗，以及减小峰值电流和平均电流。
可选的，第n个第二采样控制单元中的第m个第二采样控制单元电路可 以包括采样与非门和采样反相器；
所述采样与非门的第一输入端接入所述第n个第一串行数据，所述采样与非门的第二输入端接入所述相应的采样控制信号，所述采样与非门的输出端与所述采样反相器的输入端电连接，所述采样反相器的输出端与所述采样电路电连接，所述采样反相器用于通过其输出端输出所述相应的第二串行数据至所述采样电路。
在具体实施时，所述采样与非门的第二输入端接入相应的采样控制信号，这样，当所述采样控制信号的电位为低电压时，所述采样与非门输出的都为高电压，所述采样反相器都输出低电压，从而可以节省功耗。
在具体实施时，所述采样电路可以包括多个D触发器；
所述D触发器的输入端接入所述第二串行数据，所述D触发器的控制端接入相应的采样控制时钟信号，所述D触发器的输出端用于输出相应的并行数据。
如图4所示，在根据示例实施例的如图1所示的采样器的基础上，N等于1，M等于3；
所述第一采样控制电路11用于将串行输入数据转换为第一串行数据；
所述第二采样控制电路包括一个第二采样控制单元；
所述第二采样控制单元包括第一个第二采样控制单元电路121、第二个第二采样控制单元电路122和第三个第二采样控制单元电路123；
所述第一个第二采样控制单元电路121用于在第一采样控制信号的控制下，将第一串行数据转换为第一个第二串行数据；
所述第二个第二采样控制单元电路122用于在第二采样控制信号的控制下，将第一串行数据转换为第二个第二串行数据；
所述第三个第二采样控制单元电路123用于在第三采样控制信号的控制下，将第一串行数据转换为第三个第二串行数据；
所述采样电路13分别与所述第一个第二采样控制单元电路121、所述第二个第二采样控制单元电路122和所述第三个第二采样控制单元电路123电连接，用于在采样控制时钟信号的控制下，将所述第一个第二串行数据、所述第 二个第二串行数据和所述第三个第二串行数据转换为相应的并行数据。
如图5所示，在根据示例实施例的图4所示的采样器的基础上，
所述第一采样控制电路11包括第一反相器F1和第二反相器F2；
所述第一个第二采样控制单元电路121包括第一与非门AF1和第三反相器F3；
所述第二个第二采样控制单元电路122包括第二与非门AF2和第四反相器F4；
所述第三个第二采样控制单元电路123包括第三与非门AF3和第五反相器F5；
F1的输入端接入串行输入数据RDAT，F1的输出端与F2的输入端电连接；
AF1的第一输入端与F2的输出端电连接；AF1的第二输入端接入第一使能时钟信号EN1，AF1的输出端与F3的输入端电连接，F3的输出端用于输出第一个第二串行数据RDAT1；
AF2的第一输入端与F2的输出端电连接，AF2的第二输入端接入第二使能时钟信号EN2，AF2的输出端与F4的输入端电连接，F4的输出端用于输出第二个第二串行数据RDAT2；
AF3的第一输入端与F2的输出端电连接，AF3的第二输入端接入第三使能时钟信号EN3，AF3的输出端与F5的输入端电连接，F5的输出端用于输出第三个第二串行数据RDAT3；
所述采样电路13分别与F3的输出端、F4的输出端和F5的输出端电连接，用于在采样控制时钟信号的控制下，将所述第一个第二串行数据、所述第二个第二串行数据和所述第三个第二串行数据转换为相应的并行数据。
在图5所示的实施例中，EN1、EN2和EN3为采样控制信号。
在图5和图7中，标号为C1的为第一负载电容，标号为C2的为第二负载电容，标号为C3的为第三负载电容。
如图6所示，本公开如图5所示的采样器在工作时，采样周期包括依次设置的第一采样时间段S1、第二采样时间段S2和第三采样时间段S3；
在第一采样时间段S1，EN1为高电压，EN2和EN3为低电压，所述第一个第二采样控制单元电路121工作，以通过F3的输出端输出第一个第二串行 数据RDAT1；
在第二采样时间段S2，EN2为高电压，EN1和EN3为低电压，所述第二个第二采样控制单元电路122工作，以通过F4的输出端输出第二个第二串行数据RDAT2；
在第三采样时间段S3，EN3为高电压，EN1和EN2为低电压，所述第三个第二采样控制单元电路123工作，以通过F5的输出端输出第三个第二串行数据RDAT3。
根据示例实施例的如图5所示的采样器在工作时，在第一采样时间段S1，由于EN2和EN3为低电压，因此AF2和AF3持续输出高电压，F4和F5持续输出低电压，可以节省功耗，并减少峰值电流和平均电流；
在第二采样时间段S2，由于EN1和EN3为低电压，因此AF1和AF3持续输出高电压，F3和F5持续输出低电压，可以节省功耗，并减少峰值电流和平均电流；
在第三采样时间段S3，由于EN1和EN2为低电压，因此AF1和AF2持续输出高电压，F3和F4持续输出低电压，可以节省功耗，并减少峰值电流和平均电流。
如图7所示，在根据示例实施例的图5所示的采样器的基础上，所述采样电路包括第一采样单元61、第二采样单元62和第三采样单元63；
所述第一采样单元61包括第一D触发器、第二D触发器、第三D触发器、第四D触发器、第五D触发器、第六D触发器、第七D触发器和第八D触发器；
所述第一D触发器的输入端接入RDAT1，所述第一D触发器的输出端与第一并行数据输出端电连接；所述第一D触发器的控制端接入第一采样控制时钟信号；
所述第二D触发器的输入端接入RDAT1，所述第二D触发器的输出端与第二并行数据输出端电连接；所述第二D触发器的控制端接入第二采样控制时钟信号；
所述第三D触发器的输入端接入RDAT1，所述第三D触发器的输出端与第三并行数据输出端电连接；所述第三D触发器的控制端接入第三采样控制 时钟信号；
所述第四D触发器的输入端接入RDAT1，所述第四D触发器的输出端与第四并行数据输出端电连接；所述第四D触发器的控制端接入第四采样控制时钟信号；
所述第五D触发器的输入端接入RDAT1，所述第五D触发器的输出端与第五并行数据输出端电连接；所述第五D触发器的控制端接入第五采样控制时钟信号；
所述第六D触发器的输入端接入RDAT1，所述第六D触发器的输出端与第六并行数据输出端电连接；所述第六D触发器的控制端接入第六采样控制时钟信号；
所述第七D触发器的输入端接入RDAT1，所述第七D触发器的输出端与第七并行数据输出端电连接；所述第七D触发器的控制端接入第七采样控制时钟信号；
所述第八D触发器的输入端接入RDAT1，所述第八D触发器的输出端与第八并行数据输出端电连接；所述第八D触发器的控制端接入第八采样控制时钟信号；
所述第二采样单元62包括第九D触发器、第十D触发器、第十一D触发器、第十二D触发器、第十三D触发器、第十四D触发器、第十五D触发器和第十六D触发器；
所述第九D触发器的输入端接入RDAT2，所述第九D触发器的输出端与第九并行数据输出端电连接；所述第九D触发器的控制端接入第九采样控制时钟信号；
所述第十D触发器的输入端接入RDAT2，所述第十D触发器的输出端与第十并行数据输出端电连接；所述第十D触发器的控制端接入第十采样控制时钟信号；
所述第十一D触发器的输入端接入RDAT2，所述第十一D触发器的输出端与第十一并行数据输出端电连接；所述第十一D触发器的控制端接入第十一采样控制时钟信号；
所述第十二D触发器的输入端接入RDAT2，所述第十二D触发器的输出 端与第十二并行数据输出端电连接；所述第十二D触发器的控制端接入第十二采样控制时钟信号；
所述第十三D触发器的输入端接入RDAT2，所述第十三D触发器的输出端与第十三并行数据输出端电连接；所述第十三D触发器的控制端接入第十三采样控制时钟信号；
所述第十四D触发器的输入端接入RDAT2，所述第十四D触发器的输出端与第十四并行数据输出端电连接；所述第十四D触发器的控制端接入第十四采样控制时钟信号；
所述第十五D触发器的输入端接入RDAT2，所述第十五D触发器的输出端与第十五并行数据输出端电连接；所述第十五D触发器的控制端接入第十五采样控制时钟信号；
所述第十六D触发器的输入端接入RDAT2，所述第十六D触发器的输出端与第十六并行数据输出端电连接；所述第十六D触发器的控制端接入第十六采样控制时钟信号；
所述第三采样单元63包括第十七D触发器、第十八D触发器、第十九D触发器、第二十D触发器、第二十一D触发器、第二十二D触发器、第二十三D触发器和第二十四D触发器；
所述第十七D触发器的输入端接入RDAT3，所述第十七D触发器的输出端与第十七并行数据输出端电连接；所述第十七D触发器的控制端接入第十七采样控制时钟信号；
所述第十八D触发器的输入端接入RDAT3，所述第十八D触发器的输出端与第十八并行数据输出端电连接；所述第十八D触发器的控制端接入第十八采样控制时钟信号；
所述第十九D触发器的输入端接入RDAT3，所述第十九D触发器的输出端与第十九并行数据输出端电连接；所述第十九D触发器的控制端接入第十九采样控制时钟信号；
所述第二十D触发器的输入端接入RDAT3，所述第二十D触发器的输出端与第二十并行数据输出端电连接；所述第二十D触发器的控制端接入第二十采样控制时钟信号；
所述第二十一D触发器的输入端接入RDAT3，所述第二十一D触发器的输出端与第二十一并行数据输出端电连接；所述第二十一D触发器的控制端接入第二十一采样控制时钟信号；
所述第二十二D触发器的输入端接入RDAT3，所述第二十二D触发器的输出端与第二十二并行数据输出端电连接；所述第二十二D触发器的控制端接入第二十二采样控制时钟信号；
所述第二十三D触发器的输入端接入RDAT3，所述第二十三D触发器的输出端与第二十三并行数据输出端电连接；所述第二十三触发器的控制端接入第二十三采样控制时钟信号；
所述第二十四D触发器的输入端接入RDAT3，所述第二十四D触发器的输出端与第二十四并行数据输出端电连接；所述第二十四D触发器的控制端接入第二十四采样控制时钟信号。
在本公开实施例中，各D触发器在工作时，当该D触发器的控制端接入的时钟信号处于上升沿时，将该D触发器的输入端的信号传送至该D触发器的输出端，但不以此为限。
在图7中，标号为DOUT[1:8]的为第一并行数据输出端集合，所述第一并行数据输出端集合包括：第一并行数据输出端、第二并行数据输出端、第三并行数据输出端、第四并行数据输出端、第五并行数据输出端、第六并行数据输出端、第七并行数据输出端和第八并行数据输出端；
标号为CLK[1:8]的为第一时钟信号集合，所述第一时钟信号集合包括：第一采样控制时钟信号、第二采样控制时钟信号、第三采样控制时钟信号、第四采样控制时钟信号、第五采样控制时钟信号、第六采样控制时钟信号、第七采样控制时钟信号、第八采样控制时钟信号；
标号为DOUT[9:16]的为第二并行数据输出端集合，所述第二并行数据输出端集合包括：第九并行数据输出端、第十并行数据输出端、第十一并行数据输出端、第十二并行数据输出端、第十三并行数据输出端、第十四并行数据输出端、第十五并行数据输出端和第十六并行数据输出端；
标号为CLK[9:16]的为第二时钟信号集合，所述第二时钟信号集合包括：第九采样控制时钟信号、第十采样控制时钟信号、第十一采样控制时钟信号、 第十二采样控制时钟信号、第十三采样控制时钟信号、第十四采样控制时钟信号、第十五采样控制时钟信号、第十六采样控制时钟信号；
标号为DOUT[17:24]的为第三并行数据输出端集合，所述第三并行数据输出端集合包括：第十七并行数据输出端、第十八并行数据输出端、第十九并行数据输出端、第二十并行数据输出端、第二十一并行数据输出端、第二十二并行数据输出端、第二十三并行数据输出端和第二十四并行数据输出端；
标号为CLK[17:24]的为第三时钟信号集合，所述第三时钟信号集合包括：第十七采样控制时钟信号、第十八采样控制时钟信号、第十九采样控制时钟信号、第二十采样控制时钟信号、第二十一采样控制时钟信号、第二十二采样控制时钟信号、第二十三采样控制时钟信号、第二十四采样控制时钟信号。
图8是图7所示的采样器的工作时序图。
如图8所示，标号为CLK1的为第一采样控制时钟信号，标号为CLK4的为第四采样控制时钟信号，标号为CLK5的为第五采样控制时钟信号，标号为CLK8的为第八采样控制时钟信号，标号为CLK9的为第九采样控制时钟信号，标号为CLK12的为第十二采样控制时钟信号，标号为CLK13的为第十三采样控制时钟信号，标号为CLK16的为第十六采样控制时钟信号，标号为CLK17的为第十七采样控制时钟信号，标号为CLK20的为第二十采样控制时钟信号，标号为CLK21的为第二十一采样控制时钟信号，标号为CLK24的为第二十四采样控制时钟信号；
标号为D1的为RDAT携带的第一个数据，标号为D4的为RDAT携带的第四个数据，标号为D5的为RDAT携带的第五个数据，标号为D8的为RDAT携带的第八个数据，标号为D9的为RDAT携带的第九个数据，标号为D12的为RDAT携带的第十二个数据，标号为D13的为RDAT携带的第十三个数据，标号为D16的为RDAT携带的第十六个数据，标号为D17的为RDAT携带的第十七个数据，标号为D20的为RDAT携带的第二十个数据，标号为D21的为RDAT携带的第二十一个数据，标号为D24的为RDAT携带的第二十四个数据；
并如图8所示，当EN1为高电压时，CLK1、CLK4、CLK5和CLK8依次达到上升沿；第一并行数据输出端、第二并行数据输出端、第三并行数据输出 端、第四并行数据输出端、第五并行数据输出端、第六并行数据输出端、第七并行数据输出端和第八并行数据输出端依次输出相应的并行数据；
当EN2为高电压时，CLK9、CLK12、CLK13和CLK16依次达到上升沿，第九并行数据输出端、第十并行数据输出端、第十一并行数据输出端、第十二并行数据输出端、第十三并行数据输出端、第十四并行数据输出端、第十五并行数据输出端、第十六并行数据输出端依次输出相应的并行数据；
当EN3为高电压时，CLK17、CLK20、CLK21和CLK24依次达到上升沿，第十七并行数据输出端、第十八并行数据输出端、第十九并行数据输出端、第二十并行数据输出端、第二十一并行数据输出端、第二十二并行数据输出端、第二十三并行数据输出端、第二十四并行数据输出端依次输出相应的并行数据。
在图8中，标号为S1的为第一采样时间段，标号S2的为第二采样时间段，标号为S3的为第三采样时间段。
如图9所示，在根据示例实施例的如图1所示的采样器的基础上，N等于3，M等于2；
所述第一采样控制电路包括第一个第一采样控制单元电路81、第二个第一采样控制单元电路82和第三个第一采样控制单元电路83；
所述第二采样控制电路包括第一个第二采样控制单元、第二个第二采样控制单元和第三个第二采样控制单元；
所述第一个第二采样控制单元包括第一个第二采样控制单元电路121和第二个第二采样控制单元电路122；
所述第二个第二采样控制单元包括第三个第二采样控制单元电路123和第四个第二采样控制单元电路124；
所述第三个第二采样控制单元包括第五个第二采样控制单元电路125和第六个第二采样控制单元电路126；
所述第一个第二采样控制单元电路121用于在第一采样控制信号的控制下，将第一个第一串行数据转换为第一个第二串行数据；
所述第二个第二采样控制单元电路122用于在第二采样控制信号的控制下，将第一个第一串行数据转换为第二个第二串行数据；
所述第三个第二采样控制单元电路123用于在第三采样控制信号的控制 下，将第二个第一串行数据转换为第三个第二串行数据；
所述第四个第二采样控制单元电路124用于在第四采样控制信号的控制下，将第二个第一串行数据转换为第四个第二串行数据；
所述第五个第二采样控制单元电路125用于在第五采样控制信号的控制下，将第三个第一串行数据转换为第五个第二串行数据；
所述第六个第二采样控制单元电路126用于在第六采样控制信号的控制下，将第三个第一串行数据转换为第六个第二串行数据；
所述采样电路13分别与所述第一个第二采样控制单元电路121、所述第二个第二采样控制单元电路122、所述第三个第二采样控制单元电路123、所述第四个第二采样控制单元电路124、所述第五个第二采样控制单元电路125和所述第六个第二采样控制单元电路126电连接，用于在采样控制时钟信号的控制下，将所述第一个第二串行数据、所述第二个第二串行数据、所述第三个第二串行数据、所述第四个第二串行数据、所述第五个第二串行数据、所述第六个第二串行数据转换为相应的并行数据。
如图10所示，在图9所示的采样器的实施例的基础上，
所述第一个第一采样控制单元电路81包括第一与非门AF1和第一反相器F1；
所述第二个第一采样控制单元电路82包括第二与非门AF2和第二反相器F2；
所述第三个第一采样控制单元电路83包括第三与非门AF3和第三反相器F3；
所述第一个第二采样控制单元电路121包括第四与非门AF4和第四反相器F4；
所述第二个第二采样控制单元电路122包括第五与非门AF5和第五反相器F4；
所述第三个第二采样控制单元电路123包括第六与非门AF6和第六反相器F6；
所述第四个第二采样控制单元电路124包括第七与非门AF7和第七反相器F7；
所述第五个第二采样控制单元电路125包括第八与非门AF8和第八反相器F8；
所述第六个第二采样控制单元电路126包括第九与非门AF9和第九反相器F9；
AF1的第一输入端接入RDAT，AF1的第二输入端接入第一使能时钟信号EN1，AF1的输出端与F1的输入端电连接；
AF2的第一输入端接入RDAT，AF2的第二输入端接入第二使能时钟信号EN2，AF2的输出端与F2的输入端电连接；
AF3的第一输入端接入RDAT，AF3的第二输入端接入第三使能时钟信号EN3，AF3的输出端与F3的输入端电连接；
AF4的第一输入端与F1的输出端电连接，AF4的第二输入端接入第四使能时钟信号EN1.1，AF4的输出端与F4的输入端电连接，F4的输出端用于输出第一个第二串行数据RDAT1；
AF5的第一输入端与F1的输出端电连接，AF5的第二输入端接入第五使能时钟信号EN1.2，AF5的输出端与F5的输入端电连接，F5的输出端用于输出第二个第二串行数据RDAT2；
AF6的第一输入端与F2的输出端电连接，AF4的第二输入端接入第六使能时钟信号EN2.1，AF6的输出端与F6的输入端电连接，F6的输出端用于输出第三个第二串行数据RDAT3；
AF7的第一输入端与F2的输出端电连接，AF7的第二输入端接入第七使能时钟信号EN2.2，AF7的输出端与F7的输入端电连接，F7的输出端用于输出第四个第二串行数据RDAT4；
AF8的第一输入端与F3的输出端电连接，AF8的第二输入端接入第八使能时钟信号EN3.1，AF8的输出端与F8的输入端电连接，F8的输出端用于输出第五个第二串行数据RDAT5；
AF9的第一输入端与F3的输出端电连接，AF9的第二输入端接入第九使能时钟信号EN3.2，AF9的输出端与F9的输入端电连接，F9的输出端用于输出第六个第二串行数据RDAT4。
在图10所示的实施例中，EN1，EN2和EN3为输入控制信号，EN1.1、 EN1.2、EN2.1、EN2.2、EN3.1和EN3.2为采样控制信号。
在图10和图12中，标号为C1的为第一负载电容，标号为C2的为第二负载电容，标号为C3的为第三负载电容，标号为C4的为第四负载电容，标号为C5的为第五负载电容，标号为C6的为第六负载电容。
如图11所示，根据示例实施例的如图10所示的采样器在工作时，采样周期包括依次设置的第一采样时间段S1、第二采样时间段S2、第三采样时间段S3、第四采样时间段S4、第五采样时间段S5和第六采样时间段S6；
在第一采样时间段S1，EN1为高电压，EN2和EN3为低电压，EN1.1为高电压，EN1.2、EN2.1、EN2.2、EN3.1和EN3.2都为低电压，第一个第一采样控制单元电路81和所述第一个第二采样控制单元电路121工作，以通过F4的输出端输出第一个第二串行数据RDAT1；
在第二采样时间段S2，EN1为高电压，EN2和EN3为低电压，EN1.2为高电压，EN1.1、EN2.1、EN2.2、EN3.1和EN3.2都为低电压，第一个第一采样控制单元电路81和所述第二个第二采样控制单元电路122工作，以通过F5的输出端输出第二个第二串行数据RDAT2；
在第三采样时间段S3，EN2为高电压，EN1和EN3为低电压，EN2.1为高电压，EN1.1、EN1.2、EN2.2、EN3.1和EN3.2都为低电压，第二个第一采样控制单元电路82和所述第三个第二采样控制单元电路123工作，以通过F6的输出端输出第三个第二串行数据RDAT3；
在第四采样时间段S4，EN2为高电压，EN1和EN3为低电压，EN2.2为高电压，EN1.1、EN1.2、EN2.1、EN3.1和EN3.2都为低电压，第二个第一采样控制单元电路81和所述第四个第二采样控制单元电路124工作，以通过F7的输出端输出第四个第二串行数据RDAT4；
在第五采样时间段S5，EN3为高电压，EN1和EN2为低电压，EN3.1为高电压，EN1.1、EN1.2、EN2.1、EN2.2和EN3.2都为低电压，第三个第一采样控制单元电路83和所述第五个第二采样控制单元电路125工作，以通过F8的输出端输出第五个第二串行数据RDAT5；
在第六采样时间段S6，EN3为高电压，EN1和EN2为低电压，EN3.2为高电压，EN1.1、EN2.1、EN2.1、EN2.2和EN3.1都为低电压，第三个第一采 样控制单元电路83和所述第六个第二采样控制单元电路126工作，以通过F9的输出端输出第六个第二串行数据RDAT6。
如图12所示，在根据示例实施例的图10所示的采样器的基础上，所述采样电路包括第一采样单元61、第二采样单元62、第三采样单元63、第四采样单元64、第五采样单元65和第六采样单元66；
所述第一采样单元61包括第一D触发器、第二D触发器、第三D触发器和第四D触发器；所述第一采样单元62包括第五D触发器、第六D触发器、第七D触发器和第八D触发器；
所述第一D触发器的输入端接入RDAT1，所述第一D触发器的输出端与第一并行数据输出端电连接；所述第一D触发器的控制端接入第一采样控制时钟信号；
所述第二D触发器的输入端接入RDAT1，所述第二D触发器的输出端与第二并行数据输出端电连接；所述第二D触发器的控制端接入第二采样控制时钟信号；
所述第三D触发器的输入端接入RDAT1，所述第三D触发器的输出端与第三并行数据输出端电连接；所述第三D触发器的控制端接入第三采样控制时钟信号；
所述第四D触发器的输入端接入RDAT1，所述第四D触发器的输出端与第四并行数据输出端电连接；所述第四D触发器的控制端接入第四采样控制时钟信号；
所述第五D触发器的输入端接入RDAT2，所述第五D触发器的输出端与第五并行数据输出端电连接；所述第五D触发器的控制端接入第五采样控制时钟信号；
所述第六D触发器的输入端接入RDAT2，所述第六D触发器的输出端与第六并行数据输出端电连接；所述第六D触发器的控制端接入第六采样控制时钟信号；
所述第七D触发器的输入端接入RDAT2，所述第七D触发器的输出端与第七并行数据输出端电连接；所述第七D触发器的控制端接入第七采样控制时钟信号；
所述第八D触发器的输入端接入RDAT2，所述第八D触发器的输出端与第八并行数据输出端电连接；所述第八D触发器的控制端接入第八采样控制时钟信号；
所述第三采样单元63包括第九D触发器、第十D触发器、第十一D触发器和第十二D触发器，所述第四采样单元64包括第十三D触发器、第十四D触发器、第十五D触发器和第十六D触发器；
所述第九D触发器的输入端接入RDAT3，所述第九D触发器的输出端与第九并行数据输出端电连接；所述第九D触发器的控制端接入第九采样控制时钟信号；
所述第十D触发器的输入端接入RDAT3，所述第十D触发器的输出端与第十并行数据输出端电连接；所述第十D触发器的控制端接入第十采样控制时钟信号；
所述第十一D触发器的输入端接入RDAT3，所述第十一D触发器的输出端与第十一并行数据输出端电连接；所述第十一D触发器的控制端接入第十一采样控制时钟信号；
所述第十二D触发器的输入端接入RDAT3，所述第十二D触发器的输出端与第十二并行数据输出端电连接；所述第十二D触发器的控制端接入第十二采样控制时钟信号；
所述第十三D触发器的输入端接入RDAT4，所述第十三D触发器的输出端与第十三并行数据输出端电连接；所述第十三D触发器的控制端接入第十三采样控制时钟信号；
所述第十四D触发器的输入端接入RDAT4，所述第十四D触发器的输出端与第十四并行数据输出端电连接；所述第十四D触发器的控制端接入第十四采样控制时钟信号；
所述第十五D触发器的输入端接入RDAT4，所述第十五D触发器的输出端与第十五并行数据输出端电连接；所述第十五D触发器的控制端接入第十五采样控制时钟信号；
所述第十六D触发器的输入端接入RDAT4，所述第十六D触发器的输出端与第十六并行数据输出端电连接；所述第十六D触发器的控制端接入第十 六采样控制时钟信号；
所述第五采样单元65包括第十七D触发器、第十八D触发器、第十九D触发器和第二十D触发器；所述第五采样单元66包括第二十一D触发器、第二十二D触发器、第二十三D触发器和第二十四D触发器；
所述第十七D触发器的输入端接入RDAT5，所述第十七D触发器的输出端与第十七并行数据输出端电连接；所述第十七D触发器的控制端接入第十七采样控制时钟信号；
所述第十八D触发器的输入端接入RDAT5，所述第十八D触发器的输出端与第十八并行数据输出端电连接；所述第十八D触发器的控制端接入第十八采样控制时钟信号；
所述第十九D触发器的输入端接入RDAT5，所述第十九D触发器的输出端与第十九并行数据输出端电连接；所述第十九D触发器的控制端接入第十九采样控制时钟信号；
所述第二十D触发器的输入端接入RDAT5，所述第二十D触发器的输出端与第二十并行数据输出端电连接；所述第二十D触发器的控制端接入第二十采样控制时钟信号；
所述第二十一D触发器的输入端接入RDAT6，所述第二十一D触发器的输出端与第二十一并行数据输出端电连接；所述第二十一D触发器的控制端接入第二十一采样控制时钟信号；
所述第二十二D触发器的输入端接入RDAT6，所述第二十二D触发器的输出端与第二十二并行数据输出端电连接；所述第二十二D触发器的控制端接入第二十二采样控制时钟信号；
所述第二十三D触发器的输入端接入RDAT6，所述第二十三D触发器的输出端与第二十三并行数据输出端电连接；所述第二十三D触发器的控制端接入第二十三采样控制时钟信号；
所述第二十四D触发器的输入端接入RDAT6，所述第二十四D触发器的输出端与第二十四并行数据输出端电连接；所述第二十四D触发器的控制端接入第二十四采样控制时钟信号。
在图12中，标号为DOUT[1:4]的为第一并行数据输出端集合，所述第一 并行数据输出端集合包括：第一并行数据输出端、第二并行数据输出端、第三并行数据输出端和第四并行数据输出端；
标号为DOUT[5:8]的为第二并行数据输出端集合，所述第二并行数据输出端集合包括：第五并行数据输出端、第六并行数据输出端、第七并行数据输出端和第八并行数据输出端；
标号为CLK[1:4]的为第一时钟信号集合，所述第一时钟信号集合包括：第一采样控制时钟信号、第二采样控制时钟信号、第三采样控制时钟信号和第四采样控制时钟信号；
标号为CLK[5:6]的为第二时钟信号集合，所述第二时钟信号集合包括：第五采样控制时钟信号、第六采样控制时钟信号、第七采样控制时钟信号、第八采样控制时钟信号；
标号为DOUT[9:12]的为第三并行数据输出端集合，所述第三并行数据输出端集合包括：第九并行数据输出端、第十并行数据输出端、第十一并行数据输出端和第十二并行数据输出端；
标号为DOUT[13:16]的为第四并行数据输出端集合，所述第四并行数据输出端集合包括：第十三并行数据输出端、第十四并行数据输出端、第十五并行数据输出端和第十六并行数据输出端；
标号为CLK[9:12]的为第三时钟信号集合，所述第三时钟信号集合包括：第九采样控制时钟信号、第十采样控制时钟信号、第十一采样控制时钟信号和第十二采样控制时钟信号；
标号为CLK[13:16]的为第四时钟信号集合，所述第四时钟信号集合包括：第十三采样控制时钟信号、第十四采样控制时钟信号、第十五采样控制时钟信号、第十六采样控制时钟信号；
标号为DOUT[17:20]的为第五并行数据输出端集合，所述第五并行数据输出端集合包括：第十七并行数据输出端、第十八并行数据输出端、第十九并行数据输出端和第二十并行数据输出端；
标号为DOUT[21:24]的为第六并行数据输出端集合，所述第六并行数据输出端集合包括：第二十一并行数据输出端、第二十二并行数据输出端、第二十三并行数据输出端和第二十四并行数据输出端；
标号为CLK[17:20]的为第五时钟信号集合，所述第五时钟信号集合包括：第十七采样控制时钟信号、第十八采样控制时钟信号、第十九采样控制时钟信号和第二十采样控制时钟信号；
标号为CLK[21:24]的为第六时钟信号集合，所述第六时钟信号集合包括：第二十一采样控制时钟信号、第二十二采样控制时钟信号、第二十三采样控制时钟信号、第二十四采样控制时钟信号。
图13是图12所示的采样器的工作时序图。
如图13所示，标号为CLK1的为第一采样控制时钟信号，标号为CLK4的为第四采样控制时钟信号，标号为CLK5的为第五采样控制时钟信号，标号为CLK8的为第八采样控制时钟信号，标号为CLK9的为第九采样控制时钟信号，标号为CLK12的为第十二采样控制时钟信号，标号为CLK13的为第十三采样控制时钟信号，标号为CLK16的为第十六采样控制时钟信号，标号为CLK17的为第十七采样控制时钟信号，标号为CLK20的为第二十采样控制时钟信号，标号为CLK21的为第二十一采样控制时钟信号，标号为CLK24的为第二十四采样控制时钟信号；
标号为D1的为RDAT携带的第一个数据，标号为D4的为RDAT携带的第四个数据，标号为D5的为RDAT携带的第五个数据，标号为D8的为RDAT携带的第八个数据，标号为D9的为RDAT携带的第九个数据，标号为D12的为RDAT携带的第十二个数据，标号为D13的为RDAT携带的第十三个数据，标号为D16的为RDAT携带的第十六个数据，标号为D17的为RDAT携带的第十七个数据，标号为D20的为RDAT携带的第二十个数据，标号为D21的为RDAT携带的第二十一个数据，标号为D24的为RDAT携带的第二十四个数据；
并如图13所示，当EN1和EN1.1为高电压时，CLK1和CLK4依次达到上升沿；当EN1和EN1.2为高电压时，CLK5和CLK8依次达到上升沿；第一并行数据输出端、第二并行数据输出端、第三并行数据输出端、第四并行数据输出端、第五并行数据输出端、第六并行数据输出端、第七并行数据输出端和第八并行数据输出端依次输出相应的并行数据；
当EN2和EN2.1为高电压时，CLK9和CLK12依次达到上升沿；当EN2 和EN2.2为高电压时，CLK13和CLK16依次达到上升沿，第九并行数据输出端、第十并行数据输出端、第十一并行数据输出端、第十二并行数据输出端、第十三并行数据输出端、第十四并行数据输出端、第十五并行数据输出端、第十六并行数据输出端依次输出相应的并行数据；
当EN3和EN3.1为高电压时，CLK17和CLK20依次达到上升沿；当EN3和EN3.2为高电压时，CLK21和CLK24依次达到上升沿，第十七并行数据输出端、第十八并行数据输出端、第十九并行数据输出端、第二十并行数据输出端、第二十一并行数据输出端、第二十二并行数据输出端、第二十三并行数据输出端、第二十四并行数据输出端依次输出相应的并行数据。
本公开实施例所述的显示驱动芯片包括上述的采样器。
在本公开实施例中，所述的显示驱动芯片还可以包括时钟信号生成器、延迟电路和延迟锁相环，其中，
所述时钟信号生成器用于提取原始串行输入数据中的时钟边沿信息，以产生相应的输入时钟信号；
所述延迟电路用于控制所述原始串行输入数据延时预定时间，以得到串行输入数据，并将所述串行输入数据提供至所述采样器；
所述延迟锁相环将所述输入时钟信号转换为多个采样控制时钟信号，并将所述采样控制时钟信号提供至所述采样器。
本公开实施例所述的显示装置包括上述的显示驱动芯片。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (9)

  1. 一种采样器，包括：
    第一采样控制电路，用于将串行输入数据转换为N个第一串行数据；
    第二采样控制电路，包括N个第二采样控制单元，每个所述第二采样控制单元包括M个第二采样控制单元电路，N和M为正整数，N大于1，和/或，M大于1，第n个第二采样控制单元中的第m个第二采样控制单元电路用于在相应的采样控制信号的控制下，将第n个第一串行数据转换为相应的第二串行数据，n为小于或等于N的正整数；
    采样电路，与所述第二采样控制单元电路电连接，用于在采样控制时钟信号的控制下，将所述第二串行数据转换为相应的并行数据。
  2. 如权利要求1所述的采样器，其中，所述第一采样控制电路包括N个第一采样控制单元电路，第n个第一采样控制单元电路用于将所述串行输入数据转换为第n个第一串行数据。
  3. 如权利要求2所述的采样器，其中，所述第n个第一采样控制单元电路包括第n个第一控制反相器和第n个第二控制反相器；
    所述第n个第一控制反相器的输入端接入所述串行输入数据，所述第n个第一控制反相器的输出端与所述第n个第二控制反相器的输入端电连接；
    所述第n个第二控制反相器的输出端用于输出所述第n个第一串行数据。
  4. 如权利要求2所述的采样器，其中，所述第n个第一采样控制单元电路包括第n个控制与非门和第n个控制反相器；
    所述第n个控制与非门的第一输入端接入所述串行输入数据，所述第n个控制与非门的第二输入端接入第n输入控制信号，所述第n个控制与非门的输出端与所述第n个控制反相器的输入端电连接；
    所述第n个控制反相器的输出端用于输出所述第n个第一串行数据。
  5. 如权利要求1至4中任一权利要求所述的采样器，其中，第n个第二采样控制单元中的第m个第二采样控制单元电路包括采样与非门和采样反相器；
    所述采样与非门的第一输入端接入所述第n个第一串行数据，所述采样与 非门的第二输入端接入所述相应的采样控制信号，所述采样与非门的输出端与所述采样反相器的输入端电连接，所述采样反相器的输出端与所述采样电路电连接，所述采样反相器用于通过其输出端输出所述相应的第二串行数据至所述采样电路。
  6. 如权利要求1至4中任一权利要求所述的采样器，其中，所述采样电路包括多个D触发器；
    所述D触发器的输入端接入所述第二串行数据，所述D触发器的控制端接入相应的采样控制时钟信号，所述D触发器的输出端用于输出相应的并行数据。
  7. 一种显示驱动芯片，包括如权利要求1至6中任一权利要求所述的采样器。
  8. 如权利要求7所述的显示驱动芯片，还包括：
    时钟信号生成器，用于提取原始串行输入数据中的时钟边沿信息，以产生相应的输入时钟信号；
    延迟电路，用于控制所述原始串行输入数据延时预定时间，以得到串行输入数据，并将所述串行输入数据提供至所述采样器；
    延迟锁相环，用于将所述输入时钟信号转换为多个采样控制时钟信号，并将所述采样控制时钟信号提供至所述采样器。
  9. 一种显示装置，包括如权利要求7或8所述的显示驱动芯片。
PCT/CN2021/094645 2020-12-22 2021-05-19 采样器、显示驱动芯片和显示装置 WO2022134440A1 (zh)

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