WO2022134149A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

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Publication number
WO2022134149A1
WO2022134149A1 PCT/CN2020/140693 CN2020140693W WO2022134149A1 WO 2022134149 A1 WO2022134149 A1 WO 2022134149A1 CN 2020140693 W CN2020140693 W CN 2020140693W WO 2022134149 A1 WO2022134149 A1 WO 2022134149A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
node
source
drain
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PCT/CN2020/140693
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English (en)
French (fr)
Inventor
王选芸
戴超
吴剑龙
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US17/280,881 priority Critical patent/US20230419893A1/en
Publication of WO2022134149A1 publication Critical patent/WO2022134149A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel driving circuit and a display panel.
  • PMOS metal oxide semiconductor field effect transistors
  • LTPS low temperature polysilicon
  • Achilles' heel which is the large leakage current, especially when flickering at low frequencies
  • metal oxide transistors (oxide) can just make up for the lack of low temperature polysilicon (LTPS), combining the two fully Taking advantage of their respective advantages, they are perfectly adapted to the high standard demands of future displays.
  • the current display panel pixel circuit generally adopts the 7T1C structure.
  • the effect of this circuit in compensating the threshold voltage Vth is poor, and the threshold voltage Vth may be negative. It is difficult for the data voltage to be stored in the storage capacitor stably, and the data signal will Gradually lost, causing the screen flickering phenomenon on the macro level, and the product quality is affected.
  • the purpose of the present invention is to provide a pixel driving circuit and a display panel to solve the technical problems of screen flicker caused by large leakage current of the display panel, and serious loss of data signal caused by poor threshold voltage Vth compensation effect.
  • the present invention provides a pixel driving circuit, comprising a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor Cst, a second capacitor Cboost and an organic light emitting diode D1;
  • the second transistor is a low temperature polysilicon transistor; the gate of the first transistor T1 is connected to the first node Q, the source is connected to the second node P, and the drain is connected to the third node B; the second transistor T1
  • the gate of the transistor T2 is connected to the first scan signal Scan(n), the source of the transistor T2 is connected to the data signal Data, and the drain of the transistor T2 is connected to the second node P;
  • the gate of the third transistor T3 is connected to enable signal, its source is connected to the first power supply signal, and its drain is connected to the second node; the gate of the fourth transistor is connected to the enable signal, its source is connected to the third node, and its drain is connected One end of the first capacitor Cst is
  • the first transistor T1, the third transistor T3, and the fourth transistor T4 are low temperature polysilicon transistors.
  • the pixel driving circuit further includes a fifth transistor T5; the gate of the fifth transistor T5 is connected to the first scan signal Scan(n), and the first electrode of the fifth transistor T5 is connected to the first node Q point,
  • the second electrode is connected to the third node B;
  • the fifth transistor is an oxide semiconductor transistor or a low temperature polysilicon transistor; when the fifth transistor T5 is a p-type transistor, the first The electrode is the source, the second electrode of the fifth transistor T5 is the drain; when the fifth transistor T5 is an n-type transistor, the first electrode of the fifth transistor T5 is the drain, and the fifth transistor T5 is the drain.
  • the second electrode of the transistor T5 is the source.
  • the pixel driving circuit further includes an eighth transistor T8 and a fifth transistor T5, the gate of the eighth transistor T8 is connected to the first scan signal Scan(n), and the source of the eighth transistor T8 is connected to the first scan signal Scan(n) node Q point; the eighth transistor T8 is an oxide semiconductor transistor; the gate of the fifth transistor T5 is connected to the first scan signal Scan(n), and its first electrode is connected to the first node Q point , its second electrode is connected to the third node B; the fifth transistor T5 is an oxide semiconductor transistor or a low temperature polysilicon transistor; when the fifth transistor T5 is a p-type transistor, the fifth transistor T5 The first electrode is the source, the second electrode of the fifth transistor T5 is the drain; when the fifth transistor T5 is an n-type transistor, the first electrode of the fifth transistor T5 is the drain, the The second electrode of the fifth transistor T5 is the source.
  • the pixel driving circuit further includes a sixth transistor T6; the gate of the sixth transistor T6 is connected to the second scan signal Scan(n-1), and the first electrode of the sixth transistor T6 is connected to the first electrode of the fifth transistor T5 an electrode; the sixth transistor T6 is an oxide semiconductor transistor or a low temperature polysilicon transistor.
  • the second electrode of the sixth transistor T6 is connected to a reference voltage Vint, or is connected to the anode of the organic light emitting diode D1; when the sixth transistor T6 is a p-type transistor, the sixth transistor T6 The first electrode of the sixth transistor T6 is the source electrode, and the second electrode of the sixth transistor T6 is the drain electrode; when the sixth transistor T6 is an n-type transistor, the first electrode of the sixth transistor T6 is the drain electrode, so The second electrode of the sixth transistor T6 is the source.
  • the pixel driving circuit further includes a seventh transistor T7; the gate of the seventh transistor T7 is connected to the first scan signal Scan(n), the source of the seventh transistor T7 is connected to a reference voltage Vint, and the drain of the seventh transistor T7
  • the anode of the organic light emitting diode D1 is connected; the seventh transistor T7 is an oxide semiconductor transistor or a low temperature polysilicon transistor.
  • the pixel driving circuit further includes a seventh transistor T7; the gate of the seventh transistor T7 is connected to the enable signal EM, the source of the seventh transistor T7 is connected to a reference voltage Vint, and the drain of the seventh transistor T7 is connected to the organic light emitting diode
  • the anode of D1; the seventh transistor T7 is an oxide semiconductor transistor or a low temperature polysilicon transistor.
  • the pixel driving circuit further includes a seventh transistor T7; wherein the gate of the seventh transistor T7 is connected to the second scan signal Scan(n-1), and the source of the seventh transistor T7 is connected to the third node Point B, the drain of which is connected to the anode of the organic light emitting diode D1; the seventh transistor T7 is an oxide semiconductor transistor or a low temperature polysilicon transistor.
  • the present invention also provides a display panel including the aforementioned pixel driving circuit.
  • the technical effect of the present invention is to provide a pixel driving circuit and a display panel, which can suppress the potential change of the first node Q point within a frame time by utilizing the low leakage characteristics of the metal oxide transistor; and connect the first node Q point and the A second capacitor Cboost is connected between the gate of the second transistor T2.
  • the function of the capacitor is to adjust the potential of the first node Q point, thereby changing the variation range of the data signal Data under the gray scale of 0-255, which can improve the leakage current of the display panel. Larger causes the phenomenon of picture flicker, and the second capacitor Cboost also has the effect of compensating the threshold voltage Vth, which avoids the picture flicker caused by the serious loss of the data signal, and is beneficial to improve the brightness uniformity.
  • 1 is a schematic structural diagram of a conventional pixel driving circuit
  • FIG. 2 is a schematic diagram of the overall structure of the pixel driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of the first pixel driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of the second pixel driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of the third pixel driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of the fourth pixel driving circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of the fifth pixel driving circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of the sixth type of the pixel driving circuit according to an embodiment of the present invention.
  • FIG. 9 is a waveform diagram used by the pixel driving circuit shown in FIG. 3 , FIG. 4 , and FIG. 5 according to an embodiment of the present invention.
  • FIG. 10 is a waveform diagram used by the pixel driving circuit shown in FIG. 6 according to an embodiment of the present invention.
  • FIG. 11 is a waveform diagram used by the pixel driving circuit shown in FIG. 7 according to an embodiment of the present invention.
  • FIG. 12 is a waveform diagram used by the pixel driving circuit shown in FIG. 8 according to an embodiment of the present invention.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be a mechanical connection, an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be a mechanical connection, an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • an embodiment of the present invention provides a pixel driving circuit
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor Cst, a Two capacitors Cboost and an organic light-emitting diode D1;
  • the second transistor T2 is a low-temperature polysilicon transistor;
  • the gate of the first transistor T1 is connected to the first node Q, and its source is connected to the second node P, Its drain is connected to the third node B;
  • the gate of the second transistor T2 is connected to the first scan signal Scan(n), its source is connected to the data signal Data, and its drain is connected to the second node P ;
  • the gate of the third transistor T3 is connected to the enable signal EM, the source of the third transistor T3 is connected to the first power supply signal ELVDD, and the drain of the third transistor T3 is connected to the second node P;
  • the pixel driving circuit also includes a first Four transistor
  • the source and drain of all transistors can be either source or drain.
  • the first transistor T1, the third transistor T3, and the fourth transistor T4 are low temperature polysilicon transistors.
  • the potential variation of the first node Q point is suppressed within a frame time by utilizing the low leakage characteristics of the metal oxide transistor; and a second capacitor Cboost is connected between the first node Q point and the gate of the second transistor T2 , the function of this capacitor is to adjust the potential of the first node Q point, so as to change the variation range of the data signal Data under the gray scale of 0-255, which can improve the phenomenon of screen flicker caused by the large leakage current of the display panel.
  • the second capacitor Cboost also It has the effect of compensating for the threshold voltage Vth, which avoids the flickering of the picture caused by the serious loss of the data signal, and is beneficial to improve the brightness uniformity.
  • the pixel driving circuit can set the third transistor T3 and the fourth transistor T4 at the same time, or set the third transistor T3 or the fourth transistor T4 independently.
  • the purpose of disposing the third transistor T3 and/or the fourth transistor T4 is to realize the control of turning on and off the organic light emitting diode D1 through an enable signal EM.
  • FIG. 3 to FIG. 8 The specific circuit structures of the above three structures are shown in FIG. 3 to FIG. 8 .
  • the third transistor T3 and the fourth transistor T4 are set at the same time as an example for illustration, wherein the third transistor T3 or Either of the fourth transistors T4 can be removed.
  • FIGS. 3 to 8 the manners of Scan(n), PScan(n), and NScan(n) all represent the first scan signal Scan(n), where PScan(n) represents that the connected transistor is a P-type film Transistor, NScan(n) represents that the connected transistor is an N-type thin film transistor.
  • FIG. 8 all represent the second scan signal Scan(n-1), where PScan(n-1) -1) represents that the connected transistor is a P-type thin film transistor, and NScan(n-1) represents that the connected transistor is an N-type thin film transistor.
  • PScan(n-1) -1) represents that the connected transistor is a P-type thin film transistor
  • NScan(n-1) represents that the connected transistor is an N-type thin film transistor.
  • the low-temperature polysilicon transistors are indicated by the circled symbols in the gate portion
  • the oxide semiconductor transistors are indicated by the symbols without the circles in the gate portion.
  • the pixel driving circuit further includes a fifth transistor T5; the gate of the fifth transistor T5 is connected to the first scan signal Scan(n), and the first electrode of the fifth transistor T5 is connected to the first scan signal Scan(n) The first node Q point, the second electrode of which is connected to the third node B point.
  • the fifth transistor T5 is an oxide semiconductor transistor or a low temperature polysilicon transistor; when the fifth transistor T5 is a p-type transistor, the first electrode of the fifth transistor T5 is the source, and the fifth transistor T5 The second electrode is the drain; when the fifth transistor T5 is an n-type transistor, the first electrode of the fifth transistor T5 is the drain, and the second electrode of the fifth transistor T5 is the source.
  • the pixel driving circuit further includes a sixth transistor T6; the gate of the sixth transistor T6 is connected to the second scan signal Scan(n-1), and the source of the sixth transistor T6 is connected to the fifth transistor T5 first electrode.
  • the sixth transistor T6 is an oxide semiconductor transistor or a low temperature polysilicon transistor.
  • the drain of the sixth transistor T6 is connected to a reference voltage Vint, or is connected to the anode of the organic light emitting diode D1.
  • the sixth transistor T6 is a p-type transistor
  • the first electrode of the sixth transistor T6 is the source
  • the second electrode of the sixth transistor T6 is the drain
  • the sixth transistor T6 is n
  • the first electrode of the sixth transistor T6 is the drain electrode
  • the second electrode of the sixth transistor T6 is the source electrode.
  • the pixel driving circuit further includes a seventh transistor T7 ; wherein the gate of the seventh transistor T7 is connected to the The source of the first scan signal Scan(n) or the enable signal EM is connected to a reference voltage Vint, and the drain is connected to the anode of the organic light emitting diode D1.
  • the seventh transistor T7 is an oxide semiconductor transistor or a low temperature polysilicon transistor.
  • the source electrode of the seventh transistor T7 may be connected to the drain electrode of the sixth transistor T6 or may be separated from each other.
  • the source of the seventh transistor T7 is connected to the drain of the sixth transistor T6 .
  • the source of the seventh transistor T7 and the drain of the sixth transistor T6 are separated from each other.
  • the reference voltage Vint input by the two may be the same or different.
  • the gate of the seventh transistor T7 is connected to the second scan signal Scan(n-1), and the source of the seventh transistor T7 is connected to the third node Point B, the drain of which is connected to the anode of the organic light emitting diode D1.
  • the pixel driving circuit further includes an eighth transistor T8 and a fifth transistor T5 ; the gate of the eighth transistor T8 is connected to the first scan
  • the source of the signal Scan(n) is connected to the first node Q point.
  • the eighth transistor T8 is an oxide semiconductor transistor.
  • the gate of the fifth transistor T5 is connected to the first scan signal Scan(n), the first electrode of the fifth transistor T5 is connected to the first node Q, and the second electrode of the fifth transistor T5 is connected to the third node B.
  • the fifth transistor T5 is an oxide semiconductor transistor or a low temperature polysilicon transistor; when the fifth transistor T5 is a p-type transistor, the first electrode of the fifth transistor T5 is the source, and the fifth transistor T5 The second electrode is the drain; when the fifth transistor T5 is an n-type transistor, the first electrode of the fifth transistor T5 is the drain, and the second electrode of the fifth transistor T5 is the source.
  • the specific embodiment of this application includes 6 kinds of circuit connection relationships, but it is not limited to this.
  • the core content of this application is the connection relationship of the second capacitor Cboost.
  • a second capacitor Cboost is connected between the gates.
  • the function of the capacitor is to adjust the potential of the Q point of the first node, thereby changing the variation range of the data signal Data under the gray scale of 0-255, which can improve the screen flicker caused by the large leakage current of the display panel.
  • the second capacitor Cboost also has the effect of compensating the threshold voltage Vth, which avoids the flickering of the picture caused by the serious loss of the data signal, and is beneficial to improve the brightness uniformity.
  • the pixel driving circuits shown in FIG. 3, FIG. 4, and FIG. 5 are all driven by the waveform diagram shown in FIG. 9, including the first stage, the second stage and the third stage of the cycle in sequence, wherein the first stage It is the original state stage, the second stage is the initialization state stage, and the third stage is the program execution state stage.
  • the scan signals PScan(n) and PScan(n-1) are at high potential, the scan signal NScan(n) is at low potential, and the enable signal EM is at low potential,
  • the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on, and the third transistor T3, the fourth transistor T4, the The eighth transistor T8 is turned off; in the second stage, the scan signals PScan(n) and NScan(n) are at a high potential, the enable signal EM is at a high potential, and the scan signal PScan(n-1) is at a low potential.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned on, and the The sixth transistor T6 is turned off; in the third stage, the scan signals PScan(n-1) and NScan(n) are at a high potential, the enable signal EM is at a high potential, and the scan signal PScan(n) is at a low potential.
  • the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, the second transistor T2, the The fifth transistor T5 is turned off.
  • the scan signals PScan(n) and PScan(n-1) are at high potential, the scan signal NScan(n) is at low potential, and the enable signal EM is at low potential,
  • the second transistor T2, the sixth transistor T6, the seventh transistor T7 are turned on, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the The eighth transistor T8 is turned off; in the second stage, the scan signals PScan(n) and NScan(n) are at a high potential, the enable signal EM is at a high potential, and the scan signal PScan(n-1) is at a low potential.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned on, the sixth transistor T6, the The seventh transistor T7 is turned off; in the third stage, the scan signals PScan(n-1) and NScan(n) are at a high potential, the enable signal EM is at a high potential, and the scan signal PScan(n) is at a low potential.
  • the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, and the The second transistor T2 is turned off.
  • the scan signals PScan(n) and PScan(n-1) are at high potential, the scan signal NScan(n) is at low potential, and the enable signal EM is at low potential
  • the second transistor T2, the fifth transistor T5, the sixth transistor T6 are turned on, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the The eighth transistor T8 is turned off; in the second stage, the scan signals PScan(n) and NScan(n) are at a high potential, the enable signal EM is at a high potential, and the scan signal PScan(n-1) is at a low potential.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned on, and the The sixth transistor T6 is turned off; in the third stage, the scan signals PScan(n-1) and NScan(n) are at a high potential, the enable signal EM is at a high potential, and the scan signal PScan(n) is at a low potential.
  • the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, the second transistor T2, the The fifth transistor T5 is turned off.
  • the pixel driving circuit shown in FIG. 6 is driven by the waveform shown in FIG. 10, including the first stage, the second stage and the third stage of the cycle, wherein the first stage is the original state stage, and the first stage is the original state stage.
  • the second stage is the initialization state stage
  • the third stage is the program execution state stage.
  • the scan signals PScan(n) and NScan(n-1) are at high potential, the scan signal NScan(n) is at low potential, and the enable signal EM is at low potential,
  • the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned on, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off;
  • the scan signal PScan(n) is at a high level
  • the enable signal EM is at a high level
  • the scan signals NScan(n-1) and NScan(n) are at a low level.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fifth transistor T5 and the sixth transistor T6 are turned off;
  • the scan signals NScan(n-1) and NScan(n) are at a high level
  • the enable signal EM is at a high level
  • the scan signal PScan(n) is at a low level.
  • the first transistor T1, the The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2 is turned off.
  • the pixel driving circuit shown in FIG. 7 is driven by the waveform shown in FIG. 11, including the first stage, the second stage and the third stage of the cycle, wherein the first stage is the original state stage, and the first stage is the original state stage.
  • the second stage is the initialization state stage
  • the third stage is the program execution state stage.
  • the scan signals PScan(n) and PScan(n-1) are at high potential, the scan signal NScan(n) is at low potential, and the enable signal EM is at low potential,
  • the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off;
  • the scan signal PScan(n) is at a high level
  • the enable signal EM is at a high level
  • the scan signals PScan(n-1) and NScan(n) are at a low level.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fifth transistor T5 and the sixth transistor T6 are turned off;
  • the scan signals PScan(n-1) and NScan(n) are at high potential
  • the enable signal EM is at high potential
  • the scan signal PScan(n) is at low potential.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and the second transistor T2 and the seventh transistor T7 are turned off.
  • the pixel driving circuit shown in FIG. 8 is driven by the waveform shown in FIG. 12, including the first stage, the second stage and the third stage of the cycle, wherein the first stage is the original state stage, and the first stage is the original state stage.
  • the second stage is the initialization state stage
  • the third stage is the program execution state stage.
  • the scan signal PScan(n) is at a high potential
  • the scan signals NScan(n) and NScan(n-1) are at a low potential
  • the enable signal EM is at a low potential
  • the second transistor T2 is turned on
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off;
  • the scan signal NScan(n-1) is at a high level
  • the enable signal EM is at a high level
  • the scan signals PScan(n) and NScan(n) are at a low level.
  • the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2 and the fifth transistor T5 are turned off;
  • the scan signal NScan(n) is at a high level
  • the enable signal EM is at a high level
  • the scan signals NScan(n-1) and PScan(n) are at a low level.
  • the first transistor T1, the The third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2 and the sixth transistor T6 are turned off.
  • the present invention also provides a display panel including the pixel driving circuit described above.
  • the display panel in the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • the working principle of the display panel provided in this embodiment is consistent with the working principle of the foregoing pixel driving circuit embodiments.
  • the technical effect of the present invention is to provide a pixel driving circuit and a display panel, which can suppress the potential change of the first node Q point within a frame time by utilizing the low leakage characteristics of the metal oxide transistor; and connect the first node Q point and the A second capacitor Cboost is connected between the gate of the second transistor T2.
  • the function of the capacitor is to adjust the potential of the first node Q point, thereby changing the variation range of the data signal Data under the gray scale of 0-255, which can improve the leakage current of the display panel. Larger causes the phenomenon of picture flicker, and the second capacitor Cboost also has the effect of compensating the threshold voltage Vth, which avoids the picture flicker caused by the serious loss of the data signal, and is beneficial to improve the brightness uniformity.

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Abstract

本发明提供一种像素驱动电路及显示面板。像素驱动电路包括第一晶体管、第二晶体管、第一电容、第二电容及有机发光二极管；第二晶体管为低温多晶硅晶体管。本发明能够改善显示面板的漏电流较大造成画面闪烁的现象，利于提升亮度均匀性。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路及显示面板。
 背景技术
随着多媒体的发展，显示装置变得越来越重要。相应地，对各种类型的显示装置的要求越来越高，尤其是智能手机领域，超高频驱动显示，低功耗驱动显示，以及低频驱动显示都是现阶段和未来的发展需求方向。
P型沟道金属氧化物半导体场效应晶体管（PMOS）广泛用作显示装置的晶体管，手机领域广泛应用低温多晶硅（LTPS）。然而，低温多晶硅（LTPS）存在一个致命弱点就是漏电流较大，尤其是在低频显示时闪烁严重；而金属氧化物晶体管（oxide）正好可以弥补低温多晶硅（LTPS）的不足，将二者结合充分利用其各自的优点，完美的适应未来显示的高标准需求。
同时，如图1所示，目前显示面板像素电路普遍采用7T1C结构，该电路补偿阈值电压Vth的效果较差，会出现阈值电压Vth偏负，数据电压难以稳定存储于存储电容中，数据信号会逐渐丢失，宏观上造成画面闪烁现象，产品品质受到影响。
 技术问题
本发明的目的在于，提供一种像素驱动电路及显示面板以解决显示面板的漏电流较大造成画面闪烁，以及阈值电压Vth补偿效果差导致数据信号损失严重造成画面闪烁的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种像素驱动电路，包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电容Cst、第二电容Cboost及有机发光二极管D1；所述第二晶体管为低温多晶硅晶体管；所述第一晶体管T1的栅极连接第一节点Q点，其源极连接第二节点P点，其漏极连接第三节点B点；所述第二晶体管T2的栅极接入第一扫描信号Scan(n)，其源极接入数据信号Data，其漏极连接所述第二节点P点；所述第三晶体管T3的栅极接入使能信号，其源极接入第一电源信号，其漏极连接所述第二节点；所述第四晶体管的栅极接入所述使能信号，其源极连接所述第三节点，其漏极连接所述有机发光二极管的阳极；所述第一电容Cst的一端接入所述第一电源信号ELVDD，其另一端连接所述第一节点Q点；所述第二电容Cboost的一端连接所述第二晶体管T2的栅极，其另一端连接所述第一节点Q点；所述有机发光二极管D1的阳极连接所述第三节点B点,所述有机发光二极管D1的阴极接入第二电源信号ELVSS。
进一步地，所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4为低温多晶硅晶体管。
进一步地，所述像素驱动电路还包括第五晶体管T5；所述第五晶体管T5的栅极接入所述第一扫描信号Scan(n)，其第一电极连接所述第一节点Q点，其第二电极连接所述第三节点B点；所述第五晶体管为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管T5为p型晶体管时，所述第五晶体管T5的第一电极为源极，所述第五晶体管T5的第二电极为漏极；当所述第五晶体管T5为n型晶体管时，所述第五晶体管T5的第一电极为漏极，所述第五晶体管T5的第二电极为源极。
进一步地，所述像素驱动电路还包括第八晶体管T8以及第五晶体管T5，所述第八晶体管T8的栅极接入所述第一扫描信号Scan(n)，其源极连接所述第一节点Q点；所述第八晶体管T8为氧化物半导体晶体管；所述第五晶体管T5的栅极接入所述第一扫描信号Scan(n)，其第一电极连接所述第一节点Q点，其第二电极连接所述第三节点B点；所述第五晶体管T5为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管T5为p型晶体管时，所述第五晶体管T5的第一电极为源极，所述第五晶体管T5的第二电极为漏极；当所述第五晶体管T5为n型晶体管时，所述第五晶体管T5的第一电极为漏极，所述第五晶体管T5的第二电极为源极。
进一步地，所述像素驱动电路还包括第六晶体管T6；所述第六晶体管T6的栅极接入第二扫描信号Scan(n-1)，其第一电极连接所述第五晶体管T5的第一电极；所述第六晶体管T6为氧化物半导体晶体管或低温多晶硅晶体管。
进一步地，所述第六晶体管T6的第二电极接入一参考电压Vint，或者连接所述有机发光二极管D1的阳极；当所述第六晶体管T6为p型晶体管时，所述第六晶体管T6的第一电极为源极，所述第六晶体管T6的第二电极为漏极；当所述第六晶体管T6为n型晶体管时，所述第六晶体管T6的第一电极为漏极，所述第六晶体管T6的第二电极为源极。
进一步地，所述像素驱动电路还包括第七晶体管T7；所述第七晶体管T7的栅极接入所述第一扫描信号Scan(n)，其源极接入一参考电压Vint，其漏极连接所述有机发光二极管D1的阳极；所述第七晶体管T7为氧化物半导体晶体管或低温多晶硅晶体管。
进一步地，所述像素驱动电路还包括第七晶体管T7；所述第七晶体管T7的栅极接入使能信号EM，其源极接入一参考电压Vint，其漏极连接所述有机发光二极管D1的阳极；所述第七晶体管T7为氧化物半导体晶体管或低温多晶硅晶体管。
进一步地，所述像素驱动电路还包括第七晶体管T7；其中，所述第七晶体管T7的栅极接入所述第二扫描信号Scan(n-1)，其源极连接所述第三节点B点，其漏极连接所述有机发光二极管D1的阳极；所述第七晶体管T7为氧化物半导体晶体管或低温多晶硅晶体管。
本发明还提供一种显示面板，包括前文所述的像素驱动电路。
 有益效果
本发明的技术效果在于，提供一种像素驱动电路及显示面板，通过利用金属氧化物晶体管的低漏电特性在一帧时间内抑制第一节点Q点电位变化；并在连接第一节点Q点和第二晶体管T2的栅极间连接一个第二电容Cboost，该电容的作用是调节第一节点Q点电位，从而改变0-255灰阶下数据信号Data的变化范围，能够改善显示面板的漏电流较大造成画面闪烁的现象，另外第二电容Cboost也具有对阈值电压Vth补偿的效果，避免了数据信号损失严重造成画面闪烁，利于提升亮度均匀性。
 附图说明
图1为现有的一种像素驱动电路的结构示意图；
图2为本发明实施例的所述像素驱动电路的整体结构示意图；
图3为本发明实施例的第一种所述像素驱动电路的结构示意图；
图4为本发明实施例的第二种所述像素驱动电路的结构示意图；
图5为本发明实施例的第三种所述像素驱动电路的结构示意图；
图6为本发明实施例的第四种所述像素驱动电路的结构示意图；
图7为本发明实施例的第五种所述像素驱动电路的结构示意图；
图8为本发明实施例的第六种所述像素驱动电路的结构示意图；
图9为本发明实施例的图3、图4、图5所示的像素驱动电路所采用的波形图；
图10为本发明实施例的图6所示的像素驱动电路所采用的波形图；
图11为本发明实施例的图7所示的像素驱动电路所采用的波形图；
图12为本发明实施例的图8所示的像素驱动电路所采用的波形图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
如图2所示，本发明实施例中提供一种像素驱动电路，所述像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电容Cst、第二电容Cboost及有机发光二极管D1；具体地讲，所述第二晶体管T2为低温多晶硅晶体管；所述第一晶体管T1的栅极连接第一节点Q点，其源极连接第二节点P点，其漏极连接第三节点B点；所述第二晶体管T2的栅极接入第一扫描信号Scan(n)，其源极接入数据信号Data，其漏极连接所述第二节点P点；所述第三晶体管T3的栅极接入使能信号EM，其源极接入所述第一电源信号ELVDD，其漏极连接所述第二节点P点；所述像素驱动电路还包括第四晶体管T4，设于所述第一晶体管T1与所述有机发光二极管D1之间；所述第四晶体管T4的栅极接入所述使能信号EM，其源极连接所述第三节点B点，其漏极连接所述有机发光二极管D1的阳极；所述第一电容Cst的一端接入第一电源信号ELVDD，其另一端连接所述第一节点Q点；所述第二电容Cboost的一端连接所述第二晶体管T2的栅极，其另一端连接所述第一节点Q点；所述有机发光二极管D1的阳极连接所述第三节点B点,所述有机发光二极管D1的阴极接入第二电源信号ELVSS。
本实施例中，所有晶体管的源极及漏极可为源极或漏极。所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4为低温多晶硅晶体管。
本实施例通过利用金属氧化物晶体管的低漏电特性在一帧时间内抑制第一节点Q点电位变化；并在连接第一节点Q点和第二晶体管T2的栅极间连接一个第二电容Cboost，该电容的作用是调节第一节点Q点电位，从而改变0-255灰阶下数据信号Data的变化范围，能够改善显示面板的漏电流较大造成画面闪烁的现象，另外第二电容Cboost也具有对阈值电压Vth补偿的效果，避免了数据信号损失严重造成画面闪烁，利于提升亮度均匀性。
在本实施例中，所述像素驱动电路可同时设置所述第三晶体管T3和所述第四晶体管T4，也可单独设置所述第三晶体管T3或所述第四晶体管T4。设置所述第三晶体管T3和/或所述第四晶体管T4的目的是通过一使能信号EM实现对电路开启关闭所述有机发光二极管D1的控制。
以上三种结构的具体电路结构如图3至图8所示，在图中均以同时设置所述第三晶体管T3和所述第四晶体管T4为例说明，其中的所述第三晶体管T3或所述第四晶体管T4之一均可去除。
值得注意的是，为了简洁，在图3至图8中均省略了第一节点Q点、第二节点P点、第三节点B点及有机发光二极管D1的标注，其实际位置与图2所示结构相同。而且在图3至图8中使用Scan(n)、PScan(n)、NScan(n)的方式均表示第一扫描信号Scan(n)，其中PScan(n)代表其连接的晶体管为P型薄膜晶体管，NScan(n)代表其连接的晶体管为N型薄膜晶体管。同理，在图3至图8中使用Scan(n-1)、PScan(n-1)、NScan(n-1)的方式均表示第二扫描信号Scan(n-1)，其中PScan(n-1)代表其连接的晶体管为P型薄膜晶体管，NScan(n-1)代表其连接的晶体管为N型薄膜晶体管。并且在图2至图8中使用栅极部带圆圈的符号表示低温多晶硅晶体管，使用栅极部不带圆圈的符号表示氧化物半导体晶体管。
如图3至图8所示，所述像素驱动电路还包括第五晶体管T5；所述第五晶体管T5的栅极接入所述第一扫描信号Scan(n)，其第一电极连接所述第一节点Q点，其第二电极连接所述第三节点B点。所述第五晶体管T5为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管T5为p型晶体管时，所述第五晶体管T5的第一电极为源极，所述第五晶体管T5的第二电极为漏极；当所述第五晶体管T5为n型晶体管时，所述第五晶体管T5的第一电极为漏极，所述第五晶体管T5的第二电极为源极。
本实施例中，所述像素驱动电路还包括第六晶体管T6；所述第六晶体管T6的栅极接入第二扫描信号Scan(n-1)，其源极连接所述第五晶体管T5的第一电极。所述第六晶体管T6为氧化物半导体晶体管或低温多晶硅晶体管。
本实施例中，所述第六晶体管T6的漏极接入一参考电压Vint，或者连接所述有机发光二极管D1的阳极。当所述第六晶体管T6为p型晶体管时，所述第六晶体管T6的第一电极为源极，所述第六晶体管T6的第二电极为漏极；当所述第六晶体管T6为n型晶体管时，所述第六晶体管T6的第一电极为漏极，所述第六晶体管T6的第二电极为源极。
如图3、图5、图6、图7、图8所示，本实施例中，所述像素驱动电路还包括第七晶体管T7；其中，所述第七晶体管T7的栅极接入所述第一扫描信号Scan(n)或使能信号EM，其源极接入一参考电压Vint，其漏极连接所述有机发光二极管D1的阳极。所述第七晶体管T7为氧化物半导体晶体管或低温多晶硅晶体管。
如图3、图5、图6、图7、图8所示，所述第七晶体管T7的源极可与所述第六晶体管T6的漏极连接也可相互分离设置。在图3、图5、图6、图8中所述第七晶体管T7的源极与所述第六晶体管T6的漏极连接。在图7中所述第七晶体管T7的源极与所述第六晶体管T6的漏极相互分离设置。
如图7所示，在所述第七晶体管T7的源极与所述第六晶体管T6的漏极相互分离设置时两者输入的参考电压Vint可相同也可不同。
或者在另一种像素驱动电路结构中，如图4所示，所述第七晶体管T7的栅极接入所述第二扫描信号Scan(n-1)，其源极连接所述第三节点B点，其漏极连接所述有机发光二极管D1的阳极。
如图3、图4、图5所示，本实施例中，所述像素驱动电路还包括第八晶体管T8以及第五晶体管T5；所述第八晶体管T8的栅极接入所述第一扫描信号Scan(n)，其源极连接所述第一节点Q点。所述第八晶体管T8为氧化物半导体晶体管。所述第五晶体管T5的栅极接入所述第一扫描信号Scan(n)，其第一电极连接所述第一节点Q点，其第二电极连接所述第三节点B点。所述第五晶体管T5为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管T5为p型晶体管时，所述第五晶体管T5的第一电极为源极，所述第五晶体管T5的第二电极为漏极；当所述第五晶体管T5为n型晶体管时，所述第五晶体管T5的第一电极为漏极，所述第五晶体管T5的第二电极为源极。
另外，本申请的具体实施例中包含了6种电路连接关系，但是不限于此，本申请的核心内容是第二电容Cboost的连接关系，通过在连接第一节点Q点和第二晶体管T2的栅极间连接一个第二电容Cboost，该电容的作用是调节第一节点Q点电位，从而改变0-255灰阶下数据信号Data的变化范围，能够改善显示面板的漏电流较大造成画面闪烁的现象，另外第二电容Cboost也具有对阈值电压Vth补偿的效果，避免了数据信号损失严重造成画面闪烁，利于提升亮度均匀性。
在使用时，图3、图4、图5所示的像素驱动电路均采用图9所示的波形图进行驱动，包括依次循环的第一阶段、第二阶段及第三阶段，其中第一阶段为原始状态阶段，第二阶段为初始化状态阶段，第三阶段为程序执行状态阶段。
图3所示的像素驱动电路中，在第一阶段，扫描信号PScan(n)、PScan(n-1)为高电位，扫描信号NScan(n)为低电位，使能信号EM为低电位，此时相对于的所述第二晶体管T2、所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7打开，所述第三晶体管T3、所述第四晶体管T4、所述第八晶体管T8关闭；在第二阶段，扫描信号PScan(n)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n-1)为低电位，此时所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第七晶体管T7、所述第八晶体管T8打开，所述第六晶体管T6关闭；在第三阶段，扫描信号PScan(n-1)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n)为低电位，此时所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4、所述第六晶体管T6、所述第七晶体管T7、所述第八晶体管T8打开，所述第二晶体管T2、所述第五晶体管T5关闭。
图4所示的像素驱动电路中，在第一阶段，扫描信号PScan(n)、PScan(n-1)为高电位，扫描信号NScan(n)为低电位，使能信号EM为低电位，此时相对于的所述第二晶体管T2、所述第六晶体管T6、所述第七晶体管T7打开，所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第八晶体管T8关闭；在第二阶段，扫描信号PScan(n)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n-1)为低电位，此时所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第八晶体管T8打开，所述第六晶体管T6、所述第七晶体管T7关闭；在第三阶段，扫描信号PScan(n-1)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n)为低电位，此时所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7、所述第八晶体管T8打开，所述第二晶体管T2关闭。
图5所示的像素驱动电路中，在第一阶段，扫描信号PScan(n)、PScan(n-1)为高电位，扫描信号NScan(n)为低电位，使能信号EM为低电位，此时相对于的所述第二晶体管T2、所述第五晶体管T5、所述第六晶体管T6打开，所述第三晶体管T3、所述第四晶体管T4、所述第七晶体管T7、所述第八晶体管T8关闭；在第二阶段，扫描信号PScan(n)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n-1)为低电位，此时所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第七晶体管T7、所述第八晶体管T8打开，所述第六晶体管T6关闭；在第三阶段，扫描信号PScan(n-1)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n)为低电位，此时所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4、所述第六晶体管T6、所述第七晶体管T7、所述第八晶体管T8打开，所述第二晶体管T2、所述第五晶体管T5关闭。
在使用时，图6所示的像素驱动电路均采用图10所示的波形图进行驱动，包括依次循环的第一阶段、第二阶段及第三阶段，其中第一阶段为原始状态阶段，第二阶段为初始化状态阶段，第三阶段为程序执行状态阶段。
图6所示的像素驱动电路中，在第一阶段，扫描信号PScan(n)、NScan(n-1)为高电位，扫描信号NScan(n)为低电位，使能信号EM为低电位，此时相对于的所述第二晶体管T2、所述第五晶体管T5、所述第六晶体管T6打开，所述第三晶体管T3、所述第四晶体管T4、所述第七晶体管T7关闭；在第二阶段，扫描信号PScan(n)为高电位，使能信号EM为高电位，扫描信号NScan(n-1)、NScan(n)为低电位，此时所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第七晶体管T7、所述第八晶体管T8打开，所述第五晶体管T5、所述第六晶体管T6关闭；在第三阶段，扫描信号NScan(n-1)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n)为低电位，此时所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7、所述第八晶体管T8打开，所述第二晶体管T2关闭。
在使用时，图7所示的像素驱动电路均采用图11所示的波形图进行驱动，包括依次循环的第一阶段、第二阶段及第三阶段，其中第一阶段为原始状态阶段，第二阶段为初始化状态阶段，第三阶段为程序执行状态阶段。
图7所示的像素驱动电路中，在第一阶段，扫描信号PScan(n)、PScan(n-1)为高电位，扫描信号NScan(n)为低电位，使能信号EM为低电位，此时相对于的所述第二晶体管T2、所述第六晶体管T6、所述第七晶体管T7打开，所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5关闭；在第二阶段，扫描信号PScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n-1)、NScan(n)为低电位，此时所述第一晶体管T1、所述第二晶体管T2、所述第三晶体管T3、所述第四晶体管T4、所述第七晶体管T7、所述第八晶体管T8打开，所述第五晶体管T5、所述第六晶体管T6关闭；在第三阶段，扫描信号PScan(n-1)、NScan(n)为高电位，使能信号EM为高电位，扫描信号PScan(n)为低电位，此时所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第六晶体管T6、所述第八晶体管T8打开，所述第二晶体管T2、所述第七晶体管T7关闭。
在使用时，图8所示的像素驱动电路均采用图12所示的波形图进行驱动，包括依次循环的第一阶段、第二阶段及第三阶段，其中第一阶段为原始状态阶段，第二阶段为初始化状态阶段，第三阶段为程序执行状态阶段。
图8所示的像素驱动电路中，在第一阶段，扫描信号PScan(n)为高电位，扫描信号NScan(n)、NScan(n-1)为低电位，使能信号EM为低电位，此时相对于的所述第二晶体管T2打开，所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第六晶体管T6、所述第七晶体管T7关闭；在第二阶段，扫描信号NScan(n-1)为高电位，使能信号EM为高电位，扫描信号PScan(n)、NScan(n)为低电位，此时所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4、所述第六晶体管T6、所述第七晶体管T7、所述第八晶体管T8打开，所述第二晶体管T2、所述第五晶体管T5关闭；在第三阶段，扫描信号NScan(n)为高电位，使能信号EM为高电位，扫描信号NScan(n-1)、PScan(n)为低电位，此时所述第一晶体管T1、所述第三晶体管T3、所述第四晶体管T4、所述第五晶体管T5、所述第七晶体管T7、所述第八晶体管T8打开，所述第二晶体管T2、所述第六晶体管T6关闭。
基于同样的发明构思，本发明还提供一种显示面板，包括前文所述的像素驱动电路。本公开实施例中的显示面板可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例提供的显示面板的工作原理，与前述像素驱动电路的实施例工作原理一致，具体结构关系及工作原理参见前述像素驱动电路实施例，此处不再赘述。
本发明的技术效果在于，提供一种像素驱动电路及显示面板，通过利用金属氧化物晶体管的低漏电特性在一帧时间内抑制第一节点Q点电位变化；并在连接第一节点Q点和第二晶体管T2的栅极间连接一个第二电容Cboost，该电容的作用是调节第一节点Q点电位，从而改变0-255灰阶下数据信号Data的变化范围，能够改善显示面板的漏电流较大造成画面闪烁的现象，另外第二电容Cboost也具有对阈值电压Vth补偿的效果，避免了数据信号损失严重造成画面闪烁，利于提升亮度均匀性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的进行了一种像素驱动电路及显示面板的详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种像素驱动电路，其中，包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第二电容及有机发光二极管；所述第二晶体管为低温多晶硅晶体管；
    所述第一晶体管的栅极连接第一节点，其源极连接第二节点，其漏极连接第三节点；
    所述第二晶体管的栅极接入第一扫描信号，其源极接入数据信号，其漏极连接所述第二节点；
    所述第三晶体管的栅极接入使能信号，其源极接入第一电源信号，其漏极连接所述第二节点；
    所述第四晶体管的栅极接入所述使能信号，其源极连接所述第三节点，其漏极连接所述有机发光二极管的阳极；
    所述第一电容的一端接入所述第一电源信号，其另一端连接所述第一节点；
    所述第二电容的一端连接所述第二晶体管的栅极，其另一端连接所述第一节点；
    所述有机发光二极管的阳极连接所述第三节点，所述有机发光二极管的阴极接入第二电源信号。
  2. 如权利要求1所述的像素驱动电路，其中，所述第一晶体管、所述第三晶体管、所述第四晶体管为低温多晶硅晶体管。
  3. 如权利要求1所述的像素驱动电路，其中，还包括第五晶体管；所述第五晶体管的栅极接入所述第一扫描信号，其第一电极连接所述第一节点，其第二电极连接所述第三节点；所述第五晶体管为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管为p型晶体管时，所述第一电极为源极，所述第二电极为漏极；当所述第五晶体管为n型晶体管时，所述第一电极为漏极，所述第二电极为源极。
  4. 如权利要求3所述的像素驱动电路，其中，还包括第六晶体管；所述第六晶体管的栅极接入第二扫描信号，其第一电极连接所述第五晶体管的第一电极；所述第六晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  5. 如权利要求1所述的像素驱动电路，其中，还包括第八晶体管以及第五晶体管；
    所述第八晶体管的栅极接入所述第一扫描信号，其源极连接所述第一节点；所述第八晶体管为氧化物半导体晶体管；
    所述第五晶体管的栅极接入所述第一扫描信号，其第一电极连接所述第一节点，其第二电极连接所述第三节点；所述第五晶体管为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管为p型晶体管时，所述第五晶体管的第一电极为源极，所述第五晶体管的第二电极为漏极；当所述第五晶体管为n型晶体管时，所述第五晶体管的第一电极为漏极，所述第五晶体管的第二电极为源极。
  6. 如权利要求4所述的像素驱动电路，其中，还包括第六晶体管；所述第六晶体管的栅极接入第二扫描信号，其第一电极连接所述第五晶体管的第一电极；所述第六晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  7. 如权利要求6所述的像素驱动电路，其中，所述第六晶体管的第二电极接入一参考电压，或者连接所述有机发光二极管的阳极；当所述第六晶体管为p型晶体管时，所述第六晶体管的第一电极为源极，所述第六晶体管的第二电极为漏极；当所述第六晶体管为n型晶体管时，所述第六晶体管的第一电极为漏极，所述第六晶体管的第二电极为源极。
  8. 如权利要求6所述的像素驱动电路，其中，还包括第七晶体管；所述第七晶体管的栅极接入所述第一扫描信号，其源极接入一参考电压，其漏极连接所述有机发光二极管的阳极；所述第七晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  9. 如权利要求6所述的像素驱动电路，其中，还包括第七晶体管；所述第七晶体管的栅极接入使能信号，其源极接入一参考电压，其漏极连接所述有机发光二极管的阳极；所述第七晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  10. 如权利要求6所述的像素驱动电路，其中，还包括第七晶体管；所述第七晶体管的栅极接入所述第二扫描信号，其源极连接所述第三节点，其漏极连接所述有机发光二极管的阳极；所述第七晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  11. 一种显示面板，其中，包括像素驱动电路；所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第二电容及有机发光二极管；所述第二晶体管为低温多晶硅晶体管；
    所述第一晶体管的栅极连接第一节点，其源极连接第二节点，其漏极连接第三节点；
    所述第二晶体管的栅极接入第一扫描信号，其源极接入数据信号，其漏极连接所述第二节点；
    所述第三晶体管的栅极接入使能信号，其源极接入第一电源信号，其漏极连接所述第二节点；
    所述第四晶体管的栅极接入所述使能信号，其源极连接所述第三节点，其漏极连接所述有机发光二极管的阳极；
    所述第一电容的一端接入所述第一电源信号，其另一端连接所述第一节点；
    所述第二电容的一端连接所述第二晶体管的栅极，其另一端连接所述第一节点；
    所述有机发光二极管的阳极连接所述第三节点，所述有机发光二极管的阴极接入第二电源信号。
  12. 如权利要求11所述的显示面板，其中，所述第一晶体管、所述第三晶体管、所述第四晶体管为低温多晶硅晶体管。
  13. 如权利要求11所述的显示面板，其中，还包括第五晶体管；所述第五晶体管的栅极接入所述第一扫描信号，其第一电极连接所述第一节点，其第二电极连接所述第三节点；所述第五晶体管为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管为p型晶体管时，所述第一电极为源极，所述第二电极为漏极；当所述第五晶体管为n型晶体管时，所述第一电极为漏极，所述第二电极为源极。
  14. 如权利要求13所述的像素驱动电路，其中，还包括第六晶体管；所述第六晶体管的栅极接入第二扫描信号，其第一电极连接所述第五晶体管的第一电极；所述第六晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  15. 如权利要求11所述的显示面板，其中，还包括第八晶体管以及第五晶体管；
    所述第八晶体管的栅极接入所述第一扫描信号，其源极连接所述第一节点；所述第八晶体管为氧化物半导体晶体管；
    所述第五晶体管的栅极接入所述第一扫描信号，其第一电极连接所述第一节点，其第二电极连接所述第三节点；所述第五晶体管为氧化物半导体晶体管或低温多晶硅晶体管；当所述第五晶体管为p型晶体管时，所述第五晶体管的第一电极为源极，所述第五晶体管的第二电极为漏极；当所述第五晶体管为n型晶体管时，所述第五晶体管的第一电极为漏极，所述第五晶体管的第二电极为源极。
  16. 如权利要求15所述的显示面板，其中，还包括第六晶体管；所述第六晶体管的栅极接入第二扫描信号，其第一电极连接所述第五晶体管的第一电极；所述第六晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  17. 如权利要求16所述的显示面板，其中，所述第六晶体管的第二电极接入一参考电压，或者连接所述有机发光二极管的阳极；当所述第六晶体管为p型晶体管时，所述第六晶体管的第一电极为源极，所述第六晶体管的第二电极为漏极；当所述第六晶体管为n型晶体管时，所述第六晶体管的第一电极为漏极，所述第六晶体管的第二电极为源极。
  18. 如权利要求16所述的显示面板，其中，还包括第七晶体管；所述第七晶体管的栅极接入所述第一扫描信号，其源极接入一参考电压，其漏极连接所述有机发光二极管的阳极；所述第七晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  19. 如权利要求16所述的显示面板，其中，还包括第七晶体管；所述第七晶体管的栅极接入使能信号，其源极接入一参考电压，其漏极连接所述有机发光二极管的阳极；所述第七晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
  20. 如权利要求16所述的显示面板，其中，还包括第七晶体管；所述第七晶体管的栅极接入所述第二扫描信号，其源极连接所述第三节点，其漏极连接所述有机发光二极管的阳极；所述第七晶体管为氧化物半导体晶体管或低温多晶硅晶体管。
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