WO2022126892A1 - Serdes接口电路 - Google Patents

Serdes接口电路 Download PDF

Info

Publication number
WO2022126892A1
WO2022126892A1 PCT/CN2021/082546 CN2021082546W WO2022126892A1 WO 2022126892 A1 WO2022126892 A1 WO 2022126892A1 CN 2021082546 W CN2021082546 W CN 2021082546W WO 2022126892 A1 WO2022126892 A1 WO 2022126892A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
module
alignment
output
fifo
Prior art date
Application number
PCT/CN2021/082546
Other languages
English (en)
French (fr)
Inventor
袁磊
宣学雷
李宁
Original Assignee
深圳市紫光同创电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市紫光同创电子有限公司 filed Critical 深圳市紫光同创电子有限公司
Priority to JP2023525567A priority Critical patent/JP2023547185A/ja
Publication of WO2022126892A1 publication Critical patent/WO2022126892A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Definitions

  • the present application relates to the technical field of integrated circuit chips, and in particular, to a Serdes interface circuit.
  • the FPGA chip uses multiple channels to transmit data through the Serdes interface.
  • the PCS rx part of the Serdes uses the special character Apattern in the data stream to bind multiple physically independent channels into a parallel channel that is synchronized in timing logic; at the same time, the flexible buffer circuit planned in the PCS rx can solve the recovered clock and local clock. inconsistency problem.
  • the multi-channel data alignment, the recovery clock and the local clock frequency difference compensation function can be implemented quickly, and the multi-channel alignment function needs to be restarted, which consumes a lot of processing delay and greatly affects the transmission efficiency of the entire serdes.
  • the purpose of this application is to provide a Serdes interface circuit.
  • the Serdes interface circuit is used for multi-channel data transmission and includes a plurality of receiving bridge units. Alignment adjustment module, compensation frequency difference deletion module, FIFO, data adjustment module, compensation frequency difference compensation module, state generation module; the alignment adjustment module is used for receiving the decoded data decoded in each channel of the Serdes interface, The decoded data is adjusted to the alignment state, and the alignment state data is output; the compensation frequency difference deletion module is used to delete the special character skip pattern in the alignment state data, and the compensation frequency difference deletion data is written into the FIFO cache The data adjustment module is used to adjust the data read out of the FIFO, and output the adjustment data; the compensation frequency difference compensation module is used to insert the adjustment data and output the alignment adjustment data; The state generating module is used to control the alignment of multiple channels and judge whether the alignment is completed.
  • the number of the multi-channels is 4, and the number of the receiving bridge units is 4.
  • the compensation frequency difference deletion module deletes the special character skip pattern in the alignment state data, and writes the compensation frequency difference deletion data to into the FIFO buffer.
  • the compensating frequency difference complementing module performs an inserting operation on the adjustment data.
  • the data adjustment module includes a data selection module, a deletion information processing module, a deletion index comparison module and an output processing module; a data selection module for receiving the read data from the FIFO and outputting the data to be compared to the deletion information processing module module and output processing module; the deletion information processing module is used to output the deletion index to be compared to the deletion index comparison module for deletion operation comparison; the deletion index comparison module is used to output the selection control signal and the output control signal; the output processing module is used for for output adjustment data.
  • an interface circuit which eliminates the influence of changing the Apattern interval of special characters in each channel caused by bit errors, ensures the smooth completion of data alignment, and improves the transmission performance of serdes and the stability of system operation. .
  • FIG. 1 is a structural diagram of a Serdes interface circuit according to an embodiment of the application.
  • FIG. 2 is a structural diagram of a data adjustment module according to an embodiment of the application.
  • FIG. 3 is a timing diagram under the selection control signal according to the embodiment of the present application.
  • FIG. 4 is a timing diagram of an output control signal according to an embodiment of the present application.
  • An embodiment of the present application provides a Serdes (SERializer/DESerializer, serializer/deserializer) interface circuit, the Serdes interface circuit is used for multi-channel data transmission, and includes a plurality of receiving bridge units rx_bridge_unit), the receiving bridge The unit includes an alignment adjustment module bonding_ctrl, a compensation frequency difference deletion module ctc_del_ctrl, a FIFO (First in First out, on-chip first-in, first-out memory), a data adjustment module rx_bu_adjuster, a compensation frequency difference compensation module ctc_add_ctrl, and a status generation module cb_status_gen, which are connected in sequence.
  • Serdes Serializer/DESerializer, serializer/deserializer
  • the alignment adjustment module is used to receive the decoded data data_after_decoder decoded in each channel of the Serdes interface, adjust the decoded data to the alignment state, and output the alignment state data data_after_bonding; further, due to the special character Apattern in the decoded data
  • the interval between the two is the same and fixed, and adjusting the decoded data to the alignment state is, adjusting the decoded data to the alignment state according to the detection result of the special character Apattern.
  • the compensation frequency difference deletion module is used to delete the special character skip pattern in the alignment state data, realize the frequency difference compensation of the FIFO read side clock and the FIFO write side clock, and write the compensation frequency difference deletion data data_after_ctc_del Specifically, when the frequency of the FIFO write side clock is greater than the frequency of the FIFO read side clock, the compensation frequency difference deletion module deletes the special character skip pattern in the alignment state data, and the compensation frequency Poorly deleted data is written to the FIFO buffer.
  • the data adjustment module is used for performing data adjustment on the read data fifo_rdata of the FIFO, and outputting the adjustment data data_after_adjuster, so as to eliminate the influence of the error code on the data alignment and ensure the data alignment of each channel.
  • the compensating frequency difference complementing module is used to carry out the special character skip pattern insertion operation (skip-add) to the adjustment data, and output the alignment adjustment data dout_after_ctc_and_ceb, to ensure the realization of frequency difference compensation; Specifically, when the FIFO reads When the frequency of the side clock is greater than the frequency of the FIFO write side clock, a skip-add operation is performed on the adjustment data.
  • the state generating module is used to control the alignment of multiple channels and judge whether the alignment is completed.
  • the Serdes interface circuit of the present application eliminates the influence of changing the Apattern interval of special characters in each channel caused by bit errors, ensures the smooth completion of data alignment, and improves the transmission performance of the serdes and the stability of system operation.
  • an embodiment of the present application provides a Serdes interface circuit for multi-channel data transmission, which includes a plurality of receiving bridge units; wherein, one master channel receives the bridge unit rx_bridge_unit in master channel, and the rest are slave channels Receiving bridge unit rx_bridge_unit in slave channel (only one slave channel receiving bridge unit is shown in the figure); the master channel receiving bridge unit is used for data transmission of the master channel, and the slave channel receiving bridge unit is used for the slave channel (slave channel) data transmission.
  • the main channel receiving network bridge unit and the slave channel receiving network bridge unit both include an alignment adjustment module, a compensation frequency difference deletion module, a FIFO, a data adjustment module, a compensation frequency difference compensation module, and a state generation module, which are connected in sequence.
  • the alignment adjustment module is used to receive the decoded data data_after_decoder decoded in each channel of the Serdes interface, adjust the decoded data to the alignment state, and output the alignment state data data_after_bonding; further, due to the special character Apattern in the decoded data
  • the interval between the two is the same and fixed, and adjusting the decoded data to the alignment state is, adjusting the decoded data to the alignment state according to the detection result of the special character Apattern.
  • the compensation frequency difference deletion module is used to delete the special character skip pattern in the alignment state data, realize the frequency difference compensation of the FIFO read side clock and the FIFO write side clock, and write the compensation frequency difference deletion data data_after_ctc_del Specifically, when the frequency of the FIFO write side clock is greater than the frequency of the FIFO read side clock, the compensation frequency difference deletion module deletes the special character skip pattern in the alignment state data, and the compensation frequency Poorly deleted data is written to the FIFO buffer.
  • the special character skip pattern is the code word inserted according to the requirements of the protocol during data transmission, which is used in the frequency difference compensation.
  • the special character skip pattern is inserted and deleted to ensure that the output data frequency meets the transmission requirements;
  • the special character Apattern is In data transmission, according to the code words inserted at fixed intervals, when multi-channel transmission starts, the special characters Apattern in the data of each channel should be aligned.
  • the receiving bridge unit rx_bridge_unit through the identification of the special characters Apattern, the data is adjusted to ensure that , the final output data of Serdes is aligned with each channel.
  • the data adjustment module is used for performing data adjustment on the read data fifo_rdata of the FIFO, and outputting the adjustment data data_after_adjuster; in order to eliminate the influence of the error code on the data alignment, and ensure the data alignment of each channel.
  • the compensation frequency difference compensation module is used to perform a skip-add operation on the adjustment data, and output the alignment adjustment data doout_after_ctc_and_ceb to ensure the realization of frequency difference compensation; specifically, when the frequency of the FIFO read side clock is greater than the FIFO write When the frequency of the side clock is set, a skip-add operation is performed on the adjustment data.
  • the status generating module cb_status_gen is used to control multi-channel alignment and determine whether alignment is completed.
  • the state generation module cb_status_gen in the main channel receiving bridge unit is enabled and controlled, and the state generation module cb_status_gen controls multi-channel alignment through a built-in state machine, and judges all channels (master channel and slave channel) Whether to complete the alignment.
  • data adjustment is performed by setting a data adjustment module to ensure that all channels are based on the main channel for the skip pattern deletion operation (skip-del) of special characters.
  • the data is affected by bit errors.
  • the skip pattern will not be recognized at this time, and each channel will perform different deletion operations, resulting in the change of the interval of the special character Apattern in the channel data. Only the multi-channel alignment function can be restarted, which consumes a lot of processing delay, and the transmission efficiency of the entire serdes will be greatly affected.
  • Skip-del-index-cin, skip-del-index-cout delete operation cascade information of the master channel, skip-del information of the master channel will be transmitted to each slave channel level by level, so that each slave channel can be deleted Comparison of operations, and adjust the data accordingly to ensure that the special character apattern interval in each channel data is consistent.
  • Skip_add_index_cin, skip_add_index_cout insert operation cascade information for the master channel after receiving the adjustment data of the bridge unit rx_bu_adjuster, the data of the slave channel is guaranteed to be consistent with the master channel, and the skip pattern insertion operation of the special characters required for frequency error compensation will be performed by the master channel Control to ensure the alignment of each channel data.
  • the data adjustment module includes a data selection module din_gen, a deletion information processing module din_del_index_gen, a deletion index comparison module del_index_compare, and an output processing module output_data_gen.
  • the data selection module din_gen is used to receive the read data of the FIFO; according to the sending address of the data, as shown in Figure 3 and Figure 4, the data selection module din_gen receives the read data of the FIFO, including the read data adjuster_din at the current moment, and the subsequent The read data of the three read addresses are adjuster_din_nxt1, adjuster_din_nxt2, and adjuster_din_nxt3.
  • the data selection module din_gen of the channel selects the read data of the subsequent read address according to the selection control signal data_in_sel to ensure that the output data is not assigned to the data to be compared din and din_nxt.
  • the output processing module output_data_gen of the slave channel inserts special characters skip pattern into the data to achieve data alignment; when a certain amount of After the skip, in order to ensure that the data is not lost, the din_gen module selects the data according to the selection control signal data_in_sel to ensure that the data to be compared din and din_nxt keep the data of the previous cycle.
  • the selection control signal data_in_sel selects data as adjuster_din_nxt1, adjuster_din_nxt2, and adjuster_din_nxt3.
  • the data selection module din_gen outputs the data to be compared din and din_nxt to the deletion information processing module din_del_index_gen and the output processing module output_data_gen according to the selection control signal data_in_sel.
  • the deletion information processing module din_del_index_gen extracts the special character skip pattern deletion operation skip-del from the data of this channel (from the channel) according to the received data to be compared din and din_nxt, and outputs the deletion indexes din_del_index and din_nxt_del_index to be compared to the deletion index comparison module del_index_compare performs delete operation comparison.
  • the deletion index comparison module del_index_compare of the slave channel is used to compare the skip-del operation of the master channel and the current slave channel, and output the selection control signal data_in_sel and the output control signal data_out_sel; specifically, the deletion index comparison module del_index_compare is based on the received data to be compared Delete the indexes din_del_index, din_nxt_del_index and the main channel delete index master_del_index to compare the skip-del operation of the main channel and this channel to determine whether data adjustment is required.
  • the master channel delete index comparison module del_index_compare does not perform any operation, and the data adjustment of all channels (slave channels) is based on the master channel.
  • the selection control signal data_in_sel is used to control the generation of the next data to be compared din; the output control signal data_out_sel is used for the output processing module output_data_gen to output the adjusted data adjuster_dout.
  • the output processing module output_data_gen outputs the adjusted data adjuster_dout according to the selection of the output control signal data_out_sel, that is, the adjustment data data_after_adjuster; wherein, the buffered left data buf_left_data signal in the output processing module output_data_gen will temporarily store the data that is not output from the channel due to data adjustment.
  • the output control signal data_out_sel will indicate '2'; the special character skip pattern will be restored by the slave channel to ensure that the data of this channel is consistent with the master channel.
  • the output control signal data_out_sel will output '1' to indicate; Shifted to ensure that the current slave channel data and master channel data remain aligned.
  • CTC is the clock compensation frequency difference

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)

Abstract

一种Serdes接口电路，包括若干接收网桥单元，接收网桥单元包括，对齐调整模块，用于接收Serdes接口各个通道中解码后的解码数据，将解码数据调整到对齐状态，并输出对齐状态数据；补偿频差删除模块，用于对对齐状态数据中的特殊字符skip pattern进行删除操作，并将补偿频差删除数据写入FIFO缓存；数据调整模块，用于对FIFO的读出数据进行数据调整，并输出调整数据；补偿频差补位模块，用于对调整数据进行插入操作，并输出对齐调整数据；状态发生模块，用于控制多通道对齐，并判断是否完成对齐。该接口电路消除了误码导致的各个通道内特殊字符Apattern间隔改变的影响，保证了数据对齐的顺利完成，提高了Serdes的传输性能以及系统工作的稳定性。

Description

Serdes接口电路 【技术领域】
本申请涉及集成电路芯片技术领域，尤其涉及一种Serdes接口电路。
【背景技术】
为达到通过较少的引脚实现较高数据速率的目的，FPGA芯片通过Serdes接口使用多个channel进行数据的传输。
Serdes内PCS rx部分利用数据流内特殊字符Apattern将多个物理上独立的通道绑定成一个时序逻辑上同步的并行通道；同时，PCS rx内规划的弹性缓冲电路可以解决恢复的时钟与本地时钟不一致的问题。然而，多通道数据对齐、恢复时钟与本地时钟频差补偿功能实现的快慢，且需重启多通道对齐功能，消耗大量处理时延，整个serdes的传输效率受到极大影响。
【申请内容】
本申请的目的在于提供了一种Serdes接口电路。
为达到上述目的，本申请提供了一种Serdes接口电路，所述Serdes接口电路用于多通道数据传输包括若干接收网桥单元，所述接收网桥单元包括所述接收网桥单元包括依次连接的对齐调整模块、补偿频差删除模块、FIFO、数据调整模块、补偿频差补位模块、状态发生模块；所述对齐调整模块，用于接收Serdes接口各个通道中解码后的解码数据，将所述解码数据调整到对齐状态，并输出对齐状态数据；所述补偿频差删除模块，用于对所述对齐状态数据中的特殊字符skip pattern进行删除操作，并将补偿频差删除数据写入FIFO缓存；所述数据调整模块，用于对FIFO的读出数据进行数据调整，并输出调整数据；所述补偿频差补位模块，用于对所述调整数据进行插入操作，并输出对齐调整数据；所述状态发生模块，用于控制多通道对齐，并判断是否完成对齐。
优选的，所述多通道为4个，所述接收网桥单元为4个。
优选的，当FIFO写侧时钟的频率大于FIFO读侧时钟的频率时，所述补偿 频差删除模块对所述对齐状态数据中的特殊字符skip pattern进行删除操作，并将补偿频差删除数据写入FIFO缓存。
优选的，当FIFO读侧时钟的频率大于FIFO写侧时钟的频率时，所述补偿频差补位模块对所述调整数据进行插入操作。
优选的，所述数据调整模块包括，数据选择模块、删除信息处理模块、删除索引比较模块和输出处理模块；数据选择模块，用于接收FIFO的读出数据并将待比较数据输出至删除信息处理模块和输出处理模块；删除信息处理模块，用于输出待比较删除索引到删除索引比较模块进行删除操作比对；删除索引比较模块，用于输出选择控制信号和输出控制信号；输出处理模块，用于输出调整数据。
本申请的有益效果在于：提供了一种接口电路消除了误码导致的各个通道内特殊字符Apattern间隔改变的影响，保证了数据对齐的顺利完成，提高了serdes的传输性能以及系统工作的稳定性。
【附图说明】
图1为本申请实施例的Serdes接口电路的结构图；
图2为本申请实施例的数据调整模块的结构图；
图3为本申请实施例的选择控制信号下的时序图；
图4为本申请实施例的输出控制信号下的时序图。
【具体实施方式】
为使本说明书的目的、技术方案和优点更加清楚，下面将结合本说明书具体实施例及相应的附图对本说明书技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本说明书一部分实施例，而不是全部的实施例。基于本说明书中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本说明书保护的范围。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”和“第三”等是用于区别不同对象，而非用于描述特定顺序。此外，术语“包括”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单 元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供一种Serdes(SERializer/DESerializer，串行器/解串器)接口电路，所述Serdes接口电路用于多通道数据传输，包括若干接收网桥单元rx_bridge_unit)，所述接收网桥单元包括依次连接的对齐调整模块bonding_ctrl、补偿频差删除模块ctc_del_ctrl、FIFO(First in First out，片上先入先出内存)、数据调整模块rx_bu_adjuster、补偿频差补位模块ctc_add_ctrl、状态发生模块cb_status_gen。
所述对齐调整模块，用于接收Serdes接口各个通道中解码后的解码数据data_after_decoder，将所述解码数据调整到对齐状态，并输出对齐状态数据data_after_bonding；进一步的，由于所述解码数据中特殊字符Apattern的间隔均相同、且固定，将所述解码数据调整到对齐状态为，根据特殊字符Apattern的检测结果将所述解码数据调整到对齐状态。
所述补偿频差删除模块，用于对所述对齐状态数据中的特殊字符skip pattern进行删除操作，实现FIFO读侧时钟和FIFO写侧时钟的频差补偿，并将补偿频差删除数据data_after_ctc_del写入FIFO缓存；具体的，当FIFO写侧时钟的频率大于FIFO读侧时钟的频率时，所述补偿频差删除模块对所述对齐状态数据中的特殊字符skip pattern进行删除操作，并将补偿频差删除数据写入FIFO缓存。
所述数据调整模块，用于对FIFO的读出数据fifo_rdata进行数据调整，并输出调整数据data_after_adjuster；以消除误码对数据对齐的影响，保证各通道数据对齐。
所述补偿频差补位模块，用于对所述调整数据进行特殊字符skip pattern插入操作(skip-add)，并输出对齐调整数据dout_after_ctc_and_ceb，以保证频差补偿的实现；具体的，当FIFO读侧时钟的频率大于FIFO写侧时钟的频率时，对所述调整数据进行skip-add操作。
所述状态发生模块，用于控制多通道对齐，并判断是否完成对齐。
本申请Serdes接口电路消除了误码导致的各个通道内特殊字符Apattern间隔改变的影响，保证了数据对齐的顺利完成，提高了serdes的传输性能以及系统工作的稳定性。
在其中一个实施例中，多通道为4个，相应的，接收网桥单元为4个。
如图1所示，本申请实施例提供一种Serdes接口电路，用于多通道数据传输，其包括若干接收网桥单元；其中，一个主通道接收网桥单元rx_bridge_unit in master channel，其余为从通道接收网桥单元rx_bridge_unit in slave channel(图中仅显示1个从通道接收网桥单元)；主通道接收网桥单元用于主通道(master channel)数据传输，从通道接收网桥单元用于从通道(slave channel)数据传输。
所述主通道接收网桥单元和从通道接收网桥单元均包括依次连接的对齐调整模块、补偿频差删除模块、FIFO、数据调整模块、补偿频差补位模块、状态发生模块。
所述对齐调整模块，用于接收Serdes接口各个通道中解码后的解码数据data_after_decoder，将所述解码数据调整到对齐状态，并输出对齐状态数据data_after_bonding；进一步的，由于所述解码数据中特殊字符Apattern的间隔均相同、且固定，将所述解码数据调整到对齐状态为，根据特殊字符Apattern的检测结果将所述解码数据调整到对齐状态。
所述补偿频差删除模块，用于对所述对齐状态数据中的特殊字符skip pattern进行删除操作，实现FIFO读侧时钟和FIFO写侧时钟的频差补偿，并将补偿频差删除数据data_after_ctc_del写入FIFO缓存；具体的，当FIFO写侧时钟的频率大于FIFO读侧时钟的频率时，所述补偿频差删除模块对所述对齐状态数据中的特殊字符skip pattern进行删除操作，并将补偿频差删除数据写入FIFO缓存。
其中，特殊字符skip pattern为数据传输中，按协议要求插入的码字，在频差补偿时被使用，通过特殊字符skip pattern的插入、删除操作，保证输出数据频率符合传输要求；特殊字符Apattern为数据传输中，根据固定间隔插入的码字，多通道传输开始时，各个通道数据中特殊字符Apattern应是对齐的， 在接收网桥单元rx_bridge_unit，通过特殊字符Apattern的识别，对数据进行调整以保证，Serdes最终输出的数据是各个通道对齐的。
所述数据调整模块，用于对FIFO的读出数据fifo_rdata进行数据调整，并输出调整数据data_after_adjuster；以消除误码对数据对齐的影响，保证各通道数据对齐。
所述补偿频差补位模块，用于对所述调整数据进行skip-add操作，并输出对齐调整数据dout_after_ctc_and_ceb，以保证频差补偿的实现；具体的，当FIFO读侧时钟的频率大于FIFO写侧时钟的频率时，对所述调整数据进行skip-add操作。
所述状态发生模块cb_status_gen，用于控制多通道对齐，并判断是否完成对齐。
进一步地，所述主通道接收网桥单元中的所述状态发生模块cb_status_gen被使能控制，所述状态发生模块cb_status_gen通过内置状态机控制多通道对齐，并判断所有通道(主通道和从通道)是否完成对齐。
本申请通过设置数据调整模块进行数据调整，保证所有通道对特殊字符skip pattern删除操作(skip-del)处理均以主通道为基准，特殊字符Apattern的间隔保持固定，从而解决在网络通路传输、板上串行传输过程中，数据时受误码影响。当误码发生在skip pattern上，此时skip pattern将无法被识别，各个通道将进行不相同的删除操作，导致通道数据中特殊字符Apattern的间隔发生变化，由于误码导致特殊字符apattern间隔变化，只能重启多通道对齐功能，需消耗大量处理时延，整个serdes的传输效率将受到极大影响。
其中，Skip-del-index-cin、skip-del-index-cout为主通道删除操作级联信息，主通道的skip-del信息会一级一级传输到各个从通道，以便各个从通道进行删除操作的比对，并以此对数据进行调整，以保证各个通道数据中特殊字符apattern间隔一致。
Skip_add_index_cin、skip_add_index_cout为主通道插入操作级联信息，经接收网桥单元rx_bu_adjuster调整数据后，从通道的数据已经保证和主通道一致，频差补偿所需要的特殊字符skip pattern插入操作均会由主通道控制， 以保证各个通道数据的对齐。
在其中一个实施例中，如图2所示，所述数据调整模块包括，数据选择模块din_gen、删除信息处理模块din_del_index_gen、删除索引比较模块del_index_compare和输出处理模块output_data_gen。
数据选择模块din_gen，用于接收FIFO的读出数据；根据数据的发送地址，如图3和图4所示，数据选择模块din_gen接收FIFO的读出数据包括当前时刻的读出数据adjuster_din，以及后续三个读地址的读出数据adjuster_din_nxt1、adjuster_din_nxt2、adjuster_din_nxt3。
进一步地，若上一个周期(cycle)，删除信息处理模块din_del_index_gen中的del_index比较结果显示从通道有误码，则对待比较数据din、din_nxt进行移位、拼接，以实现数据对齐。为防止数据重复输出，从通道的数据选择模块din_gen根据选择控制信号data_in_sel，选取后续读地址的读出数据，以确保输出的数据不赋值给待比较数据din、din_nxt。
若上一个周期(cycle)，删除信息处理模块din_del_index_gen中的del_index比较结果显示主通道有误码，则从通道的输出处理模块output_data_gen在数据中插入特殊字符skip pattern以实现数据对齐；当插入一定量的skip后，为确保数据不丢失，din_gen模块根据选择控制信号data_in_sel选取数据，保证待比较数据din、din_nxt保持上一个cycle的数据。其中，选择控制信号data_in_sel选取数据为adjuster_din_nxt1、adjuster_din_nxt2、adjuster_din_nxt3。
数据选择模块din_gen根据选择控制信号data_in_sel将待比较数据din、din_nxt输出至删除信息处理模块din_del_index_gen和输出处理模块output_data_gen。
删除信息处理模块din_del_index_gen根据接收到的待比较数据din、din_nxt，提取本通道(从通道)数据中对特殊字符skip pattern删除操作skip-del，并输出待比较删除索引din_del_index、din_nxt_del_index到删除索引比较模块del_index_compare进行删除操作比对。
从通道的删除索引比较模块del_index_compare，用于比较主通道和当前 从通道的skip-del操作，并输出选择控制信号data_in_sel、输出控制信号data_out_sel；具体的，删除索引比较模块del_index_compare根据接收到的待比较删除索引din_del_index、din_nxt_del_index和主通道删除索引master_del_index，以比较主通道和本通道的skip-del操作，以判断是否需要进行数据调整。其中，主通道删除索引比较模块del_index_compare不进行任何操作，所有通道(从通道)的数据调整均以主通道为基准。
其中，选择控制信号data_in_sel用于控制下一个待比较数据din的生成；输出控制信号data_out_sel用于输出处理模块output_data_gen输出调整后数据adjuster_dout。
输出处理模块output_data_gen根据输出控制信号data_out_sel的选择，输出调整后数据adjuster_dout，也即调整数据data_after_adjuster；其中，输出处理模块output_data_gen中缓存左数据buf_left_data信号将暂存从通道因数据调整而未输出的数据。
若当前主通道有误码，输出控制信号data_out_sel将指示为‘2’；从通道将删除的特殊字符skip pattern进行恢复以保证本通道数据和主通道保持一致。
当buf_left_data有数据暂存，未输出的数据将与当前cycle的待比较数据din拼接，以满足数据位宽的要求后输出。
若从通道有误码，导致特殊字符skip pattern未被处理时，输出控制信号data_out_sel将输出‘1’进行指示；输出处理模块output_data_gen根据主通道删除索引master_del_index的指示对待比较数据din、din_nxt进行拼接、移位，以确保当前从通道数据和主通道数据保持对齐。
从图中可以发现，本申请消除了误码的影响，确保多通道对齐、频差补偿功能同时支持，提高了serdes系统的稳定性，以及数据的传输效率。CTC为时钟补偿频差。
以上所述的仅是本申请的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本申请创造构思的前提下，还可以做出改进，但这些均属于本申请的保护范围。

Claims (5)

  1. 一种Serdes接口电路，所述Serdes接口电路用于多通道数据传输，其特征在于，包括若干接收网桥单元，所述接收网桥单元包括所述接收网桥单元包括依次连接的对齐调整模块、补偿频差删除模块、FIFO、数据调整模块、补偿频差补位模块、状态发生模块；
    所述对齐调整模块，用于接收Serdes接口各个通道中解码后的解码数据，将所述解码数据调整到对齐状态，并输出对齐状态数据；
    所述补偿频差删除模块，用于对所述对齐状态数据中的特殊字符skip pattern进行删除操作，并将补偿频差删除数据写入FIFO缓存；
    所述数据调整模块，用于对FIFO的读出数据进行数据调整，并输出调整数据；
    所述补偿频差补位模块，用于对所述调整数据进行插入操作，并输出对齐调整数据；
    所述状态发生模块，用于控制多通道对齐，并判断是否完成对齐。
  2. 根据权利要求1所述的Serdes接口电路，其特征在于，所述多通道为4个，所述接收网桥单元为4个。
  3. 根据权利要求1所述的Serdes接口电路，其特征在于，当FIFO写侧时钟的频率大于FIFO读侧时钟的频率时，所述补偿频差删除模块对所述对齐状态数据中的特殊字符skip pattern进行删除操作，并将补偿频差删除数据写入FIFO缓存。
  4. 根据权利要求1所述的Serdes接口电路，其特征在于，当FIFO读侧时钟的频率大于FIFO写侧时钟的频率时，所述补偿频差补位模块对所述调整数据进行插入操作。
  5. 根据权利要求1所述的Serdes接口电路，其特征在于，所述数据调整模块包括，数据选择模块、删除信息处理模块、删除索引比较模块和输出处理模块；
    数据选择模块，用于接收FIFO的读出数据并将待比较数据输出至删除信息 处理模块和输出处理模块；
    删除信息处理模块，用于输出待比较删除索引到删除索引比较模块进行删除操作比对；
    删除索引比较模块，用于输出选择控制信号和输出控制信号；
    输出处理模块，用于输出调整数据。
PCT/CN2021/082546 2020-12-17 2021-03-24 Serdes接口电路 WO2022126892A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2023525567A JP2023547185A (ja) 2020-12-17 2021-03-24 Ｓｅｒｄｅｓインタフェース回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011495892.9A CN112600551B (zh) 2020-12-17 2020-12-17 Serdes接口电路
CN202011495892.9 2020-12-17

Publications (1)

Publication Number Publication Date
WO2022126892A1 true WO2022126892A1 (zh) 2022-06-23

Family

ID=75196997

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/082546 WO2022126892A1 (zh) 2020-12-17 2021-03-24 Serdes接口电路

Country Status (3)

Country Link
JP (1) JP2023547185A (zh)
CN (1) CN112600551B (zh)
WO (1) WO2022126892A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113676310B (zh) * 2021-07-29 2023-09-12 北京无线电测量研究所 一种用于雷达系统的数据传输装置
CN113946526B (zh) * 2021-10-29 2023-06-09 西安微电子技术研究所 一种高速串行总线的多通道数据绑定系统及方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120020436A1 (en) * 2010-07-21 2012-01-26 Global Unichip Corporation Method and device for multi-channel data alignment in transmission system
CN102820964A (zh) * 2012-07-12 2012-12-12 武汉滨湖电子有限责任公司 一种基于系统同步与参考通道的多通道数据对齐的方法
CN105718413A (zh) * 2016-01-14 2016-06-29 深圳市同创国芯电子有限公司 一种通道对齐方法、装置及系统
CN105718412A (zh) * 2016-01-14 2016-06-29 深圳市同创国芯电子有限公司 一种通道频差补偿方法、通道控制方法、装置及系统
CN206251108U (zh) * 2015-09-14 2017-06-13 颖飞公司 SerDes系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005004378A1 (en) * 2003-06-22 2005-01-13 Qq Technology, Inc. An intelligent universal calibration logic in embedded high speed transceiver (serdes) applications
WO2013145240A1 (ja) * 2012-03-29 2013-10-03 富士通株式会社 情報処理装置及び情報処理装置制御方法
US9282046B1 (en) * 2012-11-15 2016-03-08 Qlogic, Corporation Smoothing FIFO and methods thereof
CN108988991B (zh) * 2018-07-26 2020-12-01 电子科技大学 带宽自适应的串行数据传输系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120020436A1 (en) * 2010-07-21 2012-01-26 Global Unichip Corporation Method and device for multi-channel data alignment in transmission system
CN102820964A (zh) * 2012-07-12 2012-12-12 武汉滨湖电子有限责任公司 一种基于系统同步与参考通道的多通道数据对齐的方法
CN206251108U (zh) * 2015-09-14 2017-06-13 颖飞公司 SerDes系统
CN105718413A (zh) * 2016-01-14 2016-06-29 深圳市同创国芯电子有限公司 一种通道对齐方法、装置及系统
CN105718412A (zh) * 2016-01-14 2016-06-29 深圳市同创国芯电子有限公司 一种通道频差补偿方法、通道控制方法、装置及系统

Also Published As

Publication number Publication date
CN112600551A (zh) 2021-04-02
JP2023547185A (ja) 2023-11-09
CN112600551B (zh) 2022-11-01

Similar Documents

Publication Publication Date Title
KR101611516B1 (ko) 직렬 포트 메모리 통신 레이턴시 및 신뢰성을 향상시키기 위한 방법 및 시스템
TWI447591B (zh) 減少串列化器解串列化器鏈路中之潛時之技術
WO2022126892A1 (zh) Serdes接口电路
US7093061B2 (en) FIFO module, deskew circuit and rate matching circuit having the same
EP1813039B1 (en) Method and apparatus for aligning data in a wide, high-speed, source synchronous parallel link
US7243173B2 (en) Low protocol, high speed serial transfer for intra-board or inter-board data communication
JPH11505047A (ja) ソース同期クロック型データリンク
US20060095607A1 (en) PCI to PCI express protocol conversion
CN107066419B (zh) 可扩展的自适应n×n通道数据通信系统
KR100783899B1 (ko) 반도체 메모리 시스템과 칩 및 기록 데이터 마스킹 방법
US20060273941A1 (en) Content deskewing for multichannel synchronization
CN114721983B (zh) 一种ddr4加速读写装置
WO2022262587A1 (zh) 数据传输方法、装置、系统、电子设备及可读介质
US20190075191A1 (en) Data communication device, arithmetic processing device, and control method of data communication device
US20210157759A1 (en) Data Transmission System Capable of Transmitting a Great Amount of Data
JPS6195643A (ja) デ−タ伝送方式
WO2022126893A1 (zh) 用于serdes接口的桥接模块
US8312208B2 (en) Memory access controller and method implementing packet processing
EP0829095B1 (en) Method and apparatus for reducing latency time on an interface by overlapping transmitted packets
US7899955B2 (en) Asynchronous data buffer
JPH0738605A (ja) デジタルデ−タパケットスイッチングモジュール
CN114564441B (zh) 片上系统、数据处理方法及计算机设备
US7269681B1 (en) Arrangement for receiving and transmitting PCI-X data according to selected data modes
JP2020072337A (ja) 演算処理装置及び演算処理装置の制御方法
TWI739294B (zh) 信號收發系統與方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21904832

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2023525567

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21904832

Country of ref document: EP

Kind code of ref document: A1