CN206251108U - SerDes系统 - Google Patents
SerDes系统 Download PDFInfo
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- CN206251108U CN206251108U CN201621059121.4U CN201621059121U CN206251108U CN 206251108 U CN206251108 U CN 206251108U CN 201621059121 U CN201621059121 U CN 201621059121U CN 206251108 U CN206251108 U CN 206251108U
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- Prior art date
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- 238000005070 sampling Methods 0.000 claims abstract description 101
- 238000004891 communication Methods 0.000 claims abstract description 63
- 238000011084 recovery Methods 0.000 claims abstract description 14
- 238000012545 processing Methods 0.000 claims description 15
- 230000003287 optical effect Effects 0.000 claims description 6
- 230000008030 elimination Effects 0.000 claims description 2
- 238000003379 elimination reaction Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 25
- 230000008569 process Effects 0.000 abstract description 7
- 230000008054 signal transmission Effects 0.000 abstract description 6
- 238000007726 management method Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 238000012937 correction Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 206010044565 Tremor Diseases 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/853,912 US9374217B1 (en) | 2015-09-14 | 2015-09-14 | SerDes with high-bandwith low-latency clock and data recovery |
US14/853,912 | 2015-09-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN206251108U true CN206251108U (zh) | 2017-06-13 |
Family
ID=56118380
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201621059121.4U Active CN206251108U (zh) | 2015-09-14 | 2016-09-14 | SerDes系统 |
Country Status (2)
Country | Link |
---|---|
US (2) | US9374217B1 (zh) |
CN (1) | CN206251108U (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110162854A (zh) * | 2019-05-09 | 2019-08-23 | 重庆大学 | 一种高速自适应判决反馈均衡器 |
CN113406993A (zh) * | 2021-07-16 | 2021-09-17 | 盛立安元科技(杭州)股份有限公司 | 基于恢复时钟的fpga芯片时钟域同步方法及相关设备 |
WO2022126892A1 (zh) * | 2020-12-17 | 2022-06-23 | 深圳市紫光同创电子有限公司 | Serdes接口电路 |
CN114826539A (zh) * | 2021-01-29 | 2022-07-29 | 瑞昱半导体股份有限公司 | 无参考时钟的时钟数据恢复装置及其方法 |
CN114968878A (zh) * | 2021-02-24 | 2022-08-30 | 迈络思科技有限公司 | 用于高速数据调制的系统、方法和设备 |
CN115037287A (zh) * | 2021-03-05 | 2022-09-09 | 默升科技集团有限公司 | 扩频时钟转换器 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10341145B2 (en) * | 2015-03-03 | 2019-07-02 | Intel Corporation | Low power high speed receiver with reduced decision feedback equalizer samplers |
US9485119B1 (en) * | 2015-07-13 | 2016-11-01 | Inphi Corporation | Offset correction for sense amplifier |
US9553742B1 (en) * | 2015-09-15 | 2017-01-24 | Inphi Corporation | Method and apparatus for independent rise and fall waveform shaping |
US9559880B1 (en) * | 2016-03-04 | 2017-01-31 | Inphi Corporation | Eye modulation for pulse-amplitude modulation communication systems |
US10243570B1 (en) * | 2017-07-28 | 2019-03-26 | Inphi Corporation | Charge pump circuits for clock and data recovery |
KR102403623B1 (ko) * | 2017-08-18 | 2022-05-30 | 삼성전자주식회사 | 클록 신호들 사이의 스큐를 조절하도록 구성되는 전자 회로 |
US10749716B2 (en) * | 2018-04-09 | 2020-08-18 | Texas Instruments Incorporated | Signal path linearizer |
US10601575B1 (en) | 2019-01-31 | 2020-03-24 | Marvell International Ltd. | Oscillator calibration structure and method |
US11184008B2 (en) * | 2019-11-08 | 2021-11-23 | Nvidia Corp. | Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion |
US11088719B1 (en) | 2020-04-10 | 2021-08-10 | Samsung Electronics Co., Ltd. | Serdes with pin sharing |
US10897279B1 (en) | 2020-04-10 | 2021-01-19 | Samsung Electronics Co., Ltd. | DC-coupled SERDES receiver |
US11228470B2 (en) | 2020-05-18 | 2022-01-18 | Nxp B.V. | Continuous time linear equalization circuit |
US11206160B2 (en) * | 2020-05-18 | 2021-12-21 | Nxp B.V. | High bandwidth continuous time linear equalization circuit |
US10924307B1 (en) | 2020-05-18 | 2021-02-16 | Nxp B.V. | Continuous time linear equalization circuit with programmable gains |
CN112467994B (zh) * | 2020-12-30 | 2022-03-04 | 深圳市永联科技股份有限公司 | 一种用于交错并联电路的自动热均衡控制装置及方法 |
US11177932B1 (en) * | 2021-04-20 | 2021-11-16 | Faraday Technology Corp. | System for generating multi phase clocks across wide frequency band using tunable passive polyphase filters |
US11398934B1 (en) * | 2021-09-18 | 2022-07-26 | Xilinx, Inc. | Ultra-high-speed PAM-N CMOS inverter serial link |
US11646861B2 (en) | 2021-09-24 | 2023-05-09 | International Business Machines Corporation | Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes |
US11907074B2 (en) | 2021-09-24 | 2024-02-20 | International Business Machines Corporation | Low-latency deserializer having fine granularity and defective-lane compensation |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6377082B1 (en) * | 2000-08-17 | 2002-04-23 | Agere Systems Guardian Corp. | Loss-of-signal detector for clock/data recovery circuits |
US7512204B1 (en) * | 2005-03-18 | 2009-03-31 | Altera Corporation | Multi-phase-locked loop (PLL) solution for multi-link multi-rate line card applications |
US8578222B2 (en) * | 2011-02-17 | 2013-11-05 | Qualcomm Incorporated | SerDes power throttling as a function of detected error rate |
US20120269305A1 (en) * | 2011-04-21 | 2012-10-25 | Stmicroelectronics (Canada) Inc. | Bang-bang offset cancellation (autozero) |
US9210008B2 (en) * | 2013-08-07 | 2015-12-08 | Texas Instruments Incorporated | SerDes communications with retiming receiver supporting link training |
-
2015
- 2015-09-14 US US14/853,912 patent/US9374217B1/en active Active
-
2016
- 2016-05-23 US US15/162,402 patent/US9742551B2/en active Active
- 2016-09-14 CN CN201621059121.4U patent/CN206251108U/zh active Active
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110162854A (zh) * | 2019-05-09 | 2019-08-23 | 重庆大学 | 一种高速自适应判决反馈均衡器 |
WO2022126892A1 (zh) * | 2020-12-17 | 2022-06-23 | 深圳市紫光同创电子有限公司 | Serdes接口电路 |
CN114826539A (zh) * | 2021-01-29 | 2022-07-29 | 瑞昱半导体股份有限公司 | 无参考时钟的时钟数据恢复装置及其方法 |
CN114826539B (zh) * | 2021-01-29 | 2024-04-19 | 瑞昱半导体股份有限公司 | 无参考时钟的时钟数据恢复装置及其方法 |
CN114968878A (zh) * | 2021-02-24 | 2022-08-30 | 迈络思科技有限公司 | 用于高速数据调制的系统、方法和设备 |
CN115037287A (zh) * | 2021-03-05 | 2022-09-09 | 默升科技集团有限公司 | 扩频时钟转换器 |
CN115037287B (zh) * | 2021-03-05 | 2023-07-28 | 默升科技集团有限公司 | 扩频时钟转换器 |
CN113406993A (zh) * | 2021-07-16 | 2021-09-17 | 盛立安元科技(杭州)股份有限公司 | 基于恢复时钟的fpga芯片时钟域同步方法及相关设备 |
Also Published As
Publication number | Publication date |
---|---|
US9374217B1 (en) | 2016-06-21 |
US9742551B2 (en) | 2017-08-22 |
US20170078084A1 (en) | 2017-03-16 |
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Legal Events
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GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220520 Address after: Grand Cayman, Cayman Islands Patentee after: Kaiwei international Co. Address before: Grand Cayman, Cayman Islands Patentee before: Marvel technologies Cayman I Effective date of registration: 20220520 Address after: Grand Cayman, Cayman Islands Patentee after: Marvel technologies Cayman I Address before: California, USA Patentee before: INPHI Corp. Effective date of registration: 20220520 Address after: Singapore, Singapore City Patentee after: Marvell Asia Pte. Ltd. Address before: Grand Cayman, Cayman Islands Patentee before: Kaiwei international Co. |
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TR01 | Transfer of patent right |