US9374217B1 - SerDes with high-bandwith low-latency clock and data recovery - Google Patents
SerDes with high-bandwith low-latency clock and data recovery Download PDFInfo
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- US9374217B1 US9374217B1 US14/853,912 US201514853912A US9374217B1 US 9374217 B1 US9374217 B1 US 9374217B1 US 201514853912 A US201514853912 A US 201514853912A US 9374217 B1 US9374217 B1 US 9374217B1
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- 238000011084 recovery Methods 0.000 title abstract description 8
- 238000005070 sampling Methods 0.000 claims abstract description 89
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Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Abstract
Description
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/853,912 US9374217B1 (en) | 2015-09-14 | 2015-09-14 | SerDes with high-bandwith low-latency clock and data recovery |
US15/162,402 US9742551B2 (en) | 2015-09-14 | 2016-05-23 | Serdes with high-bandwith low-latency clock and data recovery |
CN201621059121.4U CN206251108U (en) | 2015-09-14 | 2016-09-14 | SerDes systems |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/853,912 US9374217B1 (en) | 2015-09-14 | 2015-09-14 | SerDes with high-bandwith low-latency clock and data recovery |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/162,402 Continuation US9742551B2 (en) | 2015-09-14 | 2016-05-23 | Serdes with high-bandwith low-latency clock and data recovery |
Publications (1)
Publication Number | Publication Date |
---|---|
US9374217B1 true US9374217B1 (en) | 2016-06-21 |
Family
ID=56118380
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/853,912 Active US9374217B1 (en) | 2015-09-14 | 2015-09-14 | SerDes with high-bandwith low-latency clock and data recovery |
US15/162,402 Active US9742551B2 (en) | 2015-09-14 | 2016-05-23 | Serdes with high-bandwith low-latency clock and data recovery |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/162,402 Active US9742551B2 (en) | 2015-09-14 | 2016-05-23 | Serdes with high-bandwith low-latency clock and data recovery |
Country Status (2)
Country | Link |
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US (2) | US9374217B1 (en) |
CN (1) | CN206251108U (en) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170019119A1 (en) * | 2015-07-13 | 2017-01-19 | Inphi Corporation | Offset correction for sense amplifier |
US9553742B1 (en) * | 2015-09-15 | 2017-01-24 | Inphi Corporation | Method and apparatus for independent rise and fall waveform shaping |
US9559880B1 (en) * | 2016-03-04 | 2017-01-31 | Inphi Corporation | Eye modulation for pulse-amplitude modulation communication systems |
CN109412585A (en) * | 2017-08-18 | 2019-03-01 | 三星电子株式会社 | It is configured as the electronic circuit of the deflection between adjustment clock signal |
US20190312756A1 (en) * | 2015-03-03 | 2019-10-10 | Intel Corporation | Low power high speed receiver with reduced decision feedback equalizer samplers |
US20190312759A1 (en) * | 2018-04-09 | 2019-10-10 | Texas Instruments Incorporated | Signal path linearizer |
US20200059348A1 (en) * | 2017-07-28 | 2020-02-20 | Inphi Corporation | Charge pump circuits for clock and data recovery |
US10601575B1 (en) * | 2019-01-31 | 2020-03-24 | Marvell International Ltd. | Oscillator calibration structure and method |
US10924307B1 (en) | 2020-05-18 | 2021-02-16 | Nxp B.V. | Continuous time linear equalization circuit with programmable gains |
US20210359883A1 (en) * | 2020-05-18 | 2021-11-18 | Nxp B.V. | High bandwidth continuous time linear equalization circuit |
US11184008B2 (en) * | 2019-11-08 | 2021-11-23 | Nvidia Corp. | Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion |
US11228470B2 (en) | 2020-05-18 | 2022-01-18 | Nxp B.V. | Continuous time linear equalization circuit |
US11398934B1 (en) * | 2021-09-18 | 2022-07-26 | Xilinx, Inc. | Ultra-high-speed PAM-N CMOS inverter serial link |
US11646861B2 (en) | 2021-09-24 | 2023-05-09 | International Business Machines Corporation | Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes |
US11907074B2 (en) | 2021-09-24 | 2024-02-20 | International Business Machines Corporation | Low-latency deserializer having fine granularity and defective-lane compensation |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110162854B (en) * | 2019-05-09 | 2023-05-26 | 重庆大学 | High-speed self-adaptive decision feedback equalizer |
US11088719B1 (en) | 2020-04-10 | 2021-08-10 | Samsung Electronics Co., Ltd. | Serdes with pin sharing |
US10897279B1 (en) | 2020-04-10 | 2021-01-19 | Samsung Electronics Co., Ltd. | DC-coupled SERDES receiver |
CN112600551B (en) * | 2020-12-17 | 2022-11-01 | 深圳市紫光同创电子有限公司 | Serdes interface circuit |
CN112467994B (en) * | 2020-12-30 | 2022-03-04 | 深圳市永联科技股份有限公司 | Automatic thermal equilibrium control device and method for staggered parallel circuit |
TWI768690B (en) * | 2021-01-29 | 2022-06-21 | 瑞昱半導體股份有限公司 | Reference-less clock and data recovery (cdr) device and method thereof |
US11240079B1 (en) * | 2021-02-24 | 2022-02-01 | Mellanox Technologies Tlv Ltd. | Systems, methods, and devices for high-speed data modulation |
CN115037287B (en) * | 2021-03-05 | 2023-07-28 | 默升科技集团有限公司 | Spread spectrum clock converter |
US11177932B1 (en) * | 2021-04-20 | 2021-11-16 | Faraday Technology Corp. | System for generating multi phase clocks across wide frequency band using tunable passive polyphase filters |
CN113406993A (en) * | 2021-07-16 | 2021-09-17 | 盛立安元科技(杭州)股份有限公司 | FPGA chip clock domain synchronization method based on recovered clock and related equipment |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6377082B1 (en) * | 2000-08-17 | 2002-04-23 | Agere Systems Guardian Corp. | Loss-of-signal detector for clock/data recovery circuits |
US7512204B1 (en) * | 2005-03-18 | 2009-03-31 | Altera Corporation | Multi-phase-locked loop (PLL) solution for multi-link multi-rate line card applications |
US20120216084A1 (en) * | 2011-02-17 | 2012-08-23 | Qualcomm, Incorporated | Serdes power throttling as a function of detected error rate |
US20120269305A1 (en) * | 2011-04-21 | 2012-10-25 | Stmicroelectronics (Canada) Inc. | Bang-bang offset cancellation (autozero) |
US20150043628A1 (en) * | 2013-08-07 | 2015-02-12 | Texas Instruments Incorporated | Serdes communications with retiming receiver supporting link training |
-
2015
- 2015-09-14 US US14/853,912 patent/US9374217B1/en active Active
-
2016
- 2016-05-23 US US15/162,402 patent/US9742551B2/en active Active
- 2016-09-14 CN CN201621059121.4U patent/CN206251108U/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6377082B1 (en) * | 2000-08-17 | 2002-04-23 | Agere Systems Guardian Corp. | Loss-of-signal detector for clock/data recovery circuits |
US7512204B1 (en) * | 2005-03-18 | 2009-03-31 | Altera Corporation | Multi-phase-locked loop (PLL) solution for multi-link multi-rate line card applications |
US20120216084A1 (en) * | 2011-02-17 | 2012-08-23 | Qualcomm, Incorporated | Serdes power throttling as a function of detected error rate |
US20120269305A1 (en) * | 2011-04-21 | 2012-10-25 | Stmicroelectronics (Canada) Inc. | Bang-bang offset cancellation (autozero) |
US20150043628A1 (en) * | 2013-08-07 | 2015-02-12 | Texas Instruments Incorporated | Serdes communications with retiming receiver supporting link training |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10756931B2 (en) * | 2015-03-03 | 2020-08-25 | Intel Corporation | Low power high speed receiver with reduced decision feedback equalizer samplers |
US20190312756A1 (en) * | 2015-03-03 | 2019-10-10 | Intel Corporation | Low power high speed receiver with reduced decision feedback equalizer samplers |
US9621176B2 (en) * | 2015-07-13 | 2017-04-11 | Inphi Corporation | Offset correction for sense amplifier |
US20170019119A1 (en) * | 2015-07-13 | 2017-01-19 | Inphi Corporation | Offset correction for sense amplifier |
US9553742B1 (en) * | 2015-09-15 | 2017-01-24 | Inphi Corporation | Method and apparatus for independent rise and fall waveform shaping |
US9559880B1 (en) * | 2016-03-04 | 2017-01-31 | Inphi Corporation | Eye modulation for pulse-amplitude modulation communication systems |
US9755870B1 (en) * | 2016-03-04 | 2017-09-05 | Inphi Corporation | Eye modulation for pulse-amplitude modulation communication systems |
US10771065B2 (en) * | 2017-07-28 | 2020-09-08 | Inphi Corporation | Charge pump circuits for clock and data recovery |
US20200059348A1 (en) * | 2017-07-28 | 2020-02-20 | Inphi Corporation | Charge pump circuits for clock and data recovery |
CN109412585A (en) * | 2017-08-18 | 2019-03-01 | 三星电子株式会社 | It is configured as the electronic circuit of the deflection between adjustment clock signal |
CN109412585B (en) * | 2017-08-18 | 2023-10-20 | 三星电子株式会社 | Electronic circuit configured to adjust skew between clock signals |
US10749716B2 (en) * | 2018-04-09 | 2020-08-18 | Texas Instruments Incorporated | Signal path linearizer |
US20190312759A1 (en) * | 2018-04-09 | 2019-10-10 | Texas Instruments Incorporated | Signal path linearizer |
US10601575B1 (en) * | 2019-01-31 | 2020-03-24 | Marvell International Ltd. | Oscillator calibration structure and method |
US11012226B2 (en) | 2019-01-31 | 2021-05-18 | Marvell Asia Pte, Ltd. | Oscillator calibration structure and method |
US11184008B2 (en) * | 2019-11-08 | 2021-11-23 | Nvidia Corp. | Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion |
US20210359883A1 (en) * | 2020-05-18 | 2021-11-18 | Nxp B.V. | High bandwidth continuous time linear equalization circuit |
US11206160B2 (en) * | 2020-05-18 | 2021-12-21 | Nxp B.V. | High bandwidth continuous time linear equalization circuit |
US11228470B2 (en) | 2020-05-18 | 2022-01-18 | Nxp B.V. | Continuous time linear equalization circuit |
US10924307B1 (en) | 2020-05-18 | 2021-02-16 | Nxp B.V. | Continuous time linear equalization circuit with programmable gains |
US11398934B1 (en) * | 2021-09-18 | 2022-07-26 | Xilinx, Inc. | Ultra-high-speed PAM-N CMOS inverter serial link |
US20230089431A1 (en) * | 2021-09-18 | 2023-03-23 | Xilinx, Inc. | Ultra-high-speed pam-n cmos inverter serial link |
US11894959B2 (en) * | 2021-09-18 | 2024-02-06 | Xilinx, Inc. | Ultra-high-speed PAM-N CMOS inverter serial link |
US11646861B2 (en) | 2021-09-24 | 2023-05-09 | International Business Machines Corporation | Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes |
US11907074B2 (en) | 2021-09-24 | 2024-02-20 | International Business Machines Corporation | Low-latency deserializer having fine granularity and defective-lane compensation |
Also Published As
Publication number | Publication date |
---|---|
US20170078084A1 (en) | 2017-03-16 |
CN206251108U (en) | 2017-06-13 |
US9742551B2 (en) | 2017-08-22 |
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