CN112600551B - Serdes interface circuit - Google Patents
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- CN112600551B CN112600551B CN202011495892.9A CN202011495892A CN112600551B CN 112600551 B CN112600551 B CN 112600551B CN 202011495892 A CN202011495892 A CN 202011495892A CN 112600551 B CN112600551 B CN 112600551B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Abstract
The invention provides a Serdes interface circuit, which comprises a plurality of receiving bridge units, wherein each receiving bridge unit comprises an alignment adjusting module used for receiving decoded data in each channel of a Serdes interface, adjusting the decoded data to an alignment state and outputting the alignment state data; the compensation frequency difference deleting module is used for deleting the special character skip pattern in the alignment state data and writing the compensation frequency difference deleting data into the FIFO cache; the data adjusting module is used for adjusting the data of the read data of the FIFO and outputting the adjusted data; the compensation frequency difference bit-complementing module is used for performing insertion operation on the adjustment data and outputting alignment adjustment data; and the state generation module is used for controlling the multi-channel alignment and judging whether the alignment is finished. The interface circuit eliminates the influence of special character Apattern interval change in each channel caused by error codes, ensures the smooth completion of data alignment, and improves the transmission performance of serdes and the stability of system work.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of integrated circuit chips, in particular to a Serdes interface circuit.
[ background ] A method for producing a semiconductor device
In order to achieve the purpose of realizing a high data rate through fewer pins, the FPGA chip transmits data through a plurality of channels through a Serdes interface.
A PCS rx part in Serdes utilizes a special character Apattern in a data stream to bind a plurality of physically independent channels into a parallel channel with a synchronous time sequence in logic; meanwhile, the elastic buffer circuit planned in the PCS rx can solve the problem that the recovered clock is inconsistent with the local clock. However, the frequency offset compensation functions of the multichannel data alignment and recovery clock and the local clock are fast and slow, the multichannel alignment function needs to be restarted, a large amount of processing time delay is consumed, and the transmission efficiency of the whole serdes is greatly influenced.
[ summary of the invention ]
The invention aims to provide a Serdes interface circuit.
In order to achieve the above object, the present invention provides a Serdes interface circuit, which is used for multichannel data transmission and comprises a plurality of receiving bridge units, wherein each receiving bridge unit comprises an alignment adjustment module, a compensation frequency difference deletion module, an FIFO, a data adjustment module, a compensation frequency difference bit-complementing module and a state generation module which are connected in sequence; the alignment adjusting module is used for receiving decoded data in each channel of the Serdes interface, adjusting the decoded data to an alignment state and outputting alignment state data; the compensation frequency difference deleting module is used for deleting the special character skip pattern in the alignment state data and writing the compensation frequency difference deleting data into the FIFO cache; the data adjusting module is used for adjusting the data of the read data of the FIFO and outputting the adjusted data; the compensation frequency difference bit complementing module is used for performing insertion operation on the adjustment data and outputting alignment adjustment data; and the state generation module is used for controlling the multi-channel alignment and judging whether the alignment is finished.
Preferably, the number of the multiple channels is 4, and the number of the receiving bridge units is 4.
Preferably, when the frequency of the FIFO write-side clock is greater than the frequency of the FIFO read-side clock, the compensation frequency difference deletion module performs a deletion operation on the special character skip pattern in the alignment state data, and writes the compensation frequency difference deletion data into the FIFO buffer.
Preferably, when the frequency of the FIFO read-side clock is greater than the frequency of the FIFO write-side clock, the compensation frequency difference bit complementing module performs an insertion operation on the adjustment data.
Preferably, the data adjusting module comprises a data selecting module, a deleted information processing module, a deleted index comparing module and an output processing module; the data selection module is used for receiving the read data of the FIFO and outputting the data to be compared to the deleted information processing module and the output processing module; the deletion information processing module is used for outputting deletion indexes to be compared to the deletion index comparison module to perform deletion operation comparison; the deletion index comparison module is used for outputting a selection control signal and an output control signal; and the output processing module is used for outputting the adjusting data.
The invention has the beneficial effects that: the interface circuit eliminates the influence of special character Apattern interval change in each channel caused by error codes, ensures the smooth completion of data alignment, and improves the transmission performance of serdes and the stability of system operation.
[ description of the drawings ]
FIG. 1 is a block diagram of a Serdes interface circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a data adjustment module according to an embodiment of the present invention;
FIG. 3 is a timing diagram of the selection control signal according to the embodiment of the present invention;
FIG. 4 is a timing diagram of the output control signal according to the embodiment of the present invention.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below with reference to the specific embodiments of the present disclosure and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present specification without any creative effort belong to the protection scope of the present specification. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The terms "first," "second," and "third," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a Serdes (SERializer/DESerializer) interface circuit, which is used for multi-channel data transmission and comprises a plurality of receiving bridge units rx _ bridge _ unit, wherein each receiving bridge unit comprises an alignment adjusting module binding _ ctrl, a compensating frequency difference deleting module ctc _ del _ ctrl, a FIFO (First in First out (FIFO) on chip), a data adjusting module rx _ bu _ adjust, a compensating frequency difference compensating module ctc _ add _ ctrl and a state generating module cb _ status _ gen which are sequentially connected.
The alignment adjusting module is used for receiving decoded data _ after _ decoder in each channel of the Serdes interface, adjusting the decoded data to an alignment state, and outputting alignment state data _ after _ bonding; furthermore, as the intervals of the special characters Apattern in the decoded data are all the same and fixed, the decoded data is adjusted to the alignment state, and the decoded data is adjusted to the alignment state according to the detection result of the special characters Apattern.
The compensation frequency difference deleting module is used for deleting the special character skip pattern in the alignment state data, realizing frequency difference compensation of a FIFO read side clock and a FIFO write side clock, and writing the compensation frequency difference deleting data _ after _ ctc _ del into the FIFO cache; specifically, when the frequency of the FIFO write-side clock is greater than the frequency of the FIFO read-side clock, the compensation frequency difference deleting module deletes the special character skip pattern in the alignment state data, and writes the compensation frequency difference deleting data into the FIFO buffer.
The data adjusting module is used for adjusting the data of the read data FIFO _ rdata of the FIFO and outputting adjusting data _ after _ adjuster; the influence of error codes on data alignment is eliminated, and data alignment of each channel is ensured.
The compensation frequency offset bit complementing module is used for performing special character skip pattern insertion operation (skip-add) on the adjusting data and outputting alignment adjusting data dout _ after _ ctc _ and _ ceb to ensure the realization of frequency offset compensation; specifically, when the frequency of the FIFO read-side clock is greater than that of the FIFO write-side clock, skip-add operation is performed on the adjustment data.
And the state generation module is used for controlling the multi-channel alignment and judging whether the alignment is finished.
The Serdes interface circuit eliminates the influence of Apattern interval change of special characters in each channel caused by error codes, ensures the smooth completion of data alignment, and improves the transmission performance of Serdes and the stability of system work.
In one embodiment, there are 4 multi-channels and correspondingly 4 receiving bridge units.
As shown in fig. 1, an embodiment of the present invention provides a Serdes interface circuit for multichannel data transmission, which includes a plurality of receiving bridge units; wherein, one master channel receives the bridge unit rx _ bridge _ unit in master channel, and the rest are slave channel receiving bridge units rx _ bridge _ unit in slave channel (only 1 slave channel receiving bridge unit is shown in the figure); the master channel receiving bridge unit is used for master channel (master channel) data transmission, and the slave channel receiving bridge unit is used for slave channel (slave channel) data transmission.
The main channel receiving network bridge unit and the slave channel receiving network bridge unit respectively comprise an alignment adjusting module, a compensating frequency difference deleting module, an FIFO, a data adjusting module, a compensating frequency difference bit-compensating module and a state generating module which are connected in sequence.
The alignment adjustment module is used for receiving decoded data _ after _ decoder in each channel of the Serdes interface, adjusting the decoded data to an alignment state, and outputting alignment state data _ after _ bonding; furthermore, as the intervals of the special characters Apattern in the decoded data are all the same and fixed, the decoded data is adjusted to the alignment state, and the decoded data is adjusted to the alignment state according to the detection result of the special characters Apattern.
The compensation frequency difference deleting module is used for deleting the special character skip pattern in the alignment state data, realizing frequency difference compensation of a FIFO read side clock and a FIFO write side clock, and writing the compensation frequency difference deleting data _ after _ ctc _ del into the FIFO cache; specifically, when the frequency of the FIFO write-side clock is greater than the frequency of the FIFO read-side clock, the compensation frequency difference deleting module deletes the special character skip pattern in the alignment state data, and writes the compensation frequency difference deleting data into the FIFO buffer.
The special character skip pattern is a code word inserted according to the protocol requirement in data transmission, and is used in frequency difference compensation, and the frequency of output data is ensured to meet the transmission requirement through the insertion and deletion operations of the special character skip pattern; the special character Apattern is a code word inserted at a fixed interval in data transmission, when multichannel transmission starts, the special character Apattern in each channel data is aligned, and at a receiving bridge unit rx _ bridge _ unit, the data is adjusted through the identification of the special character Apattern to ensure that the data finally output by Serdes is aligned in each channel.
The data adjusting module is used for adjusting the data of the read data FIFO _ rdata of the FIFO and outputting adjusting data _ after _ adjuster; the influence of error codes on data alignment is eliminated, and the data alignment of each channel is ensured.
The compensation frequency offset bit complementing module is used for performing skip-add operation on the adjusting data and outputting alignment adjusting data dout _ after _ ctc _ and _ ceb to ensure the realization of frequency offset compensation; specifically, when the frequency of the FIFO read-side clock is greater than that of the FIFO write-side clock, skip-add operation is performed on the adjustment data.
And the state generation module cb _ status _ gen is used for controlling multichannel alignment and judging whether the alignment is finished.
Further, the state generation module cb _ status _ gen in the master channel reception bridge unit is enabled to control multi-channel alignment by a built-in state machine, and determines whether all channels (master channel and slave channel) are aligned.
The invention carries out data adjustment by arranging the data adjustment module, ensures that all channels process the special character skip-pattern deleting operation (skip-del) by taking the main channel as a reference, and keeps the interval of the special character Apattern fixed, thereby solving the problem that the data is influenced by error codes in the processes of network channel transmission and on-board serial transmission. When the error code occurs on the skip pattern, the skip pattern cannot be identified at the moment, different deletion operations are carried out on each channel, so that the interval of the special character Apattern in the channel data changes, the interval of the special character Apattern changes due to the error code, the multi-channel alignment function can only be restarted, a large amount of processing time delay is consumed, and the transmission efficiency of the whole serdes is greatly influenced.
The Skip-del-index-cin and the Skip-del-index-cout are used as the cascade information of the deleting operation of the main channel, the Skip-del information of the main channel is transmitted to each slave channel in a first-stage mode, so that the deleting operation of each slave channel is compared, and the data is adjusted according to the comparison, so that the consistency of special character apttern intervals in the data of each channel is ensured.
The Skip _ add _ index _ cin and the Skip _ add _ index _ cout are the concatenation information of the insertion operation of the main channel, after the data is adjusted by the receiving bridge unit rx _ bu _ adjust, the data of the slave channel is ensured to be consistent with the main channel, and the special character Skip pattern insertion operation required by the frequency difference compensation is controlled by the main channel so as to ensure the alignment of the data of each channel.
In one embodiment, as shown in fig. 2, the data adjusting module includes a data selecting module din _ gen, a deletion information processing module din _ del _ index _ gen, a deletion index comparing module del _ index _ match, and an output processing module output _ data _ gen.
The data selection module din _ gen is used for receiving read data of the FIFO; according to the sending address of the data, as shown in fig. 3 and 4, the read data of the data selection module din _ gen receiving FIFO includes the read data adjust _ din at the current time, and the read data adjust _ din _ nxt1, adjust _ din _ nxt2 and adjust _ din _ nxt3 of the following three read addresses.
Further, if the del _ index comparison result in the information processing module din _ del _ index _ gen is deleted in the last cycle (cycle) to indicate that there is an error in the slave channel, the data din and din _ nxt to be compared are shifted and spliced to achieve data alignment. In order to prevent repeated data output, the data selection module din _ gen of the slave channel selects read data of a subsequent read address according to the selection control signal data _ in _ sel so as to ensure that the output data is not assigned to the data din and din _ nxt to be compared.
If the del _ index comparison result in the deleted information processing module din _ del _ index _ gen shows that the main channel has an error code in the last cycle (cycle), the output processing module output _ data _ gen of the slave channel inserts a special character skip pattern into the data to realize data alignment; after a certain amount of skip is inserted, in order to ensure that data is not lost, the din _ gen module selects data according to the selection control signal data _ in _ sel, and ensures that the data din and din _ nxt to be compared keep the data of the last cycle. The selection control signal data _ in _ sel selects data as adjust _ din _ nxt1, adjust _ din _ nxt2 and adjust _ din _ nxt3.
The data selection module din _ gen outputs the data din and din _ nxt to be compared to the deleted information processing module din _ del _ index _ gen and the output processing module output _ data _ gen according to the selection control signal data _ in _ sel.
The deletion information processing module din _ del _ index _ gen extracts the special character skip pattern deletion operation skip-del from the channel (slave channel) data according to the received data din and din _ nxt to be compared, and outputs the deletion indexes din _ del _ index and din _ nxt _ del _ index to be compared to the deletion index comparison module del _ index _ match for deletion operation comparison.
A delete index comparison module del _ index _ compare of the slave channel, which is used for comparing skip-del operations of the master channel and the current slave channel, and outputting a selection control signal data _ in _ sel and an output control signal data _ out _ sel; specifically, the delete index comparing module del _ index _ component compares skip-del operations of the main channel and the present channel according to the received delete indexes din _ del _ index, din _ nxt _ del _ index and the main channel delete index master _ del _ index to be compared, so as to determine whether data adjustment is required. The delete index module del _ index _ compare of the master channel does not perform any operation, and the data adjustment of all channels (slave channels) is based on the master channel.
The selection control signal data _ in _ sel is used for controlling the generation of the next data din to be compared; the output control signal data _ out _ sel is used for outputting the adjusted data adjust _ dout by the output processing module output _ data _ gen.
The output processing module output _ data _ gen outputs adjusted data adjust _ dout according to the selection of the output control signal data _ out _ sel, namely the adjusted data _ after _ adjust; the left data buf _ left _ data signal cached in the output processing module output _ data _ gen temporarily stores data which is not output due to data adjustment from the channel.
If the current main channel has error codes, the output control signal data _ out _ sel is indicated as '2'; and the slave channel recovers the deleted special character skip pattern to ensure that the data of the channel is consistent with the data of the master channel.
When buf _ left _ data has data to be temporarily stored, the data which is not output is spliced with the data din to be compared of the current cycle so as to meet the requirement of data bit width and then output.
If the slave channel has error codes, the special character skip pattern is not processed, and the output control signal data _ out _ sel outputs '1' for indication; the output processing module output _ data _ gen splices and shifts the data din and din _ nxt to be compared according to the indication of the main channel deletion index master _ del _ index so as to ensure that the current slave channel data and the main channel data are kept aligned.
It can be found from the figure that the invention eliminates the influence of error codes, ensures the simultaneous support of the functions of multi-channel alignment and frequency offset compensation, and improves the stability of the servers system and the transmission efficiency of data. CTC is the clock compensated frequency difference.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (5)
1. A Serdes interface circuit is used for multi-channel data transmission and is characterized by comprising a plurality of receiving bridge units, wherein each receiving bridge unit comprises an alignment adjusting module, a compensation frequency difference deleting module, an FIFO (first in first out), a data adjusting module, a compensation frequency difference bit supplementing module and a state generating module which are sequentially connected;
the alignment adjusting module is used for receiving decoded data in each channel of the Serdes interface, adjusting the decoded data to an alignment state, and outputting alignment state data;
the compensation frequency difference deleting module is used for deleting the special character skip pattern in the alignment state data and writing the compensation frequency difference deleting data into the FIFO cache;
the data adjusting module is used for adjusting the data of the FIFO read data, so that the FIFO read data with error codes is adjusted to be in an aligned state, and adjusting data is output;
the compensation frequency difference bit complementing module is used for performing insertion operation on the adjustment data and outputting alignment adjustment data;
and the state generation module is used for controlling the multi-channel alignment and judging whether the alignment is finished.
2. The Serdes interface circuit of claim 1, wherein the number of multi-lanes is 4 and the number of receiving bridge units is 4.
3. The Serdes interface circuit of claim 1, wherein the compensated frequency offset cancellation module cancels a special character skippattern in the alignment status data when the frequency of the FIFO write-side clock is greater than the frequency of the FIFO read-side clock, and writes the compensated frequency offset cancellation data into the FIFO buffer.
4. The Serdes interface circuit of claim 1, wherein the compensated frequency offset padding module performs an insertion operation on the adjustment data when a frequency of a FIFO read-side clock is greater than a frequency of a FIFO write-side clock.
5. The Serdes interface circuit of claim 1, wherein the data adjustment module comprises a data selection module, a delete information processing module, a delete index comparison module, and an output processing module;
the data selection module is used for receiving the read data of the FIFO and outputting the data to be compared to the deleted information processing module and the output processing module;
the deletion information processing module is used for outputting the deletion index to be compared to the deletion index comparison module to perform deletion operation comparison;
the deletion index comparison module is used for outputting a selection control signal and an output control signal;
and the output processing module is used for outputting the adjusting data.
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| CN202011495892.9A CN112600551B (en) | 2020-12-17 | 2020-12-17 | Serdes interface circuit |
| PCT/CN2021/082546 WO2022126892A1 (en) | 2020-12-17 | 2021-03-24 | Serdes interface circuit |
| JP2023525567A JP2023547185A (en) | 2020-12-17 | 2021-03-24 | Serdes interface circuit |
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| CN113946526B (en) * | 2021-10-29 | 2023-06-09 | 西安微电子技术研究所 | Multichannel data binding system and method for high-speed serial bus |
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| WO2005004378A1 (en) * | 2003-06-22 | 2005-01-13 | Qq Technology, Inc. | An intelligent universal calibration logic in embedded high speed transceiver (serdes) applications |
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| TWI438605B (en) * | 2010-07-21 | 2014-05-21 | Global Unichip Corp | Method and device for aligning multi - channel data in transmission system |
| JP5835464B2 (en) * | 2012-03-29 | 2015-12-24 | 富士通株式会社 | Information processing apparatus and information processing apparatus control method |
| CN102820964B (en) * | 2012-07-12 | 2015-03-18 | 武汉滨湖电子有限责任公司 | Method for aligning multichannel data based on system synchronizing and reference channel |
| US9282046B1 (en) * | 2012-11-15 | 2016-03-08 | Qlogic, Corporation | Smoothing FIFO and methods thereof |
| US9374217B1 (en) * | 2015-09-14 | 2016-06-21 | Inphi Corporation | SerDes with high-bandwith low-latency clock and data recovery |
| CN105718412B (en) * | 2016-01-14 | 2018-10-26 | 深圳市紫光同创电子有限公司 | A kind of channel frequency difference compensation method, channel control method, apparatus and system |
| CN105718413B (en) * | 2016-01-14 | 2018-08-21 | 深圳市紫光同创电子有限公司 | A kind of channel alignment schemes, apparatus and system |
| CN108988991B (en) * | 2018-07-26 | 2020-12-01 | 电子科技大学 | Bandwidth-adaptive serial data transmission system |
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| WO2005004378A1 (en) * | 2003-06-22 | 2005-01-13 | Qq Technology, Inc. | An intelligent universal calibration logic in embedded high speed transceiver (serdes) applications |
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