WO2022126314A9 - 显示基板及其制造方法、显示装置 - Google Patents

显示基板及其制造方法、显示装置 Download PDF

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Publication number
WO2022126314A9
WO2022126314A9 PCT/CN2020/136098 CN2020136098W WO2022126314A9 WO 2022126314 A9 WO2022126314 A9 WO 2022126314A9 CN 2020136098 W CN2020136098 W CN 2020136098W WO 2022126314 A9 WO2022126314 A9 WO 2022126314A9
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Prior art keywords
transparent conductive
metal layer
display area
display
layer
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PCT/CN2020/136098
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English (en)
French (fr)
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WO2022126314A1 (zh
Inventor
石领
陈义鹏
刘珂
方飞
张振华
田学伟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/136098 priority Critical patent/WO2022126314A1/zh
Priority to US17/604,971 priority patent/US20220399374A1/en
Priority to CN202080003321.0A priority patent/CN115398629A/zh
Publication of WO2022126314A1 publication Critical patent/WO2022126314A1/zh
Publication of WO2022126314A9 publication Critical patent/WO2022126314A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • the under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of the display device.
  • a display substrate with an under-screen camera generally includes a light-transmitting display area for arranging the camera, and the light-transmitting display area includes a plurality of pixels.
  • the connection lines in each pixel in the light-transmitting display area need to use transparent conductive traces.
  • the structure of the display substrate in the related art is relatively complex, and the manufacturing cost is relatively high.
  • the present application provides a display substrate, a manufacturing method thereof, and a display device.
  • the technical solution is as follows:
  • a display substrate comprising:
  • a base substrate having a first display area and a second display area, the first display area at least partially surrounds the second display area;
  • each of the pixels includes a pixel circuit and a target electrode connected to each other, the pixel circuit is located in the first display area or the second display area, and the target electrode is located in the second display area;
  • the pixel circuit includes: a first metal layer, a first insulating layer, at least one transparent conductive line, a second insulating layer and a second metal layer, which are located on one side of the base substrate and are stacked in sequence, and each of the transparent conductive lines A wire is connected to a metal layer in the pixel circuit.
  • the first metal layer is a first source-drain metal layer
  • the second metal layer is a second source-drain metal layer
  • the first insulating layer is a passivation layer
  • the second insulating layer is The layer is the first planar layer.
  • each transparent conductive wire is indium tin oxide.
  • the target electrode is an anode.
  • the pixel circuit is located in the second display area, and the orthographic projection of the pixel circuit on the base substrate at least partially overlaps the orthographic projection of the target electrode on the base substrate.
  • the pixel circuit is located in the first display area, and the pixel circuit is connected to the target electrode through the transparent conductive wire.
  • the at least one transparent conductive wire includes: a first transparent conductive wire
  • the first transparent conductive lines are connected to the first metal layer and configured to transmit power signals, and the first transparent conductive lines in two adjacent pixel circuits located in the same column have an integrated structure.
  • the at least one transparent conductive wire includes: a second transparent conductive wire;
  • the second transparent conductive lines are connected to the second metal layer and configured to transmit data signals, and the second transparent conductive lines in the two adjacent pixel circuits located in the same column have an integrated structure.
  • the pixel circuit further includes: a third insulating layer located on a side of the second metal layer away from the base substrate, and located between the base substrate and the first metal layer, and A transistor pattern layer, a third metal layer, a fourth metal layer and a fourth insulating layer are sequentially stacked along a direction away from the base substrate.
  • the third insulating layer is a second flat layer
  • the third metal layer is a first gate metal layer
  • the fourth metal layer is a second gate metal layer
  • the fourth insulating layer For the interlayer intervening layer.
  • the third metal layer includes a first part, a second part and a third part;
  • the at least one transparent conductive wire includes: a third transparent conductive wire, a fourth transparent conductive wire and a fifth transparent conductive wire;
  • the third transparent conductive wire is connected to the first part and is configured to transmit a light-emitting control signal, and the third transparent conductive wire in two adjacent pixel circuits located in the same row has an integrated structure;
  • the fourth transparent conductive line is connected to the second part and is configured to transmit gate driving signals, and the fourth transparent conductive lines in two adjacent pixel circuits located in the same row have an integrated structure;
  • the fifth transparent conductive wire is connected to the third part and is configured to transmit a reset signal, and the fifth transparent conductive wire in the two adjacent pixel circuits in the same row has an integrated structure.
  • the at least one transparent conductive wire includes: a sixth transparent conductive wire;
  • the sixth transparent conductive line is connected to the fourth metal layer, and is configured to transmit an initial signal, and the sixth transparent conductive line in the two adjacent pixel circuits located in the same row has an integrated structure.
  • the second display area is a light-transmitting display area.
  • the resolution of the first display area is greater than or equal to the resolution of the second display area.
  • each of the transparent conductive lines is connected to a metal layer in the pixel circuit through a via hole.
  • a method for manufacturing a display substrate comprising:
  • the base substrate having a first display area and a second display area, and the first display area at least partially surrounds the second display area;
  • a plurality of pixels are formed on one side of the base substrate, each of the pixels includes a pixel circuit and a target electrode connected to each other;
  • the pixel circuit is located in the first display area or the second display area, and the target electrode is located in the second display area;
  • a display device comprising: an integrated circuit, and the display substrate according to the above aspect;
  • the integrated circuit is electrically connected to the transparent conductive wire included in the pixel circuit in the display substrate, and the integrated circuit is used for providing signals to the transparent conductive wire.
  • the display device further includes: a photosensitive sensor, and the photosensitive sensor is located in the second display area of the display substrate.
  • the second display area is rectangular, and the orthographic projection area of the photosensitive sensor on the base substrate is less than or equal to an area of an inscribed circle of the second display area.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a hierarchical structure of a pixel circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a hierarchical structure of another pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a hierarchical structure of another pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a hierarchical structure of a pixel circuit including a via hole provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another hierarchical structure of a pixel circuit including a via hole provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of another hierarchical structure of a pixel circuit including a via hole provided by an embodiment of the present application;
  • FIG. 12 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 13 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present application.
  • FIG. 14 is a flowchart of another method for manufacturing a display substrate provided by an embodiment of the present application.
  • FIG. 15 is a structural layout of a display substrate including a transistor pattern layer provided by an embodiment of the present application.
  • 16 is a structural layout of a display substrate including a transistor pattern layer and a first gate metal layer provided by an embodiment of the present application;
  • 17 is a structural layout of a display substrate including a transistor pattern layer, a first gate metal layer and a second gate metal layer provided by an embodiment of the present application;
  • 18 is a structural layout of a display substrate including a transistor pattern layer, a first gate metal layer, a second gate metal layer, and vias provided by an embodiment of the present application;
  • 19 is a structural layout of a display substrate including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via hole and a first source and drain metal layer provided by an embodiment of the present application;
  • 20 is another structural layout of a display substrate including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via hole and a first source and drain metal layer provided by an embodiment of the present application;
  • 21 is a structural layout of a display substrate including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via hole, a first source-drain metal layer and a transparent conductive line provided by an embodiment of the present application;
  • 22 is another structural layout of a display substrate including a transistor pattern layer, a first gate metal layer, a second gate metal layer, via holes, a first source-drain metal layer and transparent conductive lines provided by an embodiment of the present application ;
  • FIG. 23 shows a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via hole, a first source/drain metal layer, a transparent conductive line, and a second source/drain electrode provided by an embodiment of the present application.
  • FIG. 24 is another example provided by an embodiment of the present application including a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via hole, a first source-drain metal layer, a transparent conductive line, and a second source-drain layer
  • FIG. 25 shows a transistor pattern layer, a first gate metal layer, a second gate metal layer, a via hole, a first source/drain metal layer, a transparent conductive line, and a second source/drain electrode provided by an embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • the display substrate may include: a base substrate 00, the base substrate 00 may have a first display area A1 and a second display area A2, and the first display area A1 may at least partially surround the second display area Area A2.
  • the second display area A2 shown is located at the top middle position of the base substrate 00.
  • the four sides of the rectangular second display area A2 may be surrounded by the first display area A1. That is, the second display area A2 may be surrounded by the first display area A1.
  • the second display area A2 may not be located at the top middle position of the base substrate 00 shown in FIG. 1 , but may be located at other positions.
  • the second display area A2 may be located at the upper left corner or the upper right corner of the base substrate 00 . This embodiment of the present application does not limit this.
  • the first display area A1 may be set as a non-transmissive display area
  • the second display area A2 may be set as a light-transmissive display area. That is, the first display area A1 cannot transmit light, and the second display area A2 can transmit light. In this way, there is no need to perform hole-digging processing on the display substrate, and required hardware structures such as photosensitive sensors can be directly disposed in the second display area A2, which lays a solid foundation for the realization of a true full display.
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present application. 1 to 3 , it can be seen that the display substrate may further include: a plurality of pixels P1 , and each pixel P1 may include a pixel circuit 10 and a target electrode 20 connected to each other.
  • the pixel circuit 10 may provide a driving signal to the target electrode 20, so that a potential difference is formed between the target electrode 20 and another electrode included in the pixel P1, and the pixel P1 emits light.
  • the target electrodes 20 included in each pixel P1 may all be located in the second display area A2, so it can be determined that the plurality of pixels P1 belong to the second display area A2, that is, all of the pixels P1 belong to the second display area A2. Pixels in the second display area A2.
  • the pixel circuits 10 included in each pixel P1 may all be located in the second display area A2, that is, the pixel circuits 10 included in each pixel P1 may be built in the second display together with the connected target electrode 20
  • the area A2 may also be referred to as a built-in pixel circuit.
  • the pixel circuits 10 included in each pixel P1 may all be located in the first display area A1, that is, the pixel circuits 10 included in each pixel P1 may be externally placed in the first display area A1 alone, or It can be called external pixel circuit.
  • some pixel circuits may be built-in, and some pixel circuits may be external.
  • the pixel circuit 10 is externally placed in the first display area A1, the second display area A2 can have better light transmittance.
  • the wiring process can be simplified and the cost can be saved.
  • FIG. 4 is a schematic structural diagram of a pixel circuit 10 provided by an embodiment of the present application.
  • the pixel circuit 10 may include: a first metal layer 101 , a first insulating layer 102 , and at least one transparent conductive line L1 (the number of which is not shown in FIG. 4 ), which are located on one side of the base substrate 00 and are stacked in sequence.
  • the second insulating layer 103 and the second metal layer 104, and each transparent conductive line L1 can be connected with a metal layer in the pixel circuit 10 to form a signal line and used for connecting with a signal terminal. Therefore, the pixel circuit 10 can transmit the driving signal to the connected target electrode 20 under the control of the signal provided by each signal terminal.
  • the target electrode 20 is generally disposed on the side of the second metal layer 104 away from the second insulating layer 103 , and an insulating layer is also disposed between the target electrode 20 and the second metal layer 104 .
  • FIGS. 1 to 3 only show the pixels P1 in the second display area A2.
  • the first display area A1 also includes a plurality of pixels.
  • the first metal layer 101 , the first insulating layer 102 , the second insulating layer 103 and the second metal layer 104 are the indispensable hierarchical structures included in the pixel circuit of the pixel in any display area. That is, the first insulating layer 102 and the second insulating layer 103 are the existing two insulating layers between the first metal layer 101 and the second metal layer 104 .
  • the transparent conductive line L1 is an additional layer structure to ensure the light transmittance of the second display area A2.
  • At least one insulating layer In order to avoid mutual interference of signals between two adjacent conductive layers, at least one insulating layer generally needs to be disposed between the two adjacent conductive layers. Therefore, in combination with the arrangement positions of the target electrode 20 and the second metal layer 104, if the transparent conductive line L1 is arranged on the side of the second metal layer 104 away from the base substrate 00, an additional insulating layer needs to be arranged to separate the target electrode.
  • the second metal layer 104 is separated from the transparent conductive line L1, or the second metal layer 104 is separated from the transparent conductive line L1.
  • the transparent conductive line L1 since the transparent conductive line L1 is disposed between the existing two insulating layers, the disposition of at least one insulating layer can be saved.
  • each layer is generally formed by a mask process, at least one mask process can be saved. Therefore, it can be determined that the display substrate provided by the embodiment of the present application has a simple structure and low manufacturing cost.
  • an embodiment of the present application discloses a display substrate, the display substrate includes a base substrate having a first display area and a second display area, and in a pixel circuit included in a pixel in the second display area,
  • the conductive wire connected to the metal layer is a transparent conductive wire, and the transparent conductive wire is located between the existing two insulating layers.
  • the display substrate provided by the embodiment of the present application not only ensures better light transmittance of the second display area, but also has a simpler structure and lower manufacturing cost.
  • the target electrode 20 described in this embodiment of the present application may be an anode.
  • the other electrode described in the above embodiment may be a cathode.
  • the target electrode 20 may also be a cathode, and correspondingly, the other electrode described in the above embodiment may be an anode.
  • each transparent conductive wire L1 described in the embodiments of the present application may be indium tin oxide (indium tin oxide, ITO).
  • ITO indium tin oxide
  • each transparent conductive wire L1 may also be called an ITO trace.
  • the material of the transparent conductive line L1 may also be other transparent and conductive materials such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • FIG. 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the first metal layer 101 described in the embodiments of the present application may be a first source & drain (SD) metal layer, SD1 for short.
  • the second metal layer 104 may be a second source-drain metal layer SD2
  • the first insulating layer 102 may be a passivation layer (passivation, PVX)
  • the second insulating layer 103 may be a first planarization layer (planarization, PLN), abbreviated as PLN1. That is, at least one transparent conductive line L1 described in the embodiments of the present application may be located between the passivation layer PVX and the first planarization layer PLN1.
  • each layer structure is generally formed in sequence along the direction away from the base substrate 00 during the process, it can be determined that the at least one transparent conductive line L1 described in the embodiment of the present application is forming the first source-drain metal layer SD1 and the After the passivation layer PVX and before the first flat layer PLN1 is formed, the passivation layer PVX is formed on the side of the passivation layer PVX away from the first source-drain metal layer SD1. That is, the transparent conductive line L1 manufacturing process may be performed after the passivation layer PVX is formed and before the first planarization layer PLN1 is formed. In addition, referring to FIG. 5 , an ITO layer may be formed first, and then one or more ITO traces are obtained through a patterning process.
  • FIG. 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit 10 may further include: a third insulating layer 105 located on the side of the second metal layer 104 away from the base substrate 00 , and a third insulating layer 105 located between the base substrate 00 and the first metal layer 101 along the side of the base substrate 104 .
  • the transistor pattern layer 106 , the third metal layer 107 , the fourth metal layer 108 , and the fourth insulating layer 109 are sequentially stacked in the direction away from the base substrate 00 .
  • the transistor pattern layer 106 may be a polysilicon (poly) material layer, referred to as a POLY layer for short.
  • the third insulating layer 105 may be the second planarization layer PLN2.
  • the third metal layer 107 may be a first gate metal layer, referred to as GATE1 for short.
  • the fourth metal layer 108 may be the second gate metal layer GATE2, and the fourth insulating layer 109 may be an interlayer (interlayer, ILD).
  • an insulating layer is also generally included between the first gate metal layer GATE1 and the second gate metal layer GATE2.
  • the pixel circuit 10 may further include: an insulating layer 110 located between the transistor pattern layer 106 and the third metal layer 107 (ie, the first gate metal layer GATE1 ), and the third metal layer 107 and the fourth metal layer 108 (ie, the first gate metal layer GATE1 ) The insulating layer 111 between the second gate metal layers (GATE2).
  • FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • the first gate metal layer GATE1 may include a first part B1 , a second part B2 and a third part B3 .
  • the at least one transparent conductive line L1 may include: a first transparent conductive line L11, a second transparent conductive line L12, a third transparent conductive line L13, a fourth transparent conductive line L14, a fifth transparent conductive line L15, and a sixth transparent conductive line L16 .
  • the first transparent conductive line L11 can be connected to the first metal layer 101 (ie, the first source-drain metal layer SD1 ), and is configured to transmit power signals. That is, as shown in FIG. 7 , the first transparent conductive wire L11 can also be used to connect to the power terminal VDD, and the power terminal VDD can transmit power signals to the first source-drain metal layer SD1 through the first transparent conductive wire L11 . In other words, the first transparent conductive line L11 is connected to the first source-drain metal layer SD1 to form a power signal line, and the pixel circuit 10 can receive the power signal from the power signal line.
  • the first transparent conductive lines L11 in two adjacent pixel circuits 10 located in the same column may have an integrated structure.
  • the pixel circuits 10 in the same column can share the same power supply signal line, that is, connect to the same DC power supply terminal VDD.
  • the second transparent conductive line L12 can be connected to the second metal layer 104 (ie, the second source-drain metal layer SD2 ), and is configured to transmit data signals. That is, as shown in FIG. 7 , the second transparent conductive wire L12 can also be used to connect with the data signal terminal DATA, and the data signal terminal DATA can transmit data signals to the second source-drain metal layer SD2 through the second transparent conductive wire L12 . In other words, the second transparent conductive line L12 is connected with the second source-drain metal layer SD2 to form a data signal line, and the pixel circuit 10 can receive the data signal from the data signal line.
  • the second transparent conductive lines L12 in two adjacent pixel circuits 10 located in the same column may have an integrated structure.
  • the same column of pixel circuits 10 can share the same data signal line, that is, connected to the same data signal terminal DATA.
  • the third transparent conductive line L13 may be connected to the first portion B1 of the first gate metal layer GATE1 and configured to transmit a light emission control signal. That is, as shown in FIG. 7 , the third transparent conductive wire L13 can also be used to connect with the light-emitting control signal terminal EM, and the light-emitting control signal terminal EM can transmit light to the first gate metal layer GATE1 through the third transparent conductive wire L13 control signal.
  • the third transparent conductive line L13 is connected to the first part B1 of the first gate metal layer GATE1 to form a light emission control signal line, and the pixel circuit 10 can receive the light emission control signal from the light emission control signal line.
  • the third transparent conductive lines L13 in two adjacent pixel circuits 10 in the same row may have an integrated structure.
  • the same row of pixel circuits 10 can share the same light-emitting control signal line, that is, connected to the same light-emitting control signal terminal EM.
  • the fourth transparent conductive line L14 may be connected to the second portion B2 of the first gate metal layer GATE1 and configured to transmit gate driving signals. That is, as shown in FIG. 7 , the fourth transparent conductive line L14 can also be used to connect with the gate signal terminal G1, and the gate signal terminal G1 can transmit the gate to the first gate metal layer GATE1 through the fourth transparent conductive line L14 drive signal. In other words, connecting the fourth transparent conductive line L14 with the second portion B2 of the first gate metal layer GATE1 may form a gate line, and the pixel circuit 10 may receive a gate driving signal from the gate line.
  • the fourth transparent conductive lines L14 in two adjacent pixel circuits 10 in the same row may have an integrated structure.
  • the same row of pixel circuits 10 may share the same gate line, that is, connect to the same gate signal terminal G1.
  • the fifth transparent conductive line L15 may be connected to the third portion B3 of the first gate metal layer GATE1 and configured to transmit a reset signal. That is, as shown in FIG. 7 , the fifth transparent conductive line L15 can also be used for connecting with the reset signal terminal RST, and the reset signal terminal RST can transmit the reset signal to the first gate metal layer GATE1 through the fifth transparent conductive line L15. In other words, the connection between the fifth transparent conductive line L15 and the third portion B3 of the first gate metal layer GATE1 can form a reset signal line, and the pixel circuit 10 can receive the reset signal from the reset signal line.
  • the fifth transparent conductive lines L15 in two adjacent pixel circuits 10 in the same row may have an integrated structure.
  • the same row of pixel circuits 10 may share the same reset signal line, that is, connected to the same reset signal terminal RST.
  • the sixth transparent conductive line L16 may be connected to the fourth metal layer 108 (ie, the second gate metal layer GATE2 ), and is configured to transmit an initial signal. That is, as shown in FIG. 7 , the sixth transparent conductive line L16 can also be used to connect with the initial signal terminal Vinit, and the initial signal terminal Vinit can transmit the initial signal to the second gate metal layer GATE2 through the sixth transparent conductive line L16. In other words, the connection between the sixth transparent conductive line L16 and the second gate metal layer GATE2 can form an initial signal line, and the pixel circuit 10 can receive the initial signal from the initial signal line.
  • the sixth transparent conductive lines L16 in two adjacent pixel circuits 10 located in the same row may have an integrated structure.
  • the same row of pixel circuits 10 may share the same initial signal line, that is, connected to the same initial signal terminal Vinit.
  • the pixel circuits 10 included in all the pixels P1 in the second display area A2 may be connected to the same initial signal terminal Vinit.
  • the pixel circuit 10 may actually include a plurality of transistors, and the signal received by the pixel circuit 10 described in the above embodiments refers to that the transistor receives the signal. Under the driving of the above-mentioned signals, the pixel circuit 10 can work reliably and transmit the driving signal to the connected target electrode 20 .
  • each type of transparent conductive line can be divided into two parts, one part is adjacent to the adjacent pixel circuit 10.
  • the corresponding type of transparent conductive wire of the circuit 10 is integrally formed, and the other part is integrally formed with the corresponding type of transparent conductive wire of another adjacent pixel circuit 10 .
  • the first transparent conductive line L11 of the pixel circuit 10 at the center position may include an upper half part L11_1 and a lower half part L11_2 .
  • the upper half L11_1 and the lower half L11_2 of the first transparent conductive line L11 of the pixel circuit 10 adjacent to the top have an integral structure;
  • the upper part L11_1 is an integral structure.
  • each transparent conductive line L1 and a metal layer in the pixel circuit 10 may be connected through a via hole.
  • FIG. 9 shows a structural layout including a via hole K1 .
  • the passivation layer PVX and the first flat layer PLN1 both include via holes K1, and the transparent conductive line L1 and the first source-drain metal layer SD1 can pass through the via holes K1 opened in the passivation layer PVX.
  • FIG. 10 shows a structural layout including a via hole K1 .
  • the passivation layer PVX, the first source-drain metal layer SD1, the interlayer interlayer ILD and the second gate metal layer GATE2 between the transparent conductive line L1 and the first gate metal layer GATE1
  • the via hole K1 penetrates the passivation layer PVX, the first source and drain metal layer SD1, the interlayer interlayer ILD and the second gate metal layer GATE2.
  • the transparent conductive line L1 and the first gate metal layer GATE1 may be connected through the via hole K1.
  • FIG. 11 shows a structural layout including the via hole K1 .
  • the passivation layer PVX, the first source-drain metal layer SD1 and the interlayer interlayer ILD between the transparent conductive line L1 and the second gate metal layer GATE2 have vias K1, and the The via hole K1 penetrates through the passivation layer PVX, the first source-drain metal layer SD1 and the interlayer interlayer ILD.
  • the transparent conductive line L1 and the second gate metal layer GATE2 may be connected through the via hole K1.
  • the transparent conductive lines L1 described in the embodiments of the present application are located between the passivation layer PVX and the first flat layer PLN1, the depths of the above-mentioned via holes K1 are shallow, and benign contacts are easily formed. , to ensure connection reliability.
  • the pixel circuit 10 may be located in the second display area A2 , that is, the pixel circuit 10 may be built-in.
  • the orthographic projection of the pixel circuit 10 on the base substrate 00 and the orthographic projection of the target electrode 20 on the base substrate 00 may at least partially overlap.
  • the connection between the pixel circuit 10 and the target electrode 20 may be the pixel circuit 10 and the target The electrodes 20 may be connected through vias.
  • the orthographic projection of the pixel circuit 10 on the base substrate 00 covers the orthographic projection of the target electrode 20 on the base substrate 00 .
  • the pixel circuit 10 may be located in the first display area A1. In this way, the pixel circuit 10 can be connected to the target electrode 20 through the transparent conductive line L1.
  • the second source-drain metal layer SD2 may be set to be connected to the transparent conductive line L1 through via holes, and the transparent conductive line L1 may be set to be connected to the target electrode 20 .
  • reliable connection between the second source-drain metal layer SD2 and the target electrode 20 can be ensured.
  • the base substrate 00 has a light-transmitting display area, that is, the second display area A2, as shown in FIG. 12 , the photosensitive sensor 001 in the display module included in the display device is (eg, a camera), can be directly disposed in the second display area A2, that is, there is no need to dig additional holes in the display panel. In this way, a solid foundation has been laid for the realization of the full-screen display panel.
  • the second display area A2 may be a rectangle, and the area of the orthographic projection of the photosensitive sensor 001 on the base substrate 00 may be smaller than or equal to the area of the inscribed circle of the second display area A2. That is, the size of the area where the photosensitive sensor 001 is located may be smaller than or equal to the size of the inscribed circle of the second display area A2.
  • the area of the orthographic projection of the photosensitive sensor 001 on the base substrate 00 may be smaller than or equal to the area of the inscribed circle of the second display area A2. That is, the size of the area where the photosensitive sensor 001 is located may be smaller than or equal to the size of the inscribed circle of the second display area A2.
  • the size of the area where the photosensitive sensor 001 is located is equal to the size of the inscribed circle Y0 of the second display area A2, that is, the shape of the area where the photosensitive sensor 001 is located may be a circle, Correspondingly, the area where the photosensitive sensor 001 is located may also be referred to as a light-transmitting hole.
  • the second display area A2 may also have other shapes than rectangles, such as circles or ellipses.
  • the resolution of the first display area A1 may be greater than the resolution of the second display area A2. That is, the area of the first display area A1 is larger than that of the second display area A2, and the number of pixels included in the first display area A1 is larger than that of the second display area A2. Moreover, the densities of the plurality of pixels P1 located in the second display area A2 and the plurality of pixels located in the first display area A1 may be different. That is, the number of pixels included in each inch in the first display area A1 and the second display area A2 are different.
  • the resolution of the first display area A1 may be less than or equal to the resolution of the second display area A2.
  • the area of the first display area A1 and the area of the second display area A2 may be the same, and the number of pixels per unit area included in the first display area A1 and the second display area A2 are the same.
  • the area of the first display area A1 may be smaller than that of the second display area A2, and the number of pixels per unit area included in the first display area A1 is smaller than the number of pixels per unit area included in the second display area A2 .
  • an embodiment of the present application discloses a display substrate, the display substrate includes a base substrate having a first display area and a second display area, and in a pixel circuit included in a pixel in the second display area,
  • the conductive wire connected to the metal layer is a transparent conductive wire, and the transparent conductive wire is located between the existing two insulating layers.
  • the display substrate provided by the embodiment of the present application not only ensures better light transmittance of the second display area, but also has a simpler structure and lower manufacturing cost.
  • FIG. 13 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present application, and the method can be used to manufacture the display substrate shown in any of FIGS. 1 to 3 , 7 , 8 and 12 . As shown in Figure 13, the method may include:
  • Step 1301 providing a base substrate.
  • the base substrate may have a first display area A1 and a second display area A2, and the first display area A1 may at least partially surround the second display area A2.
  • Step 1302 forming a plurality of pixels on one side of the base substrate.
  • each pixel P1 may include a pixel circuit 10 and a target electrode 20 that are connected to each other.
  • the pixel circuit 10 may be located in the first display area A1 or the second display area A2, and the target electrode 20 may be located in the second display area A2.
  • the pixel circuit 10 may include a first metal layer 101 , a first insulating layer 102 , at least one transparent conductive line L2 , a second insulating layer 103 and a second metal layer stacked in sequence along a direction away from the base substrate 00
  • each transparent conductive line L1 may be connected to a metal layer in the pixel circuit 10 .
  • FIG. 14 shows a flowchart of another method for manufacturing a display substrate provided by an embodiment of the present application. . As shown in Figure 14, the method may include:
  • Step 1401 providing a base substrate.
  • a base substrate may be provided first as a carrier, and the base substrate may have at least a first display area and a second display area at least partially surrounded by the first display area.
  • the base substrate may be a glass substrate or a flexible substrate.
  • Step 1402 forming a transistor pattern layer on one side of the base substrate.
  • a transistor pattern layer may be first formed on one side of the base substrate through a patterning process.
  • the patterning process may include: gluing, exposing, developing and etching.
  • FIG. 15 shows a schematic structural diagram of a base substrate 00 on which a transistor pattern layer, that is, a POLY layer, is formed.
  • Step 1403 forming a first gate metal layer on the side of the transistor pattern layer away from the base substrate.
  • the first gate metal layer may continue to be formed on the side of the transistor pattern layer away from the base substrate.
  • FIG. 16 shows a schematic structural diagram of the base substrate 00 on which the first gate metal layer GATE1 is formed.
  • Step 1404 forming a second gate metal layer on the side of the first gate metal layer away from the transistor pattern layer.
  • a second gate metal layer may be further formed on the side of the first gate metal layer away from the transistor pattern layer.
  • FIG. 17 shows a schematic structural diagram of the base substrate 00 on which the second gate metal layer GATE2 is formed.
  • Step 1405 forming an interlayer interlayer on the side of the second gate metal layer away from the first gate metal layer.
  • an interlayer interlayer may be further formed on the side of the second gate metal layer away from the first gate metal layer. And after the interlayer interposition layer is formed, the interlayer interposition layer may be processed to obtain a plurality of connection vias.
  • FIG. 18 shows a schematic structural diagram of the base substrate 00 of the via hole K1 formed on the second gate metal layer GATE2.
  • Step 1406 forming a first source-drain metal layer on the side of the interlayer interlayer away from the second gate metal layer.
  • the first source and drain metal layers may be further formed on the side of the interlayer interlayer away from the second gate metal layer.
  • FIG. 19 shows a schematic structural diagram of the base substrate 00 of the first source-drain metal layer SD1 formed on the via hole K1.
  • Step 1407 forming a passivation layer on the side of the first source-drain metal layer away from the interlayer interlayer.
  • a passivation layer may be further formed on the side of the first source-drain metal layer away from the interlayer interlayer. And after the passivation layer is formed, the passivation layer can be processed to obtain a plurality of connection vias.
  • FIG. 20 shows a schematic structural diagram of the base substrate 00 of the via hole K1 formed on the first source-drain metal layer SD1.
  • Step 1408 forming at least one transparent conductive line on the side of the passivation layer away from the first source-drain metal layer.
  • a transparent conductive layer may be formed on the side of the passivation layer away from the first source and drain metal layer, and then the transparent conductive layer is processed to obtain one or more transparent conductive layers. Conductive thread.
  • FIG. 21 shows a schematic structural diagram of the base substrate 00 of the plurality of first transparent conductive lines L1 formed on the via hole K1.
  • Step 1409 forming a first flat layer on the side of the at least one transparent conductive line away from the passivation layer.
  • the first flat layer may be further formed on the side of the at least one transparent conductive wire away from the passivation layer. And after the first flat layer is formed, the first flat layer can be processed to obtain a plurality of connection vias.
  • FIG. 22 shows a schematic structural diagram of the base substrate 00 of the via hole K1 formed on at least one transparent conductive line L1.
  • Step 14010 forming a second source-drain metal layer on the side of the first flat layer away from the at least one transparent conductive line.
  • a second source-drain metal layer may be further formed on the side of the first flat layer away from the at least one transparent conductive line.
  • FIG. 23 shows a schematic structural diagram of the base substrate 00 of the second source-drain metal layer SD2 formed on the via hole K1.
  • Step 14011 forming a second flat layer on a side of the second source-drain metal layer away from the first flat layer.
  • a second planarization layer may be further formed on the side of the second source-drain metal layer away from the first planarization layer.
  • the second flat layer can be processed to obtain a plurality of connection vias.
  • FIG. 24 shows a schematic structural diagram of the base substrate 00 of the via hole K1 formed on the second source-drain metal layer SD2.
  • Step 14012 forming an anode on the side of the second flat layer away from the second source-drain metal layer.
  • the anode may be further formed on the side of the second flat layer away from the second source-drain metal layer.
  • FIG. 25 shows a schematic structural diagram of the base substrate 00 of the anode ANODE formed on the via hole K1. Moreover, the anode ANODE can be connected to the second source-drain metal layer SD2 through the via hole K1.
  • the process sequence for manufacturing the display substrate in the embodiment of the present application is: POLY-GATE1-GATE2-ILD-SD1-PVX-ITO-PLN1-SD2-PLN2-ANODE.
  • step 1403 since insulating layers are included between the transistor pattern layer 106 and the first gate metal layer GATE1, and between the first gate metal layer GATE1 and the second gate metal layer GATE2, so Before step 1403 is performed, the step of forming an insulating layer on the side of the transistor pattern layer away from the base substrate may also be included. And before step 1404 is performed, a step of forming an insulating layer on the side of the first gate metal layer away from the transistor pattern layer may also be included.
  • the embodiments of the present application disclose a method for manufacturing a display substrate.
  • the transparent conductive lines are formed after the passivation layer is formed and before the first planarization layer is formed. Since the passivation layer and the first flat layer are existing two-layer insulating layers, the method provided by the embodiments of the present application not only ensures that the light transmittance of the second display area is higher than that of forming the transparent conductive lines at other positions. Good, and the manufactured display substrate has a simpler structure and lower manufacturing cost.
  • FIG. 26 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device may include: an integrated circuit 100 , and a display substrate 200 as shown in any one of FIGS. 1 to 3 , 7 , 8 and 12 .
  • the integrated circuit 100 can be electrically connected to the transparent conductive line L1 included in the pixel circuit 10 in the display substrate 200, and the integrated circuit 100 can be used to provide signals to the transparent conductive line L1.
  • the integrated circuit 100 may be electrically connected to the signal terminals connected to each of the transparent conductive lines L1 , and provide signals to the signal terminals to indirectly provide signals to the transparent conductive lines L1 .
  • FIG. 26 only schematically shows the position of the integrated circuit 100 , and the integrated circuit 100 may also be located on the right side of the display substrate 200 , or may be located on both the left side and the right side of the display substrate 200 . Alternatively, it may also be located on the upper side and/or the lower side of the display substrate 200 .
  • the display device can be: an organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED) display device, a liquid crystal display device, a mobile phone, a computer, a television, a display, an electronic paper, a digital photo frame or a navigator, etc. Any product or part that has a display function.
  • AMOLED active-matrix organic light-emitting diode

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Abstract

一种显示基板及其制造方法、显示装置，属于显示技术领域。其中，显示基板包括具有第一显示区（A1）和第二显示区（A2）的衬底基板（00），第二显示区（A2）内的像素（P1）所包括的像素电路（10）中，与金属层（101,104）连接的导电线为透明导电线（L1），且透明导电线（L1）位于已有的两层绝缘层（102,103）之间。如此，相对于透明导电线（L1）位于其他位置的显示基板，不仅确保了第二显示区（A2）的透光率较好，而且结构较为简单，制造成本较低。

Description

显示基板及其制造方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板及其制造方法、显示装置。
背景技术
屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
相关技术中，具有屏下摄像头的显示基板一般包括用于设置摄像头的透光显示区，且该透光显示区内包括多个像素。此外，为确保透光显示区的透光率，位于透光显示区的各个像素中的连接线需要采用透明导电走线。
但是，相关技术中的显示基板的结构较为复杂，制造成本较高。
发明内容
本申请提供了一种显示基板及其制造方法、显示装置。所述技术方案如下：
一方面，提供了一种显示基板，所述显示基板包括：
衬底基板，具有第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区；
多个像素，每个所述像素包括相互连接的像素电路和目标电极，所述像素电路位于所述第一显示区或所述第二显示区，所述目标电极位于所述第二显示区；所述像素电路包括：位于所述衬底基板一侧且依次层叠的第一金属层、第一绝缘层、至少一条透明导电线、第二绝缘层和第二金属层，每条所述透明导电线与所述像素电路中的一个金属层连接。
可选的，所述第一金属层为第一源漏极金属层，所述第二金属层为第二源漏极金属层，所述第一绝缘层为钝化层，所述第二绝缘层为第一平坦层。
可选的，每条所述透明导电线的材料为氧化铟锡。
可选的，所述目标电极为阳极。
可选的，所述像素电路位于所述第二显示区，所述像素电路在所述衬底基 板上的正投影与所述目标电极在所述衬底基板上的正投影至少部分重叠。
可选的，所述像素电路位于所述第一显示区，所述像素电路通过所述透明导电线与所述目标电极连接。
可选的，所述至少一条透明导电线包括：第一透明导电线；
所述第一透明导电线与所述第一金属层连接，被配置为传输电源信号，位于同一列且相邻的两个所述像素电路中的所述第一透明导电线为一体结构。
可选的，所述至少一条透明导电线包括：第二透明导电线；
所述第二透明导电线与所述第二金属层连接，被配置为传输数据信号，位于同一列且相邻的两个所述像素电路中的所述第二透明导电线为一体结构。
可选的，所述像素电路还包括：位于所述第二金属层远离所述衬底基板一侧的第三绝缘层，以及位于所述衬底基板与所述第一金属层之间，且沿远离所述衬底基板的方向依次层叠的晶体管图案层、第三金属层、第四金属层和第四绝缘层。
可选的，所述第三绝缘层为第二平坦层，所述第三金属层为第一栅极金属层，所述第四金属层为第二栅极金属层，所述第四绝缘层为层间介定层。
可选的，所述第三金属层包括第一部分、第二部分和第三部分；所述至少一条透明导电线包括：第三透明导电线、第四透明导电线和第五透明导电线；
所述第三透明导电线与所述第一部分连接，被配置为传输发光控制信号，位于同一行且相邻的两个所述像素电路中的所述第三透明导电线为一体结构；
所述第四透明导电线与所述第二部分连接，被配置为传输栅极驱动信号，位于同一行且相邻的两个所述像素电路中的所述第四透明导电线为一体结构；
所述第五透明导电线与所述第三部分连接，被配置为传输复位信号，位于同一行且相邻的两个所述像素电路中的所述第五透明导电线为一体结构。
可选的，所述至少一条透明导电线包括：第六透明导电线；
所述第六透明导电线与所述第四金属层连接，被配置为传输初始信号，位于同一行且相邻的两个所述像素电路中的所述第六透明导电线为一体结构。
可选的，所述第二显示区为透光显示区。
可选的，所述第一显示区的分辨率大于或等于所述第二显示区的分辨率。
可选的，每条所述透明导电线与所述像素电路中的一个金属层通过过孔连接。
另一方面，提供了一种显示基板的制造方法，所述方法包括：
提供衬底基板，所述衬底基板具有第一显示区和第二显示区，且所述第一显示区至少部分围绕所述第二显示区；
在所述衬底基板的一侧形成多个像素，每个所述像素包括相互连接的像素电路和目标电极；
其中，所述像素电路位于所述第一显示区或所述第二显示区，所述目标电极位于所述第二显示区；所述像素电路包括沿远离所述衬底基板的方向依次层叠的第一金属层、第一绝缘层、至少一条透明导电线、第二绝缘层和第二金属层，每条所述透明导电线与所述像素电路中的一个金属层连接。
又一方面，提供了一种显示装置，所述显示装置包括：集成电路，以及如上述方面所述的显示基板；
所述集成电路与所述显示基板中像素电路所包括的透明导电线电连接，所述集成电路用于向所述透明导电线提供信号。
可选的，所述显示装置还包括：感光传感器，且所述感光传感器位于所述显示基板的第二显示区内。
可选的，所述第二显示区为矩形，所述感光传感器在所述衬底基板上的正投影面积小于等于所述第二显示区的内切圆的面积。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示基板的结构示意图；
图2是本申请实施例提供的另一种显示基板的结构示意图；
图3是本申请实施例提供的又一种显示基板的结构示意图；
图4是本申请实施例提供的一种像素电路的层级结构示意图；
图5是本申请实施例提供的另一种像素电路的层级结构示意图；
图6是本申请实施例提供的又一种像素电路的层级结构示意图；
图7是本申请实施例提供的再一种显示基板的结构示意图；
图8是本申请实施例提供的再一种显示基板的结构示意图；
图9是本申请实施例提供的一种包括过孔的像素电路层级结构示意图；
图10是本申请实施例提供的另一种包括过孔的像素电路层级结构示意图；
图11是本申请实施例提供的又一种包括过孔的像素电路层级结构示意图；
图12是本申请实施例提供的再一种显示基板的结构示意图；
图13是本申请实施例提供的一种显示基板的制造方法流程图；
图14是本申请实施例提供的另一种显示基板的制造方法流程图；
图15是本申请实施例提供的一种包括晶体管图案层的显示基板结构版图；
图16是本申请实施例提供的一种包括晶体管图案层和第一栅极金属层的显示基板结构版图；
图17是本申请实施例提供的一种包括晶体管图案层、第一栅极金属层和第二栅极金属层的显示基板结构版图；
图18是本申请实施例提供的一种包括晶体管图案层、第一栅极金属层、第二栅极金属层和过孔的显示基板结构版图；
图19是本申请实施例提供的一种包括晶体管图案层、第一栅极金属层、第二栅极金属层、过孔和第一源漏极金属层的显示基板结构版图；
图20是本申请实施例提供的另一种包括晶体管图案层、第一栅极金属层、第二栅极金属层、过孔和第一源漏极金属层的显示基板结构版图；
图21是本申请实施例提供的一种包括晶体管图案层、第一栅极金属层、第二栅极金属层、过孔、第一源漏极金属层和透明导电线的显示基板结构版图；
图22是本申请实施例提供的另一种包括晶体管图案层、第一栅极金属层、第二栅极金属层、过孔、第一源漏极金属层和透明导电线的显示基板结构版图；
图23是本申请实施例提供的一种包括晶体管图案层、第一栅极金属层、第二栅极金属层、过孔、第一源漏极金属层、透明导电线和第二源漏极金属层的显示基板结构版图；
图24是本申请实施例提供的另一种包括晶体管图案层、第一栅极金属层、第二栅极金属层、过孔、第一源漏极金属层、透明导电线和第二源漏极金属层的显示基板结构版图；
图25是本申请实施例提供的一种包括晶体管图案层、第一栅极金属层、第二栅极金属层、过孔、第一源漏极金属层、透明导电线、第二源漏极金属层和 阳极的显示基板结构版图；
图26是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1是本申请实施例提供的一种显示基板的结构示意图。如图1所示，该显示基板可以包括：衬底基板00，该衬底基板00可以具有第一显示区A1和第二显示区A2，且该第一显示区A1可以至少部分围绕第二显示区A2。
例如，参考图1，其示出的第二显示区A2位于衬底基板00的顶部正中间位置，相应的，呈矩形的第二显示区A2的四侧可以均被第一显示区A1围绕，即第二显示区A2可以被第一显示区A1包围。
在一些实施例中，该第二显示区A2也可以不位于图1所示衬底基板00的顶部正中间位置处，而是位于其他位置。例如，结合图1，第二显示区A2可以位于衬底基板00的左上角位置或右上角位置处。本申请实施例对此不做限定。
可选的，可以设置第一显示区A1为非透光显示区，并设置第二显示区A2为透光显示区。即第一显示区A1不可透光，第二显示区A2可透光。如此，无需在显示基板上进行挖孔处理，可以将感光传感器等所需硬件结构直接设置于第二显示区A2内，为真全面屏(full display)的实现奠定了坚实的基础。
图2是本申请实施例提供的另一种显示基板的结构示意图。图3是本申请实施例提供的又一种显示基板的结构示意图。结合图1至图3可以看出：该显示基板还可以包括：多个像素P1，且每个像素P1均可以包括相互连接的像素电路10和目标电极20。可选的，该像素电路10可以向目标电极20提供驱动信号，以使得该目标电极20与像素P1包括的另一电极之间形成电势差，像素P1发光。
可选的，参考图2和图3，每个像素P1所包括的目标电极20可以均位于第二显示区A2内，由此可以确定多个像素P1均属于第二显示区A2，即均为第二显示区A2内的像素。参考图2，每个像素P1所包括的像素电路10可以均位于第二显示区A2内，即，每个像素P1所包括的像素电路10可以同所连接目标电极20一并内置于第二显示区A2内，也可以称为像素电路内置。或者，参考图3，每个像素P1所包括的像素电路10可以均位于第一显示区A1内，即每个像 素P1所包括的像素电路10可以单独外置于第一显示区A1内，也可以称为像素电路外置。当然，也可以部分像素电路内置，部分像素电路外置。
结合以上对第一显示区A1和第二显示区A2的介绍可知，若将像素电路10外置于第一显示区A1内，可以确保第二显示区A2的透光率较好。当然，若将像素电路10内置于第二显示区A2内，可以简化布线工艺，节省成本。
图4是本申请实施例提供的一种像素电路10的结构示意图。如图4所示，像素电路10可以包括：位于衬底基板00一侧且依次层叠的第一金属层101、第一绝缘层102、至少一条透明导电线L1(图4未示出条数)、第二绝缘层103和第二金属层104，且每条透明导电线L1可以与像素电路10中的一个金属层连接，形成一条信号线，并用于与一个信号端连接。由此，该像素电路10即可以在各信号端提供的信号控制下，向所连接的目标电极20传输驱动信号。此外，目标电极20一般设置于第二金属层104远离第二绝缘层103的一侧，且目标电极20与第二金属层104之间还设置有一绝缘层。
需要说明的是，图1至图3仅是示出了第二显示区A2内的像素P1，为确保显示基板的正常工作，第一显示区A1内也包括多个像素。并且，第一金属层101、第一绝缘层102、第二绝缘层103和第二金属层104为任一显示区内的像素中像素电路所包括的必不可少的层级结构。即，第一绝缘层102和第二绝缘层103为第一金属层101和第二金属层104之间已有的两层绝缘层。透明导电线L1是为确保第二显示区A2的透光率新增的一层结构。
由于为避免相邻的两层导电层之间信号互相干扰，相邻的两层导电层之间一般均需要设置至少一层绝缘层。因此，结合目标电极20和第二金属层104的设置位置，若将透明导电线L1设置于第二金属层104远离衬底基板00的一侧，则需要再多设置一层绝缘层将目标电极与透明导电线L1隔开，或，将第二金属层104与透明导电线L1隔开。而本申请实施例中，因将透明导电线L1设置于已有的两层绝缘层之间，故可以至少节省一层绝缘层的设置。且因各层一般均是采用掩膜版(mask)工艺制成，故可以至少节省一道MASK工艺。由此即可以确定，本申请实施例提供的显示基板结构简单，且制造成本较低。
综上所述，本申请实施例公开了一种显示基板，该显示基板包括具有第一显示区和第二显示区的衬底基板，该第二显示区内的像素所包括的像素电路中，与金属层连接的导电线为透明导电线，且该透明导电线位于已有的两层绝缘层 之间。如此，相对于透明导电线位于其他位置的显示基板，本申请实施例提供的显示基板不仅确保了第二显示区的透光率较好，而且结构较为简单，制造成本较低。
可选的，本申请实施例记载的目标电极20可以为阳极(anode)。相应的，上述实施例记载的另一电极即可以为阴极。当然，目标电极20也可以为阴极，相应的，上述实施例记载的另一电极即可以为阳极。
可选的，本申请实施例记载的每条透明导电线L1的材料可以为氧化铟锡(indium tin oxide，ITO)，如此，每条透明导电线L1也可以称为ITO走线。在一些实施例中，透明导电线L1的材料也可以为铟镓锌氧化物(indium gallium zinc oxide，IGZO)等其他透明且可导电的材料。本申请下述实施例均以透明导电线L1为ITO走线进行说明。
图5是本申请实施例提供的另一种像素电路的结构示意图。结合图4和图5可以看出：本申请实施例记载的第一金属层101可以为第一源漏极(source&drain，SD)金属层，简称SD1。第二金属层104可以为第二源漏极金属层SD2，第一绝缘层102可以为钝化层(passivation，PVX)，第二绝缘层103可以为第一平坦层(planarization，PLN)，简称PLN1。即，本申请实施例记载的至少一条透明导电线L1可以位于钝化层PVX和第一平坦层PLN1之间。
由于在工艺过程中，一般是沿远离衬底基板00的方向依次形成各层结构，因此可以确定：本申请实施例记载的至少一条透明导电线L1是在形成第一源漏极金属层SD1及钝化层PVX之后，且在形成第一平坦层PLN1之前，形成于钝化层PVX远离第一源漏极金属层SD1一侧的。即，可以在形成钝化层PVX之后，且在形成第一平坦层PLN1之前，进行透明导电线L1制造工艺。此外，结合图5，可以是先形成一层ITO层，再通过构图工艺得到一条或多条ITO走线。
可选的，图6是本申请实施例提供的又一种像素电路的结构示意图。如图6所示，像素电路10还可以包括：位于第二金属层104远离衬底基板00一侧的第三绝缘层105，以及位于衬底基板00与第一金属层101之间，且沿远离衬底基板00的方向依次层叠的晶体管图案层106、第三金属层107、第四金属层108和第四绝缘层109。
可选的，继续参考图6，晶体管图案层106可以为多晶硅(poly)材料层， 简称POLY层。第三绝缘层105可以为第二平坦层PLN2。第三金属层107可以为第一栅极(gate)金属层，简称GATE1。第四金属层108可以为第二栅极金属层GATE2，第四绝缘层109可以为层间介定层(interlayer，ILD)。此外，第一栅极金属层GATE1和第二栅极金属层GATE2之间一般也包括绝缘层。
可选的，继续参考图6，因晶体管图案层106、第三金属层107和第四金属层108均为导电材料，故为避免相邻两层导电层之间的信号相互干扰，该像素电路10还可以包括：位于晶体管图案层106与第三金属层107(即，第一栅极金属层GATE1)之间的绝缘层110，以及位于第三金属层107和第四金属层108(即，第二栅极金属层GATE2)之间的绝缘层111。
可选的，图7是本申请实施例提供的再一种显示基板的结构示意图。如图7所示，第一栅极金属层GATE1可以包括第一部分B1、第二部分B2和第三部分B3。至少一条透明导电线L1可以包括：第一透明导电线L11、第二透明导电线L12、第三透明导电线L13、第四透明导电线L14、第五透明导电线L15和第六透明导电线L16。
其中，该第一透明导电线L11可以与第一金属层101(即第一源漏极金属层SD1)连接，且被配置为传输电源信号。即，如图7所示，该第一透明导电线L11还可以用于与电源端VDD连接，电源端VDD可以通过第一透明导电线L11向第一源漏极金属层SD1传输电源信号。换言之，第一透明导电线L11与第一源漏极金属层SD1连接可以形成电源信号线，像素电路10可以接收来自电源信号线的电源信号。
可选的，结合图8示出的再一种显示基板可以看出，位于同一列且相邻的两个像素电路10中的第一透明导电线L11可以为一体结构。换言之，同一列像素电路10可以共用同一条电源信号线，即与同一个直流电源端VDD连接。
该第二透明导电线L12可以与第二金属层104(即第二源漏极金属层SD2)连接，且被配置为传输数据信号。即，如图7所示，该第二透明导电线L12还可以用于与数据信号端DATA连接，数据信号端DATA可以通过第二透明导电线L12向第二源漏极金属层SD2传输数据信号。换言之，第二透明导电线L12与第二源漏极金属层SD2连接可以形成数据信号线，像素电路10可以接收来自数据信号线的数据信号。
可选的，依然结合图8可以看出，位于同一列且相邻的两个像素电路10中 的第二透明导电线L12可以为一体结构。换言之，同一列像素电路10可以共用同一条数据信号线，即与同一个数据信号端DATA连接。
第三透明导电线L13可以与第一栅极金属层GATE1的第一部分B1连接，且被配置为传输发光控制信号。即，如图7所示，该第三透明导电线L13还可以用于与发光控制信号端EM连接，发光控制信号端EM可以通过第三透明导电线L13向第一栅极金属层GATE1传输发光控制信号。换言之，第三透明导电线L13与第一栅极金属层GATE1的第一部分B1连接可以形成发光控制信号线，像素电路10可以接收来自发光控制信号线的发光控制信号。
可选的，结合图8示出的再一种显示基板可以看出，位于同一行且相邻的两个像素电路10中的第三透明导电线L13可以为一体结构。换言之，同一行像素电路10可以共用同一条发光控制信号线，即与同一个发光控制信号端EM连接。
第四透明导电线L14可以与第一栅极金属层GATE1的第二部分B2连接，且被配置为传输栅极驱动信号。即，如图7所示，第四透明导电线L14还可以用于与栅极信号端G1连接，栅极信号端G1可以通过第四透明导电线L14向第一栅极金属层GATE1传输栅极驱动信号。换言之，第四透明导电线L14与第一栅极金属层GATE1的第二部分B2连接可以形成栅线，像素电路10可以接收来自栅线的栅极驱动信号。
可选的，结合图8示出的再一种显示基板可以看出，位于同一行且相邻的两个像素电路10中的第四透明导电线L14可以为一体结构。换言之，同一行像素电路10可以共用同一条栅线，即与同一个栅极信号端G1连接。
第五透明导电线L15可以与第一栅极金属层GATE1的第三部分B3连接，且被配置为传输复位信号。即，如图7所示，第五透明导电线L15还可以用于与复位信号端RST连接，复位信号端RST可以通过第五透明导电线L15向第一栅极金属层GATE1传输复位信号。换言之，第五透明导电线L15与第一栅极金属层GATE1的第三部分B3连接可以形成复位信号线，像素电路10可以接收来自复位信号线的复位信号。
可选的，结合图8示出的再一种显示基板可以看出，位于同一行且相邻的两个像素电路10中的第五透明导电线L15可以为一体结构。换言之，同一行像素电路10可以共用同一条复位信号线，即与同一个复位信号端RST连接。
第六透明导电线L16可以与第四金属层108(即第二栅极金属层GATE2)连接，且被配置为传输初始信号。即，如图7所示，第六透明导电线L16还可以用于与初始信号端Vinit连接，初始信号端Vinit可以通过第六透明导电线L16向第二栅极金属层GATE2传输初始信号。换言之，第六透明导电线L16与第二栅极金属层GATE2连接可以形成初始信号线，像素电路10可以接收来自初始信号线的初始信号。
可选的，结合图8示出的再一种显示基板可以看出，位于同一行且相邻的两个像素电路10中的第六透明导电线L16可以为一体结构。换言之，同一行像素电路10可以共用同一条初始信号线，即与同一个初始信号端Vinit连接。在一些实施例中，第二显示区A2内的所有像素P1所包括的像素电路10均可以与同一个初始信号端Vinit连接。
需要说明的是，结合图7和图8，像素电路10其实可以包括多个晶体管，以上实施例记载的像素电路10接收信号均是指晶体管接收信号。在上述信号的驱动下，像素电路10可以可靠工作，并向所连接的目标电极20传输驱动信号。
还需要说明的是，结合图8，为进一步确保第二显示区A2的透光率，第二显示区A2内的行和列不是严格意义上的并排对齐。此外，因一个像素电路10的上下左右均可能相邻另一像素电路10，故结合图7和图8可以看出，每类透明导电线均可以划分为两部分，一部分与相邻的一个像素电路10的对应类型透明导电线一体成型，另一部分与相邻的另一个像素电路10的对应类型透明导电线一体成型。
例如，以第一透明导电线L11为例，参考图7和图8可以看出，位于中心位置的像素电路10的第一透明导电线L11可以包括上半部分L11_1，以及下半部分L11_2。其中，上半部分L11_1与上方相邻的像素电路10的第一透明导电线L11的下半部分L11_2为一体结构；下半部分L11_2与下方相邻的像素电路10的第一透明导电线L11的上半部分L11_1为一体结构。
可选的，在本申请实施例中，每条透明导电线L1与像素电路10中的一个金属层均可以通过过孔连接。
例如，以透明导电线L1与第一源漏极金属层SD1和第二源漏极金属层SD2连接为例，图9示出了包括过孔K1的结构版图。参考图9可以看出，钝化层PVX和第一平坦层PLN1中均包括过孔K1，透明导电线L1与第一源漏极金属 层SD1可以通过开设于钝化层PVX中的过孔K1连接；透明导电线L1与第二源漏极金属层SD2可以通过开设于第一平坦层PLN1中的过孔K1连接。
又例如，以透明导电线L1与第一栅极金属层GATE1连接为例，图10示出了包括过孔K1的结构版图。参考图10可以看出，透明导电线L1与第一栅极金属层GATE1之间的钝化层PVX、第一源漏极金属层SD1、层间介定层ILD和第二栅极金属层GATE2中具有过孔K1，且该过孔K1贯穿钝化层PVX、第一源漏极金属层SD1、层间介定层ILD和第二栅极金属层GATE2。透明导电线L1与第一栅极金属层GATE1可以通过该过孔K1连接。
再例如，以透明导电线L1与第二栅极金属层GATE2连接为例，图11示出了包括过孔K1的结构版图。参考图11可以看出，透明导电线L1与第二栅极金属层GATE2之间的钝化层PVX、第一源漏极金属层SD1和层间介定层ILD中具有过孔K1，且该过孔K1贯穿钝化层PVX、第一源漏极金属层SD1和层间介定层ILD。透明导电线L1与第二栅极金属层GATE2可以通过该过孔K1连接。
结合以上实施例记载可知，由于本申请实施例记载的透明导电线L1位于钝化层PVX和第一平坦层PLN1之间，因此上述开设的各个过孔K1的深度均较浅，易形成良性接触，确保连接可靠性。
可选的，结合图2，像素电路10可以位于第二显示区A2，即像素电路10可以内置。如此，像素电路10在衬底基板00上的正投影与目标电极20在衬底基板00上的正投影可以至少部分重叠，相应的，像素电路10与目标电极20连接可以为像素电路10与目标电极20可以通过过孔连接。
例如，图7所示显示基板中，像素电路10在衬底基板00上的正投影覆盖目标电极20在衬底基板00上的正投影。
可选的，结合图3，像素电路10可以位于第一显示区A1。如此，像素电路10可以通过透明导电线L1与目标电极20连接。例如，可以设置第二源漏极金属层SD2通过过孔与透明导电线L1连接，以及设置透明导电线L1与目标电极20连接。由此，可以确保第二源漏极金属层SD2与目标电极20的可靠连接。
可选的，在本申请实施例中，因衬底基板00具有可透光的显示区，即第二显示区A2，则如图12所示，显示装置包括的显示模组中的感光传感器001(如，摄像头)，可以直接设置于该第二显示区A2内，即无需在显示面板上额外挖孔。如此，为全面屏显示面板的实现奠定了坚实的基础。
可选的，第二显示区A2可以为矩形，感光传感器001在衬底基板00上的正投影的面积可以小于或等于第二显示区A2的内切圆的面积。即，感光传感器001所处区域的尺寸可以小于或等于该第二显示区A2的内切圆的尺寸。例如，结合图12，其示出的显示面板中，感光传感器001所处区域的尺寸等于第二显示区A2的内切圆Y0的尺寸，即该感光传感器001所在区域的形状可以为圆形，相应的，该感光传感器001所在区域也可以称为透光孔。当然，在一些实施例中，第二显示区A2也可以为除矩形之外的其他形状，如圆形或椭圆形。
可选的，第一显示区A1的分辨率可以大于第二显示区A2的分辨率。即，该第一显示区A1的面积相对于第二显示区A2的面积较大，且第一显示区A1所包括的像素相对于第二显示区A2所包括的像素的数量较多。且，位于第二显示区A2的多个像素P1，与位于第一显示区A1的多个像素的密度可以不同。即，第一显示区A1和第二显示区A2内每英寸所包括的像素数量不同。
在一些实施例中，第一显示区A1的分辨率可以小于等于第二显示区A2的分辨率。例如，第一显示区A1的面积与第二显示区A2的面积可以相同，且第一显示区A1所包括的单位面积的像素与第二显示区A2所包括的单位面积的像素数量相同。或者，第一显示区A1的面积可以小于第二显示区A2的面积，且第一显示区A1所包括的单位面积的像素相对于第二显示区A2所包括的单位面积的像素的数量较少。
综上所述，本申请实施例公开了一种显示基板，该显示基板包括具有第一显示区和第二显示区的衬底基板，该第二显示区内的像素所包括的像素电路中，与金属层连接的导电线为透明导电线，且该透明导电线位于已有的两层绝缘层之间。如此，相对于透明导电线位于其他位置的显示基板，本申请实施例提供的显示基板不仅确保了第二显示区的透光率较好，而且结构较为简单，制造成本较低。
图13是本申请实施例提供的一种显示基板的制造方法流程图，该方法可以用于制造如图1至图3、图7、图8和图12任一所示的显示基板。如图13所示，该方法可以包括：
步骤1301、提供衬底基板。
其中，结合上述图1，该衬底基板可以具有第一显示区A1和第二显示区 A2，且该第一显示区A1可以至少部分围绕第二显示区A2。
步骤1302、在衬底基板的一侧形成多个像素。
其中，结合图2和图3，每个像素P1可以包括相互连接的像素电路10和目标电极20。其中，像素电路10可以位于第一显示区A1或第二显示区A2，目标电极20可以位于第二显示区A2。且，参考图4，像素电路10可以包括沿远离衬底基板00的方向依次层叠的第一金属层101、第一绝缘层102、至少一条透明导电线L2、第二绝缘层103和第二金属层104，每条透明导电线L1可以与像素电路10中的一个金属层连接。
可选的，以图6和图7示出的像素电路10，目标电极为阳极，且像素电路内置为例，图14示出了本申请实施例提供的另一种显示基板的制造方法流程图。如图14所示，该方法可以包括：
步骤1401、提供衬底基板。
可选的，可以先提供一衬底基板作为载体，且该衬底基板可以至少具有第一显示区，以及被第一显示区至少部分围绕的第二显示区。该衬底基板可以为玻璃基板或者柔性基板。
步骤1402、在衬底基板的一侧形成晶体管图案层。
可选的，在得到衬底基板后，可以先在衬底基板的一侧通过构图工艺形成晶体管图案层。可选的，该构图工艺可以包括：涂胶、曝光、显影和刻蚀。
例如，图15示出了形成有晶体管图案层，即POLY层的衬底基板00的结构示意图。
步骤1403、在晶体管图案层远离衬底基板的一侧形成第一栅极金属层。
可选的，在形成晶体管图案层之后，可以继续在晶体管图案层远离衬底基板的一侧形成第一栅极金属层。
例如，图16示出了形成有第一栅极金属层GATE1的衬底基板00的结构示意图。
步骤1404、在第一栅极金属层远离晶体管图案层的一侧形成第二栅极金属层。
可选的，在形成第一栅极金属层之后，可以再继续在第一栅极金属层远离晶体管图案层的一侧形成第二栅极金属层。
例如，图17示出了形成有第二栅极金属层GATE2的衬底基板00的结构示 意图。
步骤1405、在第二栅极金属层远离第一栅极金属层的一侧形成层间介定层。
可选的，在形成第二栅极金属层之后，可以再继续在第二栅极金属层远离第一栅极金属层的一侧形成层间介定层。且在形成层间介定层之后，可以对该层间介定层进行处理，得到多个连接过孔。
例如，图18示出了在第二栅极金属层GATE2上形成的过孔K1的衬底基板00的结构示意图。
步骤1406、在层间介定层远离第二栅极金属层的一侧形成第一源漏极金属层。
可选的，在形成层间介定层之后，可以再继续在层间介定层远离第二栅极金属层的一侧形成第一源漏极金属层。
例如，图19示出了在过孔K1上形成的第一源漏极金属层SD1的衬底基板00的结构示意图。
步骤1407、在第一源漏极金属层远离层间介定层的一侧形成钝化层。
可选的，在形成第一源漏极金属层之后，可以再继续在第一源漏极金属层远离层间介定层的一侧形成钝化层。且在形成钝化层之后，可以对该钝化层进行处理，再得到多个连接过孔。
例如，图20示出了在第一源漏极金属层SD1上形成的过孔K1的衬底基板00的结构示意图。
步骤1408、在钝化层远离第一源漏极金属层的一侧形成至少一条透明导电线。
可选的，在形成钝化层之后，可以再继续在钝化层远离第一源漏极金属层的一侧形成一层透明导电层，再对该透明导电层进行处理得到一条或多条透明导电线。
例如，图21示出了在过孔K1上形成的多条第一透明导电线L1的衬底基板00的结构示意图。
步骤1409、在至少一条透明导电线远离钝化层的一侧形成第一平坦层。
可选的，在形成至少一条透明导电线之后，可以再继续在至少一条透明导电线远离钝化层的一侧形成第一平坦层。且在形成第一平坦层之后，可以对该第一平坦层进行处理，再得到多个连接过孔。
例如，图22示出了在至少一条透明导电线L1上形成的过孔K1的衬底基板00的结构示意图。
步骤14010、在第一平坦层远离至少一条透明导电线的一侧形成第二源漏极金属层。
可选的，在形成第一平坦层之后，可以再继续在第一平坦层远离至少一条透明导电线的一侧形成第二源漏极金属层。
例如，图23示出了在过孔K1上形成的第二源漏极金属层SD2的衬底基板00的结构示意图。
步骤14011、在第二源漏极金属层远离在第一平坦层的一侧形成在第二平坦层。
可选的，在形成第二源漏极金属层之后，可以再继续在第二源漏极金属层远离在第一平坦层的一侧形成第二平坦层。且在形成第二平坦层之后，可以对该第二平坦层进行处理，再得到多个连接过孔。
例如，图24示出了在第二源漏极金属层SD2上形成的过孔K1的衬底基板00的结构示意图。
步骤14012、在第二平坦层远离第二源漏极金属层的一侧形成阳极。
可选的，在形成第二平坦层之后，可以再继续在第二平坦层远离第二源漏极金属层的一侧形成阳极。
例如，图25示出了在过孔K1上形成的阳极ANODE的衬底基板00的结构示意图。且，该阳极ANODE可以通过过孔K1与第二源漏极金属层SD2连接。
即，基于图14至图25可以确定，本申请实施例制造显示基板的工艺顺序为：POLY-GATE1-GATE2-ILD-SD1-PVX-ITO-PLN1-SD2-PLN2-ANODE。
需要说明的是，对于每个层级结构而言，图15至图25中仅分别标识出一个标号，填充颜色相同的为同一个层级。
还需要说明的是，结合图6，因晶体管图案层106和第一栅极金属层GATE1之间，以及第一栅极金属层GATE1和第二栅极金属层GATE2之间均包括绝缘层，故在执行步骤1403之前，还可以包括在晶体管图案层远离衬底基板的一侧先形成绝缘层的步骤。以及在执行步骤1404之前，还可以包括在第一栅极金属层远离晶体管图案层的一侧先形成绝缘层的步骤。
综上所述，本申请实施例公开了一种显示基板的制造方法。该方法中，透 明导电线是在形成钝化层之后，且在形成第一平坦层之间形成。由于该钝化层和第一平坦层是已有的两层绝缘层，因此相对于在其他位置处形成透明导电线，本申请实施例提供的方法不仅确保了第二显示区的透光率较好，而且制造得到的显示基板结构较为简单，制造成本较低。
可选的，图26是本申请实施例提供的一种显示装置的结构示意图。如图26所示，该显示装置可以包括：集成电路100，以及如图1至图3、图7、图8和图12任一所示的显示基板200。
结合上述附图可知，集成电路100可以与显示基板200中像素电路10所包括的透明导电线L1电连接，集成电路100可以用于向透明导电线L1提供信号。
示例的，结合图7，集成电路100可以与各条透明导电线L1所连接的信号端电连接，并向该各信号端提供信号，以间接向透明导电线L1提供信号。
需要说明的是，图26仅是示意性示出集成电路100的位置，集成电路100也可以位于显示基板200的右侧，也可以既位于显示基板200的左侧又位于显示基板200的右侧。或者，还可以位于显示基板200的上侧和/或下侧。
可选的，该显示装置可以为：有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置，液晶显示装置、手机、电脑、电视机、显示器、电子纸、数码相框或导航仪等任何具有显示功能的产品或部件。
应当理解的是，在本文中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板，具有第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区；
    多个像素，每个所述像素包括相互连接的像素电路和目标电极，所述像素电路位于所述第一显示区或所述第二显示区，所述目标电极位于所述第二显示区；所述像素电路包括：位于所述衬底基板一侧且依次层叠的第一金属层、第一绝缘层、至少一条透明导电线、第二绝缘层和第二金属层，每条所述透明导电线与所述像素电路中的一个金属层连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一金属层为第一源漏极金属层，所述第二金属层为第二源漏极金属层，所述第一绝缘层为钝化层，所述第二绝缘层为第一平坦层。
  3. 根据权利要求1所述的显示基板，其中，每条所述透明导电线的材料为氧化铟锡。
  4. 根据权利要求1所述的显示基板，其中，所述目标电极为阳极。
  5. 根据权利要求1所述的显示基板，其中，所述像素电路位于所述第二显示区，所述像素电路位于所述第二显示区，所述像素电路在所述衬底基板上的正投影与所述目标电极在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求1所述的显示基板，其中，所述像素电路位于所述第一显示区，所述像素电路通过所述透明导电线与所述目标电极连接。
  7. 根据权利要求1至6任一所述的显示基板，其中，所述至少一条透明导电线包括：第一透明导电线；
    所述第一透明导电线与所述第一金属层连接，被配置为传输电源信号，位 于同一列且相邻的两个所述像素电路中的所述第一透明导电线为一体结构。
  8. 根据权利要求1至7任一所述的显示基板，其中，所述至少一条透明导电线包括：第二透明导电线；
    所述第二透明导电线与所述第二金属层连接，被配置为传输数据信号，位于同一列且相邻的两个所述像素电路中的所述第二透明导电线为一体结构。
  9. 根据权利要求1至8任一所述的显示基板，其中，所述像素电路还包括：位于所述第二金属层远离所述衬底基板一侧的第三绝缘层，以及位于所述衬底基板与所述第一金属层之间，且沿远离所述衬底基板的方向依次层叠的晶体管图案层、第三金属层、第四金属层和第四绝缘层。
  10. 根据权利要求9所述的显示基板，其中，所述第三绝缘层为第二平坦层，所述第三金属层为第一栅极金属层，所述第四金属层为第二栅极金属层，所述第四绝缘层为层间介定层。
  11. 根据权利要求10所述的显示基板，其中，所述第三金属层包括第一部分、第二部分和第三部分；所述至少一条透明导电线包括：第三透明导电线、第四透明导电线和第五透明导电线；
    所述第三透明导电线与所述第一部分连接，被配置为传输发光控制信号，位于同一行且相邻的两个所述像素电路中的所述第三透明导电线为一体结构；
    所述第四透明导电线与所述第二部分连接，被配置为传输栅极驱动信号，位于同一行且相邻的两个所述像素电路中的所述第四透明导电线为一体结构；
    所述第五透明导电线与所述第三部分连接，被配置为传输复位信号，位于同一行且相邻的两个所述像素电路中的所述第五透明导电线为一体结构。
  12. 根据权利要求11所述的显示基板，其中，所述至少一条透明导电线包括：第六透明导电线；
    所述第六透明导电线与所述第四金属层连接，被配置为传输初始信号，位于同一行且相邻的两个所述像素电路中的所述第六透明导电线为一体结构。
  13. 根据权利要求1至12任一所述的显示基板，其中，所述第二显示区为透光显示区。
  14. 根据权利要求1至13任一所述的显示基板，其中，所述第一显示区的分辨率大于或等于所述第二显示区的分辨率。
  15. 根据权利要求1至14任一所述的显示基板，其中，每条所述透明导电线与所述像素电路中的一个金属层通过过孔连接。
  16. 根据权利要求11所述的显示基板，其中，所述第一金属层为第一源漏极金属层，所述第二金属层为第二源漏极金属层，所述第一绝缘层为钝化层，所述第二绝缘层为第一平坦层；每条所述透明导电线的材料为氧化铟锡；所述目标电极为阳极；
    所述像素电路位于所述第二显示区；所述像素电路在所述衬底基板上的正投影与所述目标电极在所述衬底基板上的正投影至少部分重叠；或者，所述像素电路位于所述第一显示区，所述像素电路通过所述透明导电线与所述目标电极连接；
    所述至少一条透明导电线包括：第一透明导电线、第二透明导电线和第六透明导电线；所述第一透明导电线与所述第一金属层连接，被配置为传输电源信号，位于同一列且相邻的两个所述像素电路中的所述第一透明导电线为一体结构；所述第二透明导电线与所述第二金属层连接，被配置为传输数据信号，位于同一列且相邻的两个所述像素电路中的所述第二透明导电线为一体结构；所述第六透明导电线与所述第四金属层连接，被配置为传输初始信号，位于同一行且相邻的两个所述像素电路中的所述第六透明导电线为一体结构；所述第二显示区为透光显示区；所述第一显示区的分辨率大于或等于所述第二显示区的分辨率；每条所述透明导电线与所述像素电路中的一个金属层通过过孔连接。
  17. 一种显示基板的制造方法，其中，所述方法包括：
    提供衬底基板，所述衬底基板具有第一显示区和第二显示区，且所述第一 显示区至少部分围绕所述第二显示区；
    在所述衬底基板的一侧形成多个像素，每个所述像素包括相互连接的像素电路和目标电极；
    其中，所述像素电路位于所述第一显示区或所述第二显示区，所述目标电极位于所述第二显示区；所述像素电路包括沿远离所述衬底基板的方向依次层叠的第一金属层、第一绝缘层、至少一条透明导电线、第二绝缘层和第二金属层，每条所述透明导电线与所述像素电路中的一个金属层连接。
  18. 一种显示装置，其中，所述显示装置包括：集成电路，以及如权利要求1至16任一所述的显示基板；
    所述集成电路与所述显示基板中像素电路所包括的透明导电线电连接，所述集成电路用于向所述透明导电线提供信号。
  19. 根据权利要求18所述的显示装置，其中，所述显示装置还包括：感光传感器，且所述感光传感器位于所述显示基板的第二显示区内。
  20. 根据权利要求19所述的显示装置，其中，所述第二显示区为矩形，所述感光传感器在所述衬底基板上的正投影面积小于等于所述第二显示区的内切圆的面积。
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