WO2022226897A1 - 显示面板及其制作方法和显示装置 - Google Patents

显示面板及其制作方法和显示装置 Download PDF

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Publication number
WO2022226897A1
WO2022226897A1 PCT/CN2021/091004 CN2021091004W WO2022226897A1 WO 2022226897 A1 WO2022226897 A1 WO 2022226897A1 CN 2021091004 W CN2021091004 W CN 2021091004W WO 2022226897 A1 WO2022226897 A1 WO 2022226897A1
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WIPO (PCT)
Prior art keywords
redundant
pixel circuits
layer
gate
conductive layer
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PCT/CN2021/091004
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English (en)
French (fr)
Inventor
王彬艳
程羽雕
龙跃
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/091004 priority Critical patent/WO2022226897A1/zh
Priority to CN202180000993.0A priority patent/CN115552617A/zh
Priority to EP21938924.4A priority patent/EP4207297A4/en
Priority to PCT/CN2021/127590 priority patent/WO2022227461A1/zh
Priority to CN202180003180.7A priority patent/CN115552628A/zh
Publication of WO2022226897A1 publication Critical patent/WO2022226897A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • An organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display panel includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light-emitting device stacked on a substrate, and the pixel circuit includes an active layer pattern. Due to the influence of the manufacturing process, during the manufacturing process of the pixel circuit, the uniformity of the pixel circuit located in the edge area of the display panel close to the under-screen camera is poor, which leads to the problem of threshold voltage (Vth) shift of the pixel circuit in this area. As a result, the sub-pixel emits light abnormally (such as dark spots, bright spots or different colors).
  • Vth threshold voltage
  • a display panel in one aspect, includes a main display area and a functional device area, the main display area at least partially surrounds the functional device area.
  • the display panel includes a plurality of first pixel circuits and a plurality of redundant pixel circuits, the plurality of first pixel circuits are located in the main display area; the plurality of redundant pixel circuits are arranged in the main display area.
  • a plurality of first pixel circuits adjacent to the edge of the functional device region are adjacent.
  • the display panel includes an active layer and an anode layer arranged in sequence along a direction perpendicular to the substrate and away from the substrate; the anode layer includes a plurality of first anodes located in the main display area, each first anode and one The first pixel circuit is electrically connected; the redundant pixel circuit includes at least a redundant active layer pattern on the active layer, and the redundant pixel circuit is electrically insulated from the anode layer.
  • the first pixel circuits in any row are arranged in a first direction
  • the first pixel circuits in any column are arranged in a second direction
  • the first direction intersects with the second direction.
  • 2 to 4 redundant pixel circuits are arranged along the first direction; 2-4 redundant pixel circuits arranged along the second direction are arranged on the edge of any column of the first pixel circuits intersecting with the functional device regions, which is close to the functional device region.
  • the main display area is close to the edge of the functional device area, and/or, the edge of the functional device area close to the main display area is a transition area, and the plurality of redundant pixel circuits are located in the transition area.
  • the transition zone includes at least a first linear extension section and two second linear extension sections; the first linear extension section is located at an edge of the transition area in the second direction, and the first linear extension section is provided with at least Two rows of redundant pixel circuits; two second straight extending sections are respectively located at two edges of the transition region in the first direction, and each second straight extending section is provided with at least two columns of redundant pixel circuits.
  • the transition area further includes four polyline extension segments; each line segment is provided with multiple rows of redundant pixel circuits, and the multiple rows of redundant pixel circuits located in different line segments are staggered in the first direction, and the first The straight line extension segment and the second straight line extension segment are connected by the polyline extension segment.
  • the transition area is an annular shape with one side open, and the opening is located at an edge of the transition area opposite to the first straight segment.
  • the transition area further includes a third straight line extension section, the third straight line extension section is located at an edge of the transition area opposite to the first straight line section, and the third straight line extension section includes at least two rows of redundant pixel circuits;
  • the transition zone is a closed annular shape.
  • the pattern formed by the plurality of redundant pixel circuit arrangements is symmetrical with respect to a straight line along the first direction of the transition region; and/or, the plurality of redundant pixel circuit arrangements are formed
  • the graph of is symmetrical with respect to a straight line along the second direction of the transition zone.
  • the first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor; the active layer further includes a first active layer pattern of the plurality of first thin film transistors.
  • the display panel further includes a first gate conductive layer, a second gate conductive layer, and a source-drain conductive layer.
  • a first gate conductive layer is disposed between the active layer and the anode layer, and includes a first gate pattern of the plurality of first pixel circuits, and the first gate pattern includes the first plurality of first pixel circuits.
  • the second gate conductive layer is disposed between the first gate conductive layer and the anode layer, and includes a second gate pattern of the plurality of first pixel circuits, and the second gate pattern includes the first gate pattern.
  • a source-drain conductive layer is disposed between the second gate conductive layer and the anode layer, and includes source-drain conductive patterns of the plurality of first pixel circuits, and the source-drain conductive patterns include the plurality of first thin films Source and drain of transistors, data lines, and voltage signal lines.
  • the orthographic projections of the entire pattern of the first gate conductive layer, the entire pattern of the second gate conductive layer, and the entire pattern of the source-drain conductive layer on the substrate are the same as the orthographic separation of the redundant active layer pattern on the substrate.
  • the display panel further includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer.
  • the first gate insulating layer is arranged between the active layer and the first gate conductive layer;
  • the second gate insulating layer is arranged between the first gate conductive layer and the second gate conductive layer;
  • the interlayer An insulating layer is disposed between the second gate conductive layer and the source-drain conductive layer.
  • the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer all cover the redundant active layer pattern; and the first gate insulating layer, the second gate insulating layer and the The interlayer insulating layer is provided with a plurality of via holes, the via holes pass through the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and the via holes are located in the lining
  • the orthographic projection on the bottom is located within the orthographic projection range of the redundant active layer pattern on the substrate.
  • the display panel further includes a passivation layer disposed between the source-drain conductive layer and the anode layer and covering the redundant active layer pattern.
  • the material of the passivation layer is filled in the plurality of via holes.
  • the redundant pixel circuit includes a plurality of redundant thin film transistors and redundant storage capacitors.
  • the first gate conductive layer further includes a first redundant gate pattern of the plurality of redundant pixel circuits, and the first redundant gate pattern includes gates of the plurality of redundant thin film transistors and the plurality of redundant thin film transistors. The first plate of the redundant storage capacitor.
  • the second gate conductive layer further includes a second redundant gate pattern of the plurality of redundant pixel circuits, the second redundant gate pattern including a second plate of the redundant storage capacitor.
  • the source-drain conductive layer further includes redundant source-drain conductive patterns of the plurality of redundant pixel circuits, and the redundant source-drain conductive patterns include the source and drain electrodes of the plurality of redundant thin film transistors, and data lines. , and a voltage signal line; the redundant source-drain conductive pattern is electrically insulated from the anode layer.
  • the redundant active layer patterns are separated from each other, the first redundant gate patterns are connected, and the second redundant gate patterns are connected; the The first direction is the row direction in which the plurality of first pixel circuits are arranged.
  • the redundant active layer patterns are separated from each other, and the redundant source-drain conductive patterns are connected; the second direction is the column direction in which the plurality of first pixel circuits are arranged .
  • the display panel further includes a plurality of second pixel circuits, and the plurality of second pixel circuits are disposed in areas of the display panel other than the functional device area.
  • the anode layer further includes a plurality of second anodes, the plurality of second anodes are located in the functional device region, and each second anode is electrically connected to a second pixel circuit.
  • the display panel further includes a transfer conductive layer, and the transfer conductive layer is located between the film layer where the plurality of first pixel circuits and the plurality of second pixel circuits are located and the anode layer, including multiple A plurality of transfer blocks are separated from each other; the plurality of transfer blocks include a first transfer block electrically connected with the first pixel circuit, and a second transfer block electrically connected with the second pixel circuit.
  • the orthographic projection of the first transition block on the substrate covers the first connection node of the first pixel circuit that is electrically connected to it, and is electrically connected to the first connection node;
  • the first connection node is The first pixel circuit is configured as a node electrically connected to the first anode;
  • the orthographic projection of the second transition block on the substrate covers the second connection node of the second pixel circuit electrically connected to it, and is electrically connected to the second connection node;
  • the second connection node is a node in the second pixel circuit that is configured to be electrically connected to the second anode.
  • the plurality of first pixel circuits and the plurality of second pixel circuits are both located in the main display area.
  • the plurality of second pixel circuits are arranged in a plurality of rows and columns, and a plurality of first pixel circuits are arranged between two adjacent second pixel circuits in the same row.
  • the display panel further includes a bezel area surrounding the main display area.
  • the plurality of second pixel circuits are located in the frame area.
  • the display panel further includes at least one connecting layer; the at least one connecting layer is located between the transfer conductive layer and the anode layer; the connecting layer includes a plurality of connecting lines, one end of the connecting lines The second transition block is electrically connected to the second pixel circuit, and the other end of the connection line is electrically connected to the second anode.
  • a display device is also provided, and the display device includes the display panel described in any one of the above embodiments.
  • a method for manufacturing a display panel includes a main display area and a functional device area, the main display area at least partially surrounds the functional device area; the display panel includes a plurality of first A pixel circuit, and a plurality of redundant pixel circuits, the plurality of first pixel circuits are located in the main display area, the plurality of redundant pixel circuits and the main display area are adjacent to the first pixels of the functional device area circuits are adjacent.
  • the fabrication method includes: fabricating an active layer on a substrate; fabricating an anode layer on a side of the active layer away from the substrate.
  • the active layer includes first active layer patterns of the plurality of first pixel circuits, and redundant active layer patterns of the plurality of redundant pixel circuits;
  • the anode layer includes A plurality of first anodes in the display area, each of which is electrically connected to a first pixel circuit; the plurality of redundant pixel circuits are electrically insulated from the anode layer.
  • the first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor. Between the forming of the active layer on the substrate and the forming of the anode layer on the side of the active layer away from the substrate, the method further includes: forming the active layer away from the substrate. A first gate conductive layer is made on one side; a second gate conductive layer is made on the side of the first gate conductive layer away from the substrate; a source is made on the side of the second gate conductive layer away from the substrate Drain conductive layer.
  • the first gate conductive layer includes first gate patterns of the plurality of first pixel circuits, the first gate patterns including the gates of the plurality of first thin film transistors, the gates of the first storage capacitors.
  • the second gate conductive layer includes a second gate pattern of the plurality of first pixel circuits, and the second gate pattern includes the first storage capacitor the second electrode plate, the first initialization power supply line, and the second initialization power supply line;
  • the source-drain conductive layer includes the source-drain conductive patterns of the plurality of first pixel circuits, and the source-drain conductive pattern includes the plurality of a source electrode and a drain electrode of a first thin film transistor, a data line, and a voltage signal line.
  • the redundant pixel circuit includes a plurality of redundant thin film transistors and redundant storage capacitors;
  • the first gate conductive layer further includes a first redundant gate pattern of the plurality of redundant pixel circuits, the first gate conductive layer a redundant gate pattern includes the gates of the redundant thin film transistors and the first plates of the redundant storage capacitors;
  • the second gate conductive layer further includes the first plates of the redundant pixel circuits Two redundant gate patterns, the second redundant gate pattern includes the second plate of the redundant storage capacitor;
  • the source-drain conductive layer further includes redundant source and drain of the plurality of redundant pixel circuits A conductive pattern, the redundant source-drain conductive pattern includes the source and drain electrodes of the plurality of redundant thin film transistors; the redundant source-drain conductive pattern is electrically insulated from the anode layer.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments
  • Fig. 2 is the pixel arrangement structure diagram of the interface area between the main display area and the functional device setting area in the display panel;
  • 3A is a structural diagram of a transition region according to some embodiments.
  • 3B is another structural diagram of a transition region according to some embodiments.
  • 3C is yet another structural diagram of a transition region according to some embodiments.
  • 3D is yet another structural diagram of a transition region according to some embodiments.
  • 3E is yet another structural diagram of a transition region according to some embodiments.
  • FIG. 4 is a structural diagram of a redundant pixel circuit according to some embodiments.
  • Figure 5A is a cross-sectional view of A'-A' and A"-A" in Figure 4;
  • Fig. 5B is another cross-sectional view of A'-A' and A"-A" in Fig. 4;
  • FIG. 6 is another structural diagram of a redundant pixel circuit according to some embodiments.
  • Figure 7 is a cross-sectional view of B'-B' and B"-B" in Figure 6;
  • FIG. 8 is a block diagram of a first pixel circuit according to some embodiments.
  • FIG. 9 is a structural diagram of a second pixel circuit disposed in a main display area according to some embodiments.
  • FIG. 10 is a structural diagram of a second pixel circuit disposed in a frame area according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • connection may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the expression “same layer setting” is used, which means that a film layer with a specific pattern is formed by one patterning process using the same mask.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the display device 1000 may be a TV, a computer, a notebook computer, a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, etc. .
  • PDA personal digital assistant
  • the display device 1000 adopts the technology of arranging functional devices on the back side of the screen (the side away from the light-emitting surface of the screen), and the functional devices are, for example, a front camera assembly, an under-screen fingerprint assembly, a 3D face recognition assembly, an iris identification assembly, and a proximity sensor. and other devices that can achieve specific functions.
  • the display device 1000 adopts the under-screen camera technology.
  • a display device 1000 includes a display panel 100 .
  • the display panel 100 may be an organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display panel.
  • OLED Organic Light-Emitting Diode
  • the display panel 100 includes a main display area 101 , a functional device area 102 , and a bezel area 104 surrounding the main display 101 .
  • the functional device is disposed on the back side of the functional device area 102, and the functional device needs to receive light from the outside when it operates. In order to improve the sensitivity of the functional device, it is necessary to ensure that the functional device can receive a sufficient amount of light, and the light transmittance of the functional device region 102 needs to be improved.
  • the display panel 100 includes a plurality of sub-pixels 110 .
  • the sub-pixels 110 include a pixel circuit 20 disposed on a substrate 120 and an anode 32 disposed on a side of the film layer where the pixel circuit 20 is located away from the substrate 120 .
  • the anode 32 includes a first anode 321 located in the main display area 101 and a second anode 322 located in the functional device area 102 .
  • the pixel circuit 20 connected to the second anode 322 is disposed in the area other than the functional device area 102 in the display panel 100 ; that is, the functional device area 102 is not provided with pixels Circuit 20, only the second anode 322 remains. Due to the poor uniformity of the pixel circuit 20 in the edge region of the display panel close to the under-screen camera during the fabrication of the pixel circuit, the pixel circuit in this region is prone to Vth offset, which in turn causes the sub-sub-region where the pixel circuit 20 is located.
  • the pixel 110 emits abnormally (such as dark spots, bright spots, etc.); that is, the pixel circuits 20 included in the sub-pixels 110 located in the main display area 101 close to the edge of the functional device area 102 have poor uniformity, resulting in the main display area 101.
  • the sub-pixels 110 near the edge of the functional device region 102 may emit abnormal light.
  • Some embodiments of the present disclosure provide a display panel 100 , referring to FIG. 1 , including a main display area 101 and a functional device area 102 , the main display area 101 at least partially surrounding the functional device area 102 .
  • a display panel 100 including a main display area 101 and a functional device area 102 , the main display area 101 at least partially surrounding the functional device area 102 .
  • part of the boundary of the functional device area 102 overlaps with part of the frame area 104
  • the main display area 101 partially surrounds the functional device area 102 ;
  • FIG. 3C the boundary of the functional device area 102 and the frame area 104 , the main display area 101 surrounds the functional device area 102 .
  • the display panel 100 includes a plurality of first pixel circuits 210 and a plurality of redundant pixel circuits 220, and the plurality of first pixel circuits 210 are located in the main display area 101;
  • the redundant pixel circuits 220 are adjacent to the plurality of first pixel circuits 210 disposed on the edge of the main display area 101 close to the functional device area 102 . That is, a redundant pixel circuit 220 adjacent to the first pixel circuit 210 is disposed on the side of the first pixel circuit 210 of the main display area 101 close to the functional device area 102 on the side of the first pixel circuit 210 close to the functional device area 102 .
  • the display panel 100 includes an active layer 310 and an anode layer 320 which are arranged in sequence along a direction perpendicular to the substrate 120 and away from the substrate 120 .
  • the anode layer 320 includes a plurality of first anodes 321 located in the main display area 101 , and each of the first anodes 321 is electrically connected to one of the first pixel circuits 210 .
  • the first pixel circuit 210 is electrically connected to the first anode 321 and is configured to transmit a driving current to the first anode 321 to control the light emitting device 30 where the first anode 321 is located to emit light.
  • the redundant pixel circuit 220 at least includes a redundant active layer pattern 311 located on the active layer 310 , and the redundant pixel circuit 220 is electrically insulated from the anode layer 320 . Due to the influence of the manufacturing process, during the manufacturing process of the pixel circuit, the pixel circuit located in the edge area of the display panel close to the under-screen camera has poor uniformity, and the problem of poor uniformity mainly occurs in the active layer 310. Therefore, redundant The pixel circuit 220 includes at least redundant active layer patterns 311 located in the active layer 310 .
  • a side of the first pixel circuit 210 that is located at the edge of the main display area 101 close to the functional device area 102 is disposed on the side close to the functional device area 102 .
  • a pixel circuit 210 is adjacent to the redundant pixel circuit 220 ; and, referring to FIG. 4 and FIG. 6 , the redundant pixel circuit 220 includes a redundant active layer pattern 311 located on the active layer 310 .
  • the edge of the active layer 310 close to the functional device region 102 is transferred from the first active layer pattern 312 of the first pixel circuit 210 to the redundant active layer pattern 311 of the redundant pixel circuit 220; thereby avoiding the first
  • the pixel circuit 210 has a problem of poor uniformity, so that the sub-pixels 20 located at the edge of the main display area 101 close to the functional device area 102 emit light normally.
  • the redundant pixel circuit 220 is electrically insulated from the anode layer 320 , that is, the redundant pixel circuit 220 does not control any sub-pixel 20 to emit light, even if the redundant active layer pattern 311 of the redundant pixel circuit 220 has poor uniformity problem, it will not affect any of the sub-pixels 20 emitting light.
  • the plurality of first pixel circuits 210 are arranged in multiple rows and columns, the first pixel circuits 210 in any row are arranged along the first direction M1 (the horizontal direction in FIG. 3A ), and the first pixel circuits 210 in any column are arranged in the first direction M1 (the horizontal direction in FIG. 3A ).
  • a pixel circuit 210 is arranged along the second direction M2 (the vertical direction in FIG. 3A ). The first direction M1 intersects the second direction M2.
  • At least two redundant pixel circuits 220 arranged along the first direction are disposed on the edge of any row of the first pixel circuits 210 that intersects with the boundary of the functional device area 102 near the functional device area 102 .
  • At the edge of any column of the first pixel circuits 210 that intersects the boundary of the functional device region 102 and is close to the functional device region 102 at least two redundant pixel circuits are arranged along the second direction.
  • each first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102, along the first direction M1 or along the second direction M2 close to the side of the functional device area 102, is provided with at least two The redundant pixel circuit 220 adjacent to the first pixel circuit 210; in order to ensure that the area with poor uniformity that may appear on the active layer 310 completely falls on the redundant active layer pattern 311 of the redundant pixel circuit 220, there are It is beneficial to improve the yield of the display panel 100 .
  • the main display area 101 is close to the first pixel circuit 210 in the edge area of the functional device area 102.
  • the opening of the functional device area 102 needs to be made larger to avoid the redundant pixel circuits 220 from affecting the lighting of the functional device, which is not conducive to the arrangement of the pixel circuits 20 included in the sub-pixels 120 in the functional device area 102 .
  • the functional device area 102 is located in the middle of the display panel 100 along the first direction, intersects with the boundary of the functional device area 102 in any row of the first pixel circuits 210 , and is divided into two parts by the functional device area 102 .
  • the functional device area 102 On the right side of the rightmost first pixel circuit 210 in the Nth row of the first pixel circuits 210 located on the left side of the functional device area 102, at least two redundant pixel circuits adjacent to the first pixel circuit 210 are provided. 220. For example, two, three or four redundant pixel circuits 220 may be provided.
  • At least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are provided; On the upper side of the uppermost first pixel circuit 210 of the first pixel circuits 210 in the 0th column located on the lower side of the functional device area 102, at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are arranged; At least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are disposed on the lower side of the lowermost first pixel circuit 210 of the first pixel circuits 210 in the Pth column on the upper side of the functional device area 102 .
  • the first pixel circuits 210 in rows N and M intersect the boundary of the functional device area 102
  • the first pixel circuits 210 in columns O and P intersect the boundary of the functional device area 102 .
  • any row of the first pixel circuits 210 intersecting with the functional device area 102 and close to the functional device area 102 there are four redundant pixel circuits 220 arranged along the first direction M1; Two redundant pixel circuits 220 arranged along the second direction M2 are disposed on the edge of any column of the first pixel circuits 210 where the device regions 102 intersect and close to the functional device region 102 .
  • two redundant pixel circuits 220 are arranged along the first direction M1;
  • Two redundant pixel circuits 220 arranged along the second direction M2 are disposed on the edge of any column of the first pixel circuits 210 where the device regions 102 intersect and close to the functional device region 102 .
  • the region where the redundant pixel circuit 220 is located is defined as the transition region 103 .
  • the transition area 103 includes the edge of the main display area 101 close to the functional device area 102, and/or the edge of the functional device area 102 close to the main display area 101 is the transition area 103; that is, the transition area 103 may include part of the main display area 101 and /or part of functional device area 102 .
  • the transition area 103 may all be located in the functional device area 102 ; or, a part of the transition area 102 is located in the functional device area 102 and a part is located in the main display area 101 ; It should be understood that the area where the first anode 321 is located is the main display area; the area where the second anode 321 is located is the functional device area 102 ; the area where the redundant pixel circuit 220 is located is the transition area 103 .
  • the shape of the boundary of the functional device region 102 may be different, and thus, the shape of the transition region 103 may also be different.
  • the boundary of the functional device region 102 may be a rectangle or an approximate rectangle, a circle or an approximate circle, etc., which is not specifically limited herein.
  • the plurality of first pixel circuits 210 are arranged in a plurality of rows and columns, and the boundary of the functional device area 102 is defined by the boundary of a plurality of segments of the first pixel circuits 210 arranged along the first direction M1 (the row direction in which the plurality of first pixel circuits 210 are arranged). , and the boundaries of a plurality of segments of the first pixel circuits 210 arranged along the second direction M2 (the row direction in which the plurality of first pixel circuits 210 are arranged) are alternately connected and formed. Referring to FIG.
  • the boundary of the functional device region 102 when a portion of the boundary of the functional device region 102 overlaps with a portion of the border region 104 , the boundary of the functional device region 102 includes at least one straight line segment extending along the first direction M1 and two extending along the second direction M2 straight line segment.
  • the transition area 103 includes at least a first linear extension section 1031 and two second linear extension sections 1032 ; the first linear extension section 1031 is located in the transition area 103 in the second direction M2 One edge, the two second linear extension sections 1032 are respectively located at the two edges of the transition region 103 in the first direction M1.
  • the boundary of the functional device area 102 is a rectangle, and a boundary of the functional device area 102 in the second direction M2 (the upper boundary of the functional device area 102 in FIG. 3B ) partially coincides with the boundary of the frame area 104 .
  • the transition area 103 may include a first linear extension section 1031 and two second linear extension sections 1032 .
  • the first linear extension section 1031 constitutes a boundary in the second direction M2 of the transition area 103 (the lower boundary of the transition area 103 in FIG. borders (left and right borders of transition region 103 in FIG. 3B ).
  • the first straight extending section 1031 is provided with at least two rows of redundant pixel circuits 220 (any column of the first pixel circuit 210 that intersects the boundary of the functional device area 102 is disposed on the edge of the first pixel circuit 210 close to the functional device area 102, and at least two rows along the edge of the functional device area 102 are provided.
  • the redundant pixel circuits 220 arranged in the two directions M2); that is, in at least one row of the first pixel circuits 210 that overlap with the partial boundary of the functional device area 102, the part that overlaps with the boundary of the functional device area 102 is close to the functional device area 102. At least two rows of redundant pixel circuits 220 are disposed on one side.
  • Each second straight line extension 1302 is provided with at least two columns of redundant pixel circuits 220 (the edges of any row of the first pixel circuits 210 that intersect with the boundary of the functional device region 102 close to the functional device region 102 are provided with at least two edge
  • One side of 102 is provided with at least two columns of redundant pixel circuits 220 .
  • the transition area 103 further includes four polyline extension segments 1033 ; each polyline extension segment 1033 includes a plurality of line segments 10331 connected in sequence, and each line segment 10331 is provided with multiple redundant lines In the pixel circuit 220, multiple rows of redundant pixel circuits 220 located in different line segments 10331 are staggered in the first direction M1;
  • the boundary shape of the functional device area 102 is approximately circular, and at the corner of the boundary of the functional device area 102, there are a plurality of straight line segments extending along the first direction M1 and a plurality of straight line segments extending along the second direction M2. Alternately connected polyline segments.
  • the transition region 103 includes a polyline extension segment 1033 , and the polyline extension segment 1033 of the transition region 103 is disposed at a position corresponding to the polyline segment of the boundary of the functional device region 102 .
  • the position of the functional device region 102 on the display panel 100 is not unique, and the shape of the transition region 103 may also be different according to different positions of the functional device region 102 on the display panel 100 .
  • the functional device area 102 can be set at the upper middle position of the display panel 100 (as shown in FIG. 3A ), or at the left or right side of the upper part of the display panel 100 , and can also be set at the middle position of the lower part of the display panel 100 ;
  • the device area 102 may be completely surrounded by the main display area 101 (as shown in FIG. 3C ), and part of the boundary of the functional device area 102 may also coincide with part of the boundary of the frame area 104 , that is, the main display area 101 partially surrounds the functional device area 102 ( as shown in Figure 3A).
  • the transition region 103 is a ring shape with an opening 1035 on one side (upper side), and the opening 1035 is located on the transition region 103 and the first Opposite edges of straight segment 1031 .
  • the transition area 103 may only include the first linear extension section 1031 and the two second linear extension sections 1032 (as shown in FIG. 3B ); (as shown in Figure 3A).
  • the transition region 103 may also include other extension sections, which will not be listed here.
  • the transition area 103 further includes a third linear extension section 1034 , and the third linear extension section 1034 is located between the transition area 103 and the first linear segment
  • the third straight extending section 1034 includes at least two rows of redundant pixel circuits 220 ; the transition area 103 is a closed ring.
  • the first linear extension section 1301 and the third linear extension section 1034 respectively constitute two boundaries in the first direction M1 of the transition area 103 (in FIG. 3C , the upper and lower boundaries of the transition area 103 ).
  • the transition area 103 may include a first linear extension section 1031, two second linear extension sections 1032 and a third linear extension section 1034; or, the transition area 103 may further include two broken line extension sections 1303 or four Polyline extension 1033.
  • the transition region 103 may also include other extension sections, which will not be listed here.
  • At least two arrayed in the first direction M1 may be arranged. Redundant pixel circuit 220 .
  • at least two redundant pixel circuits 220 arranged along the second direction M2 are provided only on the edge of any column of the first pixel circuits 210 that intersect with the boundary of the functional device region 102 near the functional device region 102 .
  • the pattern formed by the arrangement of the plurality of redundant pixel circuits 220 is symmetrical with respect to a straight line L2 along the first direction M1 of the transition region 103 .
  • the pattern formed by the arrangement of the plurality of redundant pixel circuits 220 is symmetrical with respect to a straight line L1 along the second direction M2 of the transition region 103 .
  • the plurality of redundant pixel circuits 220 are symmetrical with respect to a straight line L2 of the transition region 103 along the first direction M1, and/or are symmetrical with respect to a straight line L1 of the transition region 103 along the second direction M2, which is beneficial to improve redundant pixels
  • the uniformity of the redundant active layer patterns 311 of the circuit 220 improves the overall uniformity of the active layer 310 .
  • the first pixel circuit 210 includes a plurality of first thin film transistors (English: Thin Film Transistor; TFT for short) 211 and a first storage capacitor 212; Part A' is a cross-sectional view of a first thin film transistor 211 and a first storage capacitor 212 in the first pixel circuit 210 .
  • the first thin film transistor 211 may be a P-type transistor or an N-type transistor, which is not specifically limited herein.
  • the active layer 310 includes a plurality of first active layer patterns 312 of the first thin film transistors 211 , and each of the first pixel circuits 210 includes a first active layer pattern 312 located on the active layer 310 .
  • the display panel 100 further includes a first gate conductive layer 330 , a second gate conductive layer 340 , and a source-drain conductive layer 350 .
  • the first gate conductive layer 330 is disposed between the active layer 310 and the anode layer 320 , and includes a plurality of first gate patterns 331 of the first pixel circuits 210 , and the first gate pattern 331 includes a plurality of first thin film transistors 211 .
  • the second gate conductive layer 340 is disposed between the first gate conductive layer 330 and the anode layer 320 , and includes a plurality of second gate patterns 341 of the first pixel circuits 210 , and the second gate patterns 341 include the first storage capacitors 212 .
  • the source-drain conductive layer 350 is disposed between the second gate conductive layer 340 and the anode layer 320 , and includes a plurality of source-drain conductive patterns 351 of the first pixel circuits 210 , and the source-drain conductive pattern 351 includes a plurality of sources of the first thin film transistors 30 .
  • the first active layer pattern 312 , the first gate pattern 331 , the second gate pattern 341 and the source-drain conductive pattern 351 together constitute the first pixel circuit 210 .
  • the display panel 100 further includes a first gate insulating layer 360 disposed between the active layer 310 and the first gate conductive layer 330 ; a second gate insulating layer 360 disposed between the first gate conductive layer 330 and the second gate conductive layer 340 layer 370; interlayer insulating layer 380 disposed between the second gate conductive layer 340 and the source-drain conductive layer 350; and passivation layer 390 disposed between the source-drain conductive layer 350 and the anode layer 320, and a planarization layer 420.
  • the first gate insulating layer 360 , the second gate insulating layer 370 , the interlayer insulating layer 380 , the passivation layer 390 , and the planarization layer 420 are all of the whole-layer structure, and all cover the redundant active layer pattern 311 .
  • At least one insulating layer is arranged between two adjacent conductive layers to avoid overlapping of patterns on the two adjacent conductive layers.
  • the redundant pixel circuit 220 may only include the redundant active layer pattern 311 ; or, the redundant pixel circuit 220 may include the redundant active layer pattern 311 and the redundant first gate pattern 332 which are sequentially stacked on the substrate 120 . , a redundant second gate pattern 342 , and a redundant source-drain conductive layer pattern 352 .
  • the redundant pixel circuit 220 includes only the redundant active layer pattern 311 , all patterns of the first gate conductive layer 330 , all patterns of the second gate conductive layer 340 and source
  • the orthographic projections of all the patterns of the drain conductive layer 350 on the substrate 120 are separated from the orthographic projections of the redundant active layer patterns 311 on the substrate 120 ; that is, there is no first gate above the redundant active layer patterns 311 Conductive patterns in the conductive layer 330 , the second gate conductive layer 340 and the source-drain conductive layer 350 .
  • the structure of the redundant pixel circuit 210 is simple, and the patterns of the first gate conductive layer 330 , the second gate conductive layer 340 and the source-drain conductive layer 350 are simple, which is beneficial to improve the manufacturing efficiency of the display panel 100 .
  • the first gate insulating layer 360 , the second gate insulating layer 370 , and the interlayer insulating layer 380 are provided with a plurality of via holes 361 , and the plurality of via holes 361 pass through the first gate insulating layer 360 and the second gate insulating layer 360 .
  • the layer 370, the interlayer insulating layer 380, and the orthographic projection of the via hole 361 on the substrate 120 are located within the orthographic projection range of the redundant active layer pattern 311 on the substrate 120;
  • the structure of the remaining active layer pattern 311 is consistent with that of the first active layer pattern 312 of the first pixel circuit 210 , which is beneficial to improve the uniformity of the active layer 310 near the edge of the functional device region 102 and reduce the first active layer pattern 312 Possibility of poor uniformity.
  • the redundant pixel circuit 220 only includes the redundant active layer pattern 311, and the passivation layer 390 is provided on the side of the interlayer insulating layer 380 away from the redundant active layer pattern 311, according to the manufacturing process of the display panel 100, therefore, After the vias 361 are formed, the source-drain conductive layer 350 and the passivation layer 390 need to be formed; the vias of the first pixel circuit 210 are filled with the source-drain conductive layer 350 ; the vias 361 of the redundant pixel circuit 220 are filled with passivation The material of layer 390.
  • the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222 , that is, the redundant pixel circuit 220 includes a plurality of redundant pixel circuits 220 that are sequentially stacked on the substrate 120
  • the redundant active layer patterns 311 , the redundant first gate patterns 332 , the redundant second gate patterns 342 , and the redundant source-drain conductive layer patterns 352 . 8 is a structural diagram of the first pixel circuit 210.
  • the structure of the redundant pixel circuit 220 is the same as that of the first pixel circuit.
  • the conductive layer patterns of the redundant pixel circuit 220 can refer to the conductive layer pattern corresponding to the first pixel circuit 210 .
  • the first gate conductive layer 330 further includes first redundant gate patterns 332 of the plurality of redundant pixel circuits 220 , and the first redundant gate patterns 332 include the gates G2 of the plurality of redundant thin film transistors 221 and redundant storage capacitors 222 of the first plate C21; and the first redundant gate pattern 332 and the first gate pattern 331 are arranged in the same layer.
  • the second gate conductive layer 340 further includes a second redundant gate pattern 342 of the plurality of redundant pixel circuits 220, the second redundant gate pattern 342 includes the second electrode plate C22 of the redundant storage capacitor 222;
  • the residual gate pattern 342 is disposed in the same layer as the second gate pattern 341 .
  • the source-drain conductive layer 350 further includes redundant source-drain conductive patterns 352 of the redundant pixel circuits 220 , and the redundant source-drain conductive patterns 352 include the source electrodes S2 and the drain electrodes D2 of the redundant thin-film transistors 221 ; redundant sources
  • the drain conductive pattern 352 is electrically insulated from the anode layer 320 , and the redundant source-drain conductive pattern 352 and the source-drain conductive pattern 351 are disposed in the same layer.
  • the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222, and the redundant pixel circuit 220 is the same in structure as the first pixel circuit 210 (but the redundant pixel circuit 220 is not electrically connected to the anode layer 320, The first pixel circuit 210 is electrically connected to the first anode 321 of the anode layer 320); the first gate pattern 331 and the second gate of the plurality of first pixel circuits 210 of the main display area 101 close to the edge of the functional device area 102 can be lifted
  • the uniformity of the electrode pattern 341 and the source-drain conductive pattern 351 improves the uniformity of the plurality of first pixel circuits 210 in the main display area 101 close to the edge of the functional device area 102 , and further reduces the proximity of the main display area 101 to the functional device area 102
  • the probability of the Vth shift of the first pixel circuit 210 at the edge of the pixel circuit 210 makes the light emitting device 30 at
  • the redundant active layer patterns 311 are separated from each other (refer to FIG. 6 ), and the first redundant gate patterns 332 are connected (scan lines GL and the light-emitting signal line EM are connected), and the second redundant gate pattern 342 is connected (the first initialization power line Vint1 and the second initialization power line Vint2 are connected).
  • the redundant active layer patterns 311 are separated from each other (refer to FIG. 6 ), and the redundant source-drain conductive patterns 352 are connected (the data line DATA and the voltage signal line VDD are connected to each other).
  • the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222
  • the redundant active layer patterns 351 of two redundant pixel circuits 220 adjacent in the first direction are separated from each other , the first redundant gate pattern 332 and the second redundant gate pattern 342 are connected; the redundant active layer patterns 311 of the two adjacent redundant pixel circuits 220 along the second direction M2 are separated from each other, and the redundant source and drain Conductive pattern connection.
  • the redundant pixel circuit 220 only includes the redundant active layer pattern 311 disposed on the active layer 310, the redundant pixel circuits 220 adjacent to the two redundant pixel circuits 220 along the first direction M1 will The active layer patterns 311 are separated from each other; the redundant active layer patterns 311 of the two adjacent redundant pixel circuits 220 along the second direction M2 are separated from each other.
  • the anode layer 320 further includes a plurality of second anodes 322 located in the functional device region 102 .
  • the display panel 100 further includes a plurality of second pixel circuits 230, and each second anode 322 is electrically connected to a second pixel circuit 230; the plurality of second pixel circuits 230 are arranged in the display panel 100 in areas other than the functional device area 102 .
  • the structure of the second pixel circuit 203 may be the same as that of the first pixel circuit 210 ; disposing the second pixel circuit 230 in the area of the display panel 100 other than the functional device area 102 is beneficial to improve the light transmission of the functional device area 102 rate, so that when the functional device is working, the functional device can collect enough light.
  • the display panel 100 further includes a transition conductive layer 410 , and the first pixel circuit 210 and the second pixel circuit 230 communicate with the first anode 321 or The second anode 322 is electrically connected.
  • the transition conductive layer 410 is located between the film layer where the plurality of first pixel circuits 210 and the plurality of second pixel circuits 230 are located and the anode layer 320 , and between the passivation layer 390 and the anode layer 320 .
  • the transition conductive layer 410 can reduce the depth of a single via hole when the source-drain conductive layer 350 is connected to the anode layer 320 , improve the connection stability between the pixel circuit 20 and the light emitting device 30 indirectly, and reduce the difficulty of making the via hole process.
  • the transfer conductive layer 410 includes a plurality of transfer blocks 411 separated from each other.
  • the plurality of transfer blocks 411 include a first transfer block 4111 electrically connected to the first pixel circuit 210 , and a second transfer block 4112 electrically connected to the second pixel circuit 230 .
  • the orthographic projection of the first transition block 4111 on the substrate 120 covers the first connection node N1 of the first pixel circuit 210 that is electrically connected to it, thereby shielding the connection layer on the side of the first transition block 4111 away from the substrate 120 430. Reduce or eliminate the influence of the connection layer 430 on the first connection node N1.
  • the first transfer block 4111 is electrically connected to the first connection node N1, and the first anode 321 is electrically connected to the first transfer block 4111; so that the first anode 321 is electrically connected to the first pixel circuit 210 through the first transfer block 4111 connect.
  • the first connection node N1 is a node in the first pixel circuit 210 that is configured to be connected to the first anode electrode 321 .
  • the orthographic projection of the second transition block 4112 on the substrate 120 covers the second connection node N2 of the second pixel circuit 230 that is electrically connected to it, thereby shielding the connection layer on the side of the second transition block 4112 away from the substrate 120 430. Reduce or eliminate the influence of the connection layer 430 on the second connection node N2.
  • the second transfer block 4112 is electrically connected to the second connection node N2, and the second anode 322 is electrically connected to the second transfer block 4112; so that the second anode 322 is electrically connected to the second pixel circuit 230 through the second transfer block 4112 connect.
  • the second connection node N2 is a node in the second pixel circuit 230 that is configured to be electrically connected to the second anode 322 .
  • the display panel 100 further includes a frame area 104 surrounding the main display area 101 .
  • the second pixel circuit 230 may be disposed in the main display area 101 (as shown in FIG. 9 ) or in the frame area 104 (as shown in FIG. 10 ).
  • the plurality of first pixel circuits 210 and the plurality of second pixel circuits 230 are located in the main display area 101 .
  • a plurality of second pixel circuits 230 are arranged in multiple rows and columns, and a plurality of first pixel circuits 210 are arranged between two adjacent second pixel circuits 230 in the same row, that is, multiple columns of second pixel circuits 230
  • the second pixel circuits 230 are arranged in the main display area 101 , which is beneficial to reduce the width of the frame area 104 and increase the screen ratio of the display panel 100 .
  • arranging the second pixel circuit 230 in the frame area 104 is beneficial to increase the pixel density of the main display area 101 of the display panel 100 .
  • the pixel density is relatively high, and correspondingly, the density of the first pixel circuit 210 is relatively high, and the first pixel circuit 210 The available gap between them is very small, and it is not easy for the second pixel circuit 230 to be inserted into the gap of the first pixel circuit 210 . Therefore, the second pixel circuit 230 is disposed in the frame area 104 , which is beneficial to increase the pixel density of the main display area 101 of the display panel 100 , and is beneficial to manufacture the display panel 100 with high PPI.
  • the second anode 322 is located in the functional device area 102, and the second pixel circuit 230 is disposed in the area of the display panel 100 other than the functional device area 102; that is, the orthographic projection of the second pixel circuit 230 on the substrate 120 and the second anode
  • the orthographic projections of 322 on the substrate do not overlap, and the second anode 322 and the second pixel circuit 230 cannot be directly electrically connected through vias.
  • the display panel 100 further includes at least one connecting layer 430, and at least one connecting layer 430 is located between the transfer conductive layer 410 and the anode layer 320; the connecting layer 430 includes a plurality of connecting lines 431, One end of the connection line 431 is electrically connected to the second pixel circuit 230 through the second transfer block 4112 , and the other end of the connection line 431 is electrically connected to the second anode 322 .
  • connection lines 431 of the connection layer 430 may be made of transparent conductive materials, such as indium tin oxide (English: Indium Tin Oxides; ITO for short).
  • connection lines 431 are required to connect the multiple second anodes 322 and the multiple second pixel circuits 230 .
  • a plurality of connection lines 431 can be arranged in the same connection layer 430, and can also be arranged in different connection layers 430, so as to provide sufficient wiring space for the plurality of connection lines 431; wherein, when the number of connection layers 430 is greater than two layers Below, at least one insulating layer 440 is disposed between any two adjacent connecting layers 430 .
  • connection layers 430 is three; along the direction perpendicular to the substrate 120 and directed from the substrate 120 to the anode layer 320 , the three connection layers 430 are sequentially the first connection layer.
  • an insulating layer 441 is arranged between the first connection layer 4301 and the second connection layer 4302, and a layer of insulating layer 441 is arranged between the second connection layer 4302 and the third connection layer 4303
  • An insulating layer 442 ; and an insulating layer 443 is arranged between the transition conductive layer 410 and the first connection layer 4301 , and an insulating layer 444 is arranged between the third connection layer 4303 and the anode layer 320 .
  • connection wire 431 is electrically connected to the second transfer block 412 through the third transfer block 422 .
  • the second anodes 322 at different positions may be electrically connected to the second pixel circuit 230 through the connection lines 431 of different connection layers 430 .
  • the second anodes of different sub-pixels 120 of the same pixel unit (including at least red sub-pixels, green sub-pixels, and blue sub-pixels) are electrically connected to the second pixel circuit 230 through connection lines 431 of different layers;
  • two adjacent second anode electrodes 322 are electrically connected to the second pixel circuit 230 through connecting wires 431 of different layers, etc., which are not listed one by one here.
  • the second anode 322 is electrically connected to the second pixel circuit 230 through the connection line 431 in the third connection layer 4303; referring to FIG. 5B, the second anode 322 is electrically connected to the second pixel circuit 230 through the connection line 431 in the first connection layer 4301 It is electrically connected to the second pixel circuit 230 . 5B, it can be considered that the second anode 322 cut by A"-A" in FIG. 4 is the second anode 322 located in the central region of the functional device region 102, so that the second anode 322 is close to the surface of the substrate 110. There is no redundant pixel circuit on one side.
  • the display panel 100 further includes a pixel defining layer 450 disposed on a side of the anode layer 320 away from the substrate 120 , the pixel defining layer 450 includes a plurality of opening regions 451 , a first anode 321 Or one second anode 321 corresponds to one opening region 451 .
  • a light-emitting functional layer 460 is provided in the opening area 451.
  • the light-emitting functional layer 460 includes an electron transport layer (election transporting layer, referred to as ETL), an electron injection layer (election injection layer, referred to as EIL), a hole transport layer (hole transport layer).
  • ETL electron transport layer
  • EIL electron injection layer
  • HTL hole transport layer
  • HIL hole injection layer
  • the display panel 100 further includes a cathode conductive layer 470 disposed on the side of the pixel defining layer 450 and the light emitting functional layer away from the substrate 120 , and an encapsulation layer 480 disposed on the side of the cathode conductive layer 470 away from the substrate 120 .
  • Some embodiments of the present disclosure also provide a method for fabricating a display panel 100, the display panel 100 includes a main display area 101 and a functional device area 102, the main display area 101 at least partially surrounds the functional device area 102; the display panel 100 includes a plurality of A first pixel circuit 210 and a plurality of redundant pixel circuits 220, the plurality of first pixel circuits 210 are located in the main display area 101, and the plurality of redundant pixel circuits 220 and the main display area 101 are close to the first pixel circuit of the functional device area 102 210 adjacent.
  • the above production method includes:
  • the active layer 310 includes a plurality of first active layer patterns 312 of the first pixel circuits 210 , and a plurality of redundant active layer patterns 311 of the redundant pixel circuits 220 .
  • the anode layer 320 includes a plurality of first anodes 321 located in the main display area 101 , and each first anode 321 is electrically connected to a first pixel circuit 210 ; the plurality of redundant pixel circuits 220 are electrically insulated from the anode layer 320 .
  • the side of the first pixel circuit 210 that is located at the edge of the main display area 101 close to the functional device area 102 is close to the functional device area 102 , and includes redundant components adjacent to the first pixel circuit 210 .
  • the redundant pixel circuit 220, and the redundant pixel circuit 220 includes the redundant active layer pattern 311 located in the active layer 310, so as to avoid the problem of poor uniformity of the first active layer pattern 312 of the first pixel circuit 210, so that the The sub-pixel 120 where the first anode 321 of the display area 101 is close to the edge of the functional device area 102 can emit light normally.
  • the first pixel circuit 210 includes a plurality of first thin film transistors 211 and a first storage capacitor 212 . Between the fabrication of the active layer 310 on the substrate 120 in S10 and the fabrication of the anode layer 320 on the side of the active layer 310 away from the substrate 120 in S20, the fabrication method further includes:
  • the first gate conductive layer 330 includes a plurality of first gate patterns 331 of the first pixel circuits 210 , and the first gate patterns 331 include a plurality of gates G1 of the first thin film transistors 211 and first electrodes of the first storage capacitors 212 .
  • the second gate conductive layer 340 includes a plurality of second gate patterns 341 of the first pixel circuits 210 , and the second gate patterns 341 include the second plate C12 of the first storage capacitor 212 , the first initialization power line Vint1 , and the first 2. Initialize the power line Vint2.
  • the source-drain conductive layer 350 includes a plurality of source-drain conductive patterns 351 of the first pixel circuits 210 , and the source-drain conductive patterns 351 include a plurality of source electrodes S1 and drain electrodes D1 of the first thin film transistors 30 , data lines DATA, and voltage signal lines VDD.
  • the first active layer pattern 312, the first gate pattern 331, the second gate pattern 341 and the source-drain conductive pattern 351 together constitute the first pixel circuit 210.
  • the redundant pixel circuit 220 may only include redundant active layer patterns 311 , and may also include redundant active layer patterns 311 and redundant first gate patterns 332 stacked on the substrate 120 in sequence. , a redundant second gate pattern 342 , and a redundant source-drain conductive layer pattern 352 .
  • the redundant pixel circuit 220 only includes the redundant active layer patterns 311 , all patterns of the first gate conductive layer 330 , all patterns of the second gate conductive layer 340 , and all patterns of the source-drain conductive layer 350 are in the substrate
  • the orthographic projections on the substrate 120 are all separated from the orthographic projections of the redundant active layer patterns 311 on the substrate 120 .
  • the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222; that is, the redundant pixel circuit 220 further includes redundant active layer patterns 311, The redundant first gate pattern 332 , the redundant second gate pattern 342 , and the redundant source-drain conductive layer pattern 352 are provided.
  • the first gate conductive layer 330 further includes first redundant gate patterns 332 of the plurality of redundant pixel circuits 220 , and the redundant gate patterns 332 include the gates G2 of the redundant thin film transistors 221 and the redundant storage capacitors 222 .
  • the first electrode plate C21; the first redundant gate pattern 332 and the first gate pattern 331 are arranged in the same layer.
  • the second gate conductive layer 340 further includes a second redundant gate pattern 342 of the plurality of redundant pixel circuits 220, and the second redundant gate pattern 342 includes the second electrode plate C22 of the redundant storage capacitor 222; the second redundant gate pattern 342
  • the gate pattern 342 and the second gate pattern 341 are disposed in the same layer.
  • the source-drain conductive layer 350 further includes redundant source-drain conductive patterns 352 of the redundant pixel circuits 220 , and the redundant source-drain conductive patterns 352 include the source electrodes S2 and the drain electrodes D2 of the redundant thin-film transistors 221 ; redundant sources
  • the drain conductive pattern 352 is electrically insulated from the anode layer 320 , and the redundant source-drain conductive pattern 352 and the source-drain conductive pattern 351 are disposed in the same layer.
  • the structure of the redundant pixel circuit 220 is the same as that of the first pixel circuit 210 .
  • the redundant pixel circuit 220 is electrically insulated from the anode layer 320, and the redundant pixel circuit 220 does not control any light-emitting device 30 to emit light;
  • the first pixel circuit 210 is electrically connected to the first anode 321 for controlling the first anode 321 The light emission of the light emitting device 30 there.
  • the redundant pixel circuit 220 can improve the uniformity of the first pixel circuit 210, avoid the problem of Vth offset in the first pixel circuit 210, and solve the problem with the first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102.
  • the connected light emitting devices 30 exhibit unusual problems.

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Abstract

一种显示面板，包括主显示区及功能器件区，所述主显示区至少部分围绕所述功能器件区。所述显示面板包括多个第一像素电路，及多个冗余像素电路，所述多个第一像素电路位于所述主显示区；所述多个冗余像素电路与设置于所述主显示区靠近所述功能器件区的边缘的多个第一像素电路相邻。所述显示面板包括沿垂直于衬底且远离衬底方向依次设置的有源层和阳极层；所述阳极层包括位于所述主显示区的多个第一阳极，每个第一阳极与一个第一像素电路电连接；冗余像素电路至少包括位于有源层的冗余有源层图案，且所述冗余像素电路与所述阳极层电绝缘。

Description

显示面板及其制作方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法和显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板包括多个子像素，每个子像素均包括层叠设置在衬底上的像素电路和发光器件，像素电路包括有源层图案。由于制作工艺的影响，像素电路制作过程中，位于显示面板中靠近屏下摄像头的边缘区域的像素电路的均一性较差，导致该区域的像素电路容易发生阈值电压(Vth)偏移的问题，进而导致该子像素发光异常(比如出现暗斑、亮斑或异色)。
公开内容
一方面，提供一种显示面板。包括主显示区及功能器件区，所述主显示区至少部分围绕所述功能器件区。所述显示面板包括多个第一像素电路，及多个冗余像素电路，所述多个第一像素电路位于所述主显示区；所述多个冗余像素电路与设置于所述主显示区靠近所述功能器件区的边缘的多个第一像素电路相邻。所述显示面板包括沿垂直于衬底且远离衬底方向依次设置的有源层和阳极层；所述阳极层包括位于所述主显示区的多个第一阳极，每个第一阳极与一个第一像素电路电连接；冗余像素电路至少包括位于有源层的冗余有源层图案，且所述冗余像素电路与所述阳极层电绝缘。
在一些实施例中，任一行第一像素电路沿第一方向排列，任一列第一像素电路沿第二方向排列，所述第一方向与所述第二方向交叉。与所述功能器件区的边界相交的任一行第一像素电路的靠近所述功能器件区的边缘，设置有至少两个沿第一方向排列的冗余像素电路；与所述功能器件区的边界相交的任一列第一像素电路的靠近所述功能器件区的边缘，设置有至少两个沿第二方向排列的冗余像素电路。
在一些实施例中，与所述功能器件区相交的任一行第一像素电路的靠近所述功能器件区的边缘，设置有2～4个沿第一方向排列的冗余像素电路；与所述功能器件区相交的任一列第一像素电路的靠近所述功能器件区的边缘，设置有2～4个沿第二方向排列的冗余像素电路。
在一些实施例中，所述主显示区靠近所述功能器件区的边缘，和/或， 所述功能器件区靠近所述主显示区的边缘为过渡区，所述多个冗余像素电路位于所述过渡区。所述过渡区至少包括第一直线延伸段和两个第二直线延伸段；第一直线延伸段位于过渡区在第二方向上的一个边缘，所述第一直线延伸段设置有至少两行冗余像素电路；两个第二直线延伸段分别位于所述过渡区在第一方向上的两个边缘，每个第二直线延伸段设置有至少两列冗余像素电路。
在一些实施例中，所述过渡区还包括四个折线延伸段；每个线段设置有多行冗余像素电路，位于不同线段中的多行冗余像素电路在第一方向错开，所述第一直线延伸段与所述第二直线延伸段之间通过所述折线延伸段连接。
在一些实施例中，所述过渡区为一侧开口的环形，开口位于所述过渡区的与第一直线段相对的边缘。或者，所述过渡区还包括第三直线延伸段，第三直线延伸段位于所述过渡区的与第一直线段相对的边缘，所述第三直线延伸段包括至少两行冗余像素电路；所述过渡区为封闭的环形。
在一些实施例中，所述多个冗余像素电路排列所形成的图形相对于所述过渡区的沿第一方向的一条直线对称；和/或，所述多个冗余像素电路排列所形成的图形相对于所述过渡区的沿第二方向的一条直线对称。
在一些实施例中，第一像素电路包括多个第一薄膜晶体管和第一存储电容器；所述有源层还包括所述多个第一薄膜晶体管的第一有源层图案。所述显示面板还包括第一栅导电层、第二栅导电层、及源漏导电层。第一栅导电层设置于所述有源层与所述阳极层之间，包括所述多个第一像素电路的第一栅极图案，所述第一栅极图案包括所述多个第一薄膜晶体管的栅极、所述第一存储电容器的第一极板、扫描线、及发光信号线。第二栅导电层设置于所述第一栅导电层与所述阳极层之间，包括所述多个第一像素电路的第二栅极图案，所述第二栅极图案包括所述第一存储电容器的第二极板、第一初始化电源线、及第二初始化电源线。源漏导电层设置于所述第二栅导电层与所述阳极层之间，包括所述多个第一像素电路的源漏导电图案，所述源漏导电图案包括所述多个第一薄膜晶体管的源极和漏极、数据线、及电压信号线。
在一些实施例中，所述第一栅导电层的全部图案、所述第二栅导电层的全部图案和所述源漏导电层的全部图案在所述衬底上的正投影，均与所述冗余有源层图案在所述衬底上的正投影分离。
在一些实施例中，显示面板还包括第一栅绝缘层、第二栅绝缘层、及层间绝缘层。第一栅绝缘层设置于所述有源层与所述第一栅导电层之间；第二栅绝缘层设置于所述第一栅导电层与所述第二栅导电层之间；层间绝缘层设置于所述第二栅导电层与所述源漏导电层之间。所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层均覆盖所述冗余有源层图案；且所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中设置有多个过孔，过孔穿过所述层间绝缘层、所述第二栅绝缘层和所述第一栅绝缘层，且所述过孔在所述衬底上的正投影，位于所述冗余有源层图案在所述衬底上的正投影范围内。
在一些实施例中，显示面板还包括钝化层，钝化层设置于所述源漏导电层与所述阳极层之间，且覆盖所述冗余有源层图案。所述多个过孔内填充有所述钝化层的材料。
在一些实施例中，所述冗余像素电路包括多个冗余薄膜晶体管和冗余存储电容器。所述第一栅导电层还包括所述多个冗余像素电路的第一冗余栅极图案，所述第一冗余栅极图案包括所述多个冗余薄膜晶体管的栅极和所述冗余存储电容器的第一极板。所述第二栅导电层还包括所述多个冗余像素电路的第二冗余栅极图案，所述第二冗余栅极图案包括所述冗余存储电容器的第二极板。所述源漏导电层还包括所述多个冗余像素电路的冗余源漏导电图案，所述冗余源漏导电图案包括所述多个冗余薄膜晶体管的源极和漏极、数据线、及电压信号线；所述冗余源漏导电图案与所述阳极层电绝缘。
在一些实施例中，沿第一方向相邻的两个冗余像素电路中，冗余有源层图案相互分离，第一冗余栅极图案连接，第二冗余栅极图案连接；所述第一方向为所述多个第一像素电路排列的行方向。沿第二方向相邻的两个冗余像素电路中，冗余有源层图案相互分离，冗余源漏导电图案连接；所述第二方向为所述多个第一像素电路排列的列方向。
在一些实施例中，显示面板还包括多个第二像素电路，多个第二像素电路设置于所述显示面板中除所述功能器件区以外的区域。所述阳极层还包括多个第二阳极，多个第二阳极位于所述功能器件区，每个第二阳极与一个第二像素电路电连接。
在一些实施例中，显示面板还包括转接导电层，转接导电层位于所述多个第一像素电路和所述多个第二像素电路所在膜层与所述阳极层之间，包括多个相互分离的转接块；多个转接块包括与所述第一像素电路 电连接的第一转接块，和与所述第二像素电路电连接的第二转接块。所述第一转接块在所述衬底上的正投影，覆盖与之电连接的第一像素电路的第一连接节点，且与该第一连接节点电连接；所述第一连接节点为第一像素电路中被配置为与第一阳极电连接的节点；所述第二转接块在所述衬底上的正投影，覆盖与之电连接的第二像素电路的第二连接节点，且与该第二连接节点电连接；所述第二连接节点为第二像素电路中被配置为与第二阳极电连接的节点。
在一些实施例中，所述多个第一像素电路和所述多个第二像素电路均位于所述主显示区。所述多个第二像素电路排列成多行和多列，位于同一行的相邻的两个第二像素电路之间设有多个第一像素电路。
在一些实施例中，显示面板还包括围绕所述主显示区的边框区。所述多个第二像素电路位于所述边框区。
在一些实施例中，显示面板还包括至少一层连接层；所述至少一层连接层位于所述转接导电层与所述阳极层之间；连接层包括多条连接线，连接线的一端通过第二转接块与所述第二像素电路电连接，连接线的另一端与所述第二阳极电连接。
另一方面，还提供一种显示装置，显示装置包括上述任一实施例所述的显示面板。
再一方面，还提供一种显示面板的制作方法，所述显示面板包括主显示区及功能器件区，所述主显示区至少部分围绕所述功能器件区；所述显示面板包括多个第一像素电路，及多个冗余像素电路，所述多个第一像素电路位于所述主显示区，所述多个冗余像素电路与所述主显示区靠近所述功能器件区的第一像素电路相邻。所述制作方法包括：在衬底上制作有源层；在所述有源层远离所述衬底的一侧制作阳极层。其中，所述有源层包括所述多个第一像素电路的第一有源层图案，和所述多个冗余像素电路的冗余有源层图案；所述阳极层包括位于所述主显示区的多个第一阳极，每个第一阳极与一个第一像素电路电连接；所述多个冗余像素电路与所述阳极层电绝缘。
在一些实施例中，所述第一像素电路包括多个第一薄膜晶体管和第一存储电容器。在所述在衬底上制作有源层，与所述在所述有源层远离所述衬底的一侧制作阳极层之间，还包括：在所述有源层远离所述衬底的一侧制作第一栅导电层；在所述第一栅导电层远离所述衬底的一侧制作第二栅导电层；在所述第二栅导电层远离所述衬底的一侧制作源漏导 电层。所述第一栅导电层包括所述多个第一像素电路的第一栅极图案，所述第一栅极图案包括所述多个第一薄膜晶体管的栅极、所述第一存储电容器的第一极板、扫描线、及发光信号线；所述第二栅导电层包括所述多个第一像素电路的第二栅极图案，所述第二栅极图案包括所述第一存储电容器的第二极板、第一初始化电源线、及第二初始化电源线；所述源漏导电层包括所述多个第一像素电路的源漏导电图案，所述源漏导电图案包括所述多个第一薄膜晶体管的源极和漏极、数据线、及电压信号线。
所述第一栅导电层的全部图案、所述第二栅导电层的全部图案和所述源漏导电层的全部图案在所述衬底上的正投影，均与所述冗余有源层在所述衬底上的正投影分离。或者，所述冗余像素电路包括多个冗余薄膜晶体管和冗余存储电容器；所述第一栅导电层还包括所述多个冗余像素电路的第一冗余栅极图案，所述第一冗余栅极图案包括所述多个冗余薄膜晶体管的栅极和所述冗余存储电容器的第一极板；所述第二栅导电层还包括所述多个冗余像素电路的第二冗余栅极图案，所述第二冗余栅极图案包括所述冗余存储电容器的第二极板；所述源漏导电层还包括所述多个冗余像素电路的冗余源漏导电图案，所述冗余源漏导电图案包括所述多个冗余薄膜晶体管的源极和漏极；所述冗余源漏导电图案与所述阳极层电绝缘。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示面板的结构图；
图2为显示面板中主显示区与功能器件设置区的交界区域的像素布置结构图；
图3A为根据一些实施例的过渡区的一种结构图；
图3B为根据一些实施例的过渡区的另一种结构图；
图3C为根据一些实施例的过渡区的又一种结构图；
图3D为根据一些实施例的过渡区的又一种结构图；
图3E为根据一些实施例的过渡区的又一种结构图；
图4为根据一些实施例的冗余像素电路的一种结构图；
图5A为图4中A′-A′及A〞-A〞的一种剖面视图；
图5B为图4中A′-A′及A〞-A〞的另一种剖面视图；
图6为根据一些实施例的冗余像素电路的另一种结构图；
图7为图6中B′-B′及B〞-B〞的剖面视图；
图8为根据一些实施例的第一像素电路的结构图；
图9为根据一些实施例的第二像素电路设置在主显示区的结构图；
图10为根据一些实施例的第二像素电路设置在边框区的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”、“电连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本文参阅作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本文中，使用了“同层设置”这样的表述，其是指利用同一掩模板通过一次构图工艺形成具有特定图形的膜层。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
本公开的一些实施例提供了一种显示装置1000，参阅图1，该显示装置1000可以为电视、电脑、笔记本电脑、手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等。
显示装置1000采用在屏幕背侧(背离屏幕出光面的一侧)设置功能器件的技术，功能器件例如为前置摄像头组件、屏下指纹组件、3D人脸识别组件、虹膜识别组件、近距离传感器等可以实现特定功能的器件。例如，在屏幕背侧设置前置摄像头组件的情况下，显示装置1000即采用了屏下摄像头技术。
参阅图1，显示装置1000包括显示面板100。在一些实施例中，显示面板100可以为有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板。
显示面板100包括主显示区101、功能器件区102以及围绕主显示器101的边框区104。功能器件设置于功能器件区102的背侧，且功能器件工作时需要接受来自外界的光线。为了提高功能器件的灵敏度，需要保证功能器件能够接收到足够量的光线，需要提升功能器件区102的光线透过率。
参阅图2，显示面板100包括多个子像素110，子像素110包括设置于衬底120上的像素电路20，以及设置于像素电路20所在膜层远离衬底120一侧的阳极32。其中，阳极32包括位于主显示区101的第一阳极321，及设置于功能器件区102内的第二阳极322。
参阅图2，为了提升功能器件区102的光线透过率，将与第二阳极322连接的像素电路20设置于显示面板100中除功能器件区102以外的区域；即功能器件区102不设置像素电路20，只保留第二阳极322。由于像素电路制作过程中，显示面板上靠近屏下摄像头的边缘区域的像素电路20的均一性较差，导致该区域的像素电路容易发生Vth偏移的问题，进而导致该像素电路20所在的子像素110发光异常(比如出现暗斑、亮斑等)；即，位于主显示区101靠近功能器件区102边缘的子像素110所包含的像素电路20的均一性较差，导致位于主显示区101靠近功能器件区102边缘的子像素110可能出现发光异常的问题。
本公开的一些实施例提供一种显示面板100，参阅图1，包括主显示区101和功能器件区102，主显示区101至少部分围绕功能器件区102。示例性的，参阅图3A和图3B，功能器件区102的部分边界与边框区104的部分重合，主显示区101部分围绕功能器件区102；参阅图3C，功能器件区102的边界与边框区104的分离，主显示区101围绕功能器件区102。
参阅图3A、图3B、图3C和图3D，显示面板100包括多个第一像素电路210，及多个冗余像素电路220，多个第一像素电路210位于主显示区101；多个冗余像素电路220与设置于主显示区101靠近功能器件区102的边缘的多个第一像素电路210相邻。即，位于主显示区101靠近功能器件区102的边缘的第一像素电路210的靠近功能器件区102的一侧，设置有与该第一像素电路210相邻的冗余像素电路220。
参阅图4和图5A，显示面板100包括沿垂直于衬底120且远离衬底120方向依次设置的有源层310和阳极层320。阳极层320包括位于主显示区101的多个第一阳极321，每个第一阳极321与一个第一像素电路210电连接。第一像素电路210与第一阳极321电连接，被配置向第一阳极321传输驱动电流，以控制第一阳极321所在的发光器件30发光。
冗余像素电路220至少包括位于有源层310的冗余有源层图案311，且冗余像素电路220与阳极层320电绝缘。由于制作工艺的影响，像素电路制作过程中，位于显示面板中靠近屏下摄像头的边缘区域的像素电 路的均一性较差，均一性较差的问题主要出现于有源层310，因此，冗余像素电路220至少包括位于有源层310的冗余有源层图案311。
本公开实施例提供的显示面板100，参阅图3A～图3E，位于主显示区101靠近功能器件区102的边缘的第一像素电路210的靠近功能器件区102的一侧，设置有与该第一像素电路210相邻的冗余像素电路220；并且，参阅图4和图6，冗余像素电路220包括位于有源层310的冗余有源层图案311。使有源层310的靠近功能器件区102的边缘从第一像素电路210的第一有源层图案312上，转移至冗余像素电路220的冗余有源层图案311上；进而避免第一像素电路210出现均一性差的问题，使位于主显示区101靠近功能器件区102的边缘的子像素20正常发光。而且，冗余像素电路220与阳极层320电绝缘，即，冗余像素电路220不控制任一子像素20进行发光，即使冗余像素电路220的冗余有源层图案311出现均一性较差的问题，也不会影响任何子像素20发光。
在一些实施例中，参阅图3A，多个第一像素电路210排列为多行和多列，任一行第一像素电路210沿第一方向M1(图3A中的水平方向)排列，任一列第一像素电路210沿第二方向M2(图3A中的竖直方向)排列。第一方向M1与第二方向M2交叉。
与功能器件区102的边界相交的任一行第一像素电路210的靠近功能器件区102的边缘，设置有至少两个沿第一方向排列的冗余像素电路220。与功能器件区102的边界相交的任一列第一像素电路210的靠近功能器件区102的边缘，设置有至少两个沿第二方向排列的冗余像素电路。即，位于主显示区101靠近功能器件区102的边缘的每个第一像素电路210，沿第一方向M1或沿第二方向M2靠近功能器件区102的一侧，设置有至少两个与该第一像素电路210相邻的冗余像素电路220；以确保有源层310上可能出现的均一性较差的区域，完全落入冗余像素电路220的冗余有源层图案311上，有利于提升显示面板100的良品率。
主显示区101靠近功能器件区102的边缘区域的第一像素电路210，靠近功能器件区102一侧设置的冗余像素电路220的数量越多，冗余像素电路220占用的区域面积越大，会有越多的冗余像素电路220位于功能器件区102的边缘，导致功能器件区102的边缘的透光率降低，影响功能器件的工作。或者，需要将功能器件区102的开口制作的更大，以避免冗余像素电路220影响功能器件的采光，不利于位于功能器件区102内的子像素120所包含的像素电路20的排布。
因此，与功能器件区102相交的任一行第一像素电路210的靠近功能器件区102的边缘，设置有2～4个沿第一方向排列的冗余像素电路220；同理，与功能器件区102相交的任一列第一像素电路210的靠近功能器件区102的边缘，设置有2～4个沿第二方向排列的冗余像素电路。可以在确保位于主显示区01靠近功能器件区102的边缘的第一像素电路210不会出现均一性较差的问题的前提下，尽可能减小冗余像素电路对功能器件区102的光线透过率的影响。
示例性的，参阅图3A，功能器件区102位于显示面板100沿第一方向的中部，与功能器件区102的边界相交任一行第一像素电路210，被功能器件区102分割为两部分。其中，位于功能器件区102左侧的第N行第一像素电路210中最右端的第一像素电路210的右侧，设置有至少两个与该第一像素电路210相邻的冗余像素电路220。比如，可以设置两个、三个或四个冗余像素电路220。
位于功能器件区102右侧的第M行第一像素电路210中最左端的第一像素电路210的左侧，设置有至少两个与该第一像素电路210相邻的冗余像素电路220；位于功能器件区102下侧的第O列第一像素电路210中最上端的第一像素电路210的上侧，设置有至少两个与该第一像素电路210相邻的冗余像素电路220；位于功能器件区102上侧的第P列第一像素电路210中最下端的第一像素电路210的下侧，设置有至少两个与该第一像素电路210相邻的冗余像素电路220。其中，第N行和第M行第一像素电路210与功能器件区102的边界相交，第O列和第P列第一像素电路210与功能器件区102的边界相交。
示例性的，参阅图3A，与功能器件区102相交的任一行第一像素电路210的靠近功能器件区102的边缘，设置有四个沿第一方向M1排列的冗余像素电路220；与功能器件区102相交的任一列第一像素电路210的靠近功能器件区102的边缘，设置有两个沿第二方向M2排列的冗余像素电路220。
示例性的，参阅图3C，与功能器件区102相交的任一行第一像素电路210的靠近功能器件区102的边缘，设置有两个沿第一方向M1排列的冗余像素电路220；与功能器件区102相交的任一列第一像素电路210的靠近功能器件区102的边缘，设置有两个沿第二方向M2排列的冗余像素电路220。
在一些实施例中，将冗余像素电路220所在的区域定义为过渡区103。 过渡区103包括主显示区101靠近功能器件区102的边缘，和/或，功能器件区102靠近主显示区101的边缘为过渡区103；即，过渡区103可以包括主显示区101的部分和/或功能器件区102的部分。示例性的，过渡区103可以全部位于功能器件区102；或者，过渡区102的一部分位于功能器件区102，一部分位于主显示区101；或者，过渡区102全部位于主显示区101。需要理解的是，第一阳极321所在的区域为主显示区；第二阳极321所在的区域为功能器件区102；冗余像素电路220所在的区域为过渡区103。
根据功能器件的形状的差异，功能器件区102的边界的形状可能不同，由此，过渡区103的形状也可能不相同。示例性的，功能器件区102的边界可以为矩形或近似矩形、圆形或近似圆形等，在此不做具体限定。
多个第一像素电路210排列为多行和多列，功能器件区102的边界由多段沿第一方向M1(多个第一像素电路210排列的行方向)排列的第一像素电路210的边界，以及多段沿第二方向M2(多个第一像素电路210排列的行方向)排列的第一像素电路210的边界交替连接形成。参阅图3B，在功能器件区102的边界的部分与边框区104的部分重合时，功能器件区102的边界至少包括一个沿第一方向M1延伸的直线段，以及两个沿第二方向M2延伸的直线段。
与功能器件区102的边界对应的，过渡区103至少包括第一直线延伸段1031和两个第二直线延伸段1032；第一直线延伸段1031位于过渡区103在第二方向M2上的一个边缘，两个第二直线延伸段1032分别位于过渡区103在第一方向M1上的两个边缘。
示例性的，参阅图3B，功能器件区102的边界为矩形，且功能器件区102第二方向M2上的一个边界(图3B中功能器件区102的上边界)与边框区104的边界部分重合；此时，过渡区103可以包括第一直线延伸段1031和两个第二直线延伸段1032。第一直线延伸段1031构成过渡区103第二方向M2上的一个边界(图3B中过渡区103的下边界)，两个第二直线延伸段1032分别构成过渡区103第一方向上的两个边界(图3B中过渡区103的左边界和右边界)。
第一直线延伸段1031设置有至少两行冗余像素电路220(与功能器件区102的边界相交的任一列第一像素电路210的靠近功能器件区102的边缘，设置有至少两个沿第二方向M2排列的冗余像素电路220)；即，与功能器件区102的部分边界重合的至少一行第一像素电路210中，与 功能器件区102的边界重合的部分，靠近功能器件区102的一侧设置有至少两行冗余像素电路220。
每个第二直线延伸段1302设置有至少两列冗余像素电路220(与功能器件区102的边界相交的任一行第一像素电路210的靠近功能器件区102的边缘，设置有至少两个沿第一方向M1排列的冗余像素电路220)；即，与功能器件区102的部分边界重合的至少一列第一像素电路210中，与功能器件区102的部分边界重合的部分，靠近功能器件区102的一侧设置有至少两列冗余像素电路220。
在一些实施例中，参阅图3A和图3C，过渡区103还包括四个折线延伸段1033；每个折线延伸段1033包括多个依次连接的线段10331，每个线段10331设置有多行冗余像素电路220，位于不同线段10331中的多行冗余像素电路220在第一方向M1错开；第一直线延伸段1031与第二直线延伸段1032之间通过折线延伸段1033连接。
示例性的，功能器件区102的边界形状为近似圆形，功能器件区102的边界的拐角处，由多个沿第一方向M1延伸的直线段和多个沿第二方向M2延伸的直线段交替连接形成的折线段。与功能器件区102的边界的折线段相对应的，过渡区103包括折线延伸段1033，且过渡区103的折线延伸段1033设置于与功能器件区102的边界的折线段对应的位置。
功能器件区102在显示面板100上的位置并不唯一，根据功能器件区102在显示面板100上的不同位置，过渡区103的形状也可能不相同。例如，功能器件区102可以设置在显示面板100的上部中间位置(如图3A所示)，或者设置在显示面板100上部左侧或右侧，还可以设置在显示面板100下部的中间位置；功能器件区102可以完全被主显示区101围绕(如图3C所示)，功能器件区102的部分边界也可以与边框区104的部分边界重合，即，主显示区101部分围绕功能器件区102(如图3A所示)。
参阅图3A，在功能器件区102的上边界与边框区104的部分边界重合的情况下，过渡区103为一侧(上侧)具有开口1035的环形，开口1035位于过渡区103的与第一直线段1031相对的边缘。
过渡区103可以仅包括第一直线延伸段1031和两个第二直线延伸段1032(如图3B所示)；或者，过渡区103还包括两个折线延伸段1033或四个折线延伸段1033(如图3A所示)。过渡区103还可以包括其他延伸段，在此不再一一列举。
参阅图3C，在功能器件区102的边界全部位于主显示区101内的情况下，过渡区103还包括第三直线延伸段1034，第三直线延伸段1034位于过渡区103的与第一直线段1031相对的边缘，第三直线延伸段1034包括至少两行冗余像素电路220；过渡区103为封闭的环形。第一直线延伸段1301和第三直线延伸段1034分别构成过渡区103第一方向M1上的两个边界(图3C中，过渡区103的上下边界)。
示例性的，过渡区103可以包括第一直线延伸段1031、两个第二直线延伸段1032以及第三直线延伸段1034；或者，过渡区103还可以包括两个折线延伸段1303或四个折线延伸段1033。过渡区103还可以包括其他延伸段，在此不再一一列举。
在一些实施例中，参阅图3D，还可以仅在与功能器件区102的边界相交的任一行第一像素电路210的靠近功能器件区102的边缘，设置至少两个沿第一方向M1排列的冗余像素电路220。或者，参阅图3E，仅在与功能器件区102的边界相交的任一列第一像素电路210的靠近功能器件区102的边缘，设置至少两个沿第二方向M2排列的冗余像素电路220。
在一些实施例中，参阅图3C，多个冗余像素电路220排列所形成的图形相对于过渡区103的沿第一方向M1的一条直线L2对称。和/或，参阅图3A、图3B及图3C，参阅图3C，多个冗余像素电路220排列所形成的图形相对于过渡区103的沿第二方向M2的一条直线L1对称。多个冗余像素电路220相对于过渡区103沿第一方向M1的一条直线L2对称，和/或，相对于过渡区103的沿第二方向M2的一条直线L1对称，有利于提升冗余像素电路220的冗余有源层图案311均一性，改善有源层310整体的均一性。
在一些实施例中，参阅图4和图5A，第一像素电路210包括多个第一薄膜晶体管(英文：Thin Film Transistor；简称TFT)211和第一存储电容器212；其中图5A中A′-A′的部分为第一像素电路210中的一个第一薄膜晶体管211及第一存储电容器212的剖面视图。第一薄膜晶体管211可以为P型晶体管或N型晶体管，在此不做具体限定。
有源层310包括多个第一薄膜晶体管211的第一有源层图案312，每个第一像素电路210包括一个位于有源层310的第一有源层图案312。
参阅图4、图5A和图8，显示面板100还包括第一栅导电层330、第二栅导电层340、及源漏导电层350。
第一栅导电层330设置于有源层310与阳极层320之间，包括多个第一像素电路210的第一栅极图案331，第一栅极图案331包括多个第一薄膜晶体管211的栅极G1、第一存储电容器212的第一极板C11、扫描线GL、及发光信号线EM。
第二栅导电层340设置于第一栅导电层330与阳极层320之间，包括多个第一像素电路210的第二栅极图案341，第二栅极图案341包括第一存储电容器212的第二极板C12、第一初始化电源线Vint1、及第二初始化电源线Vint2。
源漏导电层350设置于第二栅导电层340与阳极层320之间，包括多个第一像素电路210的源漏导电图案351，源漏导电图案351包括多个第一薄膜晶体管30的源极S1和漏极D1、数据线DATA、及电压信号线VDD。第一有源层图案312、第一栅极图案331、第二栅极图案341和源漏导电图案351一起构成第一像素电路210。
显示面板100还包括设置于有源层310与第一栅导电层330之间的第一栅绝缘层360；设置于第一栅导电层330与第二栅导电层340之间的第二栅绝缘层370；设置于第二栅导电层340与源漏导电层350之间的层间绝缘层380；以及设置于源漏导电层350与阳极层320之间的钝化层390、以及平坦化层420。其中，第一栅绝缘层360、第二栅绝缘层370、层间绝缘层380、钝化层390、及平坦化层420均为整层结构，均覆盖冗余有源层图案311。相邻两个导电层之间设置至少一层绝缘层，以避免相邻两层导电层上的图案发生交叠。
冗余像素电路220可以仅包括冗余有源层图案311；或者，冗余像素电路220可以包括依次层叠设置于衬底120上的冗余有源层图案311、冗余第一栅极图案332、冗余第二栅极图案342、及冗余源漏导电层图案352。
参阅图6、图7和图8，在冗余像素电路220仅包括冗余有源层图案311的情况下，第一栅导电层330的全部图案、第二栅导电层340的全部图案和源漏导电层350的全部图案在衬底120上的正投影，均与冗余有源层图案311在衬底120上的正投影分离；即冗余有源层图案311的上方不存在第一栅导电层330、第二栅导电层340和源漏导电层350中的导电图案。这样，冗余像素电路210的结构简单，第一栅导电层330、第二栅导电层340和源漏导电层350的图案简单，有利于提升显示面板100的制作效率。
参阅图7，第一栅绝缘层360、第二栅绝缘层370、层间绝缘层380中设置有多个过孔361，多个过孔361穿过第一栅绝缘层360、第二栅绝缘层370、层间绝缘层380，且过孔361在衬底120上的正投影，位于冗余有源层图案311在衬底120上的正投影范围内；以使冗余像素电路210的冗余有源层图案311与第一像素电路210的第一有源层图案312的结构一致，有利于提升有源层310靠近功能器件区102的边缘的均一性，降低第一有源层图案312出现均一性差的可能性。
由于冗余像素电路220仅包括冗余有源层图案311，且层间绝缘层380远离冗余有源层图案311的一侧设置有钝化层390，根据显示面板100的制作过程，因此，形成过孔361后，需要制作源漏导电层350以及钝化层390；第一像素电路210的过孔内被源漏导电层350填充；冗余像素电路220的过孔361内填充有钝化层390的材料。
参阅图4、图5A和图8，在冗余像素电路220包括多个冗余薄膜晶体管221和冗余存储电容器222的确情况下，即，冗余像素电路220包括依次层叠设置于衬底120上的冗余有源层图案311、冗余第一栅极图案332、冗余第二栅极图案342、及冗余源漏导电层图案352。其中，图8为第一像素电路210的结构图，在冗余像素电路220包括多个冗余薄膜晶体管221和冗余存储电容器222的确情况下，冗余像素电路220的结构与第一像素电路210的结构相同，因此，冗余像素电路220的各导电层图案可参考第一像素电路210对应的导电层图案。
第一栅导电层330还包括多个冗余像素电路220的第一冗余栅极图案332，第一冗余栅极图案332包括多个冗余薄膜晶体管221的栅极G2和冗余存储电容器222的第一极板C21；且第一冗余栅极图案332与第一栅极图案331同层设置。
第二栅导电层340还包括多个冗余像素电路220的第二冗余栅极图案342，第二冗余栅极图案342包括冗余存储电容器222的第二极板C22；且第二冗余栅极图案342与第二栅极图案341同层设置。
源漏导电层350还包括多个冗余像素电路220的冗余源漏导电图案352，冗余源漏导电图案352包括多个冗余薄膜晶体管221的源极S2和漏极D2；冗余源漏导电图案352与阳极层320电绝缘，且冗余源漏导电图案352与源漏导电图案351同层设置。
冗余像素电路220包括多个冗余薄膜晶体管221和冗余存储电容器222，冗余像素电路220与第一像素电路210在结构上相同(但是冗余像 素电路220不与阳极层320电连接，第一像素电路210与阳极层320的第一阳极321电连接)；可以提升主显示区101靠近功能器件区102的边缘的多个第一像素电路210的第一栅极图案331、第二栅极图案341及源漏导电图案351的均一性，使主显示区101靠近功能器件区102的边缘的多个第一像素电路210的均一性更好，进一步降低主显示区101靠近功能器件区102的边缘的第一像素电路210发生Vth偏移的概率，使主显示区101靠近功能器件区102的边缘的发光器件30正常发光。
在一些实施例中，沿第一方向M1相邻的两个冗余像素电路220中，冗余有源层图案311相互分离(参阅图6)，第一冗余栅极图案332连接(扫描线GL及发光信号线EM相连)，第二冗余栅极图案342连接(第一初始化电源线Vint1及第二初始化电源线Vint2连接)。沿第二方向M2相邻的两个冗余像素电路220中，冗余有源层图案311相互分离(参阅图6)，冗余源漏导电图案352连接(数据线DATA及电压信号线VDD相连)。即，在冗余像素电路220包括多个冗余薄膜晶体管221和冗余存储电容器222的情况下，沿第一方向相邻的两个冗余像素电路220的冗余有源层图案351相互分离，第一冗余栅极图案332和第二冗余栅极图案342连接；沿第二方向M2相邻的两个冗余像素电路220的冗余有源层图案311相互分离，冗余源漏导电图案连接。
需要理解的是，在冗余像素电路220仅包括设置于有源层310上的冗余有源层图案311的情况下，沿第一方向M1相邻的两个冗余像素电路220的冗余有源层图案311相互分离；沿第二方向M2相邻的两个冗余像素电路220的冗余有源层图案311相互分离。
在一些实施例中，参阅图9或图10，阳极层320还包括多个第二阳极322，多个第二阳极322位于功能器件区102。显示面板100还包括多个第二像素电路230，每个第二阳极322与一个第二像素电路电230连接；多个第二像素电路230设置于显示面板100中除功能器件区102以外的区域。第二像素电路203的结构可以与第一像素电路210的结构相同；将第二像素电路230设置于显示面板100中除功能器件区102以外的区域，有利于提升功能器件区102的光线透过率，以使在功能器件工作时，功能器件能够采集到足够的光线。
在一些实施例中，参阅图5A、图9和图10；显示面板100还包括转接导电层410，第一像素电路210和第二像素电路230通过转接导电层410与第一阳极321或第二阳极322电连接。转接导电层410位于多 个第一像素电路210和多个第二像素电路230所在膜层与阳极层320之间，且位于钝化层390与阳极层320之间。转接导电层410能够降低源漏导电层350与阳极层320连接时单个过孔的深度，提升像素电路20间接与发光器件30之间的连接稳定性，同时降低制作过孔过程的工艺难度。
转接导电层410包括多个相互分离的转接块411。多个转接块411包括与第一像素电路210电连接的第一转接块4111，和与第二像素电路230电连接的第二转接块4112。
第一转接块4111在衬底120上的正投影，覆盖与之电连接的第一像素电路210的第一连接节点N1，进而屏蔽第一转接块4111远离衬底120一侧的连接层430，降低或消除连接层430对第一连接节点N1的影响。第一转接块4111与该第一连接节点N1电连接，第一阳极321与第一转接块4111电连接；以使第一阳极321通过第一转接块4111与第一像素电路210电连接。其中，第一连接节点N1为第一像素电路210中被配置为与第一阳极电321连接的节点。
第二转接块4112在衬底120上的正投影，覆盖与之电连接的第二像素电路230的第二连接节点N2，进而屏蔽第二转接块4112远离衬底120一侧的连接层430，降低或消除连接层430对第二连接节点N2的影响。第二转接块4112与该第二连接节点N2电连接，第二阳极322与第二转接块4112电连接；以使第二阳极322通过第二转接块4112与第二像素电路230电连接。其中，第二连接节点N2为第二像素电路230中被配置为与第二阳极322电连接的节点。
在一些实施例中，显示面板100还包括边框区104，边框区104围绕主显示区101。第二像素电路230可以设置在主显示区101(如图9所示)或者设置在边框区104(如图10所示)。
参阅图9，在第二像素电路230设置于主显示区101的情况下，多个第一像素电路210和多个第二像素电路230均位于主显示区101。多个第二像素电路230排列成多行和多列，位于同一行的相邻的两个第二像素电路230之间设有多个第一像素电路210，即，多列第二像素电路230间隔插入多列第一像素电路210之间的间隙中，第二像素电路230设置于主显示区101，有利于降低边框区104的宽度，提升显示面板100的屏占比。
参阅图10，将第二像素电路230设置于边框区104，有利于提升显示面板100的主显示区101的像素密度。示例性的，在一些高像素密度 (英文：Pixels Per Inch；简称：PPI)的显示面板100中，其像素密度较大，相应的，第一像素电路210的密度较大，第一像素电路210之间可以利用的间隙很小，第二像素电路230不容易插入第一像素电路210的间隔中。因此，第二像素电路230设置在边框区104，有利于提升显示面板100主显示区101的像素密度，有利于制作高PPI的显示面板100。
第二阳极322位于功能器件区102，而第二像素电路230设置于显示面板100中除功能器件区102以外的区域；即，第二像素电路230在衬底120上的正投影与第二阳极322在衬底上的正投影不重叠，第二阳极322与第二像素电路230之间不能通过过孔直接电连接。
因此，参阅图9和图10，显示面板100还包括至少一层连接层430，至少一层连接层430位于转接导电层410与阳极层320之间；连接层430包括多条连接线431，连接线431的一端通过第二转接块4112与第二像素电路230电连接，连接线431的另一端与第二阳极322电连接。
为提升功能器件区102的光线透过率，连接层430的连接线431可以由透明导电材料制成，例如氧化铟锡(英文：Indium Tin Oxides；简称：ITO)。
由于功能器件区102内的第二阳极322的数量为多个，因此需要多条连接线431连接多个第二阳极322和多个第二像素电路230。多条连接线431以设置于同一连接层430中，也可以设置于不同的连接层430中，以为多条连接线431提供足够的布线空间；其中，在连接层430的数量大于两层的情况下，任意相邻两层连接层430之间设置有至少一层绝缘层440。
示例性的，参阅图5B和图7，连接层430的数量为三层；沿垂直于衬底120，且由衬底120指向阳极层320的方向，三层连接层430依次为第一连接层4301、第二连接层4302和第三连接层4303，第一连接层4301与第二连接层4302之间设有一层绝缘层441，第二连接层4302与第三连接层4303之间设有一层绝缘层442；且转接导电层410与第一连接层4301之间设有一层绝缘层443，第三连接层4303与阳极层320之间设有一层绝缘层444。
参阅图5A和图5B，在显示面板100包括多层连接层430的情况下，对于需要通过连接线431进行电连接的第二像素电路230和第二阳极322而言，需要在其中一层连接层430设置连接线431外，还需要在除连接线431所在连接层430之外的其他连接层430上设置第三转接块432， 第二阳极322通过第三转接块422与连接线431电连接，和/或，连接线431通过第三转接块422与第二转接块412电连接。
在一些实施例中，从第二阳极322的数量较多，不同位置处的第二阳极322可以通过不同的连接层430的连接线431与第二像素电路230电连接。示例性的，同一个像素单元(至少包括红色子像素、绿色子像素和蓝色子像素)的不同子像素120的第二阳极，通过不同层的连接线431与第二像素电路230电连接；或者，相邻两个第二阳极322通过不同层的连接线431与第二像素电路230电连接，等等，在此不再一一列举。
示例性的，参阅5A，第二阳极322通过第三连接层4303内的连接线431与第二像素电路230电连接；参阅图5B，第二阳极322通过第一连接层4301内的连接线431与第二像素电路230电连接。其中，在图5B中，可以认为图4中A〞-A〞所截的第二阳极322是位于功能器件区102的中心区域的第二阳极322，这样，第二阳极322靠近衬底110的一侧没有冗余像素电路。
在一些数量中，参阅图5和图7，显示面板100还包括设置于阳极层320远离衬底120一侧的像素界定层450，像素界定层450包括多个开口区451，一个第一阳极321或一个第二阳极321与一个开口区451相对应。
开口区451内设有发光功能层460，示例性的，发光功能层460包括电子传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)中的一层或多层。
显示面板100还包括设置于像素界定层450和发光功能层远离衬底120一侧的阴极导电层470，以及位于阴极导电层470远离衬底120一侧的封装层480。
本公开的一些实施例还提供了一种显示面板100的制作方法，显示面板100包括主显示区101及功能器件区102，主显示区101至少部分围绕功能器件区102；显示面板100包括多个第一像素电路210，及多个冗余像素电路220，多个第一像素电路210位于主显示区101，多个冗余像素电路220与主显示区101靠近功能器件区102的第一像素电路210相邻。
上述制作方法包括：
S10，在衬底120上制作有源层310。
有源层310包括多个第一像素电路210的第一有源层图案312，和多个冗余像素电路220的冗余有源层图案311。
S20，在有源层310远离衬底120的一侧制作阳极层320。
阳极层320包括位于主显示区101的多个第一阳极321，每个第一阳极321与一个第一像素电路210电连接；多个冗余像素电路220与阳极层320电绝缘。
通过上述制作方法获得的显示面板100，位于主显示区101靠近功能器件区102的边缘的第一像素电路210的靠近功能器件区102的一侧，包括与该第一像素电路210相邻的冗余像素电路220，且冗余像素电路220包括位于有源层310的冗余有源层图案311，进而避免第一像素电路210的第一有源层图案312出现均一性差的问题，使位于主显示区101靠近功能器件区102的边缘的第一阳极321所在的子像素120能够正常发光。
在一些实施例中，第一像素电路210包括多个第一薄膜晶体管211和第一存储电容器212。在S10在衬底120上制作有源层310，与S20在有源层310远离衬底120的一侧制作阳极层320之间，上述制作方法还包括：
S11，在有源层310远离衬底120的一侧制作第一栅导电层330。
第一栅导电层330包括多个第一像素电路210的第一栅极图案331，第一栅极图案331包括多个第一薄膜晶体管211的栅极G1、第一存储电容器212的第一极板C11、扫描线GL、及发光信号线EM。
S12，在第一栅导电层330远离衬底120的一侧制作第二栅导电层340。
第二栅导电层340包括多个第一像素电路210的第二栅极图案341，第二栅极图案341包括第一存储电容器212的第二极板C12、第一初始化电源线Vint1、及第二初始化电源线Vint2。
S13，在第二栅导电层340远离衬底120的一侧制作源漏导电层350。
源漏导电层350包括多个第一像素电路210的源漏导电图案351，源漏导电图案351包括多个第一薄膜晶体管30的源极S1和漏极D1、数据线DATA、及电压信号线VDD。
第一有源层图案312、第一栅极图案331、第二栅极图案341和源漏 导电图案351一起构成第一像素电路210。
在一些实施例中，冗余像素电路220可以仅包括冗余有源层图案311，还可以包括依次层叠设置于衬底120上的冗余有源层图案311、冗余第一栅极图案332、冗余第二栅极图案342、及冗余源漏导电层图案352。
在冗余像素电路220仅包括冗余有源层图案311的情况下，第一栅导电层330的全部图案、第二栅导电层340的全部图案和源漏导电层350的全部图案在衬底120上的正投影，均与冗余有源层图案311在衬底120上的正投影分离。
在冗余像素电路220包括多个冗余薄膜晶体管221和冗余存储电容器222的情况下；即，冗余像素电路220还包括依次层叠设置于衬底120上的冗余有源层图案311、冗余第一栅极图案332、冗余第二栅极图案342、及冗余源漏导电层图案352。
第一栅导电层330还包括多个冗余像素电路220的第一冗余栅极图案332，冗余栅极图案332包括多个冗余薄膜晶体管221的栅极G2和冗余存储电容器222的第一极板C21；第一冗余栅极图案332与第一栅极图案331同层设置。
第二栅导电层340还包括多个冗余像素电路220的第二冗余栅极图案342，第二冗余栅极图案342包括冗余存储电容器222的第二极板C22；第二冗余栅极图案342与第二栅极图案341同层设置。
源漏导电层350还包括多个冗余像素电路220的冗余源漏导电图案352，冗余源漏导电图案352包括多个冗余薄膜晶体管221的源极S2和漏极D2；冗余源漏导电图案352与阳极层320电绝缘，且冗余源漏导电图案352与源漏导电图案351同层设置。
冗余像素电路220的结构与第一像素电路210的结构相同。但是，冗余像素电路220与阳极层320之间电绝缘，冗余像素电路220不控制任一发光器件30发光；第一像素电路210与第一阳极321电连接，用于控制第一阳极321所在发光器件30的发光。冗余像素电路220能够提升第一像素电路210的均一性，避免第一像素电路210产生Vth偏移的问题，从而解决与位于主显示区101靠近功能器件区102的边缘的第一像素电路210相连的发光器件30显示异常的问题。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的 保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示面板，包括主显示区及功能器件区，所述主显示区至少部分围绕所述功能器件区；
    所述显示面板包括多个第一像素电路，及多个冗余像素电路，所述多个第一像素电路位于所述主显示区；
    所述显示面板包括沿垂直于衬底且远离衬底方向依次设置的有源层和阳极层；
    所述阳极层包括位于所述主显示区的多个第一阳极，每个第一阳极与一个第一像素电路电连接；
    所述多个冗余像素电路与设置于所述主显示区靠近所述功能器件区的边缘的多个第一像素电路相邻；冗余像素电路至少包括位于有源层的冗余有源层图案，且所述冗余像素电路与所述阳极层电绝缘。
  2. 根据权利要求1所述的显示面板，其中，任一行第一像素电路沿第一方向排列，任一列第一像素电路沿第二方向排列，所述第一方向与所述第二方向交叉；
    与所述功能器件区的边界相交的任一行第一像素电路的靠近所述功能器件区的边缘，设置有至少两个沿第一方向排列的冗余像素电路；
    与所述功能器件区的边界相交的任一列第一像素电路的靠近所述功能器件区的边缘，设置有至少两个沿第二方向排列的冗余像素电路。
  3. 根据权利要求2所述的显示面板，其中，
    与所述功能器件区相交的任一行第一像素电路的靠近所述功能器件区的边缘，设置有2～4个沿第一方向排列的冗余像素电路；
    与所述功能器件区相交的任一列第一像素电路的靠近所述功能器件区的边缘，设置有2～4个沿第二方向排列的冗余像素电路。
  4. 根据权利要求1～3中任一项所述的显示面板，其中，所述多个冗余像素电路位于所述过渡区；所述过渡区包括：
    第一直线延伸段，位于过渡区在第二方向上的一个边缘，所述第一直线延伸段设置有至少两行冗余像素电路；
    两个第二直线延伸段，分别位于所述过渡区在第一方向上的两个边缘，每个第二直线延伸段设置有至少两列冗余像素电路。
  5. 根据权利要求4所述的显示面板，其中，所述过渡区还包括：
    四个折线延伸段，每个折线延伸段包括多个依次连接的线段，每个线段设置有多行冗余像素电路，位于不同线段中的多行冗余像素电路在第一方向错开，所述第一直线延伸段与所述第二直线延伸段之间通过所述折线延伸段 连接。
  6. 根据权利要求4或5所述的显示面板，其中，所述过渡区为一侧开口的环形，开口位于所述过渡区的与第一直线段相对的边缘；或者，
    所述过渡区还包括第三直线延伸段，第三直线延伸段位于所述过渡区的与第一直线段相对的边缘，所述第三直线延伸段包括至少两行冗余像素电路；所述过渡区为封闭的环形。
  7. 根据权利要求4～6中任一项所述的显示面板，其中，所述多个冗余像素电路排列所形成的图形相对于所述过渡区的沿第一方向的一条直线对称；和/或，
    所述多个冗余像素电路排列所形成的图形相对于所述过渡区的沿第二方向的一条直线对称。
  8. 根据权利要求1～7中任一项所述的显示面板，其中，第一像素电路包括多个第一薄膜晶体管和第一存储电容器；所述有源层还包括所述多个第一薄膜晶体管的第一有源层图案；
    所述显示面板还包括：
    第一栅导电层，设置于所述有源层与所述阳极层之间，包括所述多个第一像素电路的第一栅极图案，所述第一栅极图案包括所述多个第一薄膜晶体管的栅极、所述第一存储电容器的第一极板、扫描线、及发光信号线；
    第二栅导电层，设置于所述第一栅导电层与所述阳极层之间，包括所述多个第一像素电路的第二栅极图案，所述第二栅极图案包括所述第一存储电容器的第二极板、第一初始化电源线、及第二初始化电源线；
    源漏导电层，设置于所述第二栅导电层与所述阳极层之间，包括所述多个第一像素电路的源漏导电图案，所述源漏导电图案包括所述多个第一薄膜晶体管的源极和漏极、数据线、及电压信号线。
  9. 根据权利要求8所述的显示面板，其中，所述第一栅导电层的全部图案、所述第二栅导电层的全部图案和所述源漏导电层的全部图案在所述衬底上的正投影，均与所述冗余有源层图案在所述衬底上的正投影分离。
  10. 根据权利要求9所述的显示面板，还包括：
    第一栅绝缘层，设置于所述有源层与所述第一栅导电层之间；
    第二栅绝缘层，设置于所述第一栅导电层与所述第二栅导电层之间；
    层间绝缘层，设置于所述第二栅导电层与所述源漏导电层之间；
    其中，所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层均覆盖所述冗余有源层图案；
    所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中设置有多个过孔，过孔穿过所述层间绝缘层、所述第二栅绝缘层和所述第一栅绝缘层，且所述过孔在所述衬底上的正投影，位于所述冗余有源层图案在所述衬底上的正投影范围内。
  11. 根据权利要求10所述的显示面板，还包括：
    钝化层，设置于所述源漏导电层与所述阳极层之间，且覆盖所述冗余有源层图案；
    所述过孔内填充有所述钝化层的材料。
  12. 根据权利要求8所述的显示面板，其中，所述冗余像素电路包括多个冗余薄膜晶体管和冗余存储电容器；
    所述第一栅导电层还包括所述多个冗余像素电路的第一冗余栅极图案，所述第一冗余栅极图案包括所述多个冗余薄膜晶体管的栅极和所述冗余存储电容器的第一极板；
    所述第二栅导电层还包括所述多个冗余像素电路的第二冗余栅极图案，所述第二冗余栅极图案包括所述冗余存储电容器的第二极板；
    所述源漏导电层还包括所述多个冗余像素电路的冗余源漏导电图案，所述冗余源漏导电图案包括所述多个冗余薄膜晶体管的源极和漏极；所述冗余源漏导电图案与所述阳极层电绝缘。
  13. 根据权利要求12所述的显示面板，其中，沿第一方向相邻的两个冗余像素电路中，冗余有源层图案相互分离，第一冗余栅极图案连接，第二冗余栅极图案连接；所述第一方向为所述多个第一像素电路排列的行方向；
    沿第二方向相邻的两个冗余像素电路中，冗余有源层图案相互分离，冗余源漏导电图案连接；所述第二方向为所述多个第一像素电路排列的列方向。
  14. 根据权利要求1～13中任一项所述的显示面板，还包括：
    多个第二像素电路，设置于所述显示面板中除所述功能器件区以外的区域；
    所述阳极层还包括：
    多个第二阳极，位于所述功能器件区，每个第二阳极与一个第二像素电路电连接。
  15. 根据权利要求14所述的显示面板，还包括：
    转接导电层，位于所述多个第一像素电路和所述多个第二像素电路所在膜层与所述阳极层之间，包括多个相互分离的转接块；多个转接块包括与所述第一像素电路电连接的第一转接块，和与所述第二像素电路电连接的第二 转接块；
    所述第一转接块在所述衬底上的正投影，覆盖与之电连接的第一像素电路的第一连接节点，且与该第一连接节点电连接；所述第一连接节点为第一像素电路中被配置为与第一阳极电连接的节点；
    所述第二转接块在所述衬底上的正投影，覆盖与之电连接的第二像素电路的第二连接节点，且与该第二连接节点电连接；所述第二连接节点为第二像素电路中被配置为与第二阳极电连接的节点。
  16. 根据权利要求15所述的显示面板，其中，所述多个第一像素电路和所述多个第二像素电路均位于所述主显示区；
    所述多个第二像素电路排列成多行和多列，位于同一行的相邻的两个第二像素电路之间设有多个第一像素电路。
  17. 根据权利要求15所述的显示面板，还包括围绕所述主显示区的边框区；
    所述多个第二像素电路位于所述边框区。
  18. 根据权利要求15～17中任一项所述的显示面板，还包括：
    至少一层连接层，位于所述转接导电层与所述阳极层之间；所述连接层包括多条连接线，连接线的一端通过第二转接块与所述第二像素电路电连接，连接线的另一端与所述第二阳极电连接。
  19. 一种显示装置，包括如权利要求1～18中任一项所述的显示面板。
  20. 一种显示面板的制作方法，所述显示面板包括主显示区及功能器件区，所述主显示区至少部分围绕所述功能器件区；所述显示面板包括多个第一像素电路，及多个冗余像素电路，所述多个第一像素电路位于所述主显示区，所述多个冗余像素电路与所述主显示区靠近所述功能器件区的第一像素电路相邻；
    所述制作方法包括：
    在衬底上制作有源层；所述有源层包括所述多个第一像素电路的第一有源层图案，和所述多个冗余像素电路的冗余有源层图案；
    在所述有源层远离所述衬底的一侧制作阳极层；所述阳极层包括位于所述主显示区的多个第一阳极，每个第一阳极与一个第一像素电路电连接；所述多个冗余像素电路与所述阳极层电绝缘。
  21. 根据权利要求20所述的方法，其中，所述第一像素电路包括多个第一薄膜晶体管和第一存储电容器；
    在所述在衬底上制作有源层，与所述在所述有源层远离所述衬底的一侧 制作阳极层之间，还包括：
    在所述有源层远离所述衬底的一侧制作第一栅导电层；所述第一栅导电层包括所述多个第一像素电路的第一栅极图案，所述第一栅极图案包括所述多个第一薄膜晶体管的栅极、所述第一存储电容器的第一极板、扫描线、及发光信号线；
    在所述第一栅导电层远离所述衬底的一侧制作第二栅导电层；所述第二栅导电层包括所述多个第一像素电路的第二栅极图案，所述第二栅极图案包括所述第一存储电容器的第二极板、第一初始化电源线、及第二初始化电源线；
    在所述第二栅导电层远离所述衬底的一侧制作源漏导电层；所述源漏导电层包括所述多个第一像素电路的源漏导电图案，所述源漏导电图案包括所述多个第一薄膜晶体管的源极和漏极、数据线、及电压信号线；
    其中，所述第一栅导电层的全部图案、所述第二栅导电层的全部图案和所述源漏导电层的全部图案在所述衬底上的正投影，均与所述冗余有源层在所述衬底上的正投影分离；或者，
    所述冗余像素电路包括多个冗余薄膜晶体管和冗余存储电容器；所述第一栅导电层还包括所述多个冗余像素电路的第一冗余栅极图案，所述冗余栅极图案包括所述多个冗余薄膜晶体管的栅极、所述冗余存储电容器的第一极板；所述第二栅导电层还包括所述多个冗余像素电路的第二冗余栅极图案，所述第二冗余栅极图案包括所述冗余存储电容器的第二极板；所述源漏导电层还包括所述多个冗余像素电路的冗余源漏导电图案，所述冗余源漏导电图案包括所述多个冗余薄膜晶体管的源极和漏极；所述冗余源漏导电图案与所述阳极层电绝缘。
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