WO2022124559A1 - 반도체 공정용 연마 조성물, 연마 조성물의 제조 방법 및 연마 조성물을 적용한 반도체 소자의 제조 방법 - Google Patents
반도체 공정용 연마 조성물, 연마 조성물의 제조 방법 및 연마 조성물을 적용한 반도체 소자의 제조 방법 Download PDFInfo
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- WO2022124559A1 WO2022124559A1 PCT/KR2021/014480 KR2021014480W WO2022124559A1 WO 2022124559 A1 WO2022124559 A1 WO 2022124559A1 KR 2021014480 W KR2021014480 W KR 2021014480W WO 2022124559 A1 WO2022124559 A1 WO 2022124559A1
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- polishing
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- semiconductor
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- 239000011734 sodium Substances 0.000 description 1
- BDHFUVZGWQCTTF-UHFFFAOYSA-M sulfonate Chemical compound [O-]S(=O)=O BDHFUVZGWQCTTF-UHFFFAOYSA-M 0.000 description 1
- 238000010558 suspension polymerization method Methods 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 235000008521 threonine Nutrition 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000004474 valine Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 239000010457 zeolite Substances 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K3/00—Materials not provided for elsewhere
- C09K3/14—Anti-slip materials; Abrasives
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Definitions
- the present invention relates to a polishing composition for a semiconductor process, a method of manufacturing the polishing composition, and a method of manufacturing a semiconductor device to which the polishing composition is applied.
- CMP chemical mechanical polishing
- the substrate is pressed and rotated while the slurry is supplied to the polishing pad, and the surface is polished.
- the target to be planarized varies according to the stage of the process, and there are also differences in the physical properties of the slurry applied at this time.
- the CMP process has been applied to planarization of dielectrics such as silicon oxide film (SiO 2 ) and silicon nitride film (SiN), and is essentially used for planarization process for metal wiring such as tungsten (W) and copper (Cu).
- dielectrics such as silicon oxide film (SiO 2 ) and silicon nitride film (SiN)
- metal wiring such as tungsten (W) and copper (Cu).
- films of various materials having different etch selectivity characteristics are required.
- a carbon-based organic film has good etch selectivity with respect to other silicon-containing films, and thus can be used as a mask film or a sacrificial film.
- Another object of the present invention is to be applied to a polishing process of an amorphous carbon layer (ACL), thereby exhibiting a high polishing rate, and preventing carbon residue from adsorption on a semiconductor substrate during the polishing process to prevent defects It is to provide a polishing composition for a semiconductor process that prevents the occurrence.
- ACL amorphous carbon layer
- Another object of the present invention is to provide a method of manufacturing a polishing composition for a semiconductor process that maintains polishing performance at high temperatures and has high storage stability through stabilization of an accelerator in the polishing composition.
- Another object of the present invention is to provide a method of manufacturing a semiconductor device to which a polishing composition for a semiconductor process is applied.
- the polishing composition for a semiconductor process is abrasive particles; accelerator; and stabilizers.
- a method of manufacturing a polishing composition for a semiconductor process comprises: a) preparing a polishing solution by mixing a stabilizer and an accelerator in a solvent; b) adjusting the pH of the polishing solution to 2 to 5 by adding a pH adjuster to the polishing solution; and c) mixing a surfactant and abrasive particles in the abrasive solution having a pH of 2 to 5.
- a method of manufacturing a semiconductor device includes the steps of: 1) providing a polishing pad including a polishing layer; 2) supplying a polishing composition for a semiconductor process to the polishing pad; and 3) grinding the polishing object while relatively rotating so that the polishing surface of the polishing object comes into contact with the polishing surface of the polishing layer, wherein the polishing surface is an amorphous carbon film, and the polishing composition includes abrasive particles; accelerator; and stabilizers.
- the present invention can be applied to a polishing process of an amorphous carbon layer (ACL) film, can exhibit a high polishing rate, and prevent the occurrence of defects by preventing adsorption of a semiconductor substrate by carbon residue during the polishing process and excellent maintenance of polishing performance and storage stability at high temperatures.
- ACL amorphous carbon layer
- FIG. 1 is a schematic process diagram of a semiconductor device manufacturing process according to an embodiment of the present invention.
- the present invention provides abrasive particles; Accelerator; And it relates to a polishing composition for a semiconductor process comprising a stabilizer (stabilizer).
- B is located on A means that B is located directly abutting on A or B is located on A while another layer is located in between, and B is located in contact with the surface of A It is not construed as being limited to
- the complexity of the surface structure means that the line width of the semiconductor is narrowed, and the aspect ratio (horizontal to vertical ratio) is also gradually increasing, and in order to meet the increasing aspect ratio, the photoresist is getting thinner.
- the thin and elongated photoresist does not withstand the etching process and collapses. In order to prevent this, a hardmask process has been introduced.
- amorphous carbon and SiON were used as the hard mask material.
- the amorphous carbon has excellent etching resistance when used as a hard mask, when a chemical mechanical polishing process is applied using a conventional polishing composition, a low removal rate and generation of carbon residue causes carbon residue It adsorbs to the film-like surface, causing a problem of generating defects in the semiconductor substrate.
- the polishing composition for a semiconductor process of the present invention not only exhibits a high polishing rate for the amorphous carbon film, but also prevents re-adsorption of carbon residues, thereby preventing the occurrence of defects in the semiconductor substrate.
- the polishing composition supplied to the polishing process of an amorphous carbon layer may include abrasive particles, an accelerator, and a stabilizer.
- the accelerator and stabilizer may be included in a weight ratio of 0.5:1 to 3:1.
- the conventional polishing composition used for the polishing process for the amorphous carbon film has a low polishing rate, so there is a problem in that the efficiency of the polishing process is lowered.
- the polishing rate for the amorphous carbon film was improved by including the accelerator in the conventional polishing composition.
- the accelerator carbon remains on the semiconductor substrate independently of the polishing rate of the polishing process of the amorphous carbon film
- the present invention it is possible to provide a polishing composition that can increase the polishing rate of the amorphous carbon film, prevent contamination of the polishing pad, prevent deterioration of polishing performance at high temperature, and have excellent long-term storage stability.
- the polishing composition of the present invention includes abrasive particles, an accelerator, and a stabilizer, and as it includes both the accelerator and the stabilizer, the polishing rate of the amorphous carbon film by the accelerator increases and polishing by the stabilizer It is possible to increase the stability of the composition.
- the accelerator and stabilizer may be included in a weight ratio of 0.5:1 to 3:1, 0.5:1 to 2:1, 0.55:1 to 1.9:1.
- the polishing rate for the amorphous carbon film is high, and carbon residues can be prevented from adsorbing to the semiconductor substrate during the polishing process.
- the accelerator may be selected from the group consisting of anionic low molecular weight, anionic polymer, hydroxyl acid, amino acid and cerium salt.
- the cerium salt may be a trivalent cerium salt or a tetravalent cerium salt, and more specifically
- the tetravalent cerum salt may be selected from the group consisting of cerium(IV) sulfate (Ce(SO 4 ) 2 ), cerium ammonium sulfate dihydrate, and cerium ammonium nitrate, but is not limited thereto.
- the accelerator may be included in the polishing composition to facilitate removal of the surface layer of the amorphous carbon film by oxidizing the surface layer of the amorphous carbon film with an oxide or ions.
- residues of the organic film material present in the polishing stop layer can be easily removed, there is an advantage of enabling more uniform polishing.
- the cerium ammonium nitrite may be present in the slurry composition in the form of an ionic compound or a chelate compound, and when used in the form, it is possible to provide a high polishing rate for the amorphous carbon film.
- the stabilizer increases the stability of the polishing composition and prevents defects from occurring during the polishing process.
- the stabilizer is an amino acid, and more specifically, the amino acid is arginine, histidine, and lysine. , Aspartic acid, Glutamic acid, Glutamine, Cysteine, Proline, Asparagine, threonine Alanine, Glycine ), valine, leucine, isoleucine, and mixtures thereof may be selected from the group consisting of, preferably alanine, but is not limited to the above examples. Any amino acid capable of increasing stability and suppressing the occurrence of defects in the polishing process may be used without limitation.
- the polishing composition for a semiconductor process may have a polishing performance reduction rate (PPR) of 0% to 60% represented by Equation 1 below:
- the amorphous carbon layer (ACL) having a thickness of 2,000 ⁇ was polished for 60 seconds at 2 psi, carrier speed 87 rpm, platen speed 93 rpm, and the inflow flow rate of the polishing composition was 200 ml/min.
- A0 is a polishing rate measured by using the polishing composition in the polishing process under the polishing conditions
- A1 is a polishing rate measured by the polishing process after leaving the polishing composition at a temperature of 60° C. for 40 hours and cooling it at 20 to 25° C. under the polishing conditions.
- the polishing composition for a semiconductor process is often used in an actual polishing process after being manufactured and stored for a considerable amount of time before being put into an actual polishing process, so it must have excellent storage stability. That is, after the polishing composition is prepared, it is not immediately used in the polishing process, and several days may be consumed in the transport process and the storage process up to the time it is put into the actual polishing process.
- the abrasive composition prepared as described above is stored for a considerable period of time, aggregation may occur in the abrasive composition or between the abrasive particles, or a problem of reduced polishing performance may occur due to a change in components.
- the above problems will be said to be related to whether or not stability by long-term storage is secured.
- the polishing composition was placed in a high temperature state of 60° C. and left to stand for 40 hours to confirm the degree of deterioration in polishing performance.
- Leaving the polishing composition at 60° C. is to evaluate stability under severe conditions, and leaving the polishing composition at 60° C. for 1 hour is similar to storage at 15 to 25° C., which is room temperature, for about 1 day. Therefore, leaving it at 60° C. for 40 hours as described above means the polishing composition after storage for about 40 days.
- the polishing composition of the present invention has a polishing performance reduction rate (PPR) of 0% to 60%, or 0% to 30%, or 0% to 10%, even after being left for 40 hours at 60° C., which is a severe condition, or 0% to 5%, and exhibiting a reduction rate of polishing performance within the above range means exhibiting excellent stability according to long-term storage.
- PPR polishing performance reduction rate
- the abrasive particles are abrasive particles that can be applied to the polishing composition for a semiconductor process, and for example, may be selected from the group consisting of metal oxides, organic particles, organic-inorganic composite particles, and mixtures thereof.
- the metal oxide may be selected from the group consisting of colloidal silica, fumed silica, ceria, alumina, titania, zirconia, zeolite, and mixtures thereof, but the abrasive particles selectable by those skilled in the art are not limited to the above examples. can be used without limitation.
- the organic particles include polystyrene, styrene-based copolymer, poly(meth)acrylate, (meth)acrylate-based copolymer, polyvinyl chloride, polyamide, polycarbonate, polyimide polymer;
- a core/shell structure in which the polymer constitutes a core, a shell, or both, and these may be used alone or in combination, and the organic particles may be prepared by an emulsion polymerization method, a suspension polymerization method, or the like.
- the abrasive particles of the present invention may be specifically selected from the group consisting of colloidal silica, fumed silica, ceria, and mixtures thereof.
- the abrasive particles may have a diameter (D50) of 10 to 120 nm, preferably a diameter (D50) of 20 to 100 nm, and more preferably a diameter (D50) of 20 to 80 nm.
- D50 diameter of 10 to 120 nm
- D50 diameter of 20 to 100 nm
- D50 diameter of 20 to 80 nm.
- the polishing composition may further include a surfactant and a pH adjusting agent.
- a surfactant is included in the polishing composition to reduce the surface tension of the polishing composition, and according to the decrease in the surface tension, re-adsorption of carbon residues to the substrate surface is prevented, and contamination of the polishing pad problems can be avoided.
- the surfactant may include a nonionic fluorine-based polymer compound.
- the surfactant includes a fluorine-based polymer compound, and when used in a polishing process for the amorphous carbon film, it is possible to prevent re-adsorption of carbon residues generated on the surface of the semiconductor substrate.
- the surfactant contains fluorine, it is possible to suppress the growth of microorganisms such as bacteria and mold.
- bacteria and mold may occur, and the polishing composition in which the bacteria and mold are generated cannot be used in the polishing process and should be discarded.
- the surfactant includes a nonionic fluorine-based polymer compound, and when the polishing composition is stored for a long time, the generation of bacteria and mold can be prevented, and long-term storage stability can be improved.
- the surfactant of the present invention may be selected from the group consisting of FS-30, FS-31, FS-34, ET-3015, ET-3150, ET-3050, and mixtures thereof, manufactured by Chemours tm . It is not particularly limited as long as it is a material that serves to prevent re-adsorption of carbon residues on the surface of the semiconductor substrate in the process.
- the surfactant of the present invention is a nonionic surfactant, and a surfactant including a nonionic fluorine-based polymer compound may be used alone or mixed with other nonionic surfactants.
- the nonionic surfactant is polyethylene glycol, polypropylene glycol, polyethylene-propylene copolymer, polyalkyl oxide, polyoxyethylene oxide; PEO ), polyethylene oxide, polypropylene oxide, fluorine-based surfactants are sodium sulfonate fluorosurfactant, phosphate ester fluorosurfactant, amine oxide fluorosurfactant oxide fluorosurfactant, betaine fluorosurfactant, ammonium carboxylate fluorosurfactant, stearate ester fluorosurfactant, quaternary ammonium fluorosurfactant, ethylene It may be selected from the group consisting of oxide/propylene oxide fluorosurfactants (ethylene oxide/propylene oxide fluorosurfactant) and polyoxyethylene fluorosurfactant.
- the pH adjusting agent is hydrochloric acid, phosphoric acid, sulfuric acid, hydrofluoric acid, nitric acid, hydrobromic acid, iodic acid, formic acid, malonic acid, maleic acid, oxalic acid, acetic acid, adipic acid, citric acid, adipic acid, acetic acid, propionic acid, fumaric acid, lactic acid, salicylic acid , pimeline, benzoic acid, succinic acid, phthalic acid, butyric acid, glutaric acid, glutamic acid, glycolic acid, lactic acid, aspartic acid, may be at least one selected from the group consisting of tartaric acid and potassium hydroxide.
- the pH adjusting agent may represent a pH of the polishing composition for a semiconductor process of 2 to 5, preferably 2 to 4.
- the acidic environment is maintained within this range, the polishing rate and quality can be maintained above a certain level while preventing excessive corrosion of metal components or polishing equipment.
- the polishing composition for a semiconductor process includes 0.1 wt% to 0.5 wt% of abrasive particles, 1 wt% to 2 wt% of an accelerator, 1 wt% to 2 wt% of a stabilizer, and 0.001 wt% to a surfactant 0.01% by weight and the remainder of the solvent.
- the accelerator is stabilized by the stabilizer, the polishing rate by the accelerator in the polishing composition can be increased, and the occurrence of defects in the polishing process is prevented by the stabilizer and the surfactant can do.
- the solvent is ultrapure water, it is not limited to the above example, and any solvent that can be used as a solvent of the polishing composition can be used without limitation.
- the surfactant When the surfactant is included below the range value, the occurrence of surface defects of the semiconductor substrate increases during the polishing process. .
- the polishing composition is supplied to a polishing process of an amorphous carbon layer (ACL), and the polishing rate of the amorphous carbon layer may be 190 ⁇ /min or more. As described above, when the polishing rate of the amorphous carbon film is 190 ⁇ /min or more, it will be said that the polishing efficiency of the amorphous carbon film is excellent.
- the weight ratio of the accelerator and the stabilizer included in the above-described polishing composition is within the scope of the present invention, when the content of the accelerator to the abrasive particles is less than the content of the accelerator, the content of the accelerator is small and the polishing rate is low may occur. Accordingly, in order to exhibit a high polishing rate for an amorphous carbon film like the polishing composition of the present invention, to prevent the occurrence of defects in the polishing process, to prevent contamination of the polishing pad, and to increase the stability of the polishing composition, accelerators and stabilizers In addition to satisfying the weight ratio range of
- the manufacturing method for the polishing composition of the present invention comprises the steps of: a) preparing a polishing solution by mixing a stabilizer and an accelerator in a solvent; b) adjusting the pH of the polishing solution to 2 to 5 by adding a pH adjuster to the polishing solution; and d) mixing a surfactant and abrasive particles in the abrasive solution having a pH of 2 to 5.
- the first solvent may be prepared by mixing the stabilizer with the solvent, and then the accelerator may be mixed to prepare a polishing solution.
- the accelerator When the accelerator is prepared by mixing other stabilizers, pH adjusters, surfactants and abrasive particles in ultrapure water as a solvent, the accelerator is not stabilized in the abrasive composition, so that it is difficult to store for a long time or in the abrasive composition. In this case, the effect of increasing the polishing rate by the accelerator may not appear.
- a first solution is prepared by mixing a stabilizer in a solvent, an accelerator is dissolved in the first solution to prepare a polishing solution, and a polishing composition is prepared by the following steps.
- a method of manufacturing a semiconductor device includes: 1) providing a polishing pad including a polishing layer; 2) supplying a polishing composition for a semiconductor process to the polishing pad; and 3) grinding the polishing object while relatively rotating so that the polishing surface of the polishing object is in contact with the polishing surface of the polishing layer, wherein the polishing surface is an amorphous carbon film, and the polishing composition includes metal oxide particles, It includes an accelerator and a stabilizer, and the accelerator and the stabilizer may be included in a weight ratio of 0.5:1 to 2:1.
- FIG. 1 is a schematic flowchart of a semiconductor device manufacturing process according to an exemplary embodiment.
- a semiconductor substrate 130 to be polished is disposed on the polishing pad 110 .
- the polishing slurry 150 is sprayed on the polishing pad 110 through the nozzle 140 .
- the flow rate of the polishing slurry 150 supplied through the nozzle 140 may be selected according to the purpose within the range of about 10 cm 3 /min to about 1,000 cm 3 /min, for example, from about 50 cm 3 /min to It may be about 500 cm3 / min, but is not limited thereto.
- the to-be-polished surface of the semiconductor substrate 130 is in direct contact with the polishing surface of the polishing pad 110 .
- the semiconductor substrate 130 and the polishing pad 110 may be rotated relative to each other, so that the surface of the semiconductor substrate 130 may be polished.
- the rotation direction of the semiconductor substrate 130 and the rotation direction of the polishing pad 110 may be in the same direction or in opposite directions.
- the rotation speed of the semiconductor substrate 130 and the polishing pad 110 may be selected depending on the purpose in the range of about 10 rpm to about 500 rpm, respectively, for example, it may be about 30 rpm to about 200 rpm, However, the present invention is not limited thereto.
- polishing the substrate is an organic layer, and may be applied to a polishing process for a carbon-based organic layer.
- the carbon-based organic film may be exemplified by a C-SOH (spin on hardmask) film, an amorphous carbon layer, or an NCP film, and preferably has an excellent selective polishing effect and can exhibit a high polishing rate. It is an amorphous carbon film.
- polishing composition for a semiconductor process Since the detailed description of the polishing composition for a semiconductor process overlaps with the description above, the description thereof will be omitted.
- the semiconductor substrate 130 is polished and the conditioner 170 is used simultaneously with the polishing.
- the method may further include processing the polishing surface of the pad 110 .
- a mixed solution was prepared by mixing alanine as a stabilizer in ultrapure water, and a polishing solution was prepared by mixing cerium ammonium nitrite.
- a polishing composition was prepared by mixing nitric acid with the polishing solution to adjust the pH to 2.1, and mixing FS-30 manufactured by Chemours tm as a surfactant and colloidal silica having a diameter of 75 nm.
- abrasive grain Accelerator (ACC) Stabilizer (STA) Surfactants ACC:STA Example 1 0.25 1.3 1.19 0.005 1.09:1
- Example 2 0.25 2 1.92 0.005 1.04:1
- Example 3 0.25 1.3 2.22 0.005 0.59:1
- Example 4 0.25 2.23 1.19 0.005 1.87:1
- Example 5 0.25 0.6 0.46 0.005 1.3:1 Comparative Example 1 0.25 1.3 0.16 0.005 8.13:1 Comparative Example 2 0.25 0.6 1.92 0.005 0.31:1 Comparative Example 3 0.25 1.55 0.46 0.005 3.37:1
- the polishing rate was measured by performing the polishing process, and the occurrence of surface defects was confirmed.
- the polishing process conditions are, specifically, an amorphous carbon layer (ACL) having a thickness of 2,000 ⁇ for 60 seconds at 2 psi, a carrier speed of 87 rpm, a platen speed of 93 rpm, and an inflow flow rate of the polishing composition is 200 ml/min.
- ACL amorphous carbon layer
- the polishing rate of the amorphous carbon film under the above polishing conditions was measured (A0), and the occurrence of defects was confirmed using KLA Tencor AIT-XP+.
- polishing compositions of Examples and Comparative Examples were placed in an oven heated to 60° C., maintained for 40 hours, cooled at 20 to 25° C., and then the polishing process was performed under the same conditions as above to measure the polishing rate for the amorphous carbon film ( A1) was done.
- polishing performance reduction rate (PPR) expressed by the following Equation 1 was calculated using the measured polishing rate:
- the amorphous carbon layer (ACL) having a thickness of 2,000 ⁇ was polished for 60 seconds at 2 psi, carrier speed 87 rpm, platen speed 93 rpm, and the inflow flow rate of the polishing composition was 200 ml/min.
- A0 is a polishing rate measured by using the polishing composition in the polishing process under the polishing conditions
- A1 is a polishing rate measured by the polishing process after leaving the polishing composition at a temperature of 60° C. for 40 hours and cooling it at 20 to 25° C. under the polishing conditions.
- Example 1 203 199 2 11089
- Example 2 266 261 2 12274
- Example 3 194 194 0 15122
- Example 4 258 258 0 8056
- Example 5 124 25 80 40630 Comparative Example 1 172 41 76 15137 Comparative Example 2 182 182 0 35614 Comparative Example 3 172 55 68 16620
- Table 2 shows the results of confirming the polishing rate, the polishing performance reduction rate (PRR) and the occurrence of defects in Examples 1 to 5 and Comparative Examples 1 to 3 .
- the polishing compositions of Examples 1 to 4 had excellent polishing rates for the amorphous carbon film, with a polishing rate of at least 194 ⁇ /min to 266 ⁇ /min, and a polishing rate for an amorphous carbon film of 190 ⁇ /min or more. , after heating and cooling at a high temperature of 60 °C, even when the polishing process was performed, the polishing rate was all confirmed to be 190 ⁇ /min or more, and there was no decrease in polishing performance or a very small value, indicating excellent stability of the polishing composition became
- Example 5 Although the accelerator and the stabilizer were included within the weight ratio range of the present invention, the content range of the accelerator and the stabilizer in the polishing composition was not included within the scope of the present invention, so the polishing rate This was low, and the reduction rate was large even when the polishing rate was measured after heating to a high temperature, and it was confirmed that the stability was deteriorated.
- Comparative Example 1 had a polishing rate of 172 ⁇ /min before heating, and 41 ⁇ /min after heating, confirming that the value of Equation 1 was 76%.
- the polishing rate before heating was 182 ⁇ /min, and there was no change to 182 ⁇ /min after heating, but the polishing rate for the amorphous carbon film was confirmed to be 190 ⁇ /min or less, and 35,614 defects were generated. confirmed to be
- Comparative Example 3 it was confirmed that the polishing rate before heating was 172 ⁇ /min and after heating 55 ⁇ /min. In the case of the comparative examples, when there was a large difference between the polishing rate before heating and after heating, or there was no difference in the polishing rate, a defect was a problem.
- the present invention relates to a polishing composition for a semiconductor process, a method of manufacturing the polishing composition, and a method of manufacturing a semiconductor device to which the polishing composition is applied.
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Abstract
Description
연마입자 | 가속화제(ACC) | 안정화제(STA) | 계면활성제 | ACC:STA | |
실시예1 | 0.25 | 1.3 | 1.19 | 0.005 | 1.09:1 |
실시예2 | 0.25 | 2 | 1.92 | 0.005 | 1.04:1 |
실시예3 | 0.25 | 1.3 | 2.22 | 0.005 | 0.59:1 |
실시예4 | 0.25 | 2.23 | 1.19 | 0.005 | 1.87:1 |
실시예5 | 0.25 | 0.6 | 0.46 | 0.005 | 1.3:1 |
비교예1 | 0.25 | 1.3 | 0.16 | 0.005 | 8.13:1 |
비교예2 | 0.25 | 0.6 | 1.92 | 0.005 | 0.31:1 |
비교예3 | 0.25 | 1.55 | 0.46 | 0.005 | 3.37:1 |
A0 (Å/min) |
A1 (Å/min) |
PPR (%) |
Defect (ea) |
|
실시예 1 | 203 | 199 | 2 | 11089 |
실시예 2 | 266 | 261 | 2 | 12274 |
실시예 3 | 194 | 194 | 0 | 15122 |
실시예 4 | 258 | 258 | 0 | 8056 |
실시예 5 | 124 | 25 | 80 | 40630 |
비교예 1 | 172 | 41 | 76 | 15137 |
비교예 2 | 182 | 182 | 0 | 35614 |
비교예 3 | 172 | 55 | 68 | 16620 |
Claims (11)
- 연마 입자;가속화제(Accelerator); 및안정화제(stabilizer)를 포함하는반도체 공정용 연마 조성물.
- 제 1 항에 있어서,상기 가속화제 및 안정화제가 0.5:1 내지 3:1의 중량 비율로 포함되는반도체 공정용 연마 조성물.
- 제 1 항에 있어서,상기 연마 조성물은 하기의 식 1로 표시되는 연마 성능 감소율(PPR)이 0% 내지 60%인반도체 공정용 연마 조성물:[식 1]여기서,두께가 2,000Å인 비정질탄소막(ACL, Amorphous carbon layer)을 60초 동안 2 psi, 캐리어 속도 87rpm, 플레이튼 속도 93rpm 및 연마 조성물의 유입 유속이 200ml/min인 연마 조건에서 연마 공정을 진행하였으며,상기 A0는 상기 연마 조건에서 연마 조성물을 연마 공정에 이용하여 측정된 연마율이고,상기 A1은 상기 연마 조건에서 상기 연마 조성물을 60℃의 온도에서 40시간 동안 방치하고, 20 내지 25℃에서 식인 후, 연마 공정에 이용하여 측정된 연마율이다.
- 제1항에 있어서,상기 가속화제는 음이온계 저분자, 음이온계 고분자, 하이드록실산, 아미노산 및 세륨염으로 이루어진 군으로부터 선택되는반도체 공정용 연마 조성물.
- 제1항에 있어서,상기 안정화제는 아미노산인반도체 공정용 연마 조성물.
- 제1항에 있어서,상기 연마 입자는 금속 산화물, 유기 입자, 유기-무기 복합 입자 및 이들의 혼합으로 이루어진 군으로부터 선택되는반도체 공정용 연마 조성물.
- 제1항에 있어서,상기 연마 조성물은 계면활성제 및 pH 조절제를 포함하는반도체 공정용 연마 조성물.
- a) 용매에 안정화제 및 가속화제를 넣고 혼합하여 연마 용액을 제조하는 단계;b) 상기 연마 용액에 pH 조절제를 넣어 연마 용액의 pH를 2 내지 5로 조정하는 단계; 및c) 상기 pH가 2 내지 5인 연마 용액에 계면활성제 및 연마 입자를 혼합하는 단계를 포함하는반도체 공정용 연마 조성물의 제조 방법.
- 제8항에 있어서,상기 a) 단계는 용매에 안정화제를 혼합하여 혼합 용액으로 제조하고,상기 혼합 용액에 가속화제를 혼합하여 연마 용액으로 제조하는 것인반도체 공정용 연마 조성물의 제조 방법.
- 1) 연마층을 포함하는 연마패드를 제공하는 단계;2) 상기 연마패드로 반도체 공정용 연마 조성물을 공급하는 단계; 및3) 상기 연마층의 연마면에 연마 대상의 피연마면이 맞닿도록 상대 회전시키면서 상기 연마 대상을 연마시키는 단계를 포함하며,상기 연마 조성물은 연마 입자; 가속화제; 및 안정화제를 포함하는반도체 소자의 제조 방법.
- 제10항에 있어서,상기 반도체 공정용 연마 조성물은 하기의 식 1로 표시되는 연마 성능 감소율(PPR)이 0% 내지 60%인반도체 소자의 제조 방법:[식 1]여기서,두께가 2,000Å인 비정질탄소막(ACL, Amorphous carbon layer)을 60초 동안 2 psi, 캐리어 속도 87rpm, 플레이튼 속도 93rpm 및 연마 조성물의 유입 유속이 200ml/min인 연마 조건에서 연마 공정을 진행하였으며,상기 A0는 상기 연마 조건에서 연마 조성물을 연마 공정에 이용하여 측정된 연마율이고,상기 A1은 상기 연마 조건에서 상기 연마 조성물을 60℃의 온도에서 40시간 동안 방치하고, 20 내지 25℃에서 식인 후, 연마 공정에 이용하여 측정된 연마율이다.
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US18/255,600 US20240043718A1 (en) | 2020-12-09 | 2021-10-18 | Polishing composition for semiconductor processing,method for preparing polishing composition, and method for manufacturing semiconductor element to which polishing composition is applied |
CN202180082951.6A CN116568771A (zh) | 2020-12-09 | 2021-10-18 | 半导体工艺用抛光组合物、抛光组合物的制备方法以及适用抛光组合物的半导体器件的制造方法 |
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