WO2022121048A1 - 一种基于fpga的时钟同步系统 - Google Patents

一种基于fpga的时钟同步系统 Download PDF

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WO2022121048A1
WO2022121048A1 PCT/CN2020/141940 CN2020141940W WO2022121048A1 WO 2022121048 A1 WO2022121048 A1 WO 2022121048A1 CN 2020141940 W CN2020141940 W CN 2020141940W WO 2022121048 A1 WO2022121048 A1 WO 2022121048A1
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clock
fpga
signal
module
frequency
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PCT/CN2020/141940
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French (fr)
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戴朝龙
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威创集团股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268—Signal distribution or switching

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  • the invention relates to the fields of video processing and large-screen display, and more particularly, to a clock synchronization system based on FPGA.
  • clock synchronization processing has become a hard indicator of splicing processor and matrix switcher.
  • the processing equipment in the market is basically based on the internal clock for synchronization, and the internal clock is used as the reference clock of the processing equipment to achieve video output synchronization. Industry applications are limited.
  • the invention aims to overcome the above-mentioned deficiencies of the prior art, and provides a clock synchronization system based on FPGA, which can track an externally input low-frequency reference clock or reference signal in real time, and enables the device local clock to track and lock the externally inputted clock in real time through FPGA processing. reference signal.
  • An FPGA-based clock synchronization system is used to synchronize a clock signal according to a reference signal, including an FPGA processing module and a clock chip, the reference signal is externally input to the FPGA processing module, and the clock chip is input to the FPGA processing module.
  • the clock signal is edited by the FPGA processing module, and the FPGA processing module calculates the frequency difference and phase difference between the clock signal and the reference signal, and outputs a control signal to the
  • the clock chip is used for realizing synchronous locking of the reference signal and the clock signal, and finally the FPGA processing module outputs the synchronized clock signal.
  • the external reference clock inputs the reference signal Fref to the FPGA, and the variable center clock signal generated by the programmable VCXO clock chip is output to the FPGA for processing.
  • Control the programmable VCXO clock chip which can track the low-frequency reference clock input from the external in real time.
  • the local clock of the device can track and lock the reference clock input from the external input in real time.
  • the FPGA module includes a frequency discriminator module, and the frequency discriminator module is used to calculate the frequency difference and the phase difference between the clock signal and the input reference signal.
  • the frequency discriminator module uses the clock signal F to count and accumulate the input reference signal Fref within a unit time, and takes out the accumulated value from the rising edge of the parameter signal Fref, the same unit time
  • the FPGA module includes a step adjustment control module for generating corresponding control signals according to the adjustment control information given by the difference calculation and judgment module.
  • the difference judgment module is:
  • the step adjustment control module generates the interface timing of the clock chip, writes the adjustment data into the clock chip for configuration according to timing requirements, and enables the clock chip to modify the frequency offset of the clock signal and phase difference, and output an adjusted clock signal, so that the clock signal and the reference signal are tracked and locked in real time.
  • the clock chip is a VCXO clock chip.
  • the FPGA processing module dynamically controls the D/A converter in real time according to the frequency difference and the phase difference information, so as to convert the digital signal into an analog voltage signal in real time Adjust the VCXO clock chip.
  • the step adjustment control module generates the I2S interface timing control D/A converter at the same time, and writes the adjustment data into the D/A converter according to the timing requirements.
  • the D/A converter generates an analog voltage signal to control the VCXO clock chip, so that the VCXO
  • the clock chip modifies the frequency offset and phase difference of the variable clock signal F, and outputs the adjusted clock Fo, so as to achieve the purpose of real-time tracking and locking with the Fref clock signal.
  • the external input Fref reference clock signal is sent to the FPGA, and the programmable VCXO clock chip outputs a high-fold variable clock signal F to the FPGA.
  • the FPGA calculates the frequency difference and phase difference between the Fref reference clock signal and the variable clock signal F in real time, and then uses the difference information to dynamically control the D/A converter in real time.
  • the D/A converter converts the digital signal into an analog voltage signal in real time.
  • Adjust the programmable VCXO clock chip change the frequency offset and phase of the programmable VCXO clock chip, so as to achieve the Fref reference clock and the variable clock signal F tracking locked state, and then the FPGA outputs the synchronized Fo clock signal;
  • the adjustment range is wide, and the reference clock signal Fref can be compatible from low-frequency signals of tens of Hz to high-frequency clock signals of mega-level.
  • the implementation cost of the present invention is low, and the video processing equipment can synchronize the internal and external clocks under the condition of low cost, which greatly expands the application scope of the product, enhances the product performance of the processor, enriches the product function, and improves the product competitiveness. .
  • FIG. 1 is an overall structural diagram of an FPGA-based clock synchronization system of the present invention.
  • FIG. 2 is a structural diagram of an FPGA processing module of an FPGA-based clock synchronization system of the present invention.
  • FIG. 3 is a sequence diagram of an FPGA-based clock synchronization system of the present invention.
  • an FPGA-based clock synchronization system is used to synchronize the clock signal according to the reference signal, including an FPGA processing module and a clock chip, the reference signal is externally input to the FPGA processing module, and the The clock chip inputs the clock signal to the FPGA processing module for editing, and the FPGA processing module calculates the frequency difference and phase difference between the clock signal and the reference signal, and according to the frequency difference and the phase difference information
  • a control signal is output to the clock chip for realizing synchronous locking of the reference signal and the clock signal, and finally the FPGA processing module outputs the synchronized clock signal.
  • the external reference clock inputs the reference signal Fref to the FPGA, and the variable center clock signal generated by the programmable VCXO clock chip is output to the FPGA for processing.
  • Control the programmable VCXO clock chip which can track the low-frequency reference clock input from the external in real time.
  • the local clock of the device can track and lock the reference clock input from the external input in real time.
  • the FPGA module includes a frequency discriminator module, and the frequency discriminator module is used to calculate the frequency difference and the phase difference between the clock signal and the input reference signal.
  • the frequency discriminator module uses the clock signal F to count and accumulate the input reference signal Fref within a unit time, and takes out the accumulated value from the rising edge of the parameter signal Fref, the same unit time
  • the FPGA module includes a step adjustment control module for generating corresponding control signals according to the adjustment control information given by the difference calculation and judgment module.
  • the difference judgment module is:
  • the step adjustment control module generates the interface timing of the clock chip, writes the adjustment data into the clock chip for configuration according to timing requirements, and enables the clock chip to modify the frequency offset of the clock signal and phase difference, and output an adjusted clock signal, so that the clock signal and the reference signal are tracked and locked in real time.
  • the clock chip is a VCXO clock chip.
  • the FPGA processing module dynamically controls the D/A converter in real time according to the frequency difference and the phase difference information, so as to convert the digital signal into an analog voltage signal in real time Adjust the VCXO clock chip.
  • the step adjustment control module generates the I2S interface timing control D/A converter at the same time, and writes the adjustment data into the D/A converter according to the timing requirements.
  • the D/A converter generates an analog voltage signal to control the VCXO clock chip, so that the VCXO
  • the clock chip modifies the frequency offset and phase difference of the variable clock signal F, and outputs the adjusted clock Fo, so as to achieve the purpose of real-time tracking and locking with the Fref clock signal.
  • the clock F is the central clock, that is, the clock signal F
  • the clock Fref is the external reference clock that needs to be synchronized, that is, the reference signal Fref, F and Fref
  • the specific way to establish a synchronization relationship is:
  • the frequency division of F into the frequency of Fref means that F needs to be divided, and the frequency size is the same as that of Fref, and a symbol Fo needs to be introduced; the phase difference information is obtained through the phase OR of Fo and Fref;
  • the external input Fref reference clock signal is sent to the FPGA, and the programmable VCXO clock chip outputs a high-fold variable clock signal F to the FPGA.
  • the FPGA calculates the frequency difference and phase difference between the Fref reference clock signal and the variable clock signal F in real time, and then uses the difference information to dynamically control the D/A converter in real time.
  • the D/A converter converts the digital signal into an analog voltage signal in real time.
  • Adjust the programmable VCXO clock chip change the frequency offset and phase of the programmable VCXO clock chip, so as to achieve the Fref reference clock and the variable clock signal F tracking locked state, and then the FPGA outputs the synchronized Fo clock signal;
  • the adjustment range is wide, and the reference clock signal Fref can be compatible from low-frequency signals of tens of Hz to high-frequency clock signals of mega-level.
  • the implementation cost of the present invention is low, and the video processing equipment can synchronize the internal and external clocks under the condition of low cost, which greatly expands the application scope of the product, enhances the product performance of the processor, enriches the product function, and improves the product competitiveness. .

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

一种基于FPGA的时钟同步系统，涉及视频处理与大屏显示领域。用于根据参考信号实现对时钟信号的同步，包括FPGA处理模块、时钟芯片，外部输入所述参考信号到所述FPGA处理模块，同时所述时钟芯片输入所述时钟信号给所述FPGA处理模块编辑，所述FPGA处理模块计算所述时钟信号与所述参考信号的频率差、相位差，并根据所述频率差、所述相位差信息输出控制信号到所述时钟芯片，用于实现所述参考信号和所述时钟信号同步锁定，最后由所述FPGA处理模块输出同步后的时钟信号；能实时跟踪外部输入的低频率参考时钟，经过FPGA处理能够使设备本地时钟实时跟踪锁定外部输入的参考时钟，视频处理设备同步输出视频，显示端不会存在视频有快有慢和撕裂现象，使视频处理设备应用不受限制。

Description

一种基于FPGA的时钟同步系统
本申请要求于2020年12月09日提交中国专利局、申请号为202011452237.5、发明名称为“一种基于FPGA的时钟同步系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及视频处理与大屏显示领域，更具体地，涉及一种基于FPGA的时钟同步系统。
背景技术
随着拼接处理器和混合矩阵技术的发展，时钟同步处理已经成了拼接处理器和矩阵切换器的硬性指标。
目前市场的处理设备基本都是基于内部时钟作同步的，采用内部时钟作为处理设备的参考时钟实现视频输出同步，这种时钟同步方法的视频处理设备应用比较局限，时钟同步处理不灵活，在广播行业的应用受限。
发明内容
本发明旨在克服上述现有技术的不足，提供一种基于FPGA的时钟同步系统，能实时跟踪外部输入的低频率参考时钟或参考信号，经过FPGA处理能够使设备本地时钟实时跟踪锁定外部输入的参考信号。
本发明采取的技术方案是，
一种基于FPGA的时钟同步系统，用于根据参考信号实现对时钟信号的同步，包括FPGA处理模块、时钟芯片，外部输入所述参考信号到所述FPGA处理模块，同时所述时钟芯片输入所述时钟信号给所述FPGA处理模块编辑，所述FPGA处理模块计算所述时钟信号与所述参考信号的频率差、相位差，并根据所述频率差、所述相位差信息输出控制信号到所述时钟芯片，用于实现所述参考信号和所述时钟信号同步锁定，最后由所述FPGA处理模 块输出同步后的时钟信号。
本方案只需要简单的外围电路和芯片与FPGA配合即可实现外部时钟同步功能，外部参考时钟输入参考信号Fref给FPGA，可编程VCXO时钟芯片产生的可变中心时钟信号输出给FPGA作处理，FPGA控制可编程VCXO时钟芯片，能实时跟踪外部输入的低频率参考时钟，经过FPGA处理能够使设备本地时钟实时跟踪锁定外部输入的参考时钟，视频处理设备同步输出视频，显示端不会存在视频有快有慢和撕裂现象，使视频处理设备应用不受限制，广泛应用在视频处理与大屏显示行业。
优选的，所述FPGA模块包括鉴频相器模块，所述鉴频相器模块用于计算所述时钟信号与输入的参考信号之间的频率差和相位差。
优选的，所述鉴频相器模块在单位时间内用所述时钟信号F去计数累加输入的参考信号Fref，并将所述参数信号Fref的上升沿把累加的值取出来，同一个单位时间内的前后两个计数值相减得出差值T0、T1、T2…Tn，所述鉴频相器模块包括所述参考值Tref，Tref＝F/Fref，最后得出所述时钟信号的频率差值信息：ΔTn＝Tn-Tref，根据所述频率差值信息ΔTn将所述时钟信号分频成所述参考信号的频率。
优选的，所述FPGA模块还包括差值计算判断模块，用于计算判断需要调节的频率差值信息、相位差值信息与计算累积误差，所述累积误差ΔTc＝ΔT0+ΔT1+…+ΔTn。
优选的，所述FPGA模块包括步进调节控制模块，用于根据所述差值计算判断模块给过来的调节控制信息，生成相应的控制信号。
优选的，所述差值判断模块在：
当ΔTc>0或ΔTc<0时，则分别给到步进调节控制模块作出相应的调节，生成控制信号；
当ΔTc等于0时，所述差值判断模块不生成控制信息。
优选的，所述步进调节控制模块产生所述时钟芯片的接口时序，把所述调节数据根据时序要求写入所述时钟芯片进行配置，使所述时钟芯片修改所述时钟信号的频率偏移和相位差，输出调整后的时钟信号，使所述时钟信号与所述参考信号实时跟踪锁定。
优选的，所述时钟芯片为VCXO时钟芯片。
优选的，还包括D/A转换器，所述FPGA处理模块根据所述频率差、所述相位差信息去实时动态控制所述D/A转换器，用于把数字信号转换成模拟电压信号实时调节所述VCXO时钟芯片。
本方案中步进调节控制模块同时产生I2S接口时序控制D/A转换器，把调节数据根据时序要求写入D/A转换器，D/A转换器产生模拟电压信号控制VCXO时钟芯片，使VCXO时钟芯片修改可变时钟信号F的频率偏移和相位差，输出调整后的时钟Fo，达到与Fref时钟信号实时跟踪锁定的目的。
与现有技术相比，本发明的有益效果为：
1)本方案中外部输入Fref参考时钟信号给到FPGA，可编程VCXO时钟芯片输出高倍的可变时钟信号F给到FPGA。FPGA实时计算出Fref参考时钟信号与可变时钟信号F的频率差和相位差，然后利用差值信息去实时动态控制D/A转换器，D/A转换器把数字信号转换成模拟电压信号实时调节可编程VCXO时钟芯片，改变可编程VCXO时钟芯片的频率偏移和相位，从而达到Fref参考时钟与可变时钟信号F跟踪锁定状态，然后FPGA输出同步的Fo时钟信号；
2)采用FPGA来实现外部时钟同步处理，调节范围广，参考时钟信号Fref从几十Hz的低频信号，到兆级的高频时钟信号都可以兼容。
3)本发明的实现成本较低，在低成本情况下使视频处理设备做到内外时钟同步，大大扩宽了产品的应用范围，增强了处理器的产品性能，丰富产品功能，提高产品竞争力。
附图说明
图1为本发明的一种基于FPGA的时钟同步系统的整体结构图。
图2为本发明的一种基于FPGA的时钟同步系统的FPGA处理模块的结构图。
图3为本发明的一种基于FPGA的时钟同步系统的时序图。
具体实施方式
本发明附图仅用于示例性说明，不能理解为对本发明的限制。为了更好说明以下实施例，附图某些部件会有省略、放大或缩小，并不代表实际产品的尺寸；对于本领域技术人员来说，附图中某些公知结构及其说明可能省略是可以理解的。
实施例1
如图1所示，一种基于FPGA的时钟同步系统，用于根据参考信号实现对时钟信号的同步，包括FPGA处理模块、时钟芯片，外部输入所述参考信号到所述FPGA处理模块，同时所述时钟芯片输入所述时钟信号给所述FPGA处理模块编辑，所述FPGA处理模块计算所述时钟信号与所述参考信号的频率差、相位差，并根据所述频率差、所述相位差信息输出控制信号到所述时钟芯片，用于实现所述参考信号和所述时钟信号同步锁定，最后由所述FPGA处理模块输出同步后的时钟信号。
本方案只需要简单的外围电路和芯片与FPGA配合即可实现外部时钟同步功能，外部参考时钟输入参考信号Fref给FPGA，可编程VCXO时钟芯片产生的可变中心时钟信号输出给FPGA作处理，FPGA控制可编程VCXO时钟芯片，能实时跟踪外部输入的低频率参考时钟，经过FPGA处理能够使设备本地时钟实时跟踪锁定外部输入的参考时钟，视频处理设备同步输出视频，显示端不会存在视频有快有慢和撕裂现象，使视频处理设备应用不受限制，广泛应用在视频处理与大屏显示行业。
如图2所示，优选的，所述FPGA模块包括鉴频相器模块，所述鉴频相器模块用于计算所述时钟信号与输入的参考信号之间的频率差和相位差。
优选的，所述鉴频相器模块在单位时间内用所述时钟信号F去计数累加输入的参考信号Fref，并将所述参数信号Fref的上升沿把累加的值取出来，同一个单位时间内的前后两个计数值相减得出差值T0、T1、T2…Tn， 所述鉴频相器模块包括所述参考值Tref，Tref＝F/Fref，最后得出所述时钟信号的频率差值信息：ΔTn＝Tn-Tref，根据所述频率差值信息ΔTn将所述时钟信号分频成所述参考信号的频率。
优选的，所述FPGA模块还包括差值计算判断模块，用于计算判断需要调节的频率差值信息、相位差值信息与计算累积误差，所述累积误差ΔTc＝ΔT0+ΔT1+…+ΔTn。
优选的，所述FPGA模块包括步进调节控制模块，用于根据所述差值计算判断模块给过来的调节控制信息，生成相应的控制信号。
优选的，所述差值判断模块在：
当ΔTc>0或ΔTc<0时，则分别给到步进调节控制模块作出相应的调节，生成控制信号；
当ΔTc等于0时，所述差值判断模块不生成控制信息。
优选的，所述步进调节控制模块产生所述时钟芯片的接口时序，把所述调节数据根据时序要求写入所述时钟芯片进行配置，使所述时钟芯片修改所述时钟信号的频率偏移和相位差，输出调整后的时钟信号，使所述时钟信号与所述参考信号实时跟踪锁定。
优选的，所述时钟芯片为VCXO时钟芯片。
优选的，还包括D/A转换器，所述FPGA处理模块根据所述频率差、所述相位差信息去实时动态控制所述D/A转换器，用于把数字信号转换成模拟电压信号实时调节所述VCXO时钟芯片。
本方案中步进调节控制模块同时产生I2S接口时序控制D/A转换器，把调节数据根据时序要求写入D/A转换器，D/A转换器产生模拟电压信号控制VCXO时钟芯片，使VCXO时钟芯片修改可变时钟信号F的频率偏移和相位差，输出调整后的时钟Fo，达到与Fref时钟信号实时跟踪锁定的目的。
如图3所示，时钟F是中心时钟，即时钟信号F，时钟Fref是需要同步的外部参考时钟，即参考信号Fref，F和Fref建立起同步关系的具体方式为；
当F是10Mhz，而Fref是100Khz，所述Tref为：Tref＝10M/100Khz＝100，其含义就是计算F和Fref的倍数关系；
在1s的单位时间内，用时钟信号F去计数累加参考信号Fref的值，然后在参考信号Fref的上升沿把累加的值t1/t2/t3……tn取出来，前后两个上升沿的累加值相减就是Δt＝tn-t(n-1)，Δt表示Fref当前的频率大小；
然后计算F和Fref的频率差大小(其含义就是F和Fref的快慢偏差大小)，ΔTn＝Δt-Tref，ΔTn有可能是正数也可能是负数，正负表示频率快慢的意思，正数表示时钟信号F比较快，需要配置VCXO，调慢一点时钟；负数表示时钟信号F比较慢，需要配置VCXO，需要调节快一点时钟；
F分频成Fref频率大小的意思是需要把F分频，频率大小跟Fref一样大小，需要引入一个符号Fo；通过Fo与Fref的相或得出相位差信息；
1)本方案中外部输入Fref参考时钟信号给到FPGA，可编程VCXO时钟芯片输出高倍的可变时钟信号F给到FPGA。FPGA实时计算出Fref参考时钟信号与可变时钟信号F的频率差和相位差，然后利用差值信息去实时动态控制D/A转换器，D/A转换器把数字信号转换成模拟电压信号实时调节可编程VCXO时钟芯片，改变可编程VCXO时钟芯片的频率偏移和相位，从而达到Fref参考时钟与可变时钟信号F跟踪锁定状态，然后FPGA输出同步的Fo时钟信号；
2)采用FPGA来实现外部时钟同步处理，调节范围广，参考时钟信号Fref从几十Hz的低频信号，到兆级的高频时钟信号都可以兼容。
3)本发明的实现成本较低，在低成本情况下使视频处理设备做到内外时钟同步，大大扩宽了产品的应用范围，增强了处理器的产品性能，丰富产品功能，提高产品竞争力。
显然，本发明的上述实施例仅仅是为清楚地说明本发明技术方案所作的举例，而并非是对本发明的具体实施方式的限定。凡在本发明权利要求书的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (9)

  1. 一种基于FPGA的时钟同步系统，其特征在于，用于根据参考信号实现对时钟信号的同步，包括FPGA处理模块、时钟芯片，外部输入所述参考信号到所述FPGA处理模块，同时所述时钟芯片输入所述时钟信号给所述FPGA处理模块编辑，所述FPGA处理模块计算所述时钟信号与所述参考信号的频率差、相位差，并根据所述频率差、所述相位差信息输出控制信号到所述时钟芯片，用于实现所述参考信号和所述时钟信号同步锁定，最后由所述FPGA处理模块输出同步后的时钟信号。
  2. 根据权利要求1所述的一种基于FPGA的时钟同步系统，其特征在于，所述FPGA模块包括鉴频相器模块，所述鉴频相器模块用于计算所述时钟信号与输入的参考信号之间的频率差和相位差。
  3. 根据权利要求2所述的一种基于FPGA的时钟同步系统，其特征在于，所述鉴频相器模块在单位时间内用所述时钟信号F去计数累加输入的参考信号Fref，并将所述参数信号Fref的上升沿把累加的值取出来，同一个单位时间内的前后两个计数值相减得出差值T0、T1、T2…Tn，所述鉴频相器模块包括所述参考值Tref，Tref＝F/Fref，最后得出所述时钟信号的频率差值信息：ΔTn＝Tn-Tref，根据所述频率差值信息ΔTn将所述时钟信号分频成所述参考信号的频率。
  4. 根据权利要求3所述的一种基于FPGA的时钟同步系统，其特征在于，所述FPGA模块还包括差值计算判断模块，用于计算判断需要调节的频率差值信息、相位差值信息与计算累积误差，所述累积误差ΔTc＝ΔT0+ΔT1+…+ΔTn。
  5. 根据权利要求5所述的一种基于FPGA的时钟同步系统，其特征在于，所述FPGA模块包括步进调节控制模块，用于根据所述差值计算判断模块给过来的调节控制信息，生成相应的控制信号。
  6. 根据权利要求5所述的一种基于FPGA的时钟同步系统，其特征在于，所述差值判断模块在：
    当ΔTc>0或ΔTc<0时，则分别给到步进调节控制模块作出相应的调节，生成控制信号；
    当ΔTc等于0时，所述差值判断模块不生成控制信息。
  7. 根据权利要求6所述的一种基于FPGA的时钟同步系统，其特征在于，
    所述步进调节控制模块产生所述时钟芯片的接口时序，把所述调节数据根据时序要求写入所述时钟芯片进行配置，使所述时钟芯片修改所述时钟信号的频率偏移和相位差，输出调整后的时钟信号，使所述时钟信号与所述参考信号实时跟踪锁定。
  8. 根据权利要求1-7任一项所述的一种基于FPGA的时钟同步系统，其特征在于，所述时钟芯片为VCXO时钟芯片。
  9. 根据权利要求8所述的一种基于FPGA的时钟同步系统，其特征在于，还包括D/A转换器，所述FPGA处理模块根据所述频率差、所述相位差信息去实时动态控制所述D/A转换器，用于把数字信号转换成模拟电压信号实时调节所述VCXO时钟芯片。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101098220A (zh) * 2006-06-29 2008-01-02 中兴通讯股份有限公司 一种基于数字锁相环的时钟同步方法及其系统
JP2009177575A (ja) * 2008-01-25 2009-08-06 Victor Co Of Japan Ltd 基準クロック信号生成装置
US20130018616A1 (en) * 2011-07-15 2013-01-17 Askey Computer Corp. Frequency counter
CN112565554A (zh) * 2020-12-09 2021-03-26 威创集团股份有限公司 一种基于fpga的时钟同步系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2329333A4 (en) * 2008-08-21 2014-12-03 Chronologic Pty Ltd METHOD AND APPARATUS FOR SYNCHRONIZATION AND TIMING
US8082462B1 (en) * 2008-11-13 2011-12-20 Xilinx, Inc. Direct synthesis of audio clock from a video clock via phase interpolation of a dithered pulse
CN104980150A (zh) * 2014-04-09 2015-10-14 许文 一种基于fpga的时钟频率调整锁相方法
CN110912637B (zh) * 2019-12-31 2021-06-29 广东大普通信技术有限公司 一种时钟同步系统及方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101098220A (zh) * 2006-06-29 2008-01-02 中兴通讯股份有限公司 一种基于数字锁相环的时钟同步方法及其系统
JP2009177575A (ja) * 2008-01-25 2009-08-06 Victor Co Of Japan Ltd 基準クロック信号生成装置
US20130018616A1 (en) * 2011-07-15 2013-01-17 Askey Computer Corp. Frequency counter
CN112565554A (zh) * 2020-12-09 2021-03-26 威创集团股份有限公司 一种基于fpga的时钟同步系统

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