WO2022120939A1 - 芯片晶圆的堆叠方法 - Google Patents

芯片晶圆的堆叠方法 Download PDF

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Publication number
WO2022120939A1
WO2022120939A1 PCT/CN2020/138144 CN2020138144W WO2022120939A1 WO 2022120939 A1 WO2022120939 A1 WO 2022120939A1 CN 2020138144 W CN2020138144 W CN 2020138144W WO 2022120939 A1 WO2022120939 A1 WO 2022120939A1
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wafer
chips
bonded
chip
processed
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PCT/CN2020/138144
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English (en)
French (fr)
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陈坦林
郭万里
刘天建
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武汉新芯集成电路制造有限公司
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Priority to US18/266,528 priority Critical patent/US20240047416A1/en
Publication of WO2022120939A1 publication Critical patent/WO2022120939A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83893—Anodic bonding, i.e. bonding by applying a voltage across the interface in order to induce ions migration leading to an irreversible chemical bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Definitions

  • the invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a chip wafer stacking structure and a manufacturing method thereof.
  • chip-to-wafer can realize interconnection between different technology nodes and chips of different sizes, and has the advantage of high flexibility .
  • C2W can bond with the wafer by selecting known good die (KGD, known good die), which can greatly improve the yield.
  • KGD known good die
  • the C2W mass production solution is mainly based on the micro-bump packaging process.
  • the minimum connection unit size is about 40 ⁇ m, and the lower filler between the bumps is not conducive to heat dissipation.
  • the current research and development direction is towards a bumpless process with a smaller connection unit size.
  • the bumpless process uses hybrid bonding technology to achieve direct copper-to-copper bonding.
  • the size of the connection unit can be less than 10 ⁇ m to achieve higher input/output connection density, and it has better heat dissipation performance without underfill.
  • the purpose of the present invention is to provide a method for stacking chip wafers, which reduces the waiting time for chip and wafer bonding after chip activation, reduces the risk of activation failure, and improves the stacking efficiency of chip wafers.
  • the present invention provides a method for stacking chip wafers, comprising:
  • a wafer to be processed includes a substrate, a dielectric layer on the substrate, and a metal layer embedded in the dielectric layer; a bonding layer is formed, and the bonding layer covers the the dielectric layer;
  • the chip to be bonded is pre-arranged on the electrostatic chuck, and before bonding with the wafer to be bonded, it further includes:
  • the plasma activates the bonding surfaces of the wafers to be bonded and/or the bonding surfaces of the arranged chips.
  • the chips to be bonded include chips with different functions and/or sizes.
  • the chips to be bonded are respectively picked up from the first wafer to be processed to the Nth wafer to be processed, where N is an integer ⁇ 1; the first chip is picked up from the first wafer to be processed, the Picking up the i-th chip from the wafer to be processed and picking up the N-th chip from the N-th wafer to be processed, 1 ⁇ i ⁇ N; the first chip, the i-th chip and the N-th chip are arranged and combined to form a reconstruction Chips are distributed on the electrostatic chuck, and the reconstituted chips are matched with the chips on the wafer to be bonded.
  • the reconstituted chips are periodically distributed on the electrostatic chuck.
  • the steps include: dicing the keys of each to-be-processed wafer.
  • the surface is coated with metal antioxidants;
  • the steps include: cleaning the chips, removing the metal antioxidant on the bonding interface of the chips, and simultaneously treating the chips.
  • the bonding interface of the chip is subjected to hydrophilic treatment.
  • a plurality of electrostatic chucks are provided, and the chips pre-arranged on the plurality of electrostatic chucks are bonded to the wafer to be bonded.
  • the bonding layer after picking up the chip to be bonded from the wafer to be processed, it also includes:
  • a blue film or a UV film is attached to the surface of the side surface of the wafer to be processed close to the through entrance of the through silicon via;
  • the to-be-processed wafer is diced.
  • bonding layer of the wafer to be processed and the wafer carrier are bonded by bonding glue
  • the carrier wafer is debonded from the to-be-processed wafer, and the bonding adhesive is retained when the carrier wafer is removed.
  • picking up the chip to be bonded from the wafer to be processed includes: removing the chip to be bonded from the blue film or UV film and directly placing it on the electrostatic chuck.
  • the plasma gas used for the plasma activation includes: any one or a combination of two or more of oxygen gas, nitrogen gas, argon gas or hydrogen gas.
  • the electrostatic chuck is controlled to be charged or discharged through an external command, so as to realize the adsorption and release of the arranged chips.
  • the chip pre-arranged on the electrostatic chuck is bonded to the wafer to be bonded as a whole using a thermal load bonding method, wherein a load is applied to multiple pieces of the electrostatic chuck. and heating the plurality of chips and the to-be-bonded wafer under vacuum to form between the bonding surfaces of the to-be-bonded wafer and the arrayed bonding surfaces of the chips Atomic bond.
  • the present invention has the following beneficial effects:
  • the present invention provides a method for stacking chip wafers, comprising: providing a wafer to be processed, the wafer to be processed includes a substrate, a dielectric layer on the substrate, and a metal embedded in the dielectric layer forming a bonding layer, the bonding layer covering the dielectric layer; picking up the chips to be bonded from the wafer to be processed, and arranging the chips to be bonded on the electrostatic chuck; The chips arranged on the electrostatic chuck are bonded to the wafer to be bonded as a whole. All the chips to be bonded are pre-arranged on the electrostatic chuck, and the chips arranged on the electrostatic chuck are bonded to the wafer to be bonded as a whole, which can greatly reduce the damage to the chips after activation. Wafer bonding latency, reducing the risk of activation failure. It is more efficient to arrange all the chips to be bonded on the electrostatic chuck in advance, and then perform the bonding as a whole rather than arranging and distributing them at the same time.
  • FIG. 1 is a schematic flowchart of a method for stacking chip wafers according to an embodiment of the present invention.
  • FIG. 2 to FIG. 14 are schematic diagrams of steps of a method for stacking chip wafers according to an embodiment of the present invention.
  • 10-first wafer to be processed 11-first substrate; 12-first dielectric layer; 13-first metal layer; 14-bonding layer; 15-insulation layer; 16-interconnection layer; 17-test Pad layer; 18-Test pad; 17'-Hybrid bonding layer; 18'-Metal pad; A-Mount wafer; B-Blue film; C-Reconstructed chip; D 1 -First chip; D 2 - second chip; E - electrostatic chuck; W - wafer to be bonded; C' - bonded chip.
  • An embodiment of the present invention provides a method for stacking chip wafers, as shown in FIG. 1 , including:
  • the wafer to be processed includes a substrate, a dielectric layer on the substrate, and a metal layer embedded in the dielectric layer; forming a bonding layer, the bonding layer covering the dielectric layer;
  • the chips to be bonded may be the same chip or chips with different functions and/or sizes.
  • a first wafer 10 to be processed is provided, and the first wafer 10 to be processed includes a first substrate 11 , a first dielectric layer 12 on the first substrate 11 , and a first dielectric layer 12 embedded in the first substrate 11 .
  • a bonding layer 14 is formed, the bonding layer 14 covers the first dielectric layer 12, the upper surface of the bonding layer 14 is a bonding interface, and preferably the bonding interface can be a mixed bonding interface comprising a metal and an insulating layer (Hybrid bond interface, not shown in the figure).
  • the bonding layer 14 of the first wafer to be processed 10 is bonded to the wafer carrier A, which may be temporarily bonded by bonding glue.
  • the first wafer 10 to be processed is thinned, and the side surface of the first substrate 11 away from the first metal layer 13 is thinned.
  • An insulating layer 15 is formed on the surface of the thinned first substrate 11 .
  • a through-silicon via V is formed, and the through-silicon via V penetrates the insulating layer 15 , the first substrate 11 and a partial thickness of the first dielectric layer 12 and exposes the first metal layer 13 .
  • the first dielectric layer 12 is not limited to a single-layer dielectric layer, and may also be a multi-layer composite dielectric layer, such as a composite dielectric layer including a silicon dioxide layer and a silicon nitride layer.
  • An interconnection layer 16 is formed in the through silicon via V, and the material of the interconnection layer 16 is metal, such as copper or tungsten. When the material of the interconnect layer 16 is copper, it can be formed by electroplating.
  • the interconnect layer 16 is electrically connected to the first metal layer 13 .
  • a test pad layer 17 is formed, and the test pad layer 17 includes an insulating layer and a test pad 18 embedded in the insulating layer.
  • the first to-be-processed wafer 10 is tested through the test pads 18 to mark a known good die (KGD).
  • KGD known good die
  • a redistribution layer may also be included between the test pad layer 17 and the insulating layer 15, and the redistribution layer includes a redistribution medium layer and a redistribution medium layer embedded in the redistribution medium layer.
  • the distributed metal layer is electrically connected to the interconnection layer 16, and the redistributed metal layer realizes the connection of electrical signals in the wafer.
  • a hybrid bonding layer 17' is formed, which includes an insulating layer and metal pads 18' embedded in the insulating layer.
  • a redistribution layer (not shown in the figure) may also be included between the bonding layer 17 ′ and the insulating layer 15 .
  • the blue film B is attached to the back side of the first wafer 10 to be processed.
  • the wafer to be processed and the blue film B are directly bonded together without using bonding glue.
  • the carrier wafer A is debonded from the first to-be-processed wafer 10 , the carrier wafer A is removed, and the bonding adhesive is preferably retained.
  • the first wafer to be processed 10 is diced by plasma cutting or laser cutting, and a plurality of first chips D 1 are formed after dicing.
  • the first to-be-processed wafer 10 after dicing is cleaned to remove the bonding glue and particle defects caused by dicing.
  • a metal antioxidant eg, copper antioxidant
  • the copper antioxidant is a mixed solution composed of organic azoles, some auxiliary agents and water.
  • copper antioxidants include: hydroxyethylidene diphosphonic acid, ethanol, hydrogen peroxide, benzotriazole, isothiocyanate, lauryl sulfate, sodium molybdate, and trimer A mixed solution of sodium phosphate.
  • Spraying metal antioxidant can prevent or reduce the oxidation of metal (eg copper) on the surface of the bonding layer 14 (mixed bonding interface), so that the chip arrangement on the electrostatic chuck is not limited by the waiting time and increases the flexibility of dispatching.
  • the chips to be bonded are arranged on the electrostatic chuck E.
  • the chips to be bonded may come from the same wafer to be processed.
  • the chips to be bonded may also come from different wafers to be processed.
  • the chips to be bonded come from N wafers to be processed.
  • the chips to be bonded are respectively picked up from the first wafer to be processed to the Nth wafer to be processed, where N is a natural number ⁇ 1.
  • the back side is directly placed on the electrostatic chuck without additional treatment.
  • the electrostatic chuck has no high requirements on the bonding interface and can be directly adsorbed, which further simplifies the process flow.
  • the respective numbers of the first chip, the i-th chip, and the N-th chip are not limited, and may all be one or several ( ⁇ 2).
  • the reconstituted chip matches the chip on the wafer to be bonded.
  • the film expansion (blue film B) process is performed on the second wafer 20 to be processed, and the second chip D 2 to be bonded is picked up from the second wafer 20 to be processed.
  • the first chip D 1 and the second chip D 2 are arranged and combined to form a reconstructed chip C, and the reconstructed chip C can be periodically distributed on the electrostatic chuck E.
  • the reconstituted chip C can be held (attached) on the electrostatic chuck E by electrostatic attraction force.
  • the reconstituted chip C can also be held (attached) to the substrate by adhesives or adhesive foils (including adhesives designed for easy debonding), under application of high temperature or UV light After irradiation, or when the reconstituted chip is mounted on the substrate in any other way, its adhesive strength can be lost, and the reconstituted chip can be attached and detached (released) from the substrate as desired.
  • the electrostatic chuck is controlled by external commands to charge and discharge to realize the adsorption and release of the chip, which is equivalent to rapid temporary bonding and debonding, only the control of external signals is required, no need to add any additional
  • the process greatly shortens the waiting time for the chip, that is, shortens the time for copper to be oxidized, and preferably also prevents the activation and failure of the bonding interface, improves the process efficiency, and improves the bonding quality.
  • the reconstituted chip C is cleaned to remove the metal antioxidant on the bonding interface of the reconstituted chip C, and at the same time, the bonding interface is hydrophilically treated .
  • Plasma activation is a surface modification method using plasma treatment that can modify the chemical and/or physical properties of the surface of the wafer, interrupting the oxidation formed by natural or thermal oxidation on the front side of the silicon wafer Bonds of silicon molecules.
  • Plasma gases used in the plasma activation process include, but are not limited to, oxygen (O 2 ), inert gases such as nitrogen and/or argon.
  • the plasma gas can be oxygen.
  • the plasma gas can be nitrogen.
  • the plasma gas can also contain other suitable gases, such as hydrogen. According to some embodiments, the concentration of the plasma gas is less than 5%.
  • the plasma activation process is performed at a pressure between 0.05 mbar and 0.5 mbar.
  • the plasma activation process can be performed with a discharge power such as between 10 watts and 100 watts.
  • the plasma activation process is performed at a low frequency discharge power, such as between 10 watts and 40 watts.
  • the plasma activation treatment is performed for a duration such as between 5 seconds and 50 seconds.
  • the plasma activation process is performed at a flow rate between 30 seem and 80 seem.
  • the chips arranged on the electrostatic chuck E are bonded to the wafer W to be bonded as a whole.
  • the electrostatic chuck may be one or several ( ⁇ 2), and one or several ( ⁇ 2) of the reconstituted chips may be distributed on one of the electrostatic chucks.
  • the reconstructed chips distributed on several ( ⁇ 2) electrostatic chucks may be the same or different.
  • FIG. 13 shows that the chips arranged on one electrostatic chuck are bonded to the wafer W to be bonded, and the area of the one electrostatic chuck and the area of the wafer W to be bonded may be the same or different. .
  • the chips arranged on several ( ⁇ 2) electrostatic chucks can also be bonded to the wafer to be bonded, that is, the reconstruction of one wafer W to be bonded and multiple electrostatic chucks E.
  • the chip corresponds to and realizes bonding.
  • the area of the wafer W to be bonded is larger, and the area of the electrostatic chuck E is smaller than the wafer W to be bonded (it can also be equal), and several ( ⁇ 2) electrostatic chucks are used.
  • the reconstituted chips can be arranged as required to bond with the wafer W to be bonded, which increases the flexibility of distributing the reconstituted chips on the electrostatic chuck.
  • Chip to wafer (C2W) bonding one or more known good dies (KGD) are bonded to the wafer.
  • the good dies (KGD) are arranged to form a reconstructed chip C.
  • the reconstituted chip C can be repeatedly distributed or not distributed on the electrostatic chuck E as required. As shown in FIG. 13 and FIG. 14 , all the chips arranged on the electrostatic chuck E are directly pre-bonded with the corresponding chips on the wafer W to be bonded as a whole, and then the electrostatic chuck E releases all the chips and removes the static electricity.
  • All the chips arranged on the electrostatic chuck E as a whole are bonded to the corresponding chips on the wafer W to be bonded, and a direct bonding method can be used, such as a thermal load bonding method.
  • the chips and the multiple chips and the wafer to be bonded are heated under vacuum to facilitate the formation of atomic bonds between their surfaces (usually metal surfaces such as metal contact pads).
  • the chips to be bonded are pre-arranged on the electrostatic chuck; the arranged chips on the electrostatic chuck are then subjected to plasma activation on the bonding surface, and then all the chips on the electrostatic chuck are combined with The wafers to be bonded are pre-bonded. It can greatly reduce the waiting time of the chip after plasma activation, and reduce the risk of activation failure.
  • the chips are firstly arranged on the electrostatic chuck, and then the method of bonding is more efficient than arranging and distributing at the same time as bonding.
  • the arrangement of the chips to be bonded on the electrostatic chuck can be designed according to the needs. By configuring the designed arrangement distribution map in the process parameters (recipe), the redistribution of effective chips (or chips of different sizes) on the electrostatic chuck can be realized. , the distribution range and position should match the corresponding chips on the wafer to be bonded.
  • the present invention provides a method for stacking chip wafers, including: providing a wafer to be processed, the wafer to be processed includes a substrate, a dielectric layer on the substrate, and a dielectric layer embedded in the substrate. metal layer in the dielectric layer; forming a bonding layer, the bonding layer covering the dielectric layer; picking up the chips to be bonded from the wafer to be processed, and arranging the chips to be bonded on the electrostatic chuck on; bonding the chips arranged on the electrostatic chuck as a whole with the wafer to be bonded.
  • All the chips to be bonded are pre-arranged on the electrostatic chuck, and the chips arranged on the electrostatic chuck are bonded to the wafer to be bonded as a whole, which can greatly reduce the damage to the chips after activation. Wafer bonding latency, reducing the risk of activation failure. It is more efficient to arrange all the chips to be bonded on the electrostatic chuck in advance and then perform the bonding as a whole rather than arranging and distributing them at the same time as bonding.
  • the blue film in the above solution can be replaced with a UV film, and the chip can be removed from the UV film by irradiation with ultraviolet light.
  • the use of UV film is beneficial to reduce the residual glue on the back of the chip, which can make the back of the chip more flat. After placing it on the electrostatic chuck, it is more conducive to the next step of bonding. For ultra-thin chips (thickness ⁇ 100 microns), it is easier to pick them up from the film using a UV film.

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Abstract

本发明提供一种芯片晶圆的堆叠方法，包括：提供待处理晶圆，所述待处理晶圆包括衬底、位于所述衬底上的介质层和嵌设于所述介质层中的金属层；形成键合层，所述键合层覆盖所述介质层；从所述待处理晶圆上拾取待键合的芯片，将所述待键合的芯片排列在静电吸盘上；将所述静电吸盘上排列后的所述芯片作为一个整体与所述待键合的晶圆键合。将所有待键合的芯片预先排列在静电吸盘上，将所述静电吸盘上排列后的所述芯片作为一个整体与所述待键合的晶圆键合，可极大减少活化后，芯片与晶圆键合的等待时间，降低活化失效的风险。将所有待键合的芯片预先排列在静电吸盘上，然后作为一个整体进行键合的方式比在键合的同时进行排列分布效率更高。

Description

芯片晶圆的堆叠方法 技术领域
本发明属于集成电路制造技术领域，具体涉及一种芯片晶圆堆叠结构及其制作方法。
背景技术
随着微电子产业进入后摩尔时代，芯片结构向三维方向发展，以进一步满足高集成度、小尺寸和优异性能的需求。相比于晶圆-晶圆堆叠(wafer to wafer，W2W)，芯片晶圆异质集成(Chip to wafer，C2W)可以实现不同技术节点和不同尺寸芯片间的互连，具有灵活度高的优点。同时，C2W可以通过选择已知良好芯片(KGD，known good die)与晶圆进行键合，可大大提升良率。C2W已成为3D-IC技术的一个重要发展方向。
目前C2W量产方案以微凸点封装工艺为主，其最小连接单元尺寸40μm左右，而且凸点之间的下填料不利于散热。当前研发方向在朝着更小连接单元尺寸的无凸点工艺发展。无凸点工艺利用混和键合技术实现铜对铜直接键合，连接单元尺寸可以小于10μm从而实现更高的输入/输出连接密度，而且没有下填料散热性能更好。
但是无凸点工艺也存在一些问题，一方面：铜易被氧化；另一方面：待键合的若干芯片先进行混合键合界面活化处理后，再一片一片的被键合到晶圆上时，部分芯片会等待较长时间，活化可能会失效。而且不同大小的芯片集中在一个区域与晶圆键合时,效率也低。这些问题导致该技术在实际应用量产时面临巨大的挑战。
发明内容
本发明的目的在于提供一种芯片晶圆的堆叠方法，减少芯片活化后，芯片与晶圆键合的等待时间，降低活化失效的风险，提高芯片晶圆的堆叠效率。
本发明提供一种芯片晶圆的堆叠方法，包括：
提供待处理晶圆，所述待处理晶圆包括衬底、位于所述衬底上的介质层 和嵌设于所述介质层中的金属层；形成键合层，所述键合层覆盖所述介质层；
从所述待处理晶圆上拾取待键合的芯片，将所述待键合的芯片预先排列在静电吸盘上；
将所述静电吸盘上预先排列后的所述芯片作为一个整体与所述待键合的晶圆键合。
进一步的，所述待键合的芯片预先排列在所述静电吸盘上之后，与所述待键合的晶圆键合之前，还包括：
等离子体活化所述待键合的晶圆的键合表面和/或排列后的所述芯片的键合表面。
进一步的，所述待键合的芯片包括功能和/或尺寸不同的芯片。
进一步的，所述待键合的芯片分别从第一待处理晶圆至第N待处理晶圆中拾取，N为≥1的整数；从第一待处理晶圆拾取第一芯片、从第i待处理晶圆拾取第i芯片以及从第N待处理晶圆拾取第N芯片，1＜i＜N；所述第一芯片、所述第i芯片以及所述第N芯片排列组合后构成重构芯片分布在所述静电吸盘上，所述重构芯片与所述待键合的晶圆上的芯片匹配。
进一步的，所述重构芯片在所述静电吸盘上周期分布。
进一步的，从所述第一待处理晶圆至所述第N待处理晶圆中的任意一个待处理晶圆上拾取各自的芯片之前均包括：对每个待处理晶圆划片后的键合表面涂覆金属抗氧化剂；
将待键合的芯片预先排列在静电吸盘上之后，执行所述等离子体活化的步骤之前包括：清洁所述芯片，去除所述芯片的键合界面上的所述金属抗氧化剂，同时对所述芯片的键合界面进行亲水处理。
进一步的，所述的芯片晶圆的堆叠方法中提供有多个静电吸盘，所述多个静电吸盘上预先排列后的所述芯片与所述待键合的晶圆键合。
进一步的，形成所述键合层之后，从所述待处理晶圆上拾取待键合的芯片之前,还包括：
将所述待处理晶圆的所述键合层面向载片晶圆键合；
形成硅通孔，所述硅通孔贯穿所述衬底和部分厚度的所述介质层，暴露出所述金属层；在所述硅通孔中形成互连层，所述互连层与所述第一金属层 电连接；
将所述待处理晶圆靠近所述硅通孔的贯穿入口的一侧表面贴蓝膜或UV膜；
将所述载片晶圆与所述待处理晶圆解键合，移除所述载片晶圆；
将所述待处理晶圆划片。
进一步的，所述待处理晶圆的所述键合层与所述载片晶圆通过键合胶键合；
将所述载片晶圆与所述待处理晶圆解键合，移除所述载片晶圆时，保留所述键合胶。
进一步的，从所述待处理晶圆上拾取所述待键合的芯片包括：从所述蓝膜或UV膜上取下所述待键合的芯片直接放到所述静电吸盘上。
进一步的，所述等离子体活化使用的等离子体气体包括：氧气、氮气、氩气或氢气中的任意一种或两种以上的组合。
进一步的，通过外部指令控制所述静电吸盘进行充电或放电，实现对排列后的所述芯片的吸附和释放。
进一步的，将所述静电吸盘上预先排列后的所述芯片作为一个整体与所述待键合的晶圆键合采用热负荷键合方法，其中，载荷施加到位于所述静电吸盘上的多个芯片并在真空下加热所述多个芯片和所述待键合的晶圆，以在所述待键合的晶圆的键合表面和排列后的所述芯片的键合表面之间形成原子键。
与现有技术相比，本发明具有如下有益效果：
本发明提供一种芯片晶圆的堆叠方法，包括：提供待处理晶圆，所述待处理晶圆包括衬底、位于所述衬底上的介质层和嵌设于所述介质层中的金属层；形成键合层，所述键合层覆盖所述介质层；从所述待处理晶圆上拾取待键合的芯片，将所述待键合的芯片排列在静电吸盘上；将所述静电吸盘上排列后的所述芯片作为一个整体与所述待键合的晶圆键合。将所有待键合的芯片预先排列在静电吸盘上，将所述静电吸盘上排列后的所述芯片作为一个整体与所述待键合的晶圆键合，可极大减少活化后，芯片与晶圆键合的等待时间，降低活化失效的风险。将所有待键合的芯片预先排列在静电吸盘上，然 后作为一个整体进行键合的方式比在键合的同时进行排列分布效率更高。
附图说明
图1为本发明实施例的一种芯片晶圆的堆叠方法流程示意图。
图2至图14为本发明实施例的芯片晶圆的堆叠方法各步骤示意图。
其中，附图标记如下：
10-第一待处理晶圆；11-第一衬底；12-第一介质层；13-第一金属层；14-键合层；15-绝缘层；16-互连层；17-测试焊盘层；18-测试焊盘；17’-混合键合层；18’-金属焊垫；A-载片晶圆；B-蓝膜；C-重构芯片；D 1-第一芯片；D 2-第二芯片；E-静电吸盘；W-待键合的晶圆；C’-键合芯片。
具体实施方式
基于上述研究，本发明实施例提供了一种芯片晶圆的堆叠方法。以下结合附图和具体实施例对本发明进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需要说明的是，附图均采用非常简化的形式且使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明实施例提供了一种芯片晶圆的堆叠方法，如图1所示，包括：
S1、提供待处理晶圆，所述待处理晶圆包括衬底、位于所述衬底上的介质层和嵌设于所述介质层中的金属层；形成键合层，所述键合层覆盖所述介质层；
S2、从所述待处理晶圆上拾取待键合的芯片，将所述待键合的芯片排列在静电吸盘上；
S3、将所述静电吸盘上排列后的所述芯片作为一个整体与所述待键合的晶圆键合。
所述待键合的芯片可为同一种芯片，也可为功能和/或尺寸不同的芯片。
下面结合图2至图14详细介绍本发明实施例的芯片晶圆的堆叠方法的各步骤。
如图2所示，提供第一待处理晶圆10，所述第一待处理晶圆10包括第一衬底11、位于所述第一衬底11上的第一介质层12和嵌设于所述第一介质层 12中的第一金属层13。形成键合层14，所述键合层14覆盖第一介质层12，键合层14的上表面为键合界面，优选的所述键合界面可以为包含金属和绝缘层的混合键合界面(Hybrid bond键合界面，图中未示出)。如图3所示，将第一待处理晶圆10的键合层14面向载片晶圆A键合，可通过键合胶临时键合。
如图4a和图4b所示，将第一待处理晶圆10减薄，减薄所述第一衬底11远离第一金属层13的一侧表面。在减薄后的所述第一衬底11表面形成绝缘层15。形成硅通孔V，所述硅通孔V贯穿绝缘层15、第一衬底11和部分厚度的第一介质层12，暴露出第一金属层13。所述第一介质层12不限于单层的介质层，也可以是多层的复合介质层，比如为包括二氧化硅层、氮化硅层的复合介质层。在硅通孔V中形成互连层16，互连层16的材质为金属，例如为铜或者钨。互连层16的材质为铜时，可采用电镀的方法形成。互连层16与第一金属层13电连接。如图4a所示，形成测试焊盘层17，测试焊盘层17包含绝缘层和嵌设在绝缘层中的测试焊盘18。通过测试焊盘18测试第一待处理晶圆10，标记良好芯片(KGD，known good die)。优选的，在测试焊盘层17和所述绝缘层15之间还可以包含再分布层(图中未示出)，再分布层包括再分布介质层和嵌设于再分布介质层中的再分布金属层，再分布金属层与互连层16电连接，再分布金属层实现晶圆内电信号的连接。在一个替代的实施例中，如图4b所示，形成混合键合层17’，混合键合层17’包含绝缘层和嵌设在绝缘层中的金属焊垫18’，优选的，在混合键合层17’和所述绝缘层15之间还可以包含再分布层(图中未示出)。
如图5所示，将第一待处理晶圆10的背面一侧贴蓝膜B。优选的，待处理晶圆和蓝膜B直接接合在一起，无须采用键合胶。如图6所示，将所述载片晶圆A与第一待处理晶圆10解键合，移除所述载片晶圆A，优选的保留键合胶。如图6和图7所示，将所述第一待处理晶圆10划片，可采用等离子体切割或激光切割，划片后形成多个第一芯片D 1。清洗划片后的第一待处理晶圆10，以去除键合胶以及切割产生的颗粒缺陷，在切割后去除键合胶有利于键合胶保护键合层14，从而避免键合层14在之前的工艺过程中被污染。在键合层14形成之后便与载片晶圆A临时键合，因此键合层14一直受到保护，因而能提升键合质量。优选的，在清洗后的第一待处理晶圆10表面喷涂金属 抗氧化剂(例如铜抗氧化剂)。在一实施例中，铜抗氧化剂为有机唑类物质和一些助剂、水组成的混合溶液。在另一实施例中，铜抗氧化剂包括：羟基乙叉二膦酸、乙醇、过氧化氢，苯并三氮唑、异硫氰酸酯、十二烷基硫酸盐、钼酸钠和三聚磷酸钠组成的混合溶液。喷涂金属抗氧化剂可以防止或减少键合层14表面(混合键合界面)金属(例如铜)的氧化，使在静电吸盘上排列芯片时不受等待时间的限制，增加派工的灵活性。
如图8至图10所示，将待键合的芯片排列在静电吸盘E上。所述待键合的芯片可来自于同一待处理晶圆。所述待键合的芯片也可来自于不同的待处理晶圆，示例性的，所述待键合的芯片来自N个待处理晶圆。所述待键合的芯片分别从第一待处理晶圆至第N待处理晶圆中拾取，N为≥1的自然数。从第一待处理晶圆拾取第一芯片；从第i待处理晶圆拾取第i芯片，1＜i＜N；从第N待处理晶圆拾取第N芯片；所述第一芯片、第i芯片以及第N芯片排列组合后构成重构芯片分布在所述静电吸盘上。应当理解，N＝1时，所述待键合的芯片从一片待处理晶圆(第一待处理晶圆)上拾取；N＝2时，所述待键合的芯片从第一待处理晶圆和第二待处理晶圆中拾取；N≥3时，i开始取值。所述“第一”、“第二”以及“第N”仅为区别开晶圆或芯片，不代表先后顺序。
优选的，在将所述待键合的芯片从蓝膜或UV膜上取下时，背面无需另外进行处理，直接放置在静电吸盘上。这是由于静电吸盘对键合界面没有过高的要求，可以直接进行吸附，进一步简化了工艺流程。
在一个重构芯片中，所述第一芯片、第i芯片以及第N芯片各自的数量不做限制，均可为1个或若干(≥2)个。所述重构芯片与所述待键合的晶圆上的芯片匹配。所述重构芯片可在所述静电吸盘上周期分布。示例性的，例如N＝2，如图8所示，对第一待处理晶圆10进行扩膜(蓝膜B)处理，从第一待处理晶圆10拾取需键合的第一芯片D 1。如图9所示，对第二待处理晶圆20进行扩膜(蓝膜B)处理，从第二待处理晶圆20拾取需键合的第二芯片D 2。如图10所示，将第一芯片D 1、第二芯片D 2排列组合后构成重构芯片C，重构芯片C可在所述静电吸盘E上周期分布。
可通过静电吸附力将重构芯片C保持(附着)在静电吸盘E上。在另一 实施例中，重构芯片C也可保持(附着)在基板上，通过粘合剂或粘合剂箔片(包括为容易脱粘而设计的粘合剂)，在施加高温或紫外线辐射后，或以任何其他方式将重构芯片安装到基板上时，可失去其粘合强度，根据需要实现重构芯片与基板的附着与脱离(释放)。
在利用静电吸盘的实施例中，通过外部指令控制静电吸盘进行充电、放电从而实现对芯片的吸附和释放，相当于快速地进行临时键合和解键合，仅仅需要外部信号的控制，无须增加任何工艺过程，大大缩短了芯片等待的时间，也即缩短了铜被氧化的时间，优选的也能够防止键合界面激活失效，提高了工艺效率，提升了键合质量。而现有技术中，尚未发现有将待键合的芯片排列组合分布后统一临时吸附(键合)在静电吸盘上，再与晶圆键合的工艺。
如图11所示，将重构芯片C保持(附着)在静电吸盘E之后，清洁重构芯片C，去除重构芯片C的键合界面上的金属抗氧化剂，同时对键合界面亲水处理。
如图12所示，等离子体活化待键合的晶圆W的键合表面以及排列后的芯片的键合表面。等离子体活化是采用等离子体处理的表面改性方法，其能够对晶圆的表面的化学和/或物理性质进行修改，能够打断由硅晶圆的正面上的自然氧化或热氧化形成的氧化硅分子的键。等离子体活化处理使用的等离子体气体包含但不限于，氧气(O 2)、惰性气体例如，氮气和/或氩气。在一个范例中，等离子体气体能够是氧气。在另一范例中，等离子体气体能够是氮气。等离子体气体还能够包含其它适合的气体，诸如氢气。根据一些实施例，等离子体气体的浓度小于5％。在一些实施例中，以0.05mbar与0.5mbar之间的压力执行等离子体活化处理。能够以诸如10瓦与100瓦之间的放电功率执行等离子体活化处理。在一些实施例中，以诸如10瓦与40瓦之间的低频放电功率执行等离子体活化处理。在一些实施例中，在诸如5秒与50秒之间的持续时间内执行等离子体活化处理。在一些实施例中，以30sccm与80sccm之间的流率执行等离子体活化处理。
如图13所示，将所述静电吸盘E上排列后的芯片作为一个整体与所述待键合的晶圆W键合。所述静电吸盘可为1个或若干(≥2)，1个所述静电吸 盘上可分布一个或若干(≥2)个所述重构芯片。若干(≥2)个所述静电吸盘上分布的重构芯片可相同，也可不同。图13中示出了1个静电吸盘上排列后的芯片与待键合的晶圆W键合，所述1个静电吸盘的面积与待键合的晶圆W的面积可以相同，也可不同。其他实施例中，也可为若干(≥2)个静电吸盘上排列后的芯片与待键合的晶圆键合，即一个待键合的晶圆W与多个静电吸盘E上的重构芯片对应并实现键合，例如待键合的晶圆W面积较大，静电吸盘E的面积相对待键合的晶圆W较小(也可以相等)，若干(≥2)个所述静电吸盘可各自按需排布重构芯片与待键合的晶圆W键合，增大静电吸盘上分布重构芯片的灵活性。
芯片晶圆(C2W)键合，将一个或多个已知良好裸片(KGD)与晶圆键合，本实施例根据实际需要，对良好裸片(KGD)进行了排列，构成重构芯片C，重构芯片C可根据需要在静电吸盘E上重复分布或不重复分布。如图13和图14所示，将静电吸盘E上排列好的所有芯片作为一个整体直接与待键合晶圆W上的对应芯片进行预键合，之后静电吸盘E释放所有芯片，移走静电吸盘E，静电吸盘E上的所有芯片通过预键合转移至待键合晶圆W的对应芯片上，重构芯片C与待键合晶圆W的对应芯片键合后形成键合芯片C’。清洁键合芯片C’的表面，将键合芯片C’与待键合晶圆W一起进行退火完成混合键合。
静电吸盘E上排列好的所有芯片作为一个整体与待键合晶圆W上的对应芯片键合，可采用直接键合方法，例如热负荷键合方法，载荷施加到位于静电吸盘上的多个芯片并在真空下加热多个芯片和待键合的晶圆，以利于在其表面(通常是金属表面，例如金属接触垫)之间形成原子键。
本实施例将待键合的芯片预先排列后在静电吸盘上；再对静电吸盘上的排列后的所述芯片一起进行键合表面的等离子体活化，然后将静电吸盘上的所有芯片作为整体与待键合的晶圆进行预键合。可极大减少等离子体活化后芯片的等待时间，降低活化失效的风险。本实施例将芯片先按排列在静电吸盘上，然后进行键合的方式比在键合的同时进行排列分布效率更高。
待键合的芯片在静电吸盘上的排列方式可根据需要设计，通过将设计的排列分布图配置在工艺参数(recipe)中，实现有效芯片(或是大小不同芯片) 在静电吸盘上的再分布，分布的范围和位置应与待键合晶圆上相对应的芯片匹配。
综上所述，本发明提供一种芯片晶圆的堆叠方法，包括：提供待处理晶圆，所述待处理晶圆包括衬底、位于所述衬底上的介质层和嵌设于所述介质层中的金属层；形成键合层，所述键合层覆盖所述介质层；从所述待处理晶圆上拾取待键合的芯片，将所述待键合的芯片排列在静电吸盘上；将所述静电吸盘上排列后的所述芯片作为一个整体与所述待键合的晶圆键合。将所有待键合的芯片预先排列在静电吸盘上，将所述静电吸盘上排列后的所述芯片作为一个整体与所述待键合的晶圆键合，可极大减少活化后，芯片与晶圆键合的等待时间，降低活化失效的风险。将所有待键合的芯片预先排列在静电吸盘上，然后作为一个整体进行键合的方式比在键合的同时进行排列分布效率更高。可替代的，可将上述方案中的蓝膜替换成UV膜，利用紫外光照射即可实现将芯片从UV膜上取下。利用UV膜有利于减少芯片背面的残胶，能够使芯片的背面更加平整，在放置在静电吸盘上后，更有利于进行下一步键合。对于超薄芯片(厚度<100微米)，使用UV膜更容易将其从膜上拾取。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的方法而言，由于与实施例公开的器件相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (13)

  1. 一种芯片晶圆的堆叠方法，其特征在于，包括：
    提供待处理晶圆，所述待处理晶圆包括衬底、位于所述衬底上的介质层和嵌设于所述介质层中的金属层；形成键合层，所述键合层覆盖所述介质层；
    从所述待处理晶圆上拾取待键合的芯片，将所述待键合的芯片预先排列在静电吸盘上；
    将所述静电吸盘上预先排列后的所述芯片作为一个整体与所述待键合的晶圆键合。
  2. 如权利要求1所述的芯片晶圆的堆叠方法，其特征在于，所述待键合的芯片预先排列在所述静电吸盘上之后，与所述待键合的晶圆键合之前，还包括：
    等离子体活化所述待键合的晶圆的键合表面和/或排列后的所述芯片的键合表面。
  3. 如权利要求1所述的芯片晶圆的堆叠方法，其特征在于，所述待键合的芯片包括功能和/或尺寸不同的芯片。
  4. 如权利要求1所述的芯片晶圆的堆叠方法，其特征在于，所述待键合的芯片分别从第一待处理晶圆至第N待处理晶圆中拾取，N为≥1的整数；从第一待处理晶圆拾取第一芯片、从第i待处理晶圆拾取第i芯片以及从第N待处理晶圆拾取第N芯片，1＜i＜N；所述第一芯片、所述第i芯片以及所述第N芯片排列组合后构成重构芯片分布在所述静电吸盘上，所述重构芯片与所述待键合的晶圆上的芯片匹配。
  5. 如权利要求4所述的芯片晶圆的堆叠方法，其特征在于，所述重构芯片在所述静电吸盘上周期分布。
  6. 如权利要求4所述的芯片晶圆的堆叠方法，其特征在于，
    从所述第一待处理晶圆至所述第N待处理晶圆中的任意一个待处理晶圆上拾取各自的芯片之前均包括：对每个待处理晶圆划片后的键合表面涂覆金属抗氧化剂；
    将待键合的芯片预先排列在静电吸盘上之后，执行所述等离子体活化的 步骤之前包括：清洁所述芯片，去除所述芯片的键合界面上的所述金属抗氧化剂，同时对所述芯片的键合界面进行亲水处理。
  7. 如权利要求1所述的芯片晶圆的堆叠方法，其特征在于，提供有多个静电吸盘，所述多个静电吸盘上预先排列后的所述芯片与所述待键合的晶圆键合。
  8. 如权利要求1所述的芯片晶圆的堆叠方法，其特征在于，形成所述键合层之后，从所述待处理晶圆上拾取待键合的芯片之前,还包括：
    将所述待处理晶圆的所述键合层面向载片晶圆键合；
    形成硅通孔，所述硅通孔贯穿所述衬底和部分厚度的所述介质层，暴露出所述金属层；在所述硅通孔中形成互连层，所述互连层与所述第一金属层电连接；
    将所述待处理晶圆靠近所述硅通孔的贯穿入口的一侧表面贴蓝膜或UV膜；
    将所述载片晶圆与所述待处理晶圆解键合，移除所述载片晶圆；
    将所述待处理晶圆划片。
  9. 如权利要求8所述的芯片晶圆的堆叠方法，其特征在于，
    所述待处理晶圆的所述键合层与所述载片晶圆通过键合胶键合；
    将所述载片晶圆与所述待处理晶圆解键合，移除所述载片晶圆时，保留所述键合胶。
  10. 如权利要求8所述的芯片晶圆的堆叠方法，其特征在于，从所述待处理晶圆上拾取所述待键合的芯片包括：从所述蓝膜或UV膜上取下所述待键合的芯片直接放置在所述静电吸盘上。
  11. 如权利要求2所述的芯片晶圆的堆叠方法，其特征在于，所述等离子体活化使用的等离子体气体包括：氧气、氮气、氩气或氢气中的任意一种或两种以上的组合。
  12. 如权利要求1所述的芯片晶圆的堆叠方法，其特征在于，通过外部指令控制所述静电吸盘进行充电或放电，实现对排列后的所述芯片的吸附和释放。
  13. 如权利要求1所述的芯片晶圆的堆叠方法，其特征在于，将所述静 电吸盘上预先排列后的所述芯片作为一个整体与所述待键合的晶圆键合采用热负荷键合方法，其中，载荷施加到位于所述静电吸盘上的多个芯片并在真空下加热所述多个芯片和所述待键合的晶圆，以在所述待键合的晶圆的键合表面和排列后的所述芯片的键合表面之间形成原子键。
PCT/CN2020/138144 2020-12-10 2020-12-21 芯片晶圆的堆叠方法 WO2022120939A1 (zh)

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