WO2022116305A1 - 一种双面显示面板及制备方法 - Google Patents

一种双面显示面板及制备方法 Download PDF

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Publication number
WO2022116305A1
WO2022116305A1 PCT/CN2020/138001 CN2020138001W WO2022116305A1 WO 2022116305 A1 WO2022116305 A1 WO 2022116305A1 CN 2020138001 W CN2020138001 W CN 2020138001W WO 2022116305 A1 WO2022116305 A1 WO 2022116305A1
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WIPO (PCT)
Prior art keywords
layer
array
substrate
double
light
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PCT/CN2020/138001
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English (en)
French (fr)
Inventor
张磊
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Tcl华星光电技术有限公司
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Publication of WO2022116305A1 publication Critical patent/WO2022116305A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements

Definitions

  • Embodiments of the present invention relate to the field of display panels, and in particular, to a double-sided display panel and a manufacturing method.
  • the double-sided display screen has broad application prospects in the fields of commodity display, electronic bulletin board, high-end exhibition and other fields.
  • the current double-sided display usually uses two TFT-LCD substrates back-to-back bonding, and the double-sided display is achieved through two panels.
  • the inventor of the embodiment of the present invention found that since the two display panels both require separate backlights, and due to the design requirements of heat dissipation, the double-sided display screen produced will have a relatively high performance.
  • the large thickness takes up space and affects the look and feel, and the process is complicated and the yield is low, and the production cost is high; and the use of two TFT-LCD substrates for back-to-back bonding will seriously affect the lightness and thinness of the product.
  • Embodiments of the present invention provide a double-sided display panel and a manufacturing method, so as to solve the problem that the thickness of the whole machine will be increased due to the design of using two TFT-LCD substrates back-to-back, which will seriously affect the lightness and thinness of the product.
  • Embodiments of the present invention provide a double-sided display panel and a method for manufacturing the same.
  • the manufacturing cost can be reduced and the lightness and thickness of the laser display can be achieved.
  • an embodiment of the present invention provides a double-sided display panel, including:
  • the substrate includes a first surface and a second surface disposed oppositely;
  • the array substrate is disposed on the first surface of the substrate, wherein the array substrate is provided with at least two array switches;
  • a first light-emitting unit and a second light-emitting unit are respectively disposed on the first surface and the second surface of the substrate, and part of the array switches are electrically connected to the first light-emitting unit for controlling the first light-emitting unit The other part of the array switch is electrically connected to the second light-emitting unit for controlling the second light-emitting unit to emit light, so as to realize double-sided display.
  • the at least two array switches include at least a first array switch and a second array switch, wherein a first drain of the first array switch and a first drain of the first light emitting unit An anode is electrically connected, and the second drain of the second array switch is electrically connected to the second anode of the second light-emitting unit.
  • the second drain electrode extends to the second surface of the substrate to be electrically connected with the second anode electrode.
  • the second drain electrode extends to the first surface of the substrate, and the second anode of the second light emitting unit extends to the first surface of the substrate to achieve the same
  • the second drain is electrically connected.
  • the first array switches and the second array switches are alternately arranged.
  • the first surface of the substrate is provided with a first transparent electrode layer and a light shielding layer.
  • the array substrate is formed over the first transparent electrode layer and the light shielding layer.
  • the array substrate further includes a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer, and the buffer layer is formed on the first transparent electrode layer and the first transparent electrode layer.
  • the buffer layer covers the first transparent electrode layer and the light shielding layer, and the active layer and the second transparent electrode layer are spaced apart on the side of the buffer layer away from the base substrate , the gate insulating layer is formed on the side of the active layer away from the buffer layer, the gate is formed on the side of the gate insulating layer away from the active layer, and the interlayer insulation A layer covers the buffer layer, the active layer, the second transparent electrode layer, the gate insulating layer and the gate.
  • the double-sided display panel further includes an insulating layer formed on the side of the array substrate away from the first transparent electrode layer and the light shielding layer.
  • the insulating layer includes a passivation layer and a planarization layer
  • the passivation layer is formed on the side of the interlayer insulating layer away from the buffer layer
  • the passivation layer covers the The interlayer insulating layer and the first electrode, the second electrode, the third electrode and the fourth electrode, and the planarization layer is formed when the passivation layer is far from the interlayer insulating layer. side.
  • an embodiment of the present invention provides a method for fabricating a double-sided display panel, including:
  • a first light-emitting unit is formed on the first surface of the array substrate away from the first surface, and a second light-emitting unit is formed on a second surface of the substrate opposite to the first surface, wherein part of the array A switch is electrically connected to the first light-emitting unit for controlling the first light-emitting unit to emit light, and another part of the array switches is electrically connected to the second light-emitting unit for controlling the second light-emitting unit to emit light, so as to Realize double-sided display.
  • the at least two array switches include at least a first array switch and a second array switch, wherein the first array switch includes a first source electrode and a first drain electrode, and the first array switch includes a first source electrode and a first drain electrode.
  • a drain electrode is electrically connected to the first anode of the first light-emitting unit
  • the second array switch includes a second source electrode and a second drain electrode, and the second drain electrode is connected to the second electrode of the second light-emitting unit.
  • Anode electrical connection is
  • the second drain electrode extends to the second surface of the substrate to be electrically connected to the second anode.
  • the second drain electrode extends to the first surface of the substrate, and the second anode of the second light-emitting unit extends to the first surface of the substrate, so as to achieve the same
  • the second drain is electrically connected.
  • the first array switches and the second array switches are alternately arranged.
  • the method includes:
  • a first transparent electrode layer and a light shielding layer are formed on the first surface of the substrate.
  • the method includes:
  • the array substrate is formed over the first transparent electrode layer and the light shielding layer.
  • the array substrate further includes a buffer layer, an active layer, a gate insulating layer, a gate electrode and an interlayer insulating layer, including:
  • the buffer layer is formed over the first transparent electrode layer and the light shielding layer, the buffer layer covers the first transparent electrode layer and the light shielding layer, and the active layer and the second transparent electrode layer are spaced apart is formed on a side of the buffer layer away from the base substrate, the gate insulating layer is formed on a side of the active layer away from the buffer layer, and the gate is formed on the gate insulating layer On a side away from the active layer, the interlayer insulating layer covers the buffer layer, the active layer, the second transparent electrode layer, the gate insulating layer and the gate.
  • the double-sided display panel further includes an insulating layer, including:
  • the insulating layer is formed on the side of the array substrate away from the first transparent electrode layer and the light shielding layer.
  • the insulating layer includes a passivation layer and a planarization layer, including:
  • the passivation layer is formed on the side of the interlayer insulating layer away from the buffer layer, and the passivation layer covers the interlayer insulating layer and the first electrode, the second electrode and the third electrode. electrode and the fourth electrode, the planarization layer is formed on the side of the passivation layer away from the interlayer insulating layer.
  • Embodiments of the present invention provide a double-sided display panel and a manufacturing method.
  • the embodiments of the present invention provide a double-sided display panel, wherein the double-sided display panel includes: a substrate, and the substrate includes a first surface disposed oppositely and a second surface; an array substrate, which is arranged on the first surface of the substrate, wherein the array substrate is provided with at least two array switches; the first light-emitting unit and the second light-emitting unit are respectively arranged in On the first surface and the second surface of the substrate, some of the array switches are electrically connected to the first light-emitting unit, and are used to control the first light-emitting unit to emit light; the double-sided display panel provided by the embodiment of the present invention, At least two array switches that can respectively provide light to the first light-emitting unit and the second light-emitting unit are manufactured under the same manufacturing process, which can reduce the manufacturing cost and prevent the double-sided display panel from increasing its panel thickness to achieve ultra-high performance. Thin display, realize
  • FIG. 1 is a schematic diagram of a first structure of a double-sided display panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a second structure of a double-sided display panel according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a third structure of a double-sided display panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a fourth structure of a double-sided display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a fifth structure of a double-sided display panel provided by an embodiment of the present invention.
  • FIG. 6 is a first schematic flowchart of a method for manufacturing a double-sided display panel according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a second flow of a method for manufacturing a double-sided display panel according to an embodiment of the present invention.
  • FIG. 8 is a third schematic flowchart of a method for manufacturing a double-sided display panel according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a driving circuit provided by an embodiment of the present invention.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present invention, “ “ means two or more, unless otherwise expressly and specifically defined.
  • Embodiments of the present invention provide a double-sided display panel and a manufacturing method, and the display panel can be used in conjunction with a terminal, such as a smart phone, a tablet computer, a notebook computer, or a personal computer.
  • a terminal such as a smart phone, a tablet computer, a notebook computer, or a personal computer.
  • the double-sided display panel and the manufacturing method will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.
  • Embodiment 1 of the present invention provides a double-sided display panel, the double-sided display panel includes a substrate, the substrate includes a first surface and a second surface arranged oppositely; an array substrate, the array substrate is arranged on the The first surface of the substrate, wherein the array substrate is provided with at least two array switches. It also includes a first light-emitting unit and a second light-emitting unit, which are respectively disposed on the first surface and the second surface of the substrate, and part of the array switches are electrically connected to the first light-emitting unit for controlling the first light-emitting unit.
  • the light-emitting unit emits light
  • another part of the array switch is electrically connected to the second light-emitting unit for controlling the second light-emitting unit to emit light, so as to realize double-sided display.
  • the double-sided display panel provided by the embodiment of the present invention solves the technical problems that the backlight of the two panels needs to be manufactured separately if the double-sided display is achieved, so that the large thickness takes up space and affects the appearance, and the process is complicated, the yield is low, and the manufacturing cost is high.
  • the double-sided display panel provided by the embodiment of the invention may include the following technical effects: at least two array switches that can be respectively provided for the first light-emitting unit and the second light-emitting unit to emit light can be manufactured under the same manufacturing process, which can reduce the manufacturing cost and make the
  • the double-sided display panel does not increase the thickness of the panel to realize ultra-thin display, thereby realizing the lightness and thinness of the double-sided display panel.
  • the second embodiment of the present invention provides a double-sided display panel.
  • the double-sided display panel includes a substrate 2 , and the substrate 2 includes a first surface and a surface disposed opposite to each other.
  • the at least two array switches include at least a first array switch and a second array switch, wherein the first drain 452 of the first array switch is electrically connected to the first anode of the first light-emitting unit 7a1, the The second drain 454 of the second array switch is electrically connected to the second anode of the second light emitting unit 7b1.
  • the second drain 454 extends to the second surface of the substrate 2 to be electrically connected to the second anode.
  • at least two array switches are provided on the array substrate, and the at least two array switches include at least a first array switch and a second array switch, which can be respectively provided to the first array switch in the same fabrication process.
  • the at least two array switches of the light-emitting unit and the second light-emitting unit emit light, so that the manufacturing cost can be reduced, and the double-sided display panel will not increase its panel thickness to realize ultra-thin display, thereby realizing the lightness and thinness of the double-sided display panel.
  • the first light-emitting unit 7a1 is located in the first light-emitting unit 7a1, the first anode is located in the first anode layer; the second light-emitting unit 7b1 is located in the second light-emitting unit 7b1, so The second anode is located in the second anode layer.
  • the double-sided display panel includes:
  • the substrate 2 includes a first surface and a second surface arranged oppositely; a first transparent electrode layer 31 and a light shielding layer 32 are arranged on the first surface of the substrate 2, the first transparent electrode The layer 31 and the light shielding layer 32 are distributed on the first surface of the substrate 2 at intervals;
  • an array substrate formed above the first transparent electrode layer 31 and the light shielding layer 32, and the array substrate includes the at least two array switches;
  • an insulating layer formed on the side of the array substrate away from the first transparent electrode layer 31 and the light shielding layer 32;
  • the first anode 61 is formed in the insulating layer and is used for electrical connection with the first drain electrode 452.
  • the first anode 61 is connected to the first electrode of the first array switch through the first through hole 507 of the insulating layer.
  • a drain 452 is electrically connected;
  • the first pixel definition layer 7a is formed on the side of the insulating layer away from the array substrate;
  • the first encapsulation layer 81 is formed on the side of the first pixel definition layer 7a away from the insulating layer;
  • the second pixel definition layer 7b is formed on the second surface of the substrate 2;
  • the second anode 62 is formed in the second pixel definition layer 7b and is used for electrical connection with the second drain 454.
  • the second anode 62 is connected to the second drain 454 of the second array switch through an opening. electrical connection;
  • the second light emitting unit 7b1 is formed in the second pixel definition layer 7b and is used for electrical connection with the second anode 62 .
  • the at least two array switches include at least a first array switch and a second array switch
  • the first array switch includes a first source 451 and a first drain
  • the second array switch includes a second source electrode 453 and a second drain electrode 454 .
  • the array substrate includes at least two array switches, a buffer layer, an active layer 41 , a gate insulating layer 42 , a gate electrode 43 and an interlayer insulating layer 4 ,
  • the buffer layer is formed above the first transparent electrode layer 31 and the light shielding layer 32 , the buffer layer covers the first transparent electrode layer 31 and the light shielding layer 32 , the active layer 41 and the light shielding layer 32 .
  • Two transparent electrode layers 44 are formed at intervals on the side of the buffer layer away from the substrate 2 , the gate insulating layer 42 is formed on the side of the active layer 41 away from the buffer layer, and the gate 43 is formed on the side of the gate insulating layer 42 away from the active layer 41, and the interlayer insulating layer 4 covers the buffer layer, the active layer 41, the second transparent electrode layer 44, the gate insulating layer 42 and the gate 43 .
  • the openings include a first opening 501 , a second opening 502 , a third opening 503 , a fourth opening 504 , a fifth opening 505 ,
  • the sixth opening 506 and the seventh opening 507; the first opening 501, the second opening 502, the fourth opening 504 and the fifth opening 505 are provided in the interlayer insulation Layer 4, the third opening 503 and the sixth opening 506 are arranged between the interlayer insulating layer 4 and the buffer layer, and the seventh opening 507 is arranged in the interlayer insulating layer 4. Between the buffer layer and the substrate 2 .
  • the first opening 501 , the second opening 502 and the third opening 503 are located in the area corresponding to the first array switch, so The fourth opening 504, the fifth opening 505, the sixth opening 506 and the seventh opening 507 are located in the area corresponding to the second array switch; the first source 451 passes through the The first opening 501 is electrically connected to the second transparent electrode layer 44, and the first drain 452 is connected to the first transparent electrode through the second opening 502 and the third opening 503, respectively.
  • the layer 31 and the second transparent electrode layer 44 are electrically connected, the second source electrode 453 is electrically connected to the second transparent electrode layer 44 through the fourth opening 504 , and the second drain electrode 454
  • the fifth opening 505 and the sixth opening 506 are electrically connected to the first transparent electrode layer 31 and the second transparent electrode layer 44 respectively.
  • the seventh opening 507 is used to expose an end of the second drain 454 away from the insulating layer, and the second anode 62 is connected to the second anode 62 through the seventh opening 507
  • the second drains 454 of the second array switches are electrically connected.
  • the insulating layer includes a passivation layer 5 and a planarization layer 6, and the passivation layer 5 is formed on the side of the interlayer insulating layer 4 away from the buffer layer.
  • the passivation layer 5 covers the interlayer insulating layer 4 and the first source electrode 451 , the first drain electrode 452 , the second source electrode 453 and the second drain electrode 454 , and the planarization layer 6 is formed on the side of the passivation layer 5 away from the interlayer insulating layer 4 .
  • the number of the array switches is multiple, half of the array switches are connected to the first light-emitting unit 7a1 to realize display in the display area of the first surface, and the array switches are another part of the array switches. One half is connected to the second light emitting unit 7b1 to realize the display in the second surface display area.
  • the number of array switches is multiple, and the array switch includes the first array switch and the second array switch, the first array switch and the The first light-emitting unit 7a1 is connected, the second array switch is connected to the second light-emitting unit 7b1, and the first array switch and the second array switch are alternately arranged on the array substrate.
  • Embodiment 3 of the present invention provides a double-sided display panel.
  • the double-sided display panel includes a substrate 2 , and the substrate 2 includes a first surface and The second surface; the array substrate, which is arranged on the first surface of the substrate 2, wherein the array substrate is provided with at least two array switches; the first light-emitting unit 7a1 and the second light-emitting unit 7b1, respectively Provided on the first surface and the second surface of the substrate 2, some of the array switches are electrically connected to the first light-emitting unit 7a1 for controlling the first light-emitting unit 7a1 to emit light, and another part of the array switches It is electrically connected to the second light-emitting unit 7b1 for controlling the second light-emitting unit 7b1 to emit light, so as to realize double-sided display.
  • the at least two array switches include at least a first array switch and a second array switch, wherein the first drain 452 of the first array switch is electrically connected to the first anode of the first light-emitting unit 7a1, the The second drain 454 of the second array switch is electrically connected to the second anode of the second light emitting unit 7b1.
  • the second drain electrode 454 extends to the first surface of the substrate 2, and the second anode of the second light emitting unit 7b1 extends to the first surface of the substrate 2, so as to realize the connection with the second drain electrode. Pole 454 is electrically connected.
  • the double-sided display panel includes:
  • the substrate 2 includes a first surface and a second surface arranged oppositely; a first transparent electrode layer 31 and a light shielding layer 32 are arranged on the first surface of the substrate 2, the first transparent electrode The layer 31 and the light shielding layer 32 are distributed on the first surface of the substrate 2 at intervals;
  • an array substrate formed above the first transparent electrode layer 31 and the light shielding layer 32, and the array substrate includes the at least two array switches;
  • an insulating layer formed on the side of the array substrate away from the first transparent electrode layer 31 and the light shielding layer 32;
  • the first anode 61 is formed in the insulating layer and is used for electrical connection with the first drain electrode 452.
  • the first anode 61 is connected to the first electrode of the first array switch through the first through hole 507 of the insulating layer.
  • a drain 452 is electrically connected;
  • the first pixel definition layer 7a is formed on the side of the insulating layer away from the array substrate;
  • the first encapsulation layer 81 is formed on the side of the first pixel definition layer 7a away from the insulating layer;
  • the second pixel definition layer 7b is formed on the second surface of the substrate 2;
  • the second anode 62 is formed in the second pixel definition layer 7b and is used for electrical connection with the second drain 454.
  • the second anode 62 is connected to the second drain 454 of the second array switch through an opening. electrical connection;
  • the second light emitting unit 7b1 is formed in the second pixel definition layer 7b and is used for electrical connection with the second anode 62 .
  • the at least two array switches include at least a first array switch and a second array switch, and the first array switch includes a first array switch.
  • the second array switch includes a second source electrode 453 and a second drain electrode 454 .
  • the array substrate includes at least two array switches, a buffer layer, an active layer 41 , a gate insulating layer 42 , and a gate electrode.
  • the buffer layer is formed above the first transparent electrode layer 31 and the light shielding layer 32
  • the buffer layer covers the first transparent electrode layer 31 and the light shielding layer 32
  • the active layer 41 and the second transparent electrode layer 44 are formed at intervals on the side of the buffer layer away from the substrate 2
  • the gate insulating layer 42 is formed at the active layer 41 away from the buffer layer.
  • the gate 43 is formed on the side of the gate insulating layer 42 away from the active layer 41, and the interlayer insulating layer 4 covers the buffer layer, the active layer 41, the The second transparent electrode layer 44 , the gate insulating layer 42 and the gate 43 are formed.
  • the openings include a first opening 501 , a second opening 502 , a third opening 503 , and a fourth opening 504, the fifth opening 505, the sixth opening 506 and the seventh opening 507;
  • the first opening 501, the second opening 502, the fourth opening 504 and the fifth opening 505 is arranged in the interlayer insulating layer 4,
  • the third opening 503 and the sixth opening 506 are arranged between the interlayer insulating layer 4 and the buffer layer, and the seventh opening 507 It is arranged between the interlayer insulating layer 4 and the buffer layer.
  • the first opening 501 , the second opening 502 and the third opening 503 are located in the In an area corresponding to an array switch
  • the fourth opening 504, the fifth opening 505, the sixth opening 506 and the seventh opening 507 are located in the area corresponding to the second array switch
  • the first source electrode 451 is electrically connected to the second transparent electrode layer 44 through the first opening 501
  • the first drain electrode 452 is electrically connected through the second opening 502 and the third opening 503
  • the first transparent electrode layer 31 and the second transparent electrode layer 44 are respectively electrically connected
  • the second source electrode 453 is electrically connected to the second transparent electrode layer 44 through the fourth opening 504
  • the second drain 454 is electrically connected to the first transparent electrode layer 31 and the second transparent electrode layer 44 through the fifth opening 505 and the sixth opening 506 , respectively.
  • a second through hole is provided on the second surface of the substrate 2 to expose an end of the second drain electrode 454 away from the insulating layer, and the second anode 62 passes through the The seventh opening 507 and the second through hole are electrically connected to the second drain 454 of the region corresponding to the second array switch.
  • the insulating layer includes a passivation layer 5 and a planarization layer 6, and the passivation layer 5 is formed on the side of the interlayer insulating layer 4 away from the buffer layer.
  • the passivation layer 5 covers the interlayer insulating layer 4 and the first source electrode 451 , the first drain electrode 452 , the second source electrode 453 and the second drain electrode 454 , and the planarization layer 6 is formed on the side of the passivation layer 5 away from the interlayer insulating layer 4 .
  • the number of the array switches is multiple, half of the array switches are connected to the first light-emitting unit 7a1 to realize display in the display area of the first surface, and the array switches are another part of the array switches. One half is connected to the second light emitting unit 7b1 to realize the display in the second surface display area.
  • the number of array switches is multiple, and the array switch includes the first array switch and the second array switch, the first array switch and the The first light-emitting unit 7a1 is connected, the second array switch is connected to the second light-emitting unit 7b1, and the first array switch and the second array switch are alternately arranged on the array substrate.
  • the embodiment of the present invention provides a display panel.
  • the double-sided display panel provided by the embodiment of the present invention is controlled by a TFT array substrate.
  • the hole is dug into the anode design on the other side, and odd-numbered rows and even-numbered rows are used to control the signals displayed in the display area of the first side and the display area of the second side respectively; using the embodiment of the present invention to form a double-sided display panel, the manufacturing cost is reduced, and all
  • the double-sided display panel does not increase the thickness of the panel to achieve ultra-thin display and realize the thinning of the double-sided display panel.
  • Embodiment 4 of the present invention provides a method for manufacturing a double-sided display panel.
  • the method for manufacturing a double-sided display panel includes:
  • S101 Provide a substrate, and form an array substrate on a first surface of the substrate;
  • the at least two array switches include at least a first array switch and a second array switch, wherein a first drain of the first array switch and a drain of the first light-emitting unit The first anode is electrically connected, and the second drain of the second array switch is electrically connected to the second anode of the second light-emitting unit.
  • the second drain electrode extends to the second surface of the substrate to be electrically connected to the second anode electrode.
  • the second drain electrode extends to the first surface of the substrate, and the second anode of the second light-emitting unit extends to the first surface of the substrate, so as to realize electrically connected to the second drain
  • the first array switches and the second array switches are alternately arranged.
  • a fifth embodiment of the present invention provides a method for fabricating a double-sided display panel.
  • the method for fabricating a double-sided display panel includes:
  • the first glass substrate is a glass substrate, or other transparent materials, and the material of the substrate is polyimide.
  • a halftone mask is used. After the template exposes, develops and etches the ITO film layer and the metal film layer, the photoresist is peeled off to form a patterned first transparent electrode layer and a light shielding layer.
  • the array substrate includes a first array switch formed in the light-emitting area of the first surface, and a second array switch formed in the light-emitting area of the second surface;
  • the array substrate includes at least two array switches, a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer, and buffers are sequentially formed on the light shielding layer.
  • layer, an active layer, a gate insulating layer, a gate electrode and an interlayer insulating layer, and a second transparent electrode layer is formed on the interlayer insulating layer.
  • a buffer layer is prepared on the light-shielding layer, an active layer is prepared on the buffer layer, and then a gate insulating layer material and a metal are sequentially coated on the active layer. material, and then patterning the gate insulating layer material and the metal material to form a gate insulating layer and a gate, and treating the parts of the active layer that are not covered by the gate insulating layer and the gate Part of the conductor treatment is carried out; the material of the active layer is indium gallium zinc oxide, and can also be other oxide materials.
  • an ITO film layer is sequentially coated on the interlayer insulating layer, and after a mask process is performed on the ITO film layer using a half-tone mask, an ITO film layer is formed on the interlayer insulating layer.
  • the second transparent electrode layer, the first transparent electrode layer and the second transparent electrode layer form a storage capacitor.
  • the interlayer insulating layer and the buffer layer are opened by using a mask process, the array substrate is simultaneously opened by a mask process, and the interlayer insulating layer is formed.
  • a first opening, a second opening, a fourth opening and a fifth opening, a third opening and a sixth opening are formed between the interlayer insulating layer and the buffer layer, and a third opening and a sixth opening are formed between the layers
  • a seventh opening is formed between the insulating layer, the buffer layer and the substrate;
  • the first opening, the second opening and the third opening are correspondingly arranged in the corresponding positions of the first array switch area, the fourth opening, the fifth opening, the sixth opening and the seventh opening are correspondingly arranged in the area corresponding to the second array switch;
  • a first opening, a second opening, a fourth opening and a fifth opening are formed to expose the surfaces of both ends of the active layer, and a third opening is formed between the interlayer insulating layer and the buffer layer and a
  • an array substrate is formed on the light shielding layer 32 , and the array substrate includes at least two array switches, a buffer layer, an active layer 41 , and a gate insulating layer 42 . , the gate 43 and the interlayer insulating layer 4 .
  • a first metal layer is formed on the array substrate, the first metal layer is patterned, a first source electrode is formed in the first opening, the second opening and the third opening are A first drain is formed at the fourth opening, a second source is formed at the fourth opening, and a second drain is formed at the fifth opening, the sixth opening and the seventh opening;
  • the seventh opening exposes an end of the second drain away from the insulating layer, and the second anode is electrically connected to the second drain through the seventh opening.
  • the insulating layer includes a passivation layer and a planarization layer.
  • the insulating layer includes a passivation layer and a planarization layer.
  • the passivation layer 5 and the planarization layer 6 are formed on the electrode layer 45 .
  • the passivation layer 5 and the planarization layer 6 are provided with via holes to expose the electrode (source or drain) of the electrode layer 45; then the passivation layer 5 and the planarization layer
  • the ITO film is coated on the chemical layer 6, the same masking process is performed on the ITO film by using a halftone mask, a first anode 61 is formed over the storage capacitor, and a first anode 61 is formed over the first anode 61.
  • the first anode 61 is correspondingly disposed on one side of the first drain 452 , and the first anode 61 is electrically connected to the first drain 452 .
  • the first glass substrate 1 is peeled off, and the second anode 62 , the second pixel definition layer 7 b and the second anode 62 are formed on the second surface of the substrate 2 .
  • the second light-emitting unit 7b1 and the second encapsulation layer 82 are described above, and finally the second glass substrate 9 is peeled off.
  • the second anode 62 is correspondingly disposed on one side of the second drain 454 , and the second anode 62 is electrically connected to the second drain 454 .
  • Embodiment 6 of the present invention provides a method for manufacturing a double-sided display panel.
  • the method for manufacturing a double-sided display panel includes:
  • the first glass substrate is a glass substrate, or other transparent materials, and the material of the substrate is polyimide.
  • a halftone mask is used. After the template exposes, develops and etches the ITO film layer and the metal film layer, the photoresist is peeled off to form a patterned first transparent electrode layer and a light shielding layer.
  • the array substrate includes at least two array switches, a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer, and buffers are sequentially formed on the light shielding layer.
  • layer, an active layer, a gate insulating layer, a gate electrode and an interlayer insulating layer, and a second transparent electrode layer is formed on the interlayer insulating layer.
  • a buffer layer is prepared on the light-shielding layer, an active layer is prepared on the buffer layer, and then a gate insulating layer material and a metal are sequentially coated on the active layer. material, and then patterning the gate insulating layer material and the metal material to form a gate insulating layer and a gate, and treating the parts of the active layer that are not covered by the gate insulating layer and the gate Part of the conductor treatment is carried out; the material of the active layer is indium gallium zinc oxide, and can also be other oxide materials.
  • an ITO film layer is sequentially coated on the interlayer insulating layer, and after a mask process is performed on the ITO film layer using a half-tone mask, an ITO film layer is formed on the interlayer insulating layer.
  • the second transparent electrode layer, the first transparent electrode layer and the second transparent electrode layer form a storage capacitor.
  • a mask process is used to make holes in the array substrate, and a first hole, a second hole, a fourth hole and a fifth hole are formed in the interlayer insulating layer.
  • a third opening and a sixth opening are formed between the interlayer insulating layer and the buffer layer, and a seventh opening is formed between the interlayer insulating layer and the buffer layer to expose part of the lining bottom; the first opening, the second opening and the third opening are correspondingly arranged in the area corresponding to the first array switch, the fourth opening, the fifth opening, the The sixth opening and the seventh opening are correspondingly arranged in the area corresponding to the second array switch; a first through hole, a second through hole, a fourth opening and a fifth through hole are formed in the interlayer insulating layer.
  • opening holes to expose the surfaces of both ends of the active layer forming a third opening and a sixth opening between the interlayer insulating layer and the buffer layer to expose part of the surface of the light shielding layer;
  • a seventh opening is formed between the interlayer insulating layer, the buffer layer and the substrate, and the seventh opening penetrates the interlayer insulating layer and the buffer layer to expose part of the surface of the substrate .
  • an array substrate is formed on the light shielding layer 32 , and the array substrate includes at least two array switches, a buffer layer, an active layer 41 , and a gate insulating layer 42 . , the gate 43 and the interlayer insulating layer 4 .
  • a first metal layer is formed on the array substrate, the first metal layer is patterned, a first source electrode is formed in the first opening, the second opening and the third opening are A first drain is formed at the fourth opening, a second source is formed at the fourth opening, and a second drain is formed at the fifth opening, the sixth opening and the seventh opening;
  • the seventh opening exposes an end of the second drain away from the insulating layer, and the second anode is electrically connected to the second drain of the second array switch through the seventh opening.
  • the insulating layer includes a passivation layer and a planarization layer.
  • the insulating layer includes a passivation layer and a planarization layer.
  • the passivation layer 5 and the planarization layer 6 are formed on the electrode layer 45 .
  • the passivation layer 5 and the planarization layer 6 are provided with via holes to expose the electrode (source or drain) of the electrode layer 45; then the passivation layer 5 and the planarization layer
  • the ITO film is coated on the chemical layer 6, the same masking process is performed on the ITO film by using a halftone mask, a first anode 61 is formed over the storage capacitor, and a first anode 61 is formed over the first anode 61.
  • the first anode 61 is correspondingly disposed on one side of the first drain 452 , and the first anode 61 is electrically connected to the first drain 452 .
  • a mask is used before forming the second anode 62 , the second pixel definition layer 7b , the second light-emitting unit 7b1 and the second encapsulation layer 82 on the second surface of the substrate 2 .
  • a process is performed on the second surface of the substrate to form a second through hole 508 to expose an end of the second drain electrode away from the insulating layer, the second anode 62 passes through the seventh opening and The second through hole 508 is electrically connected to the second drain of the second array switch.
  • the first glass substrate 1 is peeled off, and the second anode 62 , the second pixel definition layer 7 b and the second anode 62 are formed on the second surface of the substrate 2 .
  • the second light-emitting unit 7b1 and the second encapsulation layer 82 are described above, and finally the second glass substrate 9 is peeled off.
  • the second anode 62 is correspondingly disposed on one side of the second drain 454 , and the second anode 62 is electrically connected to the second drain 454 .
  • an embodiment of the present invention provides a method for manufacturing a double-sided display panel.
  • a double-sided display panel that can display on the first side and display on the second side is formed.
  • the double-sided display panel provided by the embodiment of the present invention is controlled by a TFT array substrate, and the array substrate is designed with an odd-numbered row (or even-numbered row) Drain electrode signal on the other side through PI digging holes, and an odd-numbered row and an even-numbered row are used.
  • the embodiment of the present invention also provides a driving method of the double-sided display panel.
  • the double-sided display panel provided by the embodiment of the present invention is controlled by a TFT array substrate, and the array substrate is controlled by a TFT array substrate.
  • the odd-numbered rows (or even-numbered rows) of the drain electrode signal on one side are introduced into the anode design on the other side through the PI digging holes.
  • the odd-numbered rows and the even-numbered rows are used to control the signals displayed in the display area of the first side and the display area of the second side respectively. Please refer to Figure 9.
  • G1, G2, D1, and D2 are the driving circuits of the first side
  • G1', G2', D1', and D2' are the driving circuits of the second side, respectively driving two sides for display.

Abstract

一种双面显示面板及制备方法，双面显示面板通过薄膜晶体管阵列基板控制，阵列基板通过一侧奇数行或偶数行漏极电信号通过挖孔导入另一侧阳极设计，采用奇数行和偶数行分别控制第一面显示区域和第二面显示区域显示的信号，实现双面显示。

Description

一种双面显示面板及制备方法
本申请要求于2020年12月4日提交中国专利局、申请号为202011410391.6、发明名称为“一种双面显示面板及制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及显示面板领域，尤其涉及一种双面显示面板及制备方法。
 背景技术
目前，双面显示屏在商品陈列、电子公告牌、高端展览等领域具有广阔的应用前景，当前双面显示通常使用的是两块TFT-LCD基板背对背贴合，通过两块面板达到双面显示，在对现有技术的研究和实践过程中，本发明实施例的发明人发现，由于两块显示面板均需要单独背光，且出于散热的设计需求，制作的双面显示屏幕将会具有较大的厚度从而占用空间影响观感，且工艺复杂良率低，制作成本高；并且由于使用两块TFT-LCD基板背对背贴合，会严重影响产品轻薄效果。
 技术问题
本发明实施例提供一种双面显示面板及制备方法，以解决由于使用两块TFT-LCD基板背对背贴合的设计会增加整机厚度，会严重影响产品轻薄效果的问题。
 技术解决方案
本发明实施例提供一种双面显示面板及制备方法，通过本发明实施例提供的双面显示面板制备方法，可以降低制作成本且实现激光显示器的轻薄化。
第一方面，本发明实施例提供了一种双面显示面板，包括：
衬底，所述衬底包括相对设置的第一表面和第二表面；
阵列基板，所述阵列基板设置在所述衬底的第一表面，其中，所述阵列基板设有至少两个阵列开关；
第一发光单元和第二发光单元，分别设置于所述衬底的第一表面和第二表面，部分所述阵列开关与所述第一发光单元电连接，用于控制所述第一发光单元发光，另一部分所述阵列开关与所述第二发光单元电连接，用于控制所述第二发光单元发光，以实现双面显示。
在所述双面显示面板中，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，其中，所述第一阵列开关的第一漏极与所述第一发光单元的第一阳极电连接，所述第二阵列开关的第二漏极与所述第二发光单元的第二阳极电连接。
在所述双面显示面板中，所述第二漏极延伸至所述衬底的第二表面，以与所述第二阳极电连接。
在所述双面显示面板中，所述第二漏极延伸至所述衬底的第一表面，所述第二发光单元的第二阳极延伸至所述衬底的第一表面，以实现与所述第二漏极电连接。
在所述双面显示面板中，所述第一阵列开关和所述第二阵列开关交替设置。
在所述双面显示面板中，所述衬底的第一表面设置有第一透明电极层和遮光层。
在所述双面显示面板中，所述阵列基板形成在所述第一透明电极层和所述遮光层上方。
在所述双面显示面板中，所述阵列基板还包括缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，所述缓冲层形成在所述第一透明电极层和所述遮光层上方，所述缓冲层覆盖所述第一透明电极层和所述遮光层，所述有源层和第二透明电极层间隔形成在所述缓冲层远离所述衬底基板的一侧，所述栅极绝缘层形成在所述有源层远离所述缓冲层的一侧，所述栅极形成在所述栅极绝缘层远离所述有源层的一侧，所述层间绝缘层覆盖所述缓冲层、所述有源层、所述第二透明电极层、所述栅极绝缘层和所述栅极。
在所述双面显示面板中，所述双面显示面板还包括绝缘层，形成在所述阵列基板远离所述第一透明电极层和所述遮光层一侧。
在所述双面显示面板中，所述绝缘层包括钝化层和平坦化层，所述钝化层形成在所述层间绝缘层远离所述缓冲层一侧，所述钝化层覆盖所述层间绝缘层和所述第一电极、所述第二电极、所述第三电极和所述第四电极，所述平坦化层形成在所述钝化层远离所述层间绝缘层一侧。
第二方面，本发明实施例提供了一种双面显示面板制备方法，包括：
提供一衬底，在所述衬底第一表面形成阵列基板；
在所述阵列基板上形成至少两个阵列开关；
在所述阵列基板远离所述的第一表面上形成第一发光单元，在所述衬底的与所述第一表面相对设置的第二表面上形成第二发光单元，其中，部分所述阵列开关与所述第一发光单元电连接，用于控制所述第一发光单元发光，另一部分所述阵列开关与所述第二发光单元电连接，用于控制所述第二发光单元发光，以实现双面显示。
在双面显示面板制备方法中，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，其中，所述第一阵列开关包括第一源极与第一漏极，所述第一漏极与所述第一发光单元的第一阳极电连接，所述第二阵列开关包括第二源极和第二漏极，所述第二漏极与所述第二发光单元的第二阳极电连接。
在双面显示面板制备方法中，所述第二漏极延伸至所述衬底的第二表面，以与所述第二阳极电连接。
在双面显示面板制备方法中，所述第二漏极延伸至所述衬底的第一表面，所述第二发光单元的第二阳极延伸至所述衬底的第一表面，以实现与所述第二漏极电连接。
在双面显示面板制备方法中，所述第一阵列开关和所述第二阵列开关交替设置。
在双面显示面板制备方法中，包括：
在所述衬底的第一表面形成第一透明电极层和遮光层。
在双面显示面板制备方法中，包括：
在所述第一透明电极层和所述遮光层上方形成所述阵列基板。
在双面显示面板制备方法中，所述阵列基板还包括缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，包括：
在所述第一透明电极层和所述遮光层上方形成所述缓冲层，所述缓冲层覆盖所述第一透明电极层和所述遮光层，所述有源层和第二透明电极层间隔形成在所述缓冲层远离所述衬底基板的一侧，所述栅极绝缘层形成在所述有源层远离所述缓冲层的一侧，所述栅极形成在所述栅极绝缘层远离所述有源层的一侧，所述层间绝缘层覆盖所述缓冲层、所述有源层、所述第二透明电极层、所述栅极绝缘层和所述栅极。
在双面显示面板制备方法中，所述双面显示面板还包括绝缘层，包括：
在所述阵列基板远离所述第一透明电极层和所述遮光层一侧形成所述绝缘层。
在双面显示面板制备方法中，所述绝缘层包括钝化层和平坦化层，包括：
所述钝化层形成在所述层间绝缘层远离所述缓冲层一侧，所述钝化层覆盖所述层间绝缘层和所述第一电极、所述第二电极、所述第三电极和所述第四电极，所述平坦化层形成在所述钝化层远离所述层间绝缘层一侧。
 有益效果
本发明实施例提供一种双面显示面板及制备方法，本发明实施例通过提供一种双面显示面板，所述双面显示面板包括：衬底，所述衬底包括相对设置的第一表面和第二表面；阵列基板，所述阵列基板设置在所述衬底的第一表面，其中，所述阵列基板设有至少两个阵列开关；第一发光单元和第二发光单元，分别设置于所述衬底的第一表面和第二表面，部分所述阵列开关与所述第一发光单元电连接，用于控制所述第一发光单元发光；本发明实施例提供的双面显示面板，在同一制成下制成可以分别提供给第一发光单元与第二发光单元发光的至少两个阵列开关，可以降低制作成本，且使得所述双面显示面板不会增加其面板厚度以实现超薄显示，实现双面显示面板轻薄化。
 附图说明
图1为本发明实施例提供的双面显示面板的第一种结构示意图。
图2为本发明实施例提供的双面显示面板的第二种结构示意图。
图3为本发明实施例提供的双面显示面板的第三种结构示意图。
图4为本发明实施例提供的双面显示面板的第四种结构示意图。
图5为本发明实施例提供的双面显示面板的第五种结构示意图。
图6为本发明实施例提供的双面显示面板制备方法的第一种流程示意图。
图7为本发明实施例提供的双面显示面板制备方法的第二种流程示意图。
图8为本发明实施例提供的双面显示面板制备方法的第三种流程示意图。
图9为本发明实施例提供的驱动电路的一种结构示意图。
附图标记说明：
1-第一玻璃基板；2-衬底；3-缓冲层；31-第一透明电极层；32-遮光层；4-层间绝缘层；41-有源层；42-栅极绝缘层；43-栅极；44-第二透明电极层；45-电极层；451-第一源极、452-第一漏极；453-第二源极；454-第二漏极；5-钝化层；501-第一开孔；502-第二开孔；503-第三开孔；504-第四开孔；505-第五开孔；506-第六开孔；507-第七开孔；508-第二通孔；509-第一通孔；6-平坦化层；61-第一阳极；62-第二阳极；7a-第一像素定义层；7a1-第一发光单元；7b-第二像素定义层；7b1-第二发光单元；81-第一封装层；82-第二封装层；9-第二玻璃基板。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多所述特征。在本发明的描述中，“”的含义是两个或两个以上，除非另有明确具体的限定。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
本发明实施例提供一种双面显示面板及制备方法，该显示面板可以配合终端使用，如智能手机、平板电脑、笔记本电脑或个人计算机等。以下对该双面显示面板及制备方法进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
下面结合附图和具体实施方式对本发明予以详细描述，请参阅图1至图9。
本发明实施例一提供一种双面显示面板，所述双面显示面板包括衬底，所述衬底包括相对设置的第一表面和第二表面；阵列基板，所述阵列基板设置在所述衬底的第一表面，其中，所述阵列基板设有至少两个阵列开关。还包括第一发光单元和第二发光单元，分别设置于所述衬底的第一表面和第二表面，部分所述阵列开关与所述第一发光单元电连接，用于控制所述第一发光单元发光，另一部分所述阵列开关与所述第二发光单元电连接，用于控制所述第二发光单元发光，以实现双面显示。本发明实施例提供的双面显示面板，解决了若达成双面显示则需要单独制作两面板的背光，从而厚度大占用空间影响观感，且工艺复杂良率低，制作成本高的技术问题，本发明实施例提供的双面显示面板可以包括以下技术效果：在同一制成下制成可以分别提供给第一发光单元与第二发光单元发光的至少两个阵列开关，可以降低制作成本，且使得所述双面显示面板不会增加其面板厚度以实现超薄显示，实现双面显示面板轻薄化。
请一并参阅图1、图2和图3，本发明实施例二提供一种双面显示面板，所述双面显示面板包括衬底2，所述衬底2包括相对设置的第一表面和第二表面；阵列基板，所述阵列基板设置在所述衬底2的第一表面，其中，所述阵列基板设有至少两个阵列开关；第一发光单元7a1和第二发光单元7b1，分别设置于所述衬底2的第一表面和第二表面，部分所述阵列开关与所述第一发光单元7a1电连接，用于控制所述第一发光单元7a1发光，另一部分所述阵列开关与所述第二发光单元7b1电连接，用于控制所述第二发光单元7b1发光，以实现双面显示。所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，其中，所述第一阵列开关的第一漏极452与所述第一发光单元7a1的第一阳极电连接，所述第二阵列开关的第二漏极454与所述第二发光单元7b1的第二阳极电连接。所述第二漏极454延伸至所述衬底2的第二表面，以与所述第二阳极电连接。在本实施例中，通过在阵列基板设有至少两个阵列开关，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，在同一制成下制成可以分别提供给第一发光单元与第二发光单元发光的至少两个阵列开关，进而可以降低制作成本，且使得所述双面显示面板不会增加其面板厚度以实现超薄显示，从而实现双面显示面板轻薄化。
具体的，在本发明实施例中，所述第一发光单元7a1位于第一发光单元7a1，所述第一阳极位于第一阳极层；所述第二发光单元7b1位于第二发光单元7b1，所述第二阳极位于第二阳极层。
请参阅图3，具体的，在本发明实施例中，所述双面显示面板包括：
衬底2，所述衬底2包括相对设置的第一表面和第二表面；第一透明电极层31和遮光层32，设置在所述衬底2的第一表面，所述第一透明电极层31与所述遮光层32间隔分布在所述衬底2第一表面；
阵列基板，形成在所述第一透明电极层31和所述遮光层32上方，阵列基板包括所述至少两个阵列开关；
绝缘层，形成在所述阵列基板远离所述第一透明电极层31和所述遮光层32一侧；
第一阳极61，形成在所述绝缘层中并用于与所述第一漏极452电性连接，所述第一阳极61通过所述绝缘层的第一通孔507与第一阵列开关的第一漏极452电性连接；
第一像素定义层7a，形成在所述绝缘层远离所述阵列基板的一侧；
第一发光单元7a1，形成在所述第一像素定义层7a中并用于与所述第一阳极61电性连接；
第一封装层81，形成在所述第一像素定义层7a远离所述绝缘层的一侧；
第二像素定义层7b，形成在所述衬底2的第二表面；
第二阳极62，形成在所述第二像素定义层7b中并用于与所述第二漏极454电性连接，所述第二阳极62通过开孔与第二阵列开关的第二漏极454电性连接；
第二发光单元7b1，形成在所述第二像素定义层7b中并用于与所述第二阳极62电性连接。
请参阅图3，具体的，在本发明实施例中，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，所述第一阵列开关包括第一源极451和第一漏极452，所述第二阵列开关包括第二源极453和第二漏极454。
请参阅图3，具体的，在本发明实施例中，所述阵列基板包括至少两个阵列开关、缓冲层、有源层41、栅极绝缘层42、栅极43以及层间绝缘层4，所述缓冲层形成在所述第一透明电极层31和所述遮光层32上方，所述缓冲层覆盖所述第一透明电极层31和所述遮光层32，所述有源层41和第二透明电极层44间隔形成在所述缓冲层远离所述衬底2的一侧，所述栅极绝缘层42形成在所述有源层41远离所述缓冲层的一侧，所述栅极43形成在所述栅极绝缘层42远离所述有源层41的一侧，所述层间绝缘层4覆盖所述缓冲层、所述有源层41、所述第二透明电极层44、所述栅极绝缘层42和所述栅极43。
请参阅图3，具体的，在本发明实施例中，所述开孔包括第一开孔501、第二开孔502、第三开孔503、第四开孔504、第五开孔505、第六开孔506和第七开孔507；所述第一开孔501、所述第二开孔502、所述第四开孔504和所述第五开孔505设置于所述层间绝缘层4，所述第三开孔503和所述第六开孔506设置于所述层间绝缘层4和所述缓冲层之间，所述第七开孔507设置于所述层间绝缘层4、所述缓冲层和所述衬底2之间。
请参阅图3，具体的，在本发明实施例中，所述第一开孔501、所述第二开孔502和所述第三开孔503位于所述第一阵列开关对应的区域，所述第四开孔504、所述第五开孔505、所述第六开孔506和所述第七开孔507位于所述第二阵列开关对应的区域；所述第一源极451通过所述第一开孔501与所述第二透明电极层44电性连接，所述第一漏极452通过所述第二开孔502、所述第三开孔503分别与所述第一透明电极层31、所述第二透明电极层44电性连接，所述第二源极453通过所述第四开孔504与所述第二透明电极层44电性连接，所述第二漏极454通过所述第五开孔505、所述第六开孔506分别与所述第一透明电极层31、所述第二透明电极层44电性连接。
具体的，在本发明实施例中，所述第七开孔507用于暴露所述第二漏极454远离所述绝缘层的一端，所述第二阳极62通过所述第七开孔507与所述第二阵列开关的第二漏极454电性连接。
具体的，在本发明实施例中，所述绝缘层包括钝化层5和平坦化层6，所述钝化层5形成在所述层间绝缘层4远离所述缓冲层一侧，所述钝化层5覆盖所述层间绝缘层4和所述第一源极451、所述第一漏极452、所述第二源极453和所述第二漏极454，所述平坦化层6形成在所述钝化层5远离所述层间绝缘层4一侧。
可选的，在本发明实施例中，所述阵列开关分数量为多个，所述阵列开关一半与所述第一发光单元7a1连接以实现第一面显示区域进行显示，所述阵列开关另一半与第二发光单元7b1连接以实现第二面显示区域进行显示。
可选的，在本发明实施例中，所述阵列开关分数量为多个，所述阵列开关分包括所述第一阵列开关和所述第二阵列开关，所述第一阵列开关与所述第一发光单元7a1连接，所述第二阵列开关与第二发光单元7b1连接，所述第一阵列开关和所述第二阵列开关交替设置在阵列基板。
请一并参阅图3、图4和图5，本发明实施例三提供一种双面显示面板，所述双面显示面板包括衬底2，所述衬底2包括相对设置的第一表面和第二表面；阵列基板，所述阵列基板设置在所述衬底2的第一表面，其中，所述阵列基板设有至少两个阵列开关；第一发光单元7a1和第二发光单元7b1，分别设置于所述衬底2的第一表面和第二表面，部分所述阵列开关与所述第一发光单元7a1电连接，用于控制所述第一发光单元7a1发光，另一部分所述阵列开关与所述第二发光单元7b1电连接，用于控制所述第二发光单元7b1发光，以实现双面显示。所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，其中，所述第一阵列开关的第一漏极452与所述第一发光单元7a1的第一阳极电连接，所述第二阵列开关的第二漏极454与所述第二发光单元7b1的第二阳极电连接。所述第二漏极454延伸至所述衬底2的第一表面，所述第二发光单元7b1的第二阳极延伸至所述衬底2的第一表面，以实现与所述第二漏极454电连接。
请一并参阅图3、图4和图5，具体的，在本发明实施例中，所述双面显示面板包括：
衬底2，所述衬底2包括相对设置的第一表面和第二表面；第一透明电极层31和遮光层32，设置在所述衬底2的第一表面，所述第一透明电极层31与所述遮光层32间隔分布在所述衬底2第一表面；
阵列基板，形成在所述第一透明电极层31和所述遮光层32上方，阵列基板包括所述至少两个阵列开关；
绝缘层，形成在所述阵列基板远离所述第一透明电极层31和所述遮光层32一侧；
第一阳极61，形成在所述绝缘层中并用于与所述第一漏极452电性连接，所述第一阳极61通过所述绝缘层的第一通孔507与第一阵列开关的第一漏极452电性连接；
第一像素定义层7a，形成在所述绝缘层远离所述阵列基板的一侧；
第一发光单元7a1，形成在所述第一像素定义层7a中并用于与所述第一阳极61电性连接；
第一封装层81，形成在所述第一像素定义层7a远离所述绝缘层的一侧；
第二像素定义层7b，形成在所述衬底2的第二表面；
第二阳极62，形成在所述第二像素定义层7b中并用于与所述第二漏极454电性连接，所述第二阳极62通过开孔与第二阵列开关的第二漏极454电性连接；
第二发光单元7b1，形成在所述第二像素定义层7b中并用于与所述第二阳极62电性连接。
请一并参阅图3、图4和图5，具体的，在本发明实施例中，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，所述第一阵列开关包括第一源极451和第一漏极452，所述第二整列开关包括第二源极453和第二漏极454。
请一并参阅图3、图4和图5，具体的，在本发明实施例中，所述阵列基板包括至少两个阵列开关、缓冲层、有源层41、栅极绝缘层42、栅极43以及层间绝缘层4，所述缓冲层形成在所述第一透明电极层31和所述遮光层32上方，所述缓冲层覆盖所述第一透明电极层31和所述遮光层32，所述有源层41和第二透明电极层44间隔形成在所述缓冲层远离所述衬底2的一侧，所述栅极绝缘层42形成在所述有源层41远离所述缓冲层的一侧，所述栅极43形成在所述栅极绝缘层42远离所述有源层41的一侧，所述层间绝缘层4覆盖所述缓冲层、所述有源层41、所述第二透明电极层44、所述栅极绝缘层42和所述栅极43。
请一并参阅图3、图4和图5，具体的，在本发明实施例中，所述开孔包括第一开孔501、第二开孔502、第三开孔503、第四开孔504、第五开孔505、第六开孔506和第七开孔507；所述第一开孔501、所述第二开孔502、所述第四开孔504和所述第五开孔505设置于所述层间绝缘层4，所述第三开孔503和所述第六开孔506设置于所述层间绝缘层4和所述缓冲层之间，所述第七开孔507设置于所述层间绝缘层4和所述缓冲层之间。
请一并参阅图3、图4和图5，具体的，在本发明实施例中，所述第一开孔501、所述第二开孔502和所述第三开孔503位于所述第一阵列开关对应的区域，所述第四开孔504、所述第五开孔505、所述第六开孔506和所述第七开孔507位于所述第二阵列开关对应的区域；所述第一源极451通过所述第一开孔501与所述第二透明电极层44电性连接，所述第一漏极452通过所述第二开孔502、所述第三开孔503分别与所述第一透明电极层31、所述第二透明电极层44电性连接，所述第二源极453通过所述第四开孔504与所述第二透明电极层44电性连接，所述第二漏极454通过所述第五开孔505、所述第六开孔506分别与所述第一透明电极层31、所述第二透明电极层44电性连接。
具体的，在本发明实施例中，所述衬底2的第二表面设置有第二通孔，以暴露所述第二漏极454远离所述绝缘层的一端，所述第二阳极62通过所述第七开孔507和所述第二通孔与所述第二阵列开关对应的区域的第二漏极454电性连接。
具体的，在本发明实施例中，所述绝缘层包括钝化层5和平坦化层6，所述钝化层5形成在所述层间绝缘层4远离所述缓冲层一侧，所述钝化层5覆盖所述层间绝缘层4和所述第一源极451、所述第一漏极452、所述第二源极453和所述第二漏极454，所述平坦化层6形成在所述钝化层5远离所述层间绝缘层4一侧。
可选的，在本发明实施例中，所述阵列开关分数量为多个，所述阵列开关一半与所述第一发光单元7a1连接以实现第一面显示区域进行显示，所述阵列开关另一半与第二发光单元7b1连接以实现第二面显示区域进行显示。
可选的，在本发明实施例中，所述阵列开关分数量为多个，所述阵列开关分包括所述第一阵列开关和所述第二阵列开关，所述第一阵列开关与所述第一发光单元7a1连接，所述第二阵列开关与第二发光单元7b1连接，所述第一阵列开关和所述第二阵列开关交替设置在阵列基板。
综上所述，本发明实施例提供一种显示面板，本发明实施例提供的双面显示面板通过一块TFT阵列基板控制，阵列基板通过一侧奇数行（或偶数行）漏极电极信号通过PI挖孔导入另一侧阳极设计，采用奇数行和偶数行分别控制第一面显示区域和第二面显示区域显示的信号；采用本发明实施例形成双面显示面板，降低制作成本，且使得所述双面显示面板不会增加其面板厚度以实现超薄显示，实现双面显示面板轻薄化。
请参阅图6，本发明实施例四提供一种双面显示面板制备方法，所述双面显示面板制备方法包括：
S101、提供一衬底，在所述衬底第一表面形成阵列基板；
S102、在所述阵列基板上形成至少两个阵列开关；
S103、在所述阵列基板远离所述的第一表面上形成第一发光单元，在所述衬底的与所述第一表面相对设置的第二表面上形成第二发光单元，其中，部分所述阵列开关与所述第一发光单元电连接，用于控制所述第一发光单元发光，另一部分所述阵列开关与所述第二发光单元电连接，用于控制所述第二发光单元发光，以实现双面显示。
具体的，在本发明实施例中，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，其中，所述第一阵列开关的第一漏极与所述第一发光单元的第一阳极电连接，所述第二阵列开关的第二漏极与所述第二发光单元的第二阳极电连接。
具体的，在本发明实施例中，所述第二漏极延伸至所述衬底的第二表面，以与所述第二阳极电连接。
具体的，在本发明实施例中，所述第二漏极延伸至所述衬底的第一表面，所述第二发光单元的第二阳极延伸至所述衬底的第一表面，以实现与所述第二漏极电连接
具体的，在本发明实施例中，所述第一阵列开关和所述第二阵列开关交替设置。
请参阅图7，本发明实施例五提供一种双面显示面板制备方法，所述双面显示面板制备方法包括：
S201、提供一第一玻璃基板，在所述第一玻璃基板上形成一衬底，所述衬底定义依次交替分布的第一面发光区和第二面发光区；
具体的，在本发明实施例中，所述第一玻璃基板为玻璃基板，也可为其他的透明材料，所述衬底的材质为聚酰亚胺。
S202、在所述衬底的第一表面上形成第一透明电极层和遮光层；
具体的，在本发明实施例中，通过在所述衬底的第一表面上依次涂布ITO膜层和金属膜层，再在所述金属膜层上涂布光刻胶，利用半色调掩模板对所述ITO膜层和金属膜层进行曝光、显影以及刻蚀后，剥离所述光刻胶，形成图案化的第一透明电极层和遮光层。
S203、在所述遮光层上形成阵列基板，其中，所述阵列基板包括形成在所述第一面发光区的第一阵列开关，以及形成在所述第二面发光区的第二阵列开关；
具体的，在本发明实施例中，所述阵列基板包括至少两个阵列开关、缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，在所述遮光层上依次形成缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，在所述层间绝缘层形成第二透明电极层。
具体的，在本发明实施例中，在所述遮光层上制备缓冲层，再在所述缓冲层上制备有源层，之后在所述有源层上依次涂布栅极绝缘层材料和金属材料，之后对所述栅极绝缘层材料和金属材料进行图案化处理，形成栅极绝缘层和栅极，对所述有源层的未被所述栅极绝缘层和所述栅极覆盖的部分进行导体化处理；所述有源层的材料为铟镓锌氧化物，也可为其他氧化物材料。
具体的，在本发明实施例中，在所述层间绝缘层上依次涂布ITO膜层，利用半色调掩模板对所述ITO膜层进行光罩制程后，在所述层间绝缘层形成第二透明电极层，所述第一透明电极层和所述第二透明电极层形成存储电容。
S204、对所述阵列基板进行开孔，在所述阵列基板上形成第一金属层，并对所述第一金属层进行图案化，形成第一阵列开关和第二阵列开关，第一阵列开关包括第一源极和第一漏极，第二阵列开关包括第二源极和第二漏极；在所述第一金属层上依次形成绝缘层，其中，所述绝缘层覆盖所述第一阵列开关和所述第二阵列开关；
具体的，在本发明实施例中，采用掩膜工艺对所述层间绝缘层与所述缓冲层进行开孔，采用掩膜工艺同时对阵列基板进行开孔，在所述层间绝缘层形成第一开孔、第二开孔、第四开孔和第五开孔，在所述层间绝缘层和所述缓冲层之间形成第三开孔和第六开孔，在所述层间绝缘层、所述缓冲层和所述衬底之间形成第七开孔；所述第一开孔、所述第二开孔和所述第三开孔对应设置在所述第一阵列开关对应的区域，所述第四开孔、所述第五开孔、所述第六开孔和所述第七开孔对应设置在所述第二阵列开关对应的区域；在所述层间绝缘层形成第一开孔、第二开孔、第四开孔和第五开孔以露出所述有源层两端的表面，在所述层间绝缘层和所述缓冲层之间形成第三开孔和第六开孔以露出所述遮光层的部分表面；在所述层间绝缘层、所述缓冲层和所述衬底之间形成第七开孔，所述第七开孔贯穿所述层间绝缘层、所述缓冲层和所述衬底，以露出所述第一玻璃基板的部分表面。
请参阅图1，具体的，在本发明实施例中，在所述遮光层32上形成阵列基板，所述阵列基板包括至少两个阵列开关、缓冲层、有源层41、栅极绝缘层42、栅极43以及层间绝缘层4。在所述阵列基板上形成第一金属层，并对所述第一金属层进行图案化，在所述第一开孔形成第一源极，所述第二开孔与所述第三开孔处形成第一漏极，在所述第四开孔处形成第二源极，在所述第五开孔、所述第六开孔和所述第七开孔处形成第二漏极；所述第七开孔暴露所述第二漏极远离所述绝缘层的一端，所述第二阳极通过所述第七开孔与第二漏极电性连接。具体的，在本发明实施例中，所述绝缘层包括钝化层、平坦化层。
S205、在所述绝缘层背离所述第一金属层的表面形成第一阳极、第一像素定义层、第一发光单元和第一封装层，所述封装层一侧设置第二玻璃基板；
请参阅图2，具体的，在本发明实施例中，所述绝缘层包括钝化层、平坦化层，首先在所述电极层45上形成所述钝化层5和所述平坦化层6，所述钝化层5和所述平坦化层6上设置有过孔，用以露出所述电极层45的电极（源极或漏极）；然后在所述钝化层5和所述平坦化层6上涂布ITO膜层，利用半色调掩模板对所述ITO膜层进行同一光罩制程，在所述存储电容上方形成第一阳极61，以及在所述第一阳极61上方形成所述第一像素定义层7a和所述第一发光单元7a1和第一封装层81，最后在所述第一封装层81一侧设置第二玻璃基板9，所述第二玻璃基板9用于后续制成中。
具体的，在本发明实施例中，所述第一阳极61对应设置在所述第一漏极452一侧，所述第一阳极61与所述第一漏极452电性连接。
S206、剥离第一玻璃基板，在所述衬底的第二表面上形成第二阳极、第二像素定义层、第二发光单元和第二封装层；
请参阅图3，具体的，在本发明实施例中，剥离第一玻璃基板1，在所述衬底2的第二表面形成所述第二阳极62、所述第二像素定义层7b和所述第二发光单元7b1和第二封装层82，最后剥离第二玻璃基板9。
具体的，在本发明实施例中，所述第二阳极62对应设置在所述第二漏极454一侧，所述第二阳极62与所述第二漏极454电性连接。
请参阅图8，本发明实施例六提供一种双面显示面板制备方法，所述双面显示面板制备方法包括：
S301、提供一第一玻璃基板，在所述第一玻璃基板上形成一衬底，所述衬底定义依次交替分布的第一面发光区和第二面发光区；
具体的，在本发明实施例中，所述第一玻璃基板为玻璃基板，也可为其他的透明材料，所述衬底的材质为聚酰亚胺。
S302、在所述衬底的第一表面上形成第一透明电极层和遮光层；
具体的，在本发明实施例中，通过在所述衬底的第一表面上依次涂布ITO膜层和金属膜层，再在所述金属膜层上涂布光刻胶，利用半色调掩模板对所述ITO膜层和金属膜层进行曝光、显影以及刻蚀后，剥离所述光刻胶，形成图案化的第一透明电极层和遮光层。
S303、在所述遮光层上形成阵列基板；
具体的，在本发明实施例中，所述阵列基板包括至少两个阵列开关、缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，在所述遮光层上依次形成缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，在所述层间绝缘层形成第二透明电极层。
具体的，在本发明实施例中，在所述遮光层上制备缓冲层，再在所述缓冲层上制备有源层，之后在所述有源层上依次涂布栅极绝缘层材料和金属材料，之后对所述栅极绝缘层材料和金属材料进行图案化处理，形成栅极绝缘层和栅极，对所述有源层的未被所述栅极绝缘层和所述栅极覆盖的部分进行导体化处理；所述有源层的材料为铟镓锌氧化物，也可为其他氧化物材料。
具体的，在本发明实施例中，在所述层间绝缘层上依次涂布ITO膜层，利用半色调掩模板对所述ITO膜层进行光罩制程后，在所述层间绝缘层形成第二透明电极层，所述第一透明电极层和所述第二透明电极层形成存储电容。
S304、对所述阵列基板进行开孔，在所述阵列基板上形成第一金属层，并对所述第一金属层进行图案化，形成第一阵列开关和第二阵列开关，第一阵列开关包括第一源极和第一漏极，第二阵列开关包括第二源极和第二漏极；在所述第一金属层上依次形成绝缘层，其中，所述绝缘层覆盖所述第一阵列开关和所述第二阵列开关；
具体的，在本发明实施例中，采用掩膜工艺对阵列基板进行开孔，在所述层间绝缘层形成第一开孔、第二开孔、第四开孔和第五开孔，在所述层间绝缘层和所述缓冲层之间形成第三开孔和第六开孔，在所述层间绝缘层和所述缓冲层之间形成第七开孔，以暴露部分所述衬底；所述第一开孔、所述第二开孔和所述第三开孔对应设置在所述第一阵列开关对应的区域，所述第四开孔、所述第五开孔、所述第六开孔和所述第七开孔对应设置在所述第二阵列开关对应的区域；在所述层间绝缘层形成第一通孔、第二通孔、第四开孔和第五开孔以露出所述有源层两端的表面，在所述层间绝缘层和所述缓冲层之间形成第三开孔和第六开孔以露出所述遮光层的部分表面；在所述层间绝缘层、所述缓冲层和所述衬底之间形成第七开孔，所述第七开孔贯穿所述层间绝缘层和所述缓冲层，以露出所述衬底的部分表面。
请参阅图4，具体的，在本发明实施例中，在所述遮光层32上形成阵列基板，所述阵列基板包括至少两个阵列开关、缓冲层、有源层41、栅极绝缘层42、栅极43以及层间绝缘层4。在所述阵列基板上形成第一金属层，并对所述第一金属层进行图案化，在所述第一开孔形成第一源极，所述第二开孔与所述第三开孔处形成第一漏极，在所述第四开孔处形成第二源极，在所述第五开孔、所述第六开孔和所述第七开孔处形成第二漏极；所述第七开孔暴露所述第二漏极远离所述绝缘层的一端，所述第二阳极通过所述第七开孔与所述第二阵列开关的第二漏极电性连接。具体的，在本发明实施例中，所述绝缘层包括钝化层、平坦化层。
S305、在所述绝缘层背离所述第一金属层的表面形成第一阳极、第一像素定义层、第一发光单元和第一封装层，所述封装层一侧设置第二玻璃基板；
请参阅图5，具体的，在本发明实施例中，所述绝缘层包括钝化层、平坦化层，首先在所述电极层45上形成所述钝化层5和所述平坦化层6，所述钝化层5和所述平坦化层6上设置有过孔，用以露出所述电极层45的电极（源极或漏极）；然后在所述钝化层5和所述平坦化层6上涂布ITO膜层，利用半色调掩模板对所述ITO膜层进行同一光罩制程，在所述存储电容上方形成第一阳极61，以及在所述第一阳极61上方形成所述第一像素定义层7a和所述第一发光单元7a1和第一封装层81，最后在所述第一封装层81一侧设置第二玻璃基板9，所述第二玻璃基板9用于后续制成中。
具体的，在本发明实施例中，所述第一阳极61对应设置在所述第一漏极452一侧，所述第一阳极61与所述第一漏极452电性连接。
S306、剥离第一玻璃基板，在所述衬底的第二表面进行开孔；
具体的，在本发明实施例中，在所述衬底2的第二表面上形成第二阳极62、第二像素定义层7b、第二发光单元7b1和第二封装层82之前，采用掩膜工艺在所述衬底的第二表面进行开孔形成第二通孔508，以暴露所述第二漏极远离所述绝缘层的一端，所述第二阳极62通过所述第七开孔和所述第二通孔508与所述第二阵列开关的第二漏极电性连接。
S307、在所述衬底的第二表面上形成第二阳极、第二像素定义层、第二发光单元和第二封装层；
请参阅图3，具体的，在本发明实施例中，剥离第一玻璃基板1，在所述衬底2的第二表面形成所述第二阳极62、所述第二像素定义层7b和所述第二发光单元7b1和第二封装层82，最后剥离第二玻璃基板9。
具体的，在本发明实施例中，所述第二阳极62对应设置在所述第二漏极454一侧，所述第二阳极62与所述第二漏极454电性连接。
综上所述，本发明实施例提供一种双面显示面板制备方法，通过本发明实施例提供的双面显示面板制备方法，形成可以用第一面显示和第二面显示的双面显示面板，本发明实施例提供的双面显示面板通过一块TFT阵列基板控制，阵列基板通过一侧奇数行（或偶数行）Drain电极信号通过PI挖孔导入另一侧阳极设计，采用奇数行和偶数行分别控制第一面显示区域和第二面显示区域显示的信号；采用本发明实施例形成双面显示面板，降低制作成本，且使得所述双面显示面板不会增加其面板厚度以实现超薄显示，实现双面显示面板轻薄化。
以上对本发明实施例中双面显示面板结构进行说明，本发明实施例还提供一种双面显示面板驱动方式，本发明实施例提供的双面显示面板通过一块TFT阵列基板控制，阵列基板通过一侧奇数行（或偶数行）Drain电极信号通过PI挖孔导入另一侧阳极设计，采用奇数行和偶数行分别控制第一面显示区域和第二面显示区域显示的信号，请参阅图9，具体的，在本发明实施例中，G1、G2、D1和D2为第一面的驱动电路，G1'、G2'、D1'和D2'为第二面的驱动电路，分别驱动两侧进行显示。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。上述所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得所有其他实施例，除本发明实施例提到的与本发明实施例方案一致的此类设计，都属于本发明保护的范围。
以上对本发明实施例所提供的一种双面显示面板及基板制备方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (20)

  1. 一种双面显示面板，其中，包括：
    衬底，所述衬底包括相对设置的第一表面和第二表面；
    阵列基板，所述阵列基板设置在所述衬底的第一表面，其中，所述阵列基板设有至少两个阵列开关；
    第一发光单元和第二发光单元，分别设置于所述衬底的第一表面和第二表面，部分所述阵列开关与所述第一发光单元电连接，用于控制所述第一发光单元发光，另一部分所述阵列开关与所述第二发光单元电连接，用于控制所述第二发光单元发光，以实现双面显示。
  2. 根据权利要求1所述的双面显示面板，其中，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，其中，所述第一阵列开关的第一漏极与所述第一发光单元的第一阳极电连接，所述第二阵列开关的第二漏极与所述第二发光单元的第二阳极电连接。
  3. 根据权利要求2所述的双面显示面板，其中，所述第二漏极延伸至所述衬底的第二表面，以与所述第二阳极电连接。
  4. 根据权利要求2所述的双面显示面板，其中，所述第二漏极延伸至所述衬底的第一表面，所述第二发光单元的第二阳极延伸至所述衬底的第一表面，以实现与所述第二漏极电连接。
  5. 根据权利要求2所述的双面显示面板，其中，所述第一阵列开关和所述第二阵列开关交替设置。
  6. 根据权利要求1所述的双面显示面板，其中，所述衬底的第一表面设置有第一透明电极层和遮光层。
  7. 根据权利要求6所述的双面显示面板，其中，所述阵列基板形成在所述第一透明电极层和所述遮光层上方。
  8. 根据权利要求7所述的双面显示面板，其中，所述阵列基板还包括缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，所述缓冲层形成在所述第一透明电极层和所述遮光层上方，所述缓冲层覆盖所述第一透明电极层和所述遮光层，所述有源层和第二透明电极层间隔形成在所述缓冲层远离所述衬底基板的一侧，所述栅极绝缘层形成在所述有源层远离所述缓冲层的一侧，所述栅极形成在所述栅极绝缘层远离所述有源层的一侧，所述层间绝缘层覆盖所述缓冲层、所述有源层、所述第二透明电极层、所述栅极绝缘层和所述栅极。
  9. 根据权利要求6所述的双面显示面板，其中，所述双面显示面板还包括绝缘层，形成在所述阵列基板远离所述第一透明电极层和所述遮光层一侧。
  10. 根据权利要求6所述的双面显示面板，其中，所述绝缘层包括钝化层和平坦化层，所述钝化层形成在所述层间绝缘层远离所述缓冲层一侧，所述钝化层覆盖所述层间绝缘层和所述第一电极、所述第二电极、所述第三电极和所述第四电极，所述平坦化层形成在所述钝化层远离所述层间绝缘层一侧。
  11. 一种双面显示面板制备方法，其中，包括：
    提供一衬底，在所述衬底第一表面形成阵列基板；
    在所述阵列基板上形成至少两个阵列开关；
    在所述阵列基板远离所述的第一表面上形成第一发光单元，在所述衬底的与所述第一表面相对设置的第二表面上形成第二发光单元，其中，部分所述阵列开关与所述第一发光单元电连接，用于控制所述第一发光单元发光，另一部分所述阵列开关与所述第二发光单元电连接，用于控制所述第二发光单元发光，以实现双面显示。
  12. 根据权利要求11所述的双面显示面板制备方法，其中，所述至少两个阵列开关至少包括第一阵列开关和第二阵列开关，其中，所述第一阵列开关包括第一源极与第一漏极，所述第一漏极与所述第一发光单元的第一阳极电连接，所述第二阵列开关包括第二源极和第二漏极，所述第二漏极与所述第二发光单元的第二阳极电连接。
  13. 根据权利要求12所述的双面显示面板制备方法，其中，所述第二漏极延伸至所述衬底的第二表面，以与所述第二阳极电连接。
  14. 根据权利要求12所述的双面显示面板制备方法，其中，所述第二漏极延伸至所述衬底的第一表面，所述第二发光单元的第二阳极延伸至所述衬底的第一表面，以实现与所述第二漏极电连接。
  15. 根据权利要求12所述的双面显示面板制备方法，其中，所述第一阵列开关和所述第二阵列开关交替设置。
  16. 根据权利要求11所述的双面显示面板制备方法，其中，包括：
    在所述衬底的第一表面形成第一透明电极层和遮光层。
  17. 根据权利要求16所述的双面显示面板制备方法，其中，包括：
    在所述第一透明电极层和所述遮光层上方形成所述阵列基板。
  18. 根据权利要求17所述的双面显示面板制备方法，其中，所述阵列基板还包括缓冲层、有源层、栅极绝缘层、栅极以及层间绝缘层，包括：
    在所述第一透明电极层和所述遮光层上方形成所述缓冲层，所述缓冲层覆盖所述第一透明电极层和所述遮光层，所述有源层和第二透明电极层间隔形成在所述缓冲层远离所述衬底基板的一侧，所述栅极绝缘层形成在所述有源层远离所述缓冲层的一侧，所述栅极形成在所述栅极绝缘层远离所述有源层的一侧，所述层间绝缘层覆盖所述缓冲层、所述有源层、所述第二透明电极层、所述栅极绝缘层和所述栅极。
  19. 根据权利要求18所述的双面显示面板制备方法，其中，所述双面显示面板还包括绝缘层，包括：
    在所述阵列基板远离所述第一透明电极层和所述遮光层一侧形成所述绝缘层。
  20. 根据权利要求19所述的双面显示面板制备方法，其中，所述绝缘层包括钝化层和平坦化层，包括：
    所述钝化层形成在所述层间绝缘层远离所述缓冲层一侧，所述钝化层覆盖所述层间绝缘层和所述第一电极、所述第二电极、所述第三电极和所述第四电极，所述平坦化层形成在所述钝化层远离所述层间绝缘层一侧。
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