WO2022114078A1 - 配線基板及びプローブカード - Google Patents

配線基板及びプローブカード Download PDF

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Publication number
WO2022114078A1
WO2022114078A1 PCT/JP2021/043263 JP2021043263W WO2022114078A1 WO 2022114078 A1 WO2022114078 A1 WO 2022114078A1 JP 2021043263 W JP2021043263 W JP 2021043263W WO 2022114078 A1 WO2022114078 A1 WO 2022114078A1
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WIPO (PCT)
Prior art keywords
conductor
wiring
wiring board
wiring layer
linear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/043263
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English (en)
French (fr)
Japanese (ja)
Inventor
芳宏 戸田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to KR1020237017636A priority Critical patent/KR20230096042A/ko
Priority to JP2022565418A priority patent/JP7550238B2/ja
Priority to US18/038,639 priority patent/US20240027493A1/en
Publication of WO2022114078A1 publication Critical patent/WO2022114078A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0416—Connectors, terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass

Definitions

  • This disclosure relates to wiring boards and probe cards.
  • Japanese Unexamined Patent Publication No. 2011-29424 describes a configuration in which a wiring board having an electrode pad has a small piece portion that can be removed due to breakage or the like and a connecting conductor located in the small piece portion.
  • the connecting conductor is a conductor for supplying an electric current to the electrode pad when the electrode pad is electrolytically plated.
  • the connection conductor for electrolytic plating can be separated from the wiring conductor, and a desired wiring pattern can be obtained.
  • the wiring board according to the present disclosure is An insulating substrate with a first surface and Wiring conductors and connecting conductors located on the insulating substrate, A first wiring layer and a second wiring layer including a part of the wiring conductor, and A groove having an opening on the first surface and Equipped with The wiring conductor is With electrode pads
  • the first solid conductor included in the second wiring layer and Have The connecting conductor includes a first connecting conductor, a second connecting conductor, and an intersection of the first wiring layer that intersects the groove. The intersection is located between the first connecting conductor and the second connecting conductor.
  • the first connecting conductor is conducted to the electrode pad, the second connecting conductor is conducted to the first solid conductor, and the second connecting conductor is conducted to the first solid conductor.
  • the first wiring layer is located below the first surface or the first surface, and the second wiring layer is located below the first wiring layer.
  • the probe card according to this disclosure is With the above wiring board, With a plurality of probe pins connected to the wiring board, To prepare for.
  • FIG. 3 is a cross-sectional view taken along the line CC of the wiring board of FIG. It is a vertical sectional view which shows a part of the wiring board which concerns on Embodiment 2 of this disclosure. It is a top view of the 1st surface in the wiring board of FIG. It is sectional drawing in BB line of the wiring board of FIG. 3 is a cross-sectional view taken along the line CC of the wiring board of FIG.
  • FIG. 1 is a vertical cross-sectional view showing a part of the wiring board 10 according to the first embodiment of the present disclosure.
  • FIG. 2A is a plan view of the first surface S1 of the wiring board 10.
  • FIG. 2B is a cross-sectional view taken along the line BB of the wiring board 10.
  • FIG. 2C is a cross-sectional view taken along the line CC of the wiring board 10.
  • the wiring board 10 of the first embodiment includes an insulating substrate 11 having a first surface S1 and a second surface S2 on the opposite side of the first surface S1, and a wiring conductor 20 and a connecting conductor 30 located on the insulating substrate 11. Be prepared. In the figure, the wiring conductor 20 and the connecting conductor 30 have different hatchings, but the wiring conductor 20 and the connecting conductor 30 may have the same material and may be integrated.
  • the wiring board 10 further has a plurality of wiring layers (first wiring layer J1 to fourth wiring layer J4) inside.
  • the layer of the wiring conductor located on the first surface S1 and the second surface S2 may also be referred to as a wiring layer.
  • the insulating substrate 11 has a first insulating substrate 11A made of a ceramic material and a second insulating substrate 11B made of a resin material.
  • the first insulating substrate 11A and the second insulating substrate 11B are laminated.
  • the material of the insulating substrate 11 is not limited to the above example, and may be any material. Further, the insulating substrate 11 does not have to have a configuration in which two substrates made of two different materials are laminated, and may be a substrate made of a single material.
  • the wiring conductor 20 is a conductor that transmits an electric signal or a voltage.
  • the wiring conductor 20 includes a plurality of electrode pads 21 and 21t located on the first surface S1, a plurality of electrodes 25 located on the second surface S2, and a film conductor located on the first wiring layer J1 to the fourth wiring layer J4. It has 22 and a via conductor 23 located between the first surface S1, the first wiring layer J1 to the fourth wiring layer J4, and the second surface S2.
  • the first wiring layer J1 to the third wiring layer J3 are located in the second insulating substrate 11B.
  • the fourth wiring layer J4 is located between the first insulating substrate 11A and the second insulating substrate 11B.
  • the first wiring layer J1 to the fourth wiring layer J4 are arranged in this order from the side closest to the first surface S1.
  • the total number of wiring layers is not limited to the above example. Further, one or a plurality of wiring layers may be located in the first insulating substrate 11A.
  • the film conductor 22 of the wiring conductor 20 includes a solid conductor 24 to which a predetermined potential such as a ground potential or a power supply potential is supplied.
  • the solid conductor 24 means a conductor that extends over an area of 30% or more of the area of the wiring board 10 where the wiring conductor 20 is arranged (the area excluding the peripheral portion where the wiring conductor 20 is not arranged).
  • the solid conductor 24 may have through holes through which the via conductor 23 passes, slits or notches avoiding certain areas.
  • the solid conductor 24 corresponds to an example of the first solid conductor according to the present disclosure.
  • the electrode pads 21 and 21t are electrolytically plated.
  • the electrolytic plating may have a structure in which, for example, a nickel film of about 1 ⁇ m to 10 ⁇ m and a gold film of about 0.1 ⁇ m to 3 ⁇ m are laminated in order.
  • the plurality of electrode pads 21 and 21t may be electrically connected to any of the plurality of electrodes 25 on the opposite side via the wiring conductor 20 and may not be electrically connected to any of the electrodes 25 via the wiring conductor 20. It may be included.
  • the electrode pad 21t that is not conducting with any of the electrodes 25 on the opposite side, or the electrode pad 21t that has a high resistance between the electrodes 25 and the electrode 25, has a sufficient current from the electrode 25 on the opposite side during electrolytic plating as it is. I can't receive it.
  • the connecting conductor 30 is a conductor that supplies a current to the electrode pad 21t that cannot receive a current or a sufficient current only from the wiring conductor 20 during electrolytic plating of the electrode pads 21 and 21t.
  • the connecting conductor 30 includes a film conductor 32 located in the first wiring layer J1 and a via conductor 33 interposed between the first wiring layer J1 and the second wiring layer J2.
  • the electrode pad 21t to which a current is supplied via the connecting conductor 30 at the time of electrolytic plating is also referred to as “target electrode pad 21t”.
  • the wiring conductor 20 may include a plurality of target electrode pads 21t.
  • the wiring board 10 further has a groove X in which a part is cut off.
  • the groove X is a trace partially cut off by a laser beam, but may be a trace partially cut off by another beam such as an electron beam.
  • the groove X may be filled with an insulating material.
  • the target electrode pad 21t is located on the first surface S1 as shown in FIG. 2A.
  • an electrode pad 21 to which a current is supplied without going through the connecting conductor 30 during electrolytic plating is located on the first surface S1.
  • 2A and 2B show an example in which two adjacent target electrode pads 21t are conducting via the wiring conductor 20 of the wiring layer J1, even if the plurality of target electrode pads 21t are non-conducting to each other.
  • the conductor may be conducted in a combination different from that shown in FIGS. 2A and 2B.
  • the film conductor 32 of the connecting conductor 30 is an intersection 34 located between the first connecting conductor 30a, the second connecting conductor 30b, the first connecting conductor 30a, and the second connecting conductor 30b. And include. In FIG. 2B, only one first connecting conductor 30a and one second connecting conductor 30b are designated by reference numerals, but the plurality of connecting conductors 30 also have the first connecting conductor 30a and the second connecting conductor 30b. included.
  • the film conductor 32 is connected to the film conductor 22 of the wiring conductor 20 and is electrically connected to the target electrode pad 21t. Each film conductor 32 of the connecting conductor 30 may be linear.
  • the intersection 34 intersects the groove X.
  • the first connecting conductor 30a conducts with the target electrode pad 21t via the wiring conductor 20, and the second connecting conductor 30b is connected to the solid conductor 24 via the via conductor 33.
  • the linear film conductor 32 is cut at the intersection 34, and one of the film conductors 32 sandwiching the intersection 34 and the other are not conductive.
  • the solid conductor 24 is located in the second wiring layer J2 and overlaps with the film conductor 32 of the connecting conductor 30 in plan perspective.
  • Plane perspective corresponds to a plane in which the inside is seen through from a direction perpendicular to the first surface S1. The same applies to the subsequent "planar perspective”.
  • the solid conductor 24 may have a slit in which the grooves X intersect.
  • the solid conductor 24 is electrically connected to the electrode 25 at a position different from the cross-sectional position in FIG. 1.
  • the groove X has an opening on the first surface S1.
  • the bottom of the groove X is located below the second wiring layer J2 in the example of the first embodiment.
  • one groove X may extend so as to intersect a plurality of film conductors 32 of the connecting conductor 30, or one groove X intersects only one film conductor 32 of the connecting conductor 30. As such, a plurality of grooves X may be located.
  • the groove X has an allowable width for the position of the bottom.
  • the allowable width of the bottom position is from the depth between the first wiring layer J1 and the second wiring layer J2 to the depth between the second wiring layer J2 and the third wiring layer J3.
  • the first insulating substrate 11A and the wiring conductor 20 located on the substrate can be formed by firing a ceramic material and a metallized conductor.
  • the second insulating substrate 11B is formed, for example, by laminating a plurality of resin layers.
  • the resin layer is, for example, a polyimide resin, a polyamideimide resin, a siloxane-modified polyamideimide resin, a siloxane-modified polyimide resin, a polyphenylene sulfide resin, a total aromatic polyester resin, a BCB (benzocyclobutene) resin, an epoxy resin, a bismaleimide triazine resin, and the like. It is made of an insulating resin such as a polyphenylene ether resin, a polyquinoline resin, and a fluororesin.
  • the resin layer may further contain a filler for adjusting the moldability and the coefficient of thermal expansion.
  • the filler examples include barium sulfate, barium titanate, amorphous silica, crystalline silica, molten silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, silicon nitride, and aluminum nitride.
  • examples thereof include inorganic fillers such as boron nitride, alumina, magnesium oxide, magnesium hydroxide, titanium oxide, mica, talc, Neuburg calcium clay, organic bentonite, and zirconium phosphate.
  • the resin layer may contain one of the above fillers alone or in combination of two or more fillers as appropriate.
  • One resin layer of the second insulating substrate 11B may be formed by adhering a resin film to the lower layer, or may be formed by applying and curing a liquid precursor resin to the lower layer. May be good. After forming one resin layer, a resist film having openings corresponding to the via conductor 23 and the film conductor 22 is formed on the resin layer, and then recesses and vias corresponding to the film conductor 22 are formed by etching or laser processing. A through hole corresponding to the conductor 23 is formed.
  • a thin film forming method such as a thin film deposition method, a sputtering method, or an ion plating method, for example, a chromium (Cr) -copper (Cu) alloy layer or titanium (Ti)-is formed in the recesses and through holes of the resin layer.
  • a base conductor layer composed of a copper (Cu) alloy layer is formed.
  • the recesses and through holes are filled with a metal such as copper or gold by plating or the like, and then the resist is peeled off to form one resin layer and the wiring conductor 20 or the connecting conductor 30 located in the resin layer.
  • the formation of the resin layer and the wiring conductor 20 or the connecting conductor 30 is repeated to form the wiring conductor 20 or the connecting conductor 30 located in the plurality of resin layers and the plurality of resin layers. Further, a resist film having an opening corresponding to the electrode pad 21 is formed on the last resin layer (the highest resin layer) of the repetition, and a base conductor layer is formed in the opening by the same thin film forming method as described above. do. Then, a nickel film and a gold film are formed on the base conductor layer of the electrode pad 21 by electrolytic plating.
  • a current is passed from the electrode 25 of the first insulating substrate 11A to the underlying conductor layer via the wiring conductor 20 and the connecting conductor 30. Then, when the electrolytic plating is completed and the resist is peeled off, a substrate in which the first insulating substrate 11A and the second insulating substrate 11B are laminated is formed. In the substrate at this stage, unnecessary conduction between the target electrode pad 21t and the wiring conductor 20 is mixed via the connecting conductor 30. "Unnecessary" means that it is unnecessary when the wiring board 10 is used.
  • a laser beam is irradiated from the first surface S1 side of the insulating substrate 11 to cut the connecting conductor 30, that is, a laser trimming process is performed.
  • a laser trimming process a groove X having an opening on the first surface S1 and an intersection 34 where the connection conductor 30 and the groove X intersect are formed, and the connection conductor 30 is cut at the portion of the intersection 34. .. Then, the wiring board 10 is manufactured by removing all unnecessary continuity.
  • the connecting conductor 30 includes the first connecting conductor 30a and the second connecting conductor 30b, and the intersection 34 is located between the first connecting conductor 30a and the second connecting conductor 30b. Then, the second connecting conductor 30b conducts to the solid conductor 24, and the first connecting conductor 30a conducts to the target electrode pad 21t.
  • the electrode pad 21 can be sufficiently electrolytically plated by supplying a current to the electrode pad 21 via the connecting conductor 30, and then the groove X is formed in the insulating substrate 11 by a beam or the like.
  • the connecting conductor 30 is cut to obtain a desired wiring pattern of the wiring conductor 20.
  • the opening of the groove X is located on the first surface S1, and the intersection 34 between the connecting conductor 30 and the groove X is the first wiring layer under the first surface S1.
  • the solid conductor 24 is located in the second wiring layer J2 below the first wiring layer J1. Therefore, even when the groove X for cutting the connecting conductor 30 reaches the second wiring layer J2, only a slit is formed in the solid conductor 24, so that the electrical characteristics of the wiring conductor 20 are not significantly affected. Therefore, it is possible to take a large allowable value for the depth of the groove X that cuts the connecting conductor 30.
  • the groove X is a trace cut by a beam such as a laser.
  • the trimming process for cutting the connecting conductor 30 using a beam can be performed at high speed with less complexity. Therefore, the wiring board 10 having the groove X is provided with the wiring conductor 20 from which the connecting conductor 30 is cut with reduced complexity and high reliability.
  • FIG. 3 is a vertical sectional view showing a part of the wiring board according to the second embodiment of the present disclosure.
  • 4A is a plan view of the first surface S1 of the wiring board of FIG.
  • FIG. 4B is a cross-sectional view taken along the line BB of the wiring board of FIG.
  • FIG. 4C is a cross-sectional view taken along the line CC of the wiring board of FIG.
  • FIG. 4D is a cross-sectional view taken along the line DD of the wiring board of FIG.
  • the wiring board 10A of the second embodiment is substantially the same as the wiring board 10 of the first embodiment except that the patterns of the wiring conductor 20 and the connection conductor 30 are different.
  • a plurality of target electrode pads 21ta and 21tb are located on the first surface S1.
  • the plurality of target electrode pads 21ta and 21tb are divided into the target electrode pad 21ta of the first group located on the left side of the paper surface of FIG. 4A and the target electrode pad 21tb of the second group located on the right side of the paper surface in each arrangement region. It may be classified.
  • the connecting conductor 30 includes a band-shaped common conductor 32A located in the first wiring layer J1 and a plurality of linear conductors 32B located in the first wiring layer J1.
  • the band shape means a shape in which the dimension in the lateral direction on the plane is larger than that of the linear conductor 32B.
  • the common conductor 32A is connected to the first solid conductor 24A via a plurality of via conductors 33 (see FIG. 3).
  • the common conductor 32A is arranged between the target electrode pad 21t of the first group and the target electrode pad 21t of the second group in plan perspective.
  • the common conductor 32A may be arranged so as to extend in the longitudinal direction along the direction in which the target electrode pads 21ta of the first group are connected or the direction in which the target electrode pads 21tb of the second group are connected.
  • the groove X is located between the common conductor 32A and the target electrode pad 21ta of the first group and between the common conductor 32A and the target electrode pad 21tb of the second group in plan perspective.
  • the groove X may be arranged so that the longitudinal direction extends along the longitudinal direction of the common conductor 32A.
  • Each of the plurality of linear conductors 32B includes a first linear conductor 32Ba, a second linear conductor 32Bb, and an intersection 34 intersecting the groove X.
  • first linear conductor 32Ba a first linear conductor 32Ba
  • second linear conductor 32Bb a second linear conductor 32Bb
  • intersection 34 intersecting the groove X.
  • the intersection 34 is located between the first linear conductor 32Ba and the second linear conductor 32Bb.
  • the second linear conductor 32Bb is connected to the common conductor 32A, and the first linear conductor 32Ba conducts to the target electrode pads 21ta and 21tb via the wiring conductor 20 (membrane conductor 22 and via conductor 23).
  • One first linear conductor 32Ba may be conducted to a plurality of target electrode pads 21tb, or a plurality of first linear conductors 32Ba may be conducted to one target electrode pad 21ta.
  • the wiring conductor 20 includes a first solid conductor 24A located in the second wiring layer J2.
  • the first solid conductor 24A has an opening M1 that overlaps the groove X (or the intersection 34 of the linear conductor 32B) in plan perspective.
  • the wiring conductor 20 may include a second solid conductor 24B located at a portion overlapping the groove X in the plan perspective in the third wiring layer J3.
  • the wiring board 10A of the second embodiment can be manufactured by the same method as that of the first embodiment by different patterns of the wiring conductor 20 and the connecting conductor 30.
  • the connecting conductor 30 since the connecting conductor 30 includes the common conductor 32A, the total resistance of the connecting conductor 30 is reduced, and the connection is made during electrolytic plating before the groove X is formed.
  • a stable current can be supplied to the target electrode pads 21ta and 21tb via the conductor 30. Therefore, a plating film having a predetermined thickness can be easily formed on the target electrode pads 21ta and 21tb, and the thickness variation with other electrode pads 21 can be reduced.
  • one target electrode pad 21ta is used.
  • a plurality of linear conductors 32B (a plurality of first linear conductors 32Ba) are connected.
  • a stable current can be supplied to the target electrode pad 21ta via the connecting conductor 30, a plating film having a predetermined thickness can be easily formed on the target electrode pad 21ta, and the other electrode pad 21 and the other electrode pad 21tb can be formed. Thickness variation can be reduced.
  • the first solid conductor 24A has an opening M1 that overlaps with the intersection 34 of the connecting conductor 30 in plan perspective. Therefore, during the trimming process for cutting the connecting conductor 30, the cutting energy (laser energy in the case of the laser trimming process) can be made difficult to be absorbed by the first solid conductor 24A. Therefore, it is possible to reduce the occurrence of cutting failure of the connecting conductor 30 due to insufficient energy.
  • the second solid conductor 24B that overlaps with the opening M1 of the first solid conductor 24A in the plan perspective is located in the third wiring layer J3. Therefore, in the trimming process for cutting the connecting conductor 30, even if the depth of the groove X reaches the third wiring layer J3, the electrical characteristics of the wiring conductor 20 are not significantly affected. Therefore, it is possible to take a larger allowable value for the depth of the groove X that cuts the connecting conductor 30. Further, even if it becomes difficult to control the depth of the groove X due to the first solid conductor 24A of the second wiring layer J2 having the opening M1, the allowable value of the depth of the groove X can be made larger, so that the groove can be increased.
  • the connection conductor 30 can be cut with high reliability by keeping the depth of X within an allowable range.
  • FIG. 5 is a cross-sectional view showing a wiring board of a modified example.
  • FIG. 5 shows a cross-sectional view taken along the line CC of FIG.
  • the wiring board 10B of the modified example is the same as that of the second embodiment except for the wiring conductor 20 of the second wiring layer J2.
  • the wiring board 10B of the modified example has an opening M1 in the first solid conductor 24A of the second wiring layer J2 that overlaps the groove X (or the intersection 34 of the linear conductor 32B) in a plan view.
  • the wiring conductor 20 of the second wiring layer J2 has a conductor piece N1 located in the opening M1 and overlapping the groove X (or the intersection 34 of the linear conductor 32B).
  • the conductor piece N1 may be a floating conductor that is non-conducting to the first solid conductor 24A, or may be a conductor that is partially connected to the first solid conductor 24A.
  • the cutting energy (laser energy in the case of laser trimming) is the first solid when the connecting conductor 30 is cut by the opening M1 of the first solid conductor 24A. It can be made difficult to be absorbed by the shaped conductor 24A. Therefore, it is possible to reduce the occurrence of cutting failure of the connecting conductor 30 due to insufficient energy.
  • the conductor piece N1 overlapping the groove X is provided in the opening M1. Since the conductor piece N1 is not connected to the first solid conductor 24A or is only partially connected, the cutting energy (laser energy in the case of laser trimming processing) is used during the trimming process for cutting the connecting conductor 30.
  • FIG. 6A is a plan view showing the probe card according to the embodiment of the present disclosure.
  • FIG. 6B is a vertical sectional view showing a probe card according to the embodiment of the present disclosure.
  • the probe card 100 of the present embodiment is a component incorporated in a test device of a semiconductor wafer SW in which a plurality of semiconductor elements are formed.
  • the probe card 100 of the present embodiment includes a wiring board 10 and a plurality of probe pins 40 connected to a plurality of electrode pads 21 and 21t of the wiring board 10.
  • the probe pin 40 is made of a metal such as nickel and tungsten, and is bonded to the electrode pads 21 and 21t via a conductive bonding material such as solder.
  • the probe card 100 is interposed between a signal processing circuit for inputting and outputting a test signal or voltage and a semiconductor wafer SW to be tested, and a plurality of probe pins 40 come into contact with electrodes of the semiconductor element.
  • the configuration of the first embodiment may be applied, or the wiring board 10A of the second embodiment or the wiring board 10B of the modified example may be applied.
  • the first insulating substrate 11A of the wiring board 10 is configured by laminating a plurality of insulating layers, and may include a film conductor 22 as a wiring layer in addition to the via conductor 23. .. Further, the first insulating substrate 11A may include a heater wire 50.
  • the electrode pads 21 and 21t of the wiring board 10 have a film having a stable thickness. Therefore, the probe pin 40 can be stably joined, and the reliability of the probe pin 40 with respect to the joined portion can be improved.
  • the wiring board and probe card of the present disclosure are not limited to the above embodiment.
  • the wiring board of the probe card is shown as the use of the wiring board, but even if the wiring board of the present disclosure is applied to the wiring board on which the electronic element, the electric element, or various electric circuits are mounted. good.
  • the example in which the opening of the groove is located on the surface where the electrode pad is located is shown, but the electrode pad may be located on a different surface.
  • the first wiring layer in which the intersection where the connecting conductor and the groove intersect is located is located below the first surface where the opening of the groove is located, but the intersection is The located first wiring layer may be located on the first surface where the groove opening is located.
  • the details shown in the embodiment can be appropriately changed without departing from the spirit of the invention.
  • This disclosure can be used for wiring boards and probe cards.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
PCT/JP2021/043263 2020-11-27 2021-11-25 配線基板及びプローブカード Ceased WO2022114078A1 (ja)

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KR1020237017636A KR20230096042A (ko) 2020-11-27 2021-11-25 배선 기판 및 프로브 카드
JP2022565418A JP7550238B2 (ja) 2020-11-27 2021-11-25 配線基板及びプローブカード
US18/038,639 US20240027493A1 (en) 2020-11-27 2021-11-25 Wiring board and probe card

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JP2020196678 2020-11-27
JP2020-196678 2020-11-27

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WO2022114078A1 true WO2022114078A1 (ja) 2022-06-02

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JPH06196588A (ja) * 1992-10-26 1994-07-15 Sumitomo Kinzoku Ceramics:Kk 半導体素子収納用セラミックパッケージとその製造方法
JPH11163500A (ja) * 1997-11-25 1999-06-18 Sumitomo Metal Smi Electron Devices Inc セラミック配線基板の洗浄方法
JP2010171351A (ja) * 2008-12-25 2010-08-05 Kyocera Corp 配線基板及び配線基板の製造方法並びにプローブカード
JP2010232579A (ja) * 2009-03-30 2010-10-14 Oki Networks Co Ltd プリント配線板の製造方法
JP2012243836A (ja) * 2011-05-17 2012-12-10 Hitachi Cable Ltd フレキシブル配線基板およびその製造方法
CN104427789A (zh) * 2013-08-22 2015-03-18 富葵精密组件(深圳)有限公司 多层电路板及其制作方法

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JPWO2022114078A1 (https=) 2022-06-02
KR20230096042A (ko) 2023-06-29
JP7550238B2 (ja) 2024-09-12

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