WO2022114078A1 - 配線基板及びプローブカード - Google Patents
配線基板及びプローブカード Download PDFInfo
- Publication number
- WO2022114078A1 WO2022114078A1 PCT/JP2021/043263 JP2021043263W WO2022114078A1 WO 2022114078 A1 WO2022114078 A1 WO 2022114078A1 JP 2021043263 W JP2021043263 W JP 2021043263W WO 2022114078 A1 WO2022114078 A1 WO 2022114078A1
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- WO
- WIPO (PCT)
- Prior art keywords
- conductor
- wiring
- wiring board
- wiring layer
- linear
- Prior art date
Links
- 239000000523 sample Substances 0.000 title claims description 25
- 239000004020 conductor Substances 0.000 claims abstract description 296
- 239000007787 solid Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims description 34
- 238000002594 fluoroscopy Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 29
- 229920005989 resin Polymers 0.000 description 26
- 239000011347 resin Substances 0.000 description 26
- 238000005520 cutting process Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 14
- 238000009713 electroplating Methods 0.000 description 12
- 238000009966 trimming Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- 239000000945 filler Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004962 Polyamide-imide Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- TZCXTZWJZNENPQ-UHFFFAOYSA-L barium sulfate Chemical compound [Ba+2].[O-]S([O-])(=O)=O TZCXTZWJZNENPQ-UHFFFAOYSA-L 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000004927 clay Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002312 polyamide-imide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000454 talc Substances 0.000 description 2
- 229910052623 talc Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 229920000292 Polyquinoline Polymers 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- WNROFYMDJYEPJX-UHFFFAOYSA-K aluminium hydroxide Chemical compound [OH-].[OH-].[OH-].[Al+3] WNROFYMDJYEPJX-UHFFFAOYSA-K 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 239000000440 bentonite Substances 0.000 description 1
- 229910000278 bentonite Inorganic materials 0.000 description 1
- SVPXDRXYRYOSEX-UHFFFAOYSA-N bentoquatam Chemical compound O.O=[Si]=O.O=[Al]O[Al]=O SVPXDRXYRYOSEX-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011575 calcium Substances 0.000 description 1
- 229910000019 calcium carbonate Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052570 clay Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 229910002026 crystalline silica Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 239000012705 liquid precursor Substances 0.000 description 1
- ZLNQQNXFFQJAID-UHFFFAOYSA-L magnesium carbonate Chemical compound [Mg+2].[O-]C([O-])=O ZLNQQNXFFQJAID-UHFFFAOYSA-L 0.000 description 1
- 239000001095 magnesium carbonate Substances 0.000 description 1
- 229910000021 magnesium carbonate Inorganic materials 0.000 description 1
- VTHJTEIRLNZDEV-UHFFFAOYSA-L magnesium dihydroxide Chemical compound [OH-].[OH-].[Mg+2] VTHJTEIRLNZDEV-UHFFFAOYSA-L 0.000 description 1
- 239000000347 magnesium hydroxide Substances 0.000 description 1
- 229910001862 magnesium hydroxide Inorganic materials 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910000166 zirconium phosphate Inorganic materials 0.000 description 1
- LEHFSLREWWMLPU-UHFFFAOYSA-B zirconium(4+);tetraphosphate Chemical compound [Zr+4].[Zr+4].[Zr+4].[O-]P([O-])([O-])=O.[O-]P([O-])([O-])=O.[O-]P([O-])([O-])=O.[O-]P([O-])([O-])=O LEHFSLREWWMLPU-UHFFFAOYSA-B 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
Definitions
- This disclosure relates to wiring boards and probe cards.
- Japanese Unexamined Patent Publication No. 2011-29424 describes a configuration in which a wiring board having an electrode pad has a small piece portion that can be removed due to breakage or the like and a connecting conductor located in the small piece portion.
- the connecting conductor is a conductor for supplying an electric current to the electrode pad when the electrode pad is electrolytically plated.
- the connection conductor for electrolytic plating can be separated from the wiring conductor, and a desired wiring pattern can be obtained.
- the wiring board according to the present disclosure is An insulating substrate with a first surface and Wiring conductors and connecting conductors located on the insulating substrate, A first wiring layer and a second wiring layer including a part of the wiring conductor, and A groove having an opening on the first surface and Equipped with The wiring conductor is With electrode pads
- the first solid conductor included in the second wiring layer and Have The connecting conductor includes a first connecting conductor, a second connecting conductor, and an intersection of the first wiring layer that intersects the groove. The intersection is located between the first connecting conductor and the second connecting conductor.
- the first connecting conductor is conducted to the electrode pad, the second connecting conductor is conducted to the first solid conductor, and the second connecting conductor is conducted to the first solid conductor.
- the first wiring layer is located below the first surface or the first surface, and the second wiring layer is located below the first wiring layer.
- the probe card according to this disclosure is With the above wiring board, With a plurality of probe pins connected to the wiring board, To prepare for.
- FIG. 3 is a cross-sectional view taken along the line CC of the wiring board of FIG. It is a vertical sectional view which shows a part of the wiring board which concerns on Embodiment 2 of this disclosure. It is a top view of the 1st surface in the wiring board of FIG. It is sectional drawing in BB line of the wiring board of FIG. 3 is a cross-sectional view taken along the line CC of the wiring board of FIG.
- FIG. 1 is a vertical cross-sectional view showing a part of the wiring board 10 according to the first embodiment of the present disclosure.
- FIG. 2A is a plan view of the first surface S1 of the wiring board 10.
- FIG. 2B is a cross-sectional view taken along the line BB of the wiring board 10.
- FIG. 2C is a cross-sectional view taken along the line CC of the wiring board 10.
- the wiring board 10 of the first embodiment includes an insulating substrate 11 having a first surface S1 and a second surface S2 on the opposite side of the first surface S1, and a wiring conductor 20 and a connecting conductor 30 located on the insulating substrate 11. Be prepared. In the figure, the wiring conductor 20 and the connecting conductor 30 have different hatchings, but the wiring conductor 20 and the connecting conductor 30 may have the same material and may be integrated.
- the wiring board 10 further has a plurality of wiring layers (first wiring layer J1 to fourth wiring layer J4) inside.
- the layer of the wiring conductor located on the first surface S1 and the second surface S2 may also be referred to as a wiring layer.
- the insulating substrate 11 has a first insulating substrate 11A made of a ceramic material and a second insulating substrate 11B made of a resin material.
- the first insulating substrate 11A and the second insulating substrate 11B are laminated.
- the material of the insulating substrate 11 is not limited to the above example, and may be any material. Further, the insulating substrate 11 does not have to have a configuration in which two substrates made of two different materials are laminated, and may be a substrate made of a single material.
- the wiring conductor 20 is a conductor that transmits an electric signal or a voltage.
- the wiring conductor 20 includes a plurality of electrode pads 21 and 21t located on the first surface S1, a plurality of electrodes 25 located on the second surface S2, and a film conductor located on the first wiring layer J1 to the fourth wiring layer J4. It has 22 and a via conductor 23 located between the first surface S1, the first wiring layer J1 to the fourth wiring layer J4, and the second surface S2.
- the first wiring layer J1 to the third wiring layer J3 are located in the second insulating substrate 11B.
- the fourth wiring layer J4 is located between the first insulating substrate 11A and the second insulating substrate 11B.
- the first wiring layer J1 to the fourth wiring layer J4 are arranged in this order from the side closest to the first surface S1.
- the total number of wiring layers is not limited to the above example. Further, one or a plurality of wiring layers may be located in the first insulating substrate 11A.
- the film conductor 22 of the wiring conductor 20 includes a solid conductor 24 to which a predetermined potential such as a ground potential or a power supply potential is supplied.
- the solid conductor 24 means a conductor that extends over an area of 30% or more of the area of the wiring board 10 where the wiring conductor 20 is arranged (the area excluding the peripheral portion where the wiring conductor 20 is not arranged).
- the solid conductor 24 may have through holes through which the via conductor 23 passes, slits or notches avoiding certain areas.
- the solid conductor 24 corresponds to an example of the first solid conductor according to the present disclosure.
- the electrode pads 21 and 21t are electrolytically plated.
- the electrolytic plating may have a structure in which, for example, a nickel film of about 1 ⁇ m to 10 ⁇ m and a gold film of about 0.1 ⁇ m to 3 ⁇ m are laminated in order.
- the plurality of electrode pads 21 and 21t may be electrically connected to any of the plurality of electrodes 25 on the opposite side via the wiring conductor 20 and may not be electrically connected to any of the electrodes 25 via the wiring conductor 20. It may be included.
- the electrode pad 21t that is not conducting with any of the electrodes 25 on the opposite side, or the electrode pad 21t that has a high resistance between the electrodes 25 and the electrode 25, has a sufficient current from the electrode 25 on the opposite side during electrolytic plating as it is. I can't receive it.
- the connecting conductor 30 is a conductor that supplies a current to the electrode pad 21t that cannot receive a current or a sufficient current only from the wiring conductor 20 during electrolytic plating of the electrode pads 21 and 21t.
- the connecting conductor 30 includes a film conductor 32 located in the first wiring layer J1 and a via conductor 33 interposed between the first wiring layer J1 and the second wiring layer J2.
- the electrode pad 21t to which a current is supplied via the connecting conductor 30 at the time of electrolytic plating is also referred to as “target electrode pad 21t”.
- the wiring conductor 20 may include a plurality of target electrode pads 21t.
- the wiring board 10 further has a groove X in which a part is cut off.
- the groove X is a trace partially cut off by a laser beam, but may be a trace partially cut off by another beam such as an electron beam.
- the groove X may be filled with an insulating material.
- the target electrode pad 21t is located on the first surface S1 as shown in FIG. 2A.
- an electrode pad 21 to which a current is supplied without going through the connecting conductor 30 during electrolytic plating is located on the first surface S1.
- 2A and 2B show an example in which two adjacent target electrode pads 21t are conducting via the wiring conductor 20 of the wiring layer J1, even if the plurality of target electrode pads 21t are non-conducting to each other.
- the conductor may be conducted in a combination different from that shown in FIGS. 2A and 2B.
- the film conductor 32 of the connecting conductor 30 is an intersection 34 located between the first connecting conductor 30a, the second connecting conductor 30b, the first connecting conductor 30a, and the second connecting conductor 30b. And include. In FIG. 2B, only one first connecting conductor 30a and one second connecting conductor 30b are designated by reference numerals, but the plurality of connecting conductors 30 also have the first connecting conductor 30a and the second connecting conductor 30b. included.
- the film conductor 32 is connected to the film conductor 22 of the wiring conductor 20 and is electrically connected to the target electrode pad 21t. Each film conductor 32 of the connecting conductor 30 may be linear.
- the intersection 34 intersects the groove X.
- the first connecting conductor 30a conducts with the target electrode pad 21t via the wiring conductor 20, and the second connecting conductor 30b is connected to the solid conductor 24 via the via conductor 33.
- the linear film conductor 32 is cut at the intersection 34, and one of the film conductors 32 sandwiching the intersection 34 and the other are not conductive.
- the solid conductor 24 is located in the second wiring layer J2 and overlaps with the film conductor 32 of the connecting conductor 30 in plan perspective.
- Plane perspective corresponds to a plane in which the inside is seen through from a direction perpendicular to the first surface S1. The same applies to the subsequent "planar perspective”.
- the solid conductor 24 may have a slit in which the grooves X intersect.
- the solid conductor 24 is electrically connected to the electrode 25 at a position different from the cross-sectional position in FIG. 1.
- the groove X has an opening on the first surface S1.
- the bottom of the groove X is located below the second wiring layer J2 in the example of the first embodiment.
- one groove X may extend so as to intersect a plurality of film conductors 32 of the connecting conductor 30, or one groove X intersects only one film conductor 32 of the connecting conductor 30. As such, a plurality of grooves X may be located.
- the groove X has an allowable width for the position of the bottom.
- the allowable width of the bottom position is from the depth between the first wiring layer J1 and the second wiring layer J2 to the depth between the second wiring layer J2 and the third wiring layer J3.
- the first insulating substrate 11A and the wiring conductor 20 located on the substrate can be formed by firing a ceramic material and a metallized conductor.
- the second insulating substrate 11B is formed, for example, by laminating a plurality of resin layers.
- the resin layer is, for example, a polyimide resin, a polyamideimide resin, a siloxane-modified polyamideimide resin, a siloxane-modified polyimide resin, a polyphenylene sulfide resin, a total aromatic polyester resin, a BCB (benzocyclobutene) resin, an epoxy resin, a bismaleimide triazine resin, and the like. It is made of an insulating resin such as a polyphenylene ether resin, a polyquinoline resin, and a fluororesin.
- the resin layer may further contain a filler for adjusting the moldability and the coefficient of thermal expansion.
- the filler examples include barium sulfate, barium titanate, amorphous silica, crystalline silica, molten silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, silicon nitride, and aluminum nitride.
- examples thereof include inorganic fillers such as boron nitride, alumina, magnesium oxide, magnesium hydroxide, titanium oxide, mica, talc, Neuburg calcium clay, organic bentonite, and zirconium phosphate.
- the resin layer may contain one of the above fillers alone or in combination of two or more fillers as appropriate.
- One resin layer of the second insulating substrate 11B may be formed by adhering a resin film to the lower layer, or may be formed by applying and curing a liquid precursor resin to the lower layer. May be good. After forming one resin layer, a resist film having openings corresponding to the via conductor 23 and the film conductor 22 is formed on the resin layer, and then recesses and vias corresponding to the film conductor 22 are formed by etching or laser processing. A through hole corresponding to the conductor 23 is formed.
- a thin film forming method such as a thin film deposition method, a sputtering method, or an ion plating method, for example, a chromium (Cr) -copper (Cu) alloy layer or titanium (Ti)-is formed in the recesses and through holes of the resin layer.
- a base conductor layer composed of a copper (Cu) alloy layer is formed.
- the recesses and through holes are filled with a metal such as copper or gold by plating or the like, and then the resist is peeled off to form one resin layer and the wiring conductor 20 or the connecting conductor 30 located in the resin layer.
- the formation of the resin layer and the wiring conductor 20 or the connecting conductor 30 is repeated to form the wiring conductor 20 or the connecting conductor 30 located in the plurality of resin layers and the plurality of resin layers. Further, a resist film having an opening corresponding to the electrode pad 21 is formed on the last resin layer (the highest resin layer) of the repetition, and a base conductor layer is formed in the opening by the same thin film forming method as described above. do. Then, a nickel film and a gold film are formed on the base conductor layer of the electrode pad 21 by electrolytic plating.
- a current is passed from the electrode 25 of the first insulating substrate 11A to the underlying conductor layer via the wiring conductor 20 and the connecting conductor 30. Then, when the electrolytic plating is completed and the resist is peeled off, a substrate in which the first insulating substrate 11A and the second insulating substrate 11B are laminated is formed. In the substrate at this stage, unnecessary conduction between the target electrode pad 21t and the wiring conductor 20 is mixed via the connecting conductor 30. "Unnecessary" means that it is unnecessary when the wiring board 10 is used.
- a laser beam is irradiated from the first surface S1 side of the insulating substrate 11 to cut the connecting conductor 30, that is, a laser trimming process is performed.
- a laser trimming process a groove X having an opening on the first surface S1 and an intersection 34 where the connection conductor 30 and the groove X intersect are formed, and the connection conductor 30 is cut at the portion of the intersection 34. .. Then, the wiring board 10 is manufactured by removing all unnecessary continuity.
- the connecting conductor 30 includes the first connecting conductor 30a and the second connecting conductor 30b, and the intersection 34 is located between the first connecting conductor 30a and the second connecting conductor 30b. Then, the second connecting conductor 30b conducts to the solid conductor 24, and the first connecting conductor 30a conducts to the target electrode pad 21t.
- the electrode pad 21 can be sufficiently electrolytically plated by supplying a current to the electrode pad 21 via the connecting conductor 30, and then the groove X is formed in the insulating substrate 11 by a beam or the like.
- the connecting conductor 30 is cut to obtain a desired wiring pattern of the wiring conductor 20.
- the opening of the groove X is located on the first surface S1, and the intersection 34 between the connecting conductor 30 and the groove X is the first wiring layer under the first surface S1.
- the solid conductor 24 is located in the second wiring layer J2 below the first wiring layer J1. Therefore, even when the groove X for cutting the connecting conductor 30 reaches the second wiring layer J2, only a slit is formed in the solid conductor 24, so that the electrical characteristics of the wiring conductor 20 are not significantly affected. Therefore, it is possible to take a large allowable value for the depth of the groove X that cuts the connecting conductor 30.
- the groove X is a trace cut by a beam such as a laser.
- the trimming process for cutting the connecting conductor 30 using a beam can be performed at high speed with less complexity. Therefore, the wiring board 10 having the groove X is provided with the wiring conductor 20 from which the connecting conductor 30 is cut with reduced complexity and high reliability.
- FIG. 3 is a vertical sectional view showing a part of the wiring board according to the second embodiment of the present disclosure.
- 4A is a plan view of the first surface S1 of the wiring board of FIG.
- FIG. 4B is a cross-sectional view taken along the line BB of the wiring board of FIG.
- FIG. 4C is a cross-sectional view taken along the line CC of the wiring board of FIG.
- FIG. 4D is a cross-sectional view taken along the line DD of the wiring board of FIG.
- the wiring board 10A of the second embodiment is substantially the same as the wiring board 10 of the first embodiment except that the patterns of the wiring conductor 20 and the connection conductor 30 are different.
- a plurality of target electrode pads 21ta and 21tb are located on the first surface S1.
- the plurality of target electrode pads 21ta and 21tb are divided into the target electrode pad 21ta of the first group located on the left side of the paper surface of FIG. 4A and the target electrode pad 21tb of the second group located on the right side of the paper surface in each arrangement region. It may be classified.
- the connecting conductor 30 includes a band-shaped common conductor 32A located in the first wiring layer J1 and a plurality of linear conductors 32B located in the first wiring layer J1.
- the band shape means a shape in which the dimension in the lateral direction on the plane is larger than that of the linear conductor 32B.
- the common conductor 32A is connected to the first solid conductor 24A via a plurality of via conductors 33 (see FIG. 3).
- the common conductor 32A is arranged between the target electrode pad 21t of the first group and the target electrode pad 21t of the second group in plan perspective.
- the common conductor 32A may be arranged so as to extend in the longitudinal direction along the direction in which the target electrode pads 21ta of the first group are connected or the direction in which the target electrode pads 21tb of the second group are connected.
- the groove X is located between the common conductor 32A and the target electrode pad 21ta of the first group and between the common conductor 32A and the target electrode pad 21tb of the second group in plan perspective.
- the groove X may be arranged so that the longitudinal direction extends along the longitudinal direction of the common conductor 32A.
- Each of the plurality of linear conductors 32B includes a first linear conductor 32Ba, a second linear conductor 32Bb, and an intersection 34 intersecting the groove X.
- first linear conductor 32Ba a first linear conductor 32Ba
- second linear conductor 32Bb a second linear conductor 32Bb
- intersection 34 intersecting the groove X.
- the intersection 34 is located between the first linear conductor 32Ba and the second linear conductor 32Bb.
- the second linear conductor 32Bb is connected to the common conductor 32A, and the first linear conductor 32Ba conducts to the target electrode pads 21ta and 21tb via the wiring conductor 20 (membrane conductor 22 and via conductor 23).
- One first linear conductor 32Ba may be conducted to a plurality of target electrode pads 21tb, or a plurality of first linear conductors 32Ba may be conducted to one target electrode pad 21ta.
- the wiring conductor 20 includes a first solid conductor 24A located in the second wiring layer J2.
- the first solid conductor 24A has an opening M1 that overlaps the groove X (or the intersection 34 of the linear conductor 32B) in plan perspective.
- the wiring conductor 20 may include a second solid conductor 24B located at a portion overlapping the groove X in the plan perspective in the third wiring layer J3.
- the wiring board 10A of the second embodiment can be manufactured by the same method as that of the first embodiment by different patterns of the wiring conductor 20 and the connecting conductor 30.
- the connecting conductor 30 since the connecting conductor 30 includes the common conductor 32A, the total resistance of the connecting conductor 30 is reduced, and the connection is made during electrolytic plating before the groove X is formed.
- a stable current can be supplied to the target electrode pads 21ta and 21tb via the conductor 30. Therefore, a plating film having a predetermined thickness can be easily formed on the target electrode pads 21ta and 21tb, and the thickness variation with other electrode pads 21 can be reduced.
- one target electrode pad 21ta is used.
- a plurality of linear conductors 32B (a plurality of first linear conductors 32Ba) are connected.
- a stable current can be supplied to the target electrode pad 21ta via the connecting conductor 30, a plating film having a predetermined thickness can be easily formed on the target electrode pad 21ta, and the other electrode pad 21 and the other electrode pad 21tb can be formed. Thickness variation can be reduced.
- the first solid conductor 24A has an opening M1 that overlaps with the intersection 34 of the connecting conductor 30 in plan perspective. Therefore, during the trimming process for cutting the connecting conductor 30, the cutting energy (laser energy in the case of the laser trimming process) can be made difficult to be absorbed by the first solid conductor 24A. Therefore, it is possible to reduce the occurrence of cutting failure of the connecting conductor 30 due to insufficient energy.
- the second solid conductor 24B that overlaps with the opening M1 of the first solid conductor 24A in the plan perspective is located in the third wiring layer J3. Therefore, in the trimming process for cutting the connecting conductor 30, even if the depth of the groove X reaches the third wiring layer J3, the electrical characteristics of the wiring conductor 20 are not significantly affected. Therefore, it is possible to take a larger allowable value for the depth of the groove X that cuts the connecting conductor 30. Further, even if it becomes difficult to control the depth of the groove X due to the first solid conductor 24A of the second wiring layer J2 having the opening M1, the allowable value of the depth of the groove X can be made larger, so that the groove can be increased.
- the connection conductor 30 can be cut with high reliability by keeping the depth of X within an allowable range.
- FIG. 5 is a cross-sectional view showing a wiring board of a modified example.
- FIG. 5 shows a cross-sectional view taken along the line CC of FIG.
- the wiring board 10B of the modified example is the same as that of the second embodiment except for the wiring conductor 20 of the second wiring layer J2.
- the wiring board 10B of the modified example has an opening M1 in the first solid conductor 24A of the second wiring layer J2 that overlaps the groove X (or the intersection 34 of the linear conductor 32B) in a plan view.
- the wiring conductor 20 of the second wiring layer J2 has a conductor piece N1 located in the opening M1 and overlapping the groove X (or the intersection 34 of the linear conductor 32B).
- the conductor piece N1 may be a floating conductor that is non-conducting to the first solid conductor 24A, or may be a conductor that is partially connected to the first solid conductor 24A.
- the cutting energy (laser energy in the case of laser trimming) is the first solid when the connecting conductor 30 is cut by the opening M1 of the first solid conductor 24A. It can be made difficult to be absorbed by the shaped conductor 24A. Therefore, it is possible to reduce the occurrence of cutting failure of the connecting conductor 30 due to insufficient energy.
- the conductor piece N1 overlapping the groove X is provided in the opening M1. Since the conductor piece N1 is not connected to the first solid conductor 24A or is only partially connected, the cutting energy (laser energy in the case of laser trimming processing) is used during the trimming process for cutting the connecting conductor 30.
- FIG. 6A is a plan view showing the probe card according to the embodiment of the present disclosure.
- FIG. 6B is a vertical sectional view showing a probe card according to the embodiment of the present disclosure.
- the probe card 100 of the present embodiment is a component incorporated in a test device of a semiconductor wafer SW in which a plurality of semiconductor elements are formed.
- the probe card 100 of the present embodiment includes a wiring board 10 and a plurality of probe pins 40 connected to a plurality of electrode pads 21 and 21t of the wiring board 10.
- the probe pin 40 is made of a metal such as nickel and tungsten, and is bonded to the electrode pads 21 and 21t via a conductive bonding material such as solder.
- the probe card 100 is interposed between a signal processing circuit for inputting and outputting a test signal or voltage and a semiconductor wafer SW to be tested, and a plurality of probe pins 40 come into contact with electrodes of the semiconductor element.
- the configuration of the first embodiment may be applied, or the wiring board 10A of the second embodiment or the wiring board 10B of the modified example may be applied.
- the first insulating substrate 11A of the wiring board 10 is configured by laminating a plurality of insulating layers, and may include a film conductor 22 as a wiring layer in addition to the via conductor 23. .. Further, the first insulating substrate 11A may include a heater wire 50.
- the electrode pads 21 and 21t of the wiring board 10 have a film having a stable thickness. Therefore, the probe pin 40 can be stably joined, and the reliability of the probe pin 40 with respect to the joined portion can be improved.
- the wiring board and probe card of the present disclosure are not limited to the above embodiment.
- the wiring board of the probe card is shown as the use of the wiring board, but even if the wiring board of the present disclosure is applied to the wiring board on which the electronic element, the electric element, or various electric circuits are mounted. good.
- the example in which the opening of the groove is located on the surface where the electrode pad is located is shown, but the electrode pad may be located on a different surface.
- the first wiring layer in which the intersection where the connecting conductor and the groove intersect is located is located below the first surface where the opening of the groove is located, but the intersection is The located first wiring layer may be located on the first surface where the groove opening is located.
- the details shown in the embodiment can be appropriately changed without departing from the spirit of the invention.
- This disclosure can be used for wiring boards and probe cards.
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Abstract
Description
第1面を有する絶縁基板と、
前記絶縁基板に位置する配線導体及び接続導体と、
前記配線導体の一部が含まれる第1配線層及び第2配線層と、
前記第1面に開口部を有する溝と、
を備え、
前記配線導体は、
電極パッドと、
前記第2配線層に含まれる第1ベタ状導体と、
を有し、
前記接続導体は、第1接続導体と、第2接続導体と、前記第1配線層で前記溝と交差した交差部とを含み、
前記交差部は前記第1接続導体と前記第2接続導体との間に位置し、
前記第1接続導体が前記電極パッドに導通され、前記第2接続導体が前記第1ベタ状導体に導通され、
前記第1配線層は、前記第1面又は前記第1面の下に位置し、前記第2配線層は前記第1配線層の下に位置する。
上記の配線基板と、
前記配線基板に接続された複数のプローブピンと、
を備える。
図1は、本開示の実施形態1に係る配線基板10の一部を示す縦断面図である。図2Aは、配線基板10の第1面S1の平面図である。図2Bは、配線基板10のB-B線における断面図である。図2Cは、配線基板10のC-C線における断面図である。
対象電極パッド21tは、図2Aに示すように、第1面S1に位置する。加えて、第1面S1には、電解めっきの際に接続導体30を介さずに電流が供給される電極パッド21が位置する。図2A及び図2Bは、隣り合う2つの対象電極パッド21tが配線層J1の配線導体20を介して導通している例を示すが、複数の対象電極パッド21tは、互いに非導通であってもよいし、図2A及び図2Bとは異なる組合せで導通していてもよい。
続いて、配線基板10の製造方法の一例について説明する。第1絶縁基板11Aと、当該基板に位置する配線導体20とは、セラミック素材の焼成、並びに、メタライズ導体により形成できる。
図3は、本開示の実施形態2に係る配線基板の一部を示す縦断面図である。図4Aは、図3の配線基板の第1面S1の平面図である。図4Bは図3の配線基板のB-B線における断面図である。図4Cは、図3の配線基板のC-C線における断面図である。図4Dは図3の配線基板のD-D線における断面図である。
図5は、変形例の配線基板を示す断面図である。図5は、図3のC-C線における断面図を示す。変形例の配線基板10Bは、第2配線層J2の配線導体20以外は実施形態2と同様である。
図6Aは、本開示の実施形態に係るプローブカードを示す平面図である。図6Bは、本開示の実施形態に係るプローブカードを示す縦断面図である。本実施形態のプローブカード100は、複数の半導体素子が形成された半導体ウエハSWの試験装置に組み込まれる構成部品である。本実施形態のプローブカード100は、配線基板10と、配線基板10の複数の電極パッド21、21tに接続された複数のプローブピン40とを備える。
11 絶縁基板
S1 第1面
S2 第2面
20 配線導体
21、21t、21ta、21tb 電極パッド
22 膜導体
23 ビア導体
24 ベタ状導体
24A 第1ベタ状導体
M1 開口
N1 導体片
24B 第2ベタ状導体
25 電極
30 接続導体
30a 第1接続導体
30b 第2接続導体
32 膜導体
32A 共通導体
32B 線状導体
32Ba 第1線状導体
32Bb 第2線状導体
33 ビア導体
34 交差部
X 溝
J1 第1配線層
J2 第2配線層
J3 第3配線層
J4 第4配線層
100 プローブカード
Claims (8)
- 第1面を有する絶縁基板と、
前記絶縁基板に位置する配線導体及び接続導体と、
前記配線導体の一部が含まれる第1配線層及び第2配線層と、
前記第1面に開口部を有する溝と、
を備え、
前記配線導体は、
電極パッドと、
前記第2配線層に含まれる第1ベタ状導体と、
を有し、
前記接続導体は、第1接続導体と、第2接続導体と、前記第1配線層で前記溝と交差した交差部とを含み、
前記交差部は前記第1接続導体と前記第2接続導体との間に位置し、
前記第1接続導体が前記電極パッドに導通され、前記第2接続導体が前記第1ベタ状導体に導通され、
前記第1配線層は、前記第1面又は前記第1面の下に位置し、前記第2配線層は前記第1配線層の下に位置する、
配線基板。 - 前記溝はビームにより切り取られた跡である、
請求項1記載の配線基板。 - 複数の前記電極パッドを有し、
前記接続導体は、前記第1配線層に位置する複数の線状導体と、前記第1配線層に位置する帯状の共通導体とを含み、
前記複数の線状導体の各々が、第1線状導体と、第2線状導体と、前記第1線状導体と前記第2線状導体との間に位置する前記交差部とを含み、
前記各々の線状導体の前記第1線状導体が前記複数の電極パッドのいずれかに導通され、前記各々の線状導体の前記第2線状導体が前記共通導体に接続されている、
請求項1又は請求項2記載の配線基板。 - 前記接続導体は、1つの前記電極パッドに導通された複数の線状導体を含む、
請求項1から請求項3のいずれか一項に記載の配線基板。 - 前記第1ベタ状導体は、平面透視で前記交差部と重なる開口を有する、
請求項1から請求項4のいずれか一項に記載の配線基板。 - 前記第2配線層の下に位置する第3配線層と、
前記第3配線層に位置し、平面透視で前記開口と重なる第2ベタ状導体と、
を有する、
請求項5記載の配線基板。 - 前記配線導体は、
前記開口内に位置し平面透視で前記交差部と重なる導体片を含む、
請求項5記載の配線基板。 - 請求項1から請求項7のいずれか一項に記載の配線基板と、
前記配線基板に接続された複数のプローブピンと、
を備えるプローブカード。
Priority Applications (3)
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US18/038,639 US20240027493A1 (en) | 2020-11-27 | 2021-11-25 | Wiring board and probe card |
KR1020237017636A KR20230096042A (ko) | 2020-11-27 | 2021-11-25 | 배선 기판 및 프로브 카드 |
JP2022565418A JPWO2022114078A1 (ja) | 2020-11-27 | 2021-11-25 |
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JP (1) | JPWO2022114078A1 (ja) |
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JPH06196588A (ja) * | 1992-10-26 | 1994-07-15 | Sumitomo Kinzoku Ceramics:Kk | 半導体素子収納用セラミックパッケージとその製造方法 |
JPH11163500A (ja) * | 1997-11-25 | 1999-06-18 | Sumitomo Metal Smi Electron Devices Inc | セラミック配線基板の洗浄方法 |
JP2010171351A (ja) * | 2008-12-25 | 2010-08-05 | Kyocera Corp | 配線基板及び配線基板の製造方法並びにプローブカード |
JP2010232579A (ja) * | 2009-03-30 | 2010-10-14 | Oki Networks Co Ltd | プリント配線板の製造方法 |
JP2012243836A (ja) * | 2011-05-17 | 2012-12-10 | Hitachi Cable Ltd | フレキシブル配線基板およびその製造方法 |
CN104427789A (zh) * | 2013-08-22 | 2015-03-18 | 富葵精密组件(深圳)有限公司 | 多层电路板及其制作方法 |
-
2021
- 2021-11-25 KR KR1020237017636A patent/KR20230096042A/ko unknown
- 2021-11-25 US US18/038,639 patent/US20240027493A1/en active Pending
- 2021-11-25 JP JP2022565418A patent/JPWO2022114078A1/ja active Pending
- 2021-11-25 WO PCT/JP2021/043263 patent/WO2022114078A1/ja active Application Filing
Patent Citations (8)
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JPS6296885U (ja) * | 1985-12-09 | 1987-06-20 | ||
JPS63224392A (ja) * | 1987-03-13 | 1988-09-19 | 日本メクトロン株式会社 | 多層プリント配線板およびその加工法 |
JPH06196588A (ja) * | 1992-10-26 | 1994-07-15 | Sumitomo Kinzoku Ceramics:Kk | 半導体素子収納用セラミックパッケージとその製造方法 |
JPH11163500A (ja) * | 1997-11-25 | 1999-06-18 | Sumitomo Metal Smi Electron Devices Inc | セラミック配線基板の洗浄方法 |
JP2010171351A (ja) * | 2008-12-25 | 2010-08-05 | Kyocera Corp | 配線基板及び配線基板の製造方法並びにプローブカード |
JP2010232579A (ja) * | 2009-03-30 | 2010-10-14 | Oki Networks Co Ltd | プリント配線板の製造方法 |
JP2012243836A (ja) * | 2011-05-17 | 2012-12-10 | Hitachi Cable Ltd | フレキシブル配線基板およびその製造方法 |
CN104427789A (zh) * | 2013-08-22 | 2015-03-18 | 富葵精密组件(深圳)有限公司 | 多层电路板及其制作方法 |
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