WO2022111340A1 - 一种时钟校准电路 - Google Patents

一种时钟校准电路 Download PDF

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Publication number
WO2022111340A1
WO2022111340A1 PCT/CN2021/131026 CN2021131026W WO2022111340A1 WO 2022111340 A1 WO2022111340 A1 WO 2022111340A1 CN 2021131026 W CN2021131026 W CN 2021131026W WO 2022111340 A1 WO2022111340 A1 WO 2022111340A1
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Prior art keywords
clock
sleep mode
modem
clock signal
signal
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PCT/CN2021/131026
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English (en)
French (fr)
Inventor
晏龙
唐博
邹旭
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紫光展锐(重庆)科技有限公司
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Priority claimed from CN202011360851.9A external-priority patent/CN112422126B/zh
Application filed by 紫光展锐(重庆)科技有限公司 filed Critical 紫光展锐(重庆)科技有限公司
Publication of WO2022111340A1 publication Critical patent/WO2022111340A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a clock calibration circuit.
  • the system In a communication or positioning system, the system usually has two modes of work and sleep.
  • the system uses a specific clock to determine the system clock signal; and when the system switches to sleep mode, the specific clock also enters the sleep mode, and the sleep mode makes the system clock signal a certain lag;
  • the system clock signal needs to be calibrated. But how to calibrate the system clock signal is a problem to be solved.
  • the embodiment of the present application provides a clock calibration circuit, which can not only realize the calibration of the system clock, but also can effectively improve the calibration efficiency and reduce the power consumption of the system.
  • a clock calibration circuit provided by an embodiment of the present application includes: a clock generation module, a clock frequency division module, and a modem; the input end of the clock frequency division module is respectively connected to the clock generation module and the output end of the modem, The output end is connected with the input end of the modem, and the input end of the clock generation module is connected with the output end of the modem; wherein:
  • the modem When the modem is switched from the working mode to the sleep mode, it generates a sleep mode indication signal and a first control signal, outputs the sleep mode indication signal to the clock generation module, and outputs the first control signal to the clock frequency division module;
  • the clock generation module switches from the working mode to the sleep mode in response to the sleep mode indication signal, generates a first clock signal in the sleep mode, and outputs the first clock signal in the sleep mode to the clock frequency dividing module;
  • the clock frequency dividing module divides the frequency of the first clock signal in the sleep mode based on the configuration parameters corresponding to the sleep mode in response to the first control signal, generates a second clock signal in the sleep mode, and divides the first clock signal in the sleep mode.
  • two clock signals are output to the modem;
  • the system clock signal is calibrated based on the second clock signal in the sleep mode.
  • the clock frequency dividing module includes a configuration parameter register unit, a selection control unit and a frequency divider; the input end of the configuration parameter register unit is connected to the output end of the clock generation module, and the selection control unit The input end of the unit is respectively connected with the configuration parameter register unit and the output end of the modem, the output end is connected with the input end of the frequency divider, and the output end of the frequency divider is connected with the input end of the modem ; wherein, the configuration parameter register unit stores configuration parameters corresponding to the sleep mode.
  • the modem outputs the first control signal to the selection control unit to control the selection control unit to be electrically connected, and the configuration parameters corresponding to the sleep mode output by the configuration parameter register unit and outputting the first clock signal in the sleep mode to the frequency divider;
  • the frequency divider divides the frequency of the first clock signal in the sleep mode based on the configuration parameters corresponding to the sleep mode, generates a second clock signal in the sleep mode, and outputs the second clock signal in the sleep mode to the modem .
  • the modem outputs the first control signal to the selection control unit to control the selection control unit to be electrically connected, and the configuration parameters corresponding to the sleep mode output by the configuration parameter register unit and outputting the first clock signal in the sleep mode to the frequency divider;
  • the frequency divider divides the frequency of the first clock signal in the sleep mode based on the configuration parameters corresponding to the sleep mode, generates a second clock signal in the sleep mode, and outputs the second clock signal in the sleep mode to the modem .
  • the configuration parameter register unit includes a first configuration parameter register and a second configuration parameter register, and the selection control unit is a switch of the second type;
  • the first configuration parameter register and the second configuration parameter register The input terminals of the first configuration parameter register are respectively connected to the output terminal of the clock generation module, the output terminal of the first configuration parameter register is connected to the first input terminal of the second type of switch, and the output terminal of the second configuration parameter register connected with the second input end of the switch of the second type, the output end of the switch of the second type is connected with the input end of the frequency divider, and the control end is connected with the output end of the modem;
  • the modem outputs the first control signal to the switch of the second type, so as to control the output terminal of the switch of the second type to be in electrical communication with the first input terminal, and to output the output terminal of the first configuration parameter register.
  • the configuration parameters corresponding to the sleep mode and the first clock signal in the sleep mode are output to the frequency divider; wherein, the first configuration parameter register stores the configuration parameters corresponding to the sleep mode.
  • the working mode indication signal and the second control signal are generated
  • the modem outputs the working mode indication signal to the clock generation module, the clock generation module switches from the sleep mode to the working mode in response to the working mode indication signal, and generates a first clock signal in the working mode, and outputting the first clock signal in the working mode to the first configuration parameter register and the second configuration parameter register;
  • the modem outputs the second control signal to the switch of the second type, so as to control the output terminal of the switch of the second type to be electrically connected to the input terminal of the second type, and output the output terminal of the second configuration parameter register.
  • the configuration parameters corresponding to the working mode and the first clock signal in the working mode are output to the frequency divider;
  • the frequency divider divides the frequency of the first clock signal in the work mode based on the configuration parameters corresponding to the work mode, generates a second clock signal in the work mode, and outputs the second clock signal in the work mode to the modem ; wherein, the second configuration parameter register stores configuration parameters corresponding to the working mode.
  • the clock calibration circuit further includes a phase-locked loop, an input end of the phase-locked loop is connected to an output end of the clock generation module, and an output end is connected to an input end of the modem;
  • the clock generation module also outputs the first clock signal in the working mode to the phase-locked loop;
  • the system clock signal is updated based on the second clock signal in the working mode output by the frequency divider and the clock signal output by the phase-locked loop.
  • the first clock signal is a 26M clock signal
  • the second clock signal is a 32K clock signal
  • the clock generation module includes a crystal resonator and a crystal oscillator, the crystal oscillator is connected to the crystal resonator, and the input end of the crystal oscillator is connected to the output end of the modem, The output end is connected to the input end of the clock frequency dividing module.
  • the crystal oscillator is any one of a voltage-controlled crystal oscillator, a temperature-compensated crystal oscillator, a digital temperature-compensated crystal oscillator, and an oven-controlled crystal oscillator.
  • the modem when the modem switches from the working mode to the sleep mode, it outputs the generated sleep mode indication signal to the clock generation module and the clock frequency division module; the clock generation module switches from the work mode to the sleep mode in response to the sleep mode indication signal , and output the generated first clock signal in the sleep mode to the clock frequency division module; the clock frequency division module divides the frequency of the first clock signal in the sleep mode based on the configuration parameters corresponding to the sleep mode in response to the sleep mode indication signal, and generates the second clock signal in the sleep mode, and output the second clock signal in the sleep mode to the modem; when the modem switches from the sleep mode to the working mode, the system clock signal is calibrated based on the second clock signal in the sleep mode, Therefore, the calibration of the system clock signal can be realized when switching from the sleep mode to the working mode, so as to ensure the accuracy and synchronization of the system clock signal; in addition, the use of this clock calibration circuit and clock calibration method can effectively improve the calibration efficiency and reduce the system cost. power consumption.
  • FIG. 1 is a schematic structural diagram of a clock calibration circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another clock calibration circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another clock calibration circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another clock calibration circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another clock calibration circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another clock calibration circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a communication or positioning system provided by an embodiment of the present application.
  • IoT Internet of Things, Internet of Things.
  • LTE Long Term Evolution, Long Term Evolution, is the long-term evolution of the UMTS (Universal Mobile Telecommunications System, Universal Mobile Telecommunications System) technical standard formulated by the 3GPP (The 3rd Generation Partnership Project, 3rd Generation Partnership Project).
  • NR New Radio
  • 5G technology will achieve ultra-low latency and high reliability.
  • GNSS Global Navigation Satellite System
  • global navigation satellite system GNSS positioning requires the use of a set of satellites' pseudorange, ephemeris, satellite launch time and other observations, and must also know the user's clock offset.
  • the system In a communication or positioning system, the system usually has two modes of work and sleep.
  • the system uses a specific clock to determine the system clock signal; and when the system switches to sleep mode, the specific clock also enters the sleep mode, and the sleep mode makes the system clock signal a certain lag; When switching back to operating mode, the system clock signal needs to be calibrated.
  • FIG. 1 it is a schematic structural diagram of a clock calibration circuit provided by an embodiment of the present application.
  • the clock calibration circuit can be applied to a communication or positioning system, and specifically can be applied to IoT chips such as communication or positioning (eg, NR, LTE, WCDMA, GSM, GNSS) in the communication or positioning system.
  • the clock calibration circuit includes a clock generation module X, a modem, a clock generation module Y and a calibration module; the clock generation module X is connected with the modem, and the calibration module is connected with the modem and the clock generation module Y respectively.
  • the clock signals generated by the clock generation module X and the clock generation module Y are different. For example, the clock generation module X generates a 26M clock signal, and the clock generation module Y generates a 32K clock signal.
  • the modem determines the system clock signal based on the clock signal generated by the clock generating module X.
  • the calibration module is started to calculate the conversion relationship between the system clock signal (or the clock signal generated by the clock generation module X) and the clock signal generated by the clock generation module Y.
  • the startup calibration module determines the compensation value of the system clock signal according to the clock signal generated by the clock generation module Y in the system sleep mode, and sends the compensation value to the modem; the modem is based on the compensation value Calibrate the system clock signal to ensure the accuracy and synchronization of the system clock signal. It should be noted that the calibration module can also be set inside the modem.
  • the above-mentioned clock calibration circuit and clock calibration method need to start the calibration module frequently, but it takes a long time to start once, and frequent startup will seriously increase the power consumption of the system (or IoT chip).
  • the embodiment of the present application provides another clock calibration circuit, which can not only realize the calibration of the system clock signal when switching from the sleep mode to the working mode, ensure the accuracy and synchronization of the system clock signal, but also can effectively reduce the system power consumption.
  • a detailed description will be given below.
  • FIG. 2 is a schematic structural diagram of another clock calibration circuit provided by an embodiment of the present application.
  • the clock calibration circuit can also be applied to a communication or positioning system, and specifically can be applied to IoT chips such as communication or positioning (eg, NR, LTE, WCDMA, GSM, GNSS) in a communication or positioning system.
  • IoT chips such as communication or positioning (eg, NR, LTE, WCDMA, GSM, GNSS) in a communication or positioning system.
  • the clock calibration circuit 200 includes a clock generation module 20 , a clock frequency division module 30 and a modem 40 .
  • An input end of the clock frequency division module 30 is connected with the output end of the clock generation module 20, and the other input end is connected with an output end of the modem 40; the output end of the clock frequency division module 30 is connected with the input end of the modem 40; the clock generates An input terminal of the module 20 is connected to an output terminal of the modem 40 .
  • the clock frequency division module 30 stores configuration parameters corresponding to the sleep mode, where the configuration parameters include a frequency division coefficient and a frequency offset value.
  • the modem 40 generates a sleep mode indication signal and a first control signal when switching from the working mode to the sleep mode, outputs the sleep mode indication signal to the clock generation module 20 , and outputs the first control signal to the clock frequency division module 30 .
  • the clock generation module 20 switches from the working mode to the sleep mode in response to the sleep mode indication signal, generates a first clock signal in the sleep mode, and converts the first clock signal in the sleep mode to the sleep mode.
  • the signal is output to the clock frequency dividing module 30 .
  • the clock frequency dividing module 30 After receiving the first control signal sent by the modem 40 and the first clock signal in the sleep mode sent by the clock generation module 20, the clock frequency dividing module 30 responds to the first control signal based on the stored configuration parameters corresponding to the sleep mode. The frequency of the first clock signal in the sleep mode is divided to generate the second clock signal in the sleep mode, and the second clock signal in the sleep mode is output to the modem 40 . When the modem 40 is switched from the sleep mode to the working mode, the system clock signal is calibrated based on the second clock signal in the sleep mode output by the clock frequency dividing module 30 .
  • the clock frequency dividing module 30 specifically includes a configuration parameter register unit 31 , a selection control unit 32 and a frequency divider 33 .
  • the input end of the configuration parameter register unit 31 is connected with the output end of the clock generation module 20, and its output end is connected with an input end of the selection control unit 32; the other input end of the selection control unit 32 is connected with an output end of the modem 40, Its output end is connected with the input end of the frequency divider 33 ; the output end of the frequency divider 33 is connected with the input end of the modem 40 .
  • the configuration parameters corresponding to the sleep mode are stored in the configuration parameter register unit 31 .
  • the modem 40 when the modem 40 outputs the first control signal to the clock frequency dividing module 30, it specifically outputs the first control signal to the selection control unit 32 to control the selection control unit 32 to be electrically connected.
  • the clock generation module 20 When the clock generation module 20 outputs the first clock signal in the sleep mode to the clock frequency dividing module 30 , it specifically outputs the first clock signal in the sleep mode to the configuration parameter register unit 31 .
  • the configuration parameter register unit 31 outputs the stored configuration parameters corresponding to the sleep mode and the received first clock signal in the sleep mode to the frequency divider 33 through the electrically connected selection control unit 32 .
  • the frequency divider 33 divides the frequency of the first clock signal in the sleep mode based on the configuration parameters corresponding to the sleep mode, generates a second clock signal in the sleep mode, and outputs the second clock signal in the sleep mode to the modem 40 .
  • the selection control unit 32 is a switch of the first type.
  • the first type of switch may be a single pole single throw switch (SPST).
  • the control terminal 321 of the SPST switch is connected to an output terminal of the modem 40
  • the output terminal 322 is connected to the input terminal of the frequency divider
  • the input terminal 323 is connected to the output terminal of the configuration parameter register unit 31 .
  • the modem 40 uses the first control signal (that is, the control signal for instructing the switch to be closed) to control the single-pole single-throw switch to be closed after the input terminal 323 is electrically connected to the output terminal 322, so as to configure the configuration parameters corresponding to the sleep mode output by the configuration parameter register unit 31.
  • the first clock signal in the sleep mode is output to the frequency divider 33 .
  • the selection control unit 32 is a switch of the second type.
  • the second type of switch may be a single pole double throw switch (SPDT).
  • the configuration parameter register unit 31 includes a first configuration parameter register 311 and a second configuration parameter register 312.
  • the first configuration parameter register 311 stores configuration parameters corresponding to the sleep mode
  • the second configuration parameter register 312 stores configuration parameters corresponding to the working mode, including frequency coefficient and frequency offset value.
  • the configuration parameters corresponding to the sleep mode are different from the configuration parameters corresponding to the working mode.
  • the frequency offset value of the clock signal generated by the clock frequency dividing module 30 in the sleep mode relative to the clock signal generated by the clock generation module 20 is larger than that in the working mode.
  • the input ends of the first configuration parameter register 311 and the second configuration parameter register 312 are respectively connected to the output end of the clock generation module 20, the output end of the first configuration parameter register 311 is connected to the first input end 323 of the SPDT switch, and the first The output end of the second configuration parameter register 312 is connected to the second input end 324 of the SPDT switch; the output end 322 of the SPDT switch is connected to the input end of the frequency divider 33 , and the control end 321 is connected to an output end of the modem 40 .
  • the modem 40 uses the first control signal to control the SPDT switch to switch to the first connected state, that is, the first input end 323 of the SPDT switch is electrically connected to the output end 322, so that the first configuration parameter register unit 311 outputs the The configuration parameters corresponding to the sleep mode and the first clock signal in the sleep mode are output to the frequency divider 33 .
  • the modem 40 when the modem 40 is switched from the sleep mode to the working mode, the working mode indication signal and the second control signal are generated.
  • the modem 40 outputs the working mode indication signal to the clock generating module 20, and the clock generating module 20 switches from the sleep mode to the working mode in response to the working mode indicating signal, and generates the first clock signal in the working mode, and converts the first clock signal in the working mode to the working mode.
  • a clock signal is output to the first configuration parameter register 311 and the second configuration parameter register 312 .
  • the modem 40 outputs the second control signal to the SPDT switch, so as to control the SPDT switch to switch to the second connected state, that is, the second input terminal 324 of the SPDT switch is electrically connected to the output terminal 322, so as to connect the second input terminal 324 to the output terminal 322.
  • the configuration parameters corresponding to the working mode output by the second configuration parameter register and the first clock signal in the working mode are output to the frequency divider 33 .
  • the frequency divider 33 divides the frequency of the first clock signal in the working mode based on the configuration parameters corresponding to the working mode, generates a second clock signal in the working mode, and outputs the second clock signal in the working mode to the modem 40 .
  • the modem 40 may update or verify the system clock signal based on the second clock signal in the working mode output by the frequency divider 33 .
  • the clock calibration circuit 200 further includes a phase-locked loop 50 , an input end of the phase-locked loop 50 is connected to an output end of the clock generating module 20 , and an output end of the phase-locked loop 50 is connected to the modem 40 an input connection of .
  • the clock generating module 20 also outputs the generated first clock signal in the working mode to the phase-locked loop 50 , and outputs the generated first clock signal to the modem 40 after being processed by the phase-locked loop 50 .
  • the system clock signal is updated or verified based on the second clock signal in the working mode output by the frequency divider 33 and the clock signal output by the phase-locked loop 50 .
  • the first clock signal generated by the clock generation module 20 may be a 26M clock signal
  • the second clock signal generated by the clock frequency dividing module 30 (or frequency divider 33 ) may be a 32K clock signal.
  • the clock generation module 20 can be composed of a crystal resonator and a crystal oscillator, the crystal oscillator is connected with the crystal resonator, an input end of the crystal oscillator is connected with an output end of the modem, and its output end is connected with the input of the clock frequency dividing module 30 . end connection.
  • the crystal resonator and crystal oscillator cooperate to generate a specific type of clock signal (eg 26M clock signal).
  • the crystal oscillator is any one of a voltage-controlled crystal oscillator, a temperature-compensated crystal oscillator, a digital temperature-compensated crystal oscillator, and an oven-controlled crystal oscillator.
  • the crystal resonator is a 26M crystal resonator (26M Crystal)
  • the crystal oscillator is a digital temperature compensated crystal oscillator (DCXO).
  • DCXO digital temperature compensated crystal oscillator
  • the crystal oscillator may also be other types of crystal oscillators, and the type of the crystal oscillator is not limited in this embodiment of the present application.
  • the system clock in the embodiments of the present application may refer to the clock of the entire system of the IoT chip, which may be provided by a modem.
  • the first control signal and the sleep mode indication signal involved in the embodiments of the present application may be different signals or the same signal, but different function modules perform different actions in response to the same signal; similarly, the second control signal
  • the signal and the working mode indication signal may be different signals or the same signal.
  • the different functional modules involved in the embodiments of the present application are connected to the input terminal or output terminal of the same functional module, the different functional modules may be connected to the same input terminal or the same output terminal of the same functional module, or may be connected to the same input terminal or the same output terminal of the same functional module.
  • the input terminals of the phase-locked loop and the configuration parameter register unit may be connected to the same output terminal of the clock generation module, or may be connected to different output terminals of the clock generation module.
  • the connection relationship in the drawings is only an adaptive representation, and is not a limitation of the present application.
  • the clock calibration circuit includes the following functional modules:
  • 26M Crystal 26M crystal resonator, provides external 26M crystal input; DCXO, digital temperature compensated crystal oscillator; 26M Crystal and DCXO constitute the clock generation module described above, and cooperate to generate 26M clock signal.
  • the DCXO circuit is divided into normal mode (ie working mode) and LP mode (ie sleep mode).
  • normal mode after cdac calibration at room temperature, the 26M frequency offset at room temperature can be controlled within 0.4ppm; in LP mode
  • the 26M frequency offset will increase, but the frequency offset error between the two is theoretically a fixed value. The specific difference is determined by different types of crystals and different batches, which can be determined by actual measurement.
  • LP div reg the first configuration parameter register mentioned above, is used to store the frequency division coefficient corresponding to the conversion of 26M clock and 32K clock in LP mode, and the 32K clock generated by 26M clock and/or frequency division in LP mode. frequency offset.
  • Normal div reg the second configuration parameter register mentioned above, is used to store the frequency division coefficient corresponding to the conversion of the 26M clock and the 32K clock in the working mode, and the 32K clock generated by the 26M clock and/or frequency division in the Normal mode. frequency offset.
  • Divider the frequency divider mentioned above, is used to divide the 26M clock to generate 32K_less clock.
  • the frequency division coefficient can be adjusted according to Normal div reg/LP div reg. /LP div reg/Pd_xtal adjustment.
  • Pd_xtal the mode indication signal mentioned above, is an indication signal for entering the LP mode or the Normal mode. Modem, modem; PLL, phase-locked loop; selector, that is, the selection control unit described above.
  • connection relationship between the above-mentioned functional modules is shown in FIG. 6, and the description in the previous embodiment can also be referred to; the signal transmission and signal processing process involved in the clock calibration are completed cooperatively among the above-mentioned functional modules, and can also be referred to.
  • the descriptions in the foregoing embodiments are not repeated here.
  • the clock calibration circuit and the corresponding clock calibration method provided by the embodiments of the present application can be applied to communication or positioning systems.
  • the clock calibration circuit can be set in an IoT chip, and the IoT chip is set in a smart terminal
  • IoT chips or smart terminals can synchronize clocks with satellites or base stations, thereby ensuring the accuracy of data interaction.
  • the system clock signal can be calibrated when switching from the sleep mode to the working mode, thereby ensuring the accuracy and synchronization of the system clock signal ;
  • the clock calibration circuit and clock calibration method shown in Figure 1 since the clock signal used for calibration is obtained by dividing the clock frequency, there is no need for the calibration module to calculate the conversion relationship between the clock signals, and there is no need to set the calibration module. , and there is no frequent startup of the calibration module; therefore, using the clock calibration circuit and clock calibration method shown in any of Figures 2 to 6, the calibration efficiency is higher and the system power consumption is lower.
  • the structure of the clock calibration circuit in the embodiment of the present application can be improved and optimized according to actual needs.

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Abstract

一种时钟校准电路(200)，包括：相互连接的时钟产生模块(20)、时钟分频模块(30)和调制解调器(40)；调制解调器(40)切换为休眠模式时，将产生的休眠模式指示信号输出给时钟产生模块(20)，将产生的第一控制信号输出给时钟分频模块(30)；时钟产生模块(20)响应休眠模式指示信号切换为休眠模式，将产生的休眠模式下的第一时钟信号输出给时钟分频模块(30)；时钟分频模块(30)响应第一控制信号基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并输出给调制解调器(40)；调制解调器(40)切换为工作模式时，基于休眠模式下的第二时钟信号对系统时钟信号进行校准，从而不仅可以实现对系统时钟的校准，还可以有效提高校准效率和降低系统功耗。

Description

一种时钟校准电路 技术领域
本申请涉及电子技术领域，尤其涉及一种时钟校准电路。
背景技术
在通信或定位系统中，系统通常存在工作和休眠两种模式。系统正常工作时，系统利用某特定时钟来确定系统时钟信号；而当系统切换为休眠模式后，该特定时钟也进入休眠模式，休眠模式使得系统时钟信号存在一定的滞后；故当系统由休眠模式切换回工作模式时，需要对系统时钟信号进行校准。但如何对系统时钟信号进行校准是有待解决的问题。
发明内容
本申请实施例提供了一种时钟校准电路，不仅可以实现对系统时钟的校准，还可以有效提高校准效率和降低系统功耗。
本申请实施例提供的一种时钟校准电路，包括：时钟产生模块、时钟分频模块和调制解调器；所述时钟分频模块的输入端分别与所述时钟产生模块和所述调制解调器的输出端连接，输出端与所述调制解调器的输入端连接，所述时钟产生模块的输入端与所述调制解调器的输出端连接；其中：
所述调制解调器在由工作模式切换为休眠模式时，产生休眠模式指示信号和第一控制信号，将所述休眠模式指示信号输出给所述时钟产生模块，将所述第一控制信号输出给所述时钟分频模块；
所述时钟产生模块响应所述休眠模式指示信号由工作模式切换为休眠模式，并产生休眠模式下的第一时钟信号，以及将休眠模式下的第一时钟信号输出给所述时钟分频模块；
所述时钟分频模块响应所述第一控制信号基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给所述调制解调器；
所述调制解调器在由休眠模式切换为工作模式时，基于休眠模式下的第二 时钟信号对系统时钟信号进行校准。
在一实施例中，所述时钟分频模块包括配置参数寄存单元、选择控制单元和分频器；所述配置参数寄存单元的输入端与所述时钟产生模块的输出端连接，所述选择控制单元的输入端分别与所述配置参数寄存单元和所述调制解调器的输出端连接，输出端与所述分频器的输入端连接，所述分频器的输出端与所述调制解调器的输入端连接；其中，所述配置参数寄存单元存储休眠模式对应的配置参数。
在一实施例中，所述调制解调器将所述第一控制信号输出给所述选择控制单元，以控制所述选择控制单元电连通，将所述配置参数寄存单元输出的休眠模式对应的配置参数以及休眠模式下的第一时钟信号输出给所述分频器；
所述分频器基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给所述调制解调器。
在一实施例中，所述调制解调器将所述第一控制信号输出给所述选择控制单元，以控制所述选择控制单元电连通，将所述配置参数寄存单元输出的休眠模式对应的配置参数以及休眠模式下的第一时钟信号输出给所述分频器；
所述分频器基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给所述调制解调器。
在一实施例中，所述配置参数寄存单元包括第一配置参数寄存器和第二配置参数寄存器，所述选择控制单元为第二类型的开关；所述第一配置参数寄存器和第二配置参数寄存器的输入端分别与所述时钟产生模块的输出端连接，所述第一配置参数寄存器的输出端与所述第二类型的开关的第一输入端连接，所述第二配置参数寄存器的输出端与所述第二类型的开关的第二输入端连接，所述第二类型的开关的输出端与所述分频器的输入端连接，控制端与所述调制解调器的输出端连接；
所述调制解调器将所述第一控制信号输出给所述第二类型的开关，以控制所述第二类型的开关的输出端与第一输入端电连通，将所述第一配置参数寄存器输出的休眠模式对应的配置参数以及休眠模式下的第一时钟信号输出给所 述分频器；其中，所述第一配置参数寄存器存储休眠模式对应的配置参数。
在一实施例中，所述调制解调器在由休眠模式切换为工作模式时，产生工作模式指示信号和第二控制信号；
所述调制解调器将所述工作模式指示信号输出给所述时钟产生模块，所述时钟产生模块响应所述工作模式指示信号由休眠模式切换为工作模式，并产生工作模式下的第一时钟信号，以及将工作模式下的第一时钟信号输出给所述第一配置参数寄存器和第二配置参数寄存器；
所述调制解调器将所述第二控制信号输出给所述第二类型的开关，以控制所述第二类型的开关的输出端与第二输入端电连通，将所述第二配置参数寄存器输出的工作模式对应的配置参数以及工作模式下的第一时钟信号输出给所述分频器；
所述分频器基于工作模式对应的配置参数对工作模式下的第一时钟信号进行分频，产生工作模式下的第二时钟信号，并将工作模式下的第二时钟信号输出给所述调制解调器；其中，所述第二配置参数寄存器存储工作模式对应的配置参数。
在一实施例中，所述时钟校准电路还包括锁相环，所述锁相环的输入端与所述时钟产生模块的一输出端连接，输出端与所述调制解调器的输入端连接；
所述时钟产生模块还将工作模式下的第一时钟信号输出给所述锁相环；
所述调制解调器处于工作模式时，基于所述分频器输出的工作模式下的第二时钟信号以及所述锁相环输出的时钟信号对系统时钟信号进行更新。
在一实施例中，第一时钟信号为26M时钟信号，第二时钟信号为32K时钟信号。
在一实施例中，所述时钟产生模块包括晶体谐振器和晶体振荡器，所述晶体振荡器与所述晶体谐振器连接，所述晶体振荡器的输入端与所述调制解调器的输出端连接，输出端与所述时钟分频模块的输入端连接。
在一实施例中，所述晶体振荡器为压控晶体振荡器、温补晶体振荡器、数字温补晶体振荡器、恒温晶体振荡器中的任一种。
本申请实施例中，调制解调器在由工作模式切换为休眠模式时，将产生的休眠模式指示信号输出给时钟产生模块和时钟分频模块；时钟产生模块响应休 眠模式指示信号由工作模式切换为休眠模式，并将产生的休眠模式下的第一时钟信号输出给时钟分频模块；时钟分频模块响应休眠模式指示信号基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给调制解调器；调制解调器在由休眠模式切换为工作模式时，基于休眠模式下的第二时钟信号对系统时钟信号进行校准，从而可以实现在由休眠模式切换回工作模式时对系统时钟信号的校准，保证系统时钟信号的准确性和同步性；另外，采用此时钟校准电路以及时钟校准方式，可以有效提高校准效率和降低系统功耗。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种时钟校准电路的结构示意图；
图2是本申请实施例提供的另一种时钟校准电路的结构示意图；
图3是本申请实施例提供的又一种时钟校准电路的结构示意图；
图4是本申请实施例提供的又一种时钟校准电路的结构示意图；
图5是本申请实施例提供的又一种时钟校准电路的结构示意图；
图6是本申请实施例提供的又一种时钟校准电路的结构示意图；
图7是本申请实施例提供的一种通信或者定位系统的架构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
下面先对本申请实施例所涉及的一些术语进行介绍：
IoT：Internet of Things，物联网。
LTE：Long Term Evolution，长期演进，是由3GPP(The 3rd Generation Partnership Project，第三代合作伙伴计划)组织制定的UMTS(Universal Mobile Telecommunications System，通用移动通信系统)技术标准的长期演进。
NR：New Radio，基于OFDM的全新空口设计的全球性5G标准，也是下一代非常重要的蜂窝移动技术基础，5G技术将实现超低时延、高可靠性。
GNSS：Global Navigation Satellite System，全球导航卫星系统，GNSS定位需要利用一组卫星的伪距、星历、卫星发射时间等观测量，同时还必须知道用户钟差。
在通信或定位系统中，系统通常存在工作和休眠两种模式。系统正常工作时，系统利用某特定时钟来确定系统时钟信号；而当系统切换为休眠模式后，该特定时钟也进入休眠模式，休眠模式使得系统时钟信号存在一定的滞后；故当系统由休眠模式切换回工作模式时，需要对系统时钟信号进行校准。
如图1所示，为本申请实施例提供的一种时钟校准电路的结构示意图。该时钟校准电路可以应用于通信或定位系统中，具体可以应用于通信或定位系统中的通信或定位(如NR、LTE、WCDMA、GSM、GNSS)等IoT芯片中。该时钟校准电路包括时钟产生模块X、调制解调器、时钟产生模块Y和校准模块；时钟产生模块X和调制解调器连接，校准模块分别与调制解调器和时钟产生模块Y连接。时钟产生模块X和时钟产生模块Y产生的时钟信号不同，如时钟产生模块X产生的是26M时钟信号，时钟产生模块Y产生的是32K时钟信号。
当系统(包括调制解调器和时钟产生模块X)处于工作状态时，调制解调器基于时钟产生模块X产生的时钟信号确定系统时钟信号。当系统由工作模式切换为休眠模式时，启动校准模块计算系统时钟信号(或者说时钟产生模块X产生的时钟信号)与时钟产生模块Y产生的时钟信号之间的转换关系。当系统由休眠模式切换回工作模式时，启动校准模块根据时钟产生模块Y在系统休眠模式下产生的时钟信号确定系统时钟信号的补偿值，并将该补偿值发送给调制解调器；调制解调器基于该补偿值对系统时钟信号进行校准，以保证系统时钟信号的准确性和同步性。需要说明的是，校准模块也可以设置在调制解调器内部。
上述时钟校准电路和时钟校准方式需要频繁启动校准模块，但启动一次耗时较久，并且频繁启动会严重加剧系统(或者说IoT芯片)的功耗。
基于此，本申请实施例提供了另一种时钟校准电路，不仅可以实现在由休眠模式切换回工作模式时对系统时钟信号的校准，保证系统时钟信号的准确性和同步性，还可以有效降低系统功耗。以下进行详细说明。
请参阅图2，为本申请实施例提供的另一种时钟校准电路的结构示意图。该时钟校准电路同样可以应用于通信或定位系统中，具体可以应用于通信或定位系统中的通信或定位(如NR、LTE、WCDMA、GSM、GNSS)等IoT芯片中。
如图2所示，时钟校准电路200包括时钟产生模块20、时钟分频模块30和调制解调器40。时钟分频模块30的一输入端与时钟产生模块20的输出端连接，另一输入端与调制解调器40的一输出端连接；时钟分频模块30的输出端与调制解调器40的输入端连接；时钟产生模块20的输入端与调制解调器40的一输出端连接。时钟分频模块30存储休眠模式对应的配置参数，该配置参数包括分频系数和频偏值。
其中，调制解调器40在由工作模式切换为休眠模式时，产生休眠模式指示信号和第一控制信号，并将休眠模式指示信号输出给时钟产生模块20，将第一控制信号输出给时钟分频模块30。时钟产生模块20在接收到调制解调器40发送的休眠模式指示信号后，响应休眠模式指示信号由工作模式切换为休眠模式，并产生休眠模式下的第一时钟信号，以及将休眠模式下的第一时钟信号输出给时钟分频模块30。
时钟分频模块30在接收到调制解调器40发送的第一控制信号以及接收到时钟产生模块20发送的休眠模式下的第一时钟信号之后，响应第一控制信号基于其存储的休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给调制解调器40。调制解调器40在由休眠模式切换为工作模式时，基于时钟分频模块30输出的休眠模式下的第二时钟信号对系统时钟信号进行校准。
如图3所示，示出了时钟分频模块30的一种电路结构。时钟分频模块30具体包括配置参数寄存单元31、选择控制单元32和分频器33。配置参数寄存 单元31的输入端与时钟产生模块20的输出端连接，其输出端与选择控制单元32的一输入端连接；选择控制单元32的另一输入端与调制解调器40的一输出端连接，其输出端与分频器33的输入端连接；分频器33的输出端与调制解调器40的输入端连接。休眠模式对应的配置参数存储在配置参数寄存单元31中。
其中，调制解调器40将第一控制信号输出给时钟分频模块30时，具体是将第一控制信号输出给选择控制单元32，以控制选择控制单元32电连通。时钟产生模块20将休眠模式下的第一时钟信号输出给时钟分频模块30时，具体是将休眠模式下的第一时钟信号输出给配置参数寄存单元31。配置参数寄存单元31通过电连通的选择控制单元32，将其存储的休眠模式对应的配置参数以及接收到的休眠模式下的第一时钟信号输出给分频器33。分频器33基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给调制解调器40。
在一实施例中，选择控制单元32为第一类型的开关。如图4所示，第一类型的开关可以为单刀单掷开关(SPST)。单刀单掷开关的控制端321与调制解调器40的一输出端连接，输出端322与分频器的输入端连接，输入端323与配置参数寄存单元31的输出端连接。调制解调器40利用第一控制信号(即用于指示开关闭合的控制信号)控制单刀单掷开关闭合后输入端323与输出端322电连通，从而将配置参数寄存单元31输出的休眠模式对应的配置参数以及休眠模式下的第一时钟信号输出给分频器33。采用此电路结构，可以通过控制开关状态，灵活的控制时钟分频模块的启动与关闭，这样可以节省功耗。
在另一实施例中，选择控制单元32为第二类型的开关。如图5所示，第二类型的开关可以为单刀双掷开关(SPDT)。配置参数寄存单元31包括第一配置参数寄存器311和第二配置参数寄存器312，第一配置参数寄存器311存储休眠模式对应的配置参数，第二配置参数寄存器312存储工作模式对应的配置参数，包括分频系数和频偏值。休眠模式对应的配置参数与工作模式对应的配置参数不同，通常休眠模式下时钟分频模块30产生的时钟信号相对时钟产生模块20产生的时钟信号的频偏值，较工作模式下的更大。第一配置参数寄存器311和第二配置参数寄存器312的输入端分别与时钟产生模块20的输出 端连接，第一配置参数寄存器311的输出端与单刀双掷开关的第一输入端323连接，第二配置参数寄存器312的输出端与单刀双掷开关的第二输入端324连接；单刀双掷开关的输出端322与分频器33的输入端连接，控制端321与调制解调器40的一输出端连接。
其中，调制解调器40利用第一控制信号控制单刀双掷开关切换为第一连通状态，即单刀双掷开关的第一输入端323与输出端322电连通，从而将第一配置参数寄存单元311输出的休眠模式对应的配置参数以及休眠模式下的第一时钟信号输出给分频器33。
其中，对于图5所示的时钟校准电路，调制解调器40在由休眠模式切换为工作模式时，产生工作模式指示信号和第二控制信号。调制解调器40将工作模式指示信号输出给时钟产生模块20，时钟产生模块20响应该工作模式指示信号由休眠模式切换为工作模式，并产生工作模式下的第一时钟信号，以及将工作模式下的第一时钟信号输出给第一配置参数寄存器311和第二配置参数寄存器312。调制解调器40将第二控制信号输出给单刀双掷开关，以控制单刀双掷开关切换为第二连通状态，即单刀双掷开关的第二输入端324与输出端322电连通，从而将所述第二配置参数寄存器输出的工作模式对应的配置参数以及工作模式下的第一时钟信号输出给分频器33。分频器33基于工作模式对应的配置参数对工作模式下的第一时钟信号进行分频，产生工作模式下的第二时钟信号，并将工作模式下的第二时钟信号输出给调制解调器40。在可行的实施例中，调制解调器40可以基于分频器33输出的工作模式下的第二时钟信号对系统时钟信号进行更新或者校验。
在另一可行的实施例中，如图5所示，时钟校准电路200还包括锁相环50，锁相环50的输入端与时钟产生模块20的一输出端连接，其输出端与调制解调器40的一输入端连接。时钟产生模块20还将产生的工作模式下的第一时钟信号输出给锁相环50，经过锁相环50的处理之后输出给调制解调器40。调制解调器40处于工作模式时，基于分频器33输出的工作模式下的第二时钟信号以及锁相环50输出的时钟信号对系统时钟信号进行更新或者校验。
本申请实施例中，时钟产生模块20产生的第一时钟信号可以为26M时钟信号，时钟分频模块30(或者说分频器33)产生的第二时钟信号可以为32K 时钟信号。时钟产生模块20可以由晶体谐振器和晶体振荡器组成，晶体振荡器与晶体谐振器连接，晶体振荡器的一输入端和调制解调器的一输出端连接，其输出端与时钟分频模块30的输入端连接。晶体谐振器和晶体振荡器协作产生特定类型的时钟信号(如26M时钟信号)。在可行的实施例中，晶体振荡器为压控晶体振荡器、温补晶体振荡器、数字温补晶体振荡器、恒温晶体振荡器中的任一种。如图6所示，晶体谐振器为26M晶体谐振器(26M Crystal)，晶体振荡器为数字温补晶体振荡器(DCXO)。需要说明的是，该晶体振荡器还可以是其他类型的晶体振荡器，本申请实施例对晶体振荡器的类型不作限定。
需要说明的是，本申请实施例中的系统时钟可以是指IoT芯片整个系统的时钟，其可以由调制解调器提供。本申请实施例所涉及的第一控制信号和休眠模式指示信号可以是不同的信号，也可以是相同的信号，只是不同的功能模块响应该相同信号所执行的动作不同；同理，第二控制信号和工作模式指示信号可以是不同的信号，也可以是相同的信号。另外，本申请实施例所涉及的不同功能模块与同一功能模块的输入端或者输出端连接时，该不同功能模块可以连接的是该同一功能模块的同一输入端或者同一输出端，也可以连接的是该同一功能模块的不同输入端或者不同输出端。如图5和图6所示，锁相环和配置参数寄存单元的输入端可以与时钟产生模块的同一输出端连接，也可以与时钟产生模块的不同输出端连接。附图中的连接关系仅是适应性表示，并不是对本申请的限制。
下面结合图6，以采用32K_less时钟为例对上述时钟校准电路的各个功能模块进行说明。如图6所示：时钟校准电路包括如下功能模块：
26M Crystal，26M晶体谐振器，提供外部26M晶体输入；DCXO，数字温补晶体振荡器；26M Crystal和DCXO构成前文所述的时钟产生模块，协作产生26M时钟信号。为低功耗考虑，DCXO电路分normal模式(即工作模式)和LP模式(即睡眠模式)，normal模式时在常温下经过cdac校准后，常温26M频偏可控制在0.4ppm内；LP模式下26M频偏会增加，但两者间的频偏误差理论上是一个固定值，具体差值由不同型号不同批次晶体决定，可以通过实测确定。
LP div reg，即前文所述的第一配置参数寄存器，用于存储LP模式下26M 时钟和32K时钟转换所对应的分频系数，以及LP模式下26M时钟和/或分频产生的32K时钟的频偏。Normal div reg，即前文所述的第二配置参数寄存器，用于存储工作模式下26M时钟和32K时钟转换所对应的分频系数，以及Normal模式下26M时钟和/或分频产生的32K时钟的频偏。Divider，即前文所述的分频器，用于将26M时钟分频产生32K_less时钟，分频系数可根据Normal div reg/LP div reg调整，分频输出得到的32K_less的频偏可根据Normal div reg/LP div reg/Pd_xtal调整。Pd_xtal，即前文所述的模式指示信号，为进入LP模式或者Normal模式的指示信号。Modem，调制解调器；PLL，锁相环；选择器，即前文所述的选择控制单元。
其中，上述各个功能模块之间的连接关系如图6所示，亦可参考前文实施例中的描述；上述各个功能模块之间协作完成时钟校准所涉及的信号传输以及信号处理过程，亦可参考前文实施例中的描述，此处不再赘述。
本申请实施例提供的时钟校准电路以及相应的时钟校准方式均可应用于通信或定位系统中，如图7所示，该时钟校准电路可以设置在IoT芯片中，该IoT芯片设置于一智能终端上，基于钟校准电路所实现的时钟校准方式，可以使得在通信或者定位应用中，IoT芯片或者说智能终端能够与卫星或者基站实现时钟同步，从而保证数据交互的准确性。
采用图2-图6中任一图所示的时钟校准电路以及时钟校准方式，可以实现在由休眠模式切换回工作模式时对系统时钟信号的校准，从而保证系统时钟信号的准确性和同步性；另外，相对图1所示的时钟校准电路以及时钟校准方式，由于用于校准的时钟信号时通过时钟分频得到的，所以无需校准模块进行时钟信号之间转换关系的计算，无需设置校准模块，更不存在校准模块的频繁启动；故采用图2-图6中任一图所示的时钟校准电路以及时钟校准方式，校准效率更高，系统功耗更低。
需要说明的是，对于前述的各个实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某一些动作可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
本申请实施例时钟校准电路的结构可以根据实际需要进行改进和优化。
以上所述是本申请的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (20)

  1. 一种时钟校准电路，其特征在于，所述时钟校准电路包括时钟产生模块、时钟分频模块和调制解调器；所述时钟分频模块的输入端分别与所述时钟产生模块和所述调制解调器的输出端连接，输出端与所述调制解调器的输入端连接，所述时钟产生模块的输入端与所述调制解调器的输出端连接；其中：
    所述调制解调器在由工作模式切换为休眠模式时，产生休眠模式指示信号和第一控制信号，将所述休眠模式指示信号输出给所述时钟产生模块，将所述第一控制信号输出给所述时钟分频模块；
    所述时钟产生模块响应所述休眠模式指示信号由工作模式切换为休眠模式，并产生休眠模式下的第一时钟信号，以及将休眠模式下的第一时钟信号输出给所述时钟分频模块；
    所述时钟分频模块响应所述第一控制信号基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给所述调制解调器；
    所述调制解调器在由休眠模式切换为工作模式时，基于休眠模式下的第二时钟信号对系统时钟信号进行校准。
  2. 如权利要求1所述的时钟校准电路，其特征在于，所述时钟分频模块包括配置参数寄存单元、选择控制单元和分频器；所述配置参数寄存单元的输入端与所述时钟产生模块的输出端连接，所述选择控制单元的输入端分别与所述配置参数寄存单元和所述调制解调器的输出端连接，输出端与所述分频器的输入端连接，所述分频器的输出端与所述调制解调器的输入端连接；其中，所述配置参数寄存单元存储休眠模式对应的配置参数。
  3. 如权利要求2所述的时钟校准电路，其特征在于，所述调制解调器将所述第一控制信号输出给所述选择控制单元，以控制所述选择控制单元电连通，将所述配置参数寄存单元输出的休眠模式对应的配置参数以及休眠模式下的第一时钟信号输出给所述分频器；
    所述分频器基于休眠模式对应的配置参数对休眠模式下的第一时钟信号进行分频，产生休眠模式下的第二时钟信号，并将休眠模式下的第二时钟信号输出给所述调制解调器。
  4. 如权利要求3所述的时钟校准电路，其特征在于，所述选择控制单元为第一类型的开关，所述第一类型的开关的输入端与所述配置参数寄存单元的输出端连接，输出端与所述分频器的输入端连接，控制端与所述调制解调器的输出端连接；所述调制解调器将所述第一控制信号输出给所述第一类型的开关，以控制所述第一类型的开关闭合后电连通。
  5. 如权利要求3所述的时钟校准电路，其特征在于，所述配置参数寄存单元包括第一配置参数寄存器和第二配置参数寄存器，所述选择控制单元为第二类型的开关；所述第一配置参数寄存器和第二配置参数寄存器的输入端分别与所述时钟产生模块的输出端连接，所述第一配置参数寄存器的输出端与所述第二类型的开关的第一输入端连接，所述第二配置参数寄存器的输出端与所述第二类型的开关的第二输入端连接，所述第二类型的开关的输出端与所述分频器的输入端连接，控制端与所述调制解调器的输出端连接；
    所述调制解调器将所述第一控制信号输出给所述第二类型的开关，以控制所述第二类型的开关的输出端与第一输入端电连通，将所述第一配置参数寄存器输出的休眠模式对应的配置参数以及休眠模式下的第一时钟信号输出给所述分频器；其中，所述第一配置参数寄存器存储休眠模式对应的配置参数。
  6. 如权利要求5所述的时钟校准电路，其特征在于，所述调制解调器在由休眠模式切换为工作模式时，产生工作模式指示信号和第二控制信号；
    所述调制解调器将所述工作模式指示信号输出给所述时钟产生模块，所述时钟产生模块响应所述工作模式指示信号由休眠模式切换为工作模式，并产生工作模式下的第一时钟信号，以及将工作模式下的第一时钟信号输出给所述第一配置参数寄存器和第二配置参数寄存器；
    所述调制解调器将所述第二控制信号输出给所述第二类型的开关，以控制 所述第二类型的开关的输出端与第二输入端电连通，将所述第二配置参数寄存器输出的工作模式对应的配置参数以及工作模式下的第一时钟信号输出给所述分频器；
    所述分频器基于工作模式对应的配置参数对工作模式下的第一时钟信号进行分频，产生工作模式下的第二时钟信号，并将工作模式下的第二时钟信号输出给所述调制解调器；其中，所述第二配置参数寄存器存储工作模式对应的配置参数。
  7. 如权利要求6所述的时钟校准电路，其特征在于，所述时钟校准电路还包括锁相环，所述锁相环的输入端与所述时钟产生模块的一输出端连接，输出端与所述调制解调器的输入端连接；
    所述时钟产生模块还将工作模式下的第一时钟信号输出给所述锁相环；
    所述调制解调器处于工作模式时，基于所述分频器输出的工作模式下的第二时钟信号以及所述锁相环输出的时钟信号对系统时钟信号进行更新。
  8. 如权利要求1-7中任一项所述的时钟校准电路，其特征在于，第一时钟信号为26M时钟信号，第二时钟信号为32K时钟信号。
  9. 如权利要求1-7中任一项所述的时钟校准电路，其特征在于，所述时钟产生模块包括晶体谐振器和晶体振荡器，所述晶体振荡器与所述晶体谐振器连接，所述晶体振荡器的输入端与所述调制解调器的输出端连接，输出端与所述时钟分频模块的输入端连接。
  10. 如权利要求9所述的时钟校准电路，其特征在于，所述晶体振荡器为压控晶体振荡器、温补晶体振荡器、数字温补晶体振荡器、恒温晶体振荡器中的任一种。
  11. 如权利要求4所述的时钟校准电路，其特征在于，所述第一类型的开关为单刀单掷开关。
  12. 如权利要求5-7中任一项所述的时钟校准电路，其特征在于，所述第二类型的开关为单刀双掷开关。
  13. 如权利要求6-10中任一项所述的时钟校准电路，其特征在于，所述工作模式对应的配置参数包括工作模式对应的分频系数和频偏值；所述休眠模式对应的配置参数包括休眠模式对应的分频系数和频偏值；所述工作模式对应的频偏值大于所述休眠模式对应的频偏值。
  14. 如权利要求6-10中任一项所述的时钟校准电路，其特征在于，所述调制解调器基于所述分频器输出的工作模式下的第二时钟信号对系统时钟信号进行更新或者校验。
  15. 如权利要求7所述的时钟校准电路，其特征在于，所述锁相环的输入端和所述配置参数寄存单元的输入端，与所述时钟产生模块的同一输出端连接。
  16. 如权利要求7所述的时钟校准电路，其特征在于，所述锁相环的输入端和所述配置参数寄存单元的输入端，与所述时钟产生模块的不同输出端连接。
  17. 如权利要求1-16中任一项所述的时钟校准电路，其特征在于，所述时钟校准电路应用于通信或定位系统。
  18. 如权利要求1-17中任一项所述的时钟校准电路，其特征在于，所述时钟校准电路应用于通信或定位系统中的IoT芯片。
  19. 一种芯片，其特征在于，所述芯片包括如权利要求1-18中任一项所述的时钟校准电路。
  20. 一种模组设备，其特征在于，所述模组设备包括通信模组、电源模组以及芯片模组，其中：
    所述电源模组用于为所述模组设备提供电能；
    所述通信模组用于进行模组设备内部通信，或者用于所述模组设备与外部设备进行通信；
    所述芯片模组包括如权利要求1-18中任一项所述的时钟校准电路。
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CN205179018U (zh) * 2015-12-08 2016-04-20 四川九洲电器集团有限责任公司 一种信号发生器
CN112422126A (zh) * 2020-11-27 2021-02-26 紫光展锐(重庆)科技有限公司 一种时钟校准电路

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