WO2022110757A1 - 电位产生电路、反相器、延时电路和逻辑门电路 - Google Patents

电位产生电路、反相器、延时电路和逻辑门电路 Download PDF

Info

Publication number
WO2022110757A1
WO2022110757A1 PCT/CN2021/098722 CN2021098722W WO2022110757A1 WO 2022110757 A1 WO2022110757 A1 WO 2022110757A1 CN 2021098722 W CN2021098722 W CN 2021098722W WO 2022110757 A1 WO2022110757 A1 WO 2022110757A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
terminal
potential
substrate
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/098722
Other languages
English (en)
French (fr)
Inventor
朱磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US17/446,302 priority Critical patent/US11681313B2/en
Publication of WO2022110757A1 publication Critical patent/WO2022110757A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks

Definitions

  • Figure 1 is a schematic diagram of an input signal and an output signal passing through a delay circuit. After the input signal passes through the delay circuit, a delayed signal is output. As shown in Figure 1, the output signal is the signal after the input signal is delayed by a time T. Figure 1 shows the case where both the rising edge and the falling edge of the input signal are delayed by time T, and there is another case where only the rising edge of the input signal is delayed by time T or only the falling edge of the input signal is delayed by time T.
  • the present application provides a potential generating circuit that can output a potential that varies with any one of a power supply voltage, an operating temperature, and a manufacturing process.
  • the present application provides an inverter, which can make the variation of the rising edge delay time or the falling edge delay time of the inverter smaller, and improve the inverter's ability to control the accuracy of the delay time.
  • the present application provides a delay circuit to reduce the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the rising edge delay time and/or the falling edge delay time of the delay circuit, so that the rising edge delay time and/or The variation in the falling edge delay time is small.
  • the first transistor is a P-type transistor
  • the second transistor is an N-type transistor
  • the source terminal of the first transistor is connected to the first voltage node
  • the source terminal of the second transistor is connected to the second voltage node
  • the drain terminal of the first transistor is connected to the drain terminal of the second transistor
  • the substrate terminal of the second transistor is connected to the second voltage node.
  • the third voltage node is connected to a power supply terminal
  • the first reference voltage is connected to a power supply terminal
  • the potential of the third voltage node is greater than the potential of the first reference voltage
  • the buffer is connected to the output terminal and outputs a substrate potential, the value of the substrate potential is equal to the potential value of the substrate terminal of the first transistor.
  • a potential generating circuit comprising:
  • a first transistor and a second transistor the potential of the substrate end of the second transistor varies with a first parameter, and the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit item;
  • the gate terminal of the first transistor is connected to the drain terminal of the first transistor
  • the gate terminal of the second transistor is connected to the drain terminal of the second transistor
  • the substrate terminal of the second transistor serves as the The output terminal of the potential generating circuit.
  • a first transistor and a second transistor are provided, the gate terminal of the first transistor is connected to the drain terminal of the first transistor, the gate terminal of the second transistor is connected to the drain terminal of the second transistor, and the second transistor T2
  • the potential of the substrate end of the second transistor changes with the change of the first parameter
  • the substrate end of the second transistor is used as the output end of the potential generating circuit. Since the potential of the substrate end of the second transistor changes with the change of the first parameter, the output The terminal can output a potential that changes with any one of supply voltage, operating temperature and manufacturing process.
  • the first parameter is a power supply voltage or an operating temperature of the potential generating circuit
  • the potential of the substrate end of the second transistor decreases as the first parameter increases
  • the substrate of the second transistor decreases.
  • the potential of the bottom end increases as the first parameter decreases.
  • the first transistor is a P-type transistor
  • the second transistor is an N-type transistor
  • the source terminal of the first transistor is connected to the first voltage node
  • the source terminal of the second transistor is connected to the second voltage node
  • the drain terminal of the first transistor is connected to the drain terminal of the second transistor
  • the substrate terminal of the first transistor is connected to the first voltage node.
  • a constant current source the first end of the constant current source is connected to the third voltage node, and the second end of the constant current source is connected to the second voltage node.
  • the error amplifier forms a feedback loop with the second transistor, and the substrate terminal of the second transistor is connected to a voltage node of the first feedback loop.
  • the negative input terminal of the error amplifier is connected to the second voltage node
  • the positive input terminal of the error amplifier is connected to the first reference voltage
  • the output terminal of the error amplifier is connected to the substrate of the second transistor end.
  • the first voltage node is connected to a power supply terminal, the first reference voltage is connected to a ground terminal, and the potential of the third voltage node is lower than the potential of the first reference voltage.
  • the present application provides a delay circuit, comprising:
  • the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, and the substrate terminal of the fourth transistor is connected to the potential of the substrate terminal of the first transistor , the substrate terminal of the fifth transistor is connected to the ground terminal, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.
  • the ratio of the channel length of the first transistor to the channel length of the fourth transistor denotes the ratio of the channel length of the second transistor to the channel length of the fifth transistor.
  • the ratio is L
  • the ratio is N
  • the H equals the L
  • the M equals the N.
  • the potential of the substrate end of the first transistor in the potential generating circuit can vary with any one of the supply voltage, operating temperature and manufacturing process, it can be used for the P in the inverter.
  • the substrate terminal of the P-type transistor provides the substrate potential that changes with the change of the first parameter, so the current flowing through the P-type transistor in the inverter can be adjusted, and the change value of the current flowing through the P-type transistor in the inverter can be adjusted. Compensation is performed so that the change of the rising edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the precision of the rising edge delay time is improved.
  • the present application provides a delay circuit, including:
  • the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, and the substrate terminal of the fourth transistor is connected to the potential of the substrate terminal of the first transistor , the substrate terminal of the fifth transistor is connected to the power terminal, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.
  • the delay circuit since the potential of the substrate end of the second transistor in the potential generating circuit can be changed with any one of the supply voltage, the operating temperature and the manufacturing process, it can be used for N in the inverter.
  • the substrate terminal of the N-type transistor provides the substrate potential that changes with the change of the first parameter, so the current flowing through the N-type transistor in the inverter can be adjusted, and the change value of the current flowing through the N-type transistor in the inverter can be adjusted. Compensation is performed so that the change of the falling edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the precision of the falling edge delay time is improved.
  • the ratio of the channel length of the first transistor to the channel length of the fourth transistor denotes the ratio of the channel length of the second transistor to the channel length of the fifth transistor.
  • the ratio is L
  • the ratio is N
  • the H equals the L
  • the M equals the N.
  • the present application provides a delay circuit, comprising:
  • the first potential generating circuit is the potential generating circuit according to any one of the first aspect and the embodiments of the first aspect;
  • the second potential generating circuit is the potential generating circuit according to any one of the embodiments of the second aspect and the second aspect;
  • the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, and the substrate end of the fourth transistor is connected to the first potential generating circuit in the first potential generating circuit.
  • the potential of the substrate terminal of a transistor, the substrate terminal of the fifth transistor is connected to the potential of the substrate terminal of the second transistor in the second potential generating circuit, the fourth transistor is a P-type transistor, and the fifth transistor is a P-type transistor.
  • the transistors are N-type transistors.
  • the delay circuit provided by the present application can simultaneously compensate the influence of any changes in power supply voltage, operating temperature and manufacturing process on the rising edge delay time and the falling edge delay time, so that the rising edge delay time T and the falling edge delay time
  • the change of the delay time T is small, which improves the control ability of the delay circuit on the accuracy of the rising edge delay time and the falling edge delay time.
  • the ratio of the channel length of the first transistor in the first potential generating circuit to the channel length of the fourth transistor denote the ratio of the second transistor in the first potential generating circuit as H1.
  • the ratio of the channel length to the channel length of the fifth transistor is L1
  • the ratio of the channel width of the first transistor in the first potential generating circuit to the channel width of the fourth transistor is M1
  • N1 Denote the ratio of the channel width of the second transistor in the first potential generating circuit to the channel width of the fifth transistor as N1
  • the H1 is equal to the L1
  • the M1 is equal to the N1;
  • the ratio of the channel length of the first transistor in the second potential generating circuit to the channel length of the fourth transistor denote the channel length of the second transistor in the second potential generating circuit and
  • the ratio of the channel lengths of the fifth transistor is L2
  • the ratio of the channel width of the first transistor in the second potential generating circuit to the channel width of the fourth transistor is M2
  • the first transistor is denoted as M2.
  • the ratio of the channel width of the second transistor to the channel width of the fifth transistor in the two-potential generating circuit is N2
  • the H2 is equal to the L2
  • the M2 is equal to the N2.
  • the application provides an inverter, comprising:
  • the source terminal of the P-type transistor is connected to the power supply terminal
  • the drain terminal of the P-type transistor is connected to the drain terminal of the N-type transistor
  • the source terminal of the N-type transistor is connected to the ground terminal
  • the gate terminal of the P-type transistor is connected to the gate terminal of the N-type transistor and is used as the input terminal of the inverter, and the drain terminal of the P-type transistor is used as the output terminal of the inverter;
  • the substrate terminal of the P-type transistor is connected to the substrate potential
  • the substrate terminal of the N-type transistor is connected to the ground terminal
  • the substrate potential varies with a first parameter
  • the first parameter is the inversion Any of the power supply voltage, operating temperature and manufacturing process of the device.
  • the first parameter is the power supply voltage or operating temperature of the inverter
  • the substrate potential increases as the first parameter increases, and the substrate potential decreases as the first parameter increases.
  • the substrate potential can be changed with any one of the power supply voltage, the operating temperature and the manufacturing process, it can provide the P-type transistor with the substrate potential that changes with the change of the first parameter.
  • the substrate end of TP2 so the current flowing through the P-type transistor TP2 of the inverter can be adjusted, and the change value of the current flowing through the P-type transistor TP2 can be compensated, so that the change of the rising edge delay time T of the inverter is small. , to improve the inverter's ability to control the accuracy of the rising edge delay time.
  • the application provides an inverter, comprising:
  • the source terminal of the P-type transistor is connected to the power supply terminal
  • the drain terminal of the P-type transistor is connected to the drain terminal of the N-type transistor
  • the source terminal of the N-type transistor is connected to the ground terminal
  • the gate terminal of the P-type transistor is connected to the gate terminal of the N-type transistor and is used as the input terminal of the inverter, and the drain terminal of the P-type transistor is used as the output terminal of the inverter;
  • the substrate terminal of the N-type transistor is connected to the substrate potential
  • the substrate terminal of the P-type transistor is connected to the power supply terminal
  • the substrate potential varies with a first parameter
  • the first parameter is the inversion Any of the power supply voltage, operating temperature and manufacturing process of the device.
  • the substrate potential can be changed with any one of the power supply voltage, the operating temperature and the manufacturing process, it can provide the N-type transistor with the substrate potential that changes with the change of the first parameter.
  • the substrate end of TN2 so the current flowing through the N-type transistor TN2 of the inverter can be adjusted, and the change value of the current flowing through the N-type transistor TN2 can be compensated, so that the change of the falling edge delay time T of the inverter is small. , to improve the inverter's ability to control the accuracy of the falling edge delay time.
  • the first parameter is the power supply voltage or operating temperature of the inverter
  • the first substrate potential decreases as the first parameter decreases, and the second substrate potential increases as the first parameter decreases.
  • the present application provides a delay circuit, comprising:
  • One end of the capacitor is connected to the output end of the inverter, and the other end of the capacitor is connected to the power supply end or the ground end.
  • the capacitor is a capacitor array.
  • the delay circuit provided by the present application can compensate the change value of the current flowing through the P-type transistor TP2 of the inverter, so that the change of the delay time T of the rising edge of the inverter is small, which can make the delay time of the delay circuit less.
  • the change of the rising edge delay time T is small, which improves the control ability of the delay circuit to the accuracy of the rising edge delay time.
  • a logic gate circuit comprising:
  • the substrate terminal of the P-type transistor is connected to the substrate potential
  • the substrate terminal of the N-type transistor is connected to the ground terminal
  • the substrate potential varies with the change of the first parameter, so that all The change value of the delay time from the input end to the output end of the logic gate circuit with the change of the first parameter is within a first range
  • the first parameter includes the power supply voltage of the logic gate circuit, the operating temperature and the manufacturing process. either.
  • the logic gate circuit provided by the present application can make the rising edge delay time of the logic gate circuit from the input end to the output end change less when any one of the power supply voltage, the operating temperature and the manufacturing process changes, and the logic gate circuit can improve the efficiency of the logic gate circuit.
  • the ability to control the accuracy of the rising edge delay time can be made.
  • the present application provides a logic gate circuit, comprising:
  • the substrate terminal of the N-type transistor is connected to the substrate potential
  • the substrate terminal of the P-type transistor is connected to the power supply terminal
  • the substrate potential changes with the change of the first parameter, so that all
  • the change value of the delay time from the input end to the output end of the logic gate circuit with the change of the first parameter is within a first range
  • the first parameter includes the power supply voltage of the logic gate circuit, the operating temperature and the manufacturing process. either.
  • the logic gate circuit provided by the present application can make the falling edge delay time of the logic gate circuit from the input end to the output end change less when any one of the power supply voltage, the operating temperature and the manufacturing process changes, and the logic gate circuit can improve the performance of the logic gate circuit.
  • the ability to control the accuracy of the falling edge delay time can be made.
  • 1 is a schematic diagram of an input signal and an output signal passing through a delay circuit
  • FIG. 2 is a schematic diagram of an input signal and an output signal passing through a delay circuit
  • FIG. 3 is a schematic diagram of an input signal and an output signal passing through a delay circuit
  • FIG. 4 is a schematic structural diagram of a potential generating circuit according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a potential generating circuit according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • FIG. 14 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • FIG. 15 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • 16 is a schematic structural diagram of an inverter provided by an embodiment of the application.
  • 17 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • FIG. 18 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • 19 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • 20 is a schematic structural diagram of a potential generating circuit according to an embodiment of the application.
  • 21 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • 22 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • FIG. 23 is a schematic structural diagram of a potential generating circuit according to an embodiment of the application.
  • 24 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • 25 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • 26 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • FIG. 27 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • FIG. 28 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • FIG. 29 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • FIG. 30 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • 31 is a schematic structural diagram of an inverter provided by an embodiment of the present application.
  • 32 is a schematic structural diagram of an inverter provided by an embodiment of the application.
  • FIG. 33 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • FIG. 34 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • FIG. 35 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • FIG. 36 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • 38 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • FIG. 39 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • 40 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • 41 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • 43 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • 44 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • 45 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • 46 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • 47 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • 49 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • FIG. 50 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • FIG. 51 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • FIG. 52 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • 53 is a schematic structural diagram of a control circuit provided by an embodiment of the application.
  • FIG. 54 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of an input signal and an output signal passing through a delay circuit. As shown in Figure 1, the delay time T between the rising edge of the output signal and the rising edge of the input signal is the rising edge edge delay time.
  • Falling edge delay time as shown in Figure 1, the delay time T between the falling edge of the output signal and the falling edge of the input signal is the falling edge delay time.
  • the delay circuit provided by the present application can realize the delay time T for both the rising edge and the falling edge of the input signal, and the width of the pulse signal remains unchanged. As shown in FIG. 1, it can also realize the delay time T for the rising edge of the input signal. , the falling edge delay time T of the input signal can also be realized.
  • 2 is a schematic diagram of an input signal and an output signal passing through a delay circuit. As shown in FIG. 2 , the rising edge of the input signal is delayed by time T to obtain the output signal, and the width of the pulse signal is shortened by time T.
  • 3 is a schematic diagram of an input signal and an output signal passing through a delay circuit. As shown in FIG. 3 , the falling edge of the input signal is delayed by time T to obtain an output signal, and the width of the pulse signal is extended by time T. It should be noted that, only one cycle of the pulse signal is shown in FIG. 1 to FIG. 3 .
  • the delay circuit provided by the present application can be applied to scenarios where the delay time of the delay circuit needs to be precisely controlled, for example, it can be applied to DRAM, and can simultaneously compensate for changes in power supply voltage, operating temperature and any one of the manufacturing process to delay the delay.
  • the influence of time makes the change of the delay time T smaller, and the control ability of the delay circuit to the accuracy of the delay time is improved.
  • the delay unit in the existing delay circuit includes an inverter, and the inverter is composed of two transistors (P-type transistor and N-type transistor).
  • the delay time T of the output signal passing through the delay circuit will vary with the power supply voltage. , the working temperature and the change of the manufacturing process have a large change, which will affect the accuracy of the delay time.
  • the present application starts from the structure of the delay unit. When the power supply voltage, the operating temperature and the manufacturing process change, the current flowing through the two transistors of the inverter will change, and the delay will be caused.
  • the delay circuit includes a potential generating circuit and a delay unit
  • the potential generating circuit includes a first transistor and a second transistor
  • the potential of the substrate end of the first transistor varies with the first parameter
  • the potential of the substrate end of the second transistor varies with the change of the first parameter
  • the first parameter is any one of the power supply voltage, the working temperature and the manufacturing process of the potential generating circuit.
  • the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor, and the substrate end of the fifth transistor is connected to the second transistor The potential of the substrate terminal of the transistor.
  • the substrate potential of the fourth transistor can be provided with the substrate potential varying with the variation of the first parameter. terminal, the potential of the substrate terminal of the second transistor may vary with any one of the supply voltage, operating temperature and manufacturing process, so that the substrate potential varying with the variation of the first parameter can be provided to the substrate of the fifth transistor Therefore, the current flowing through the two transistors of the first inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the change of the delay time T of the delay circuit is small, Improve the delay circuit's ability to control the delay time accuracy.
  • FIG. 4 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • the potential generating circuit of this embodiment may include: a first transistor T1 and a second transistor T2, wherein the first transistor T1
  • the potential of the substrate end of the second transistor T2 changes with the change of the first parameter.
  • the first parameter is any one of the power supply voltage of the potential generating circuit, the operating temperature and the manufacturing process.
  • the potential of the substrate end of the second transistor T2 changes with the change of the first parameter. Variety.
  • the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the substrate terminal of the first transistor T1 is used as the first output terminal of the potential generating circuit, and the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2.
  • the substrate terminal of the second transistor T2 serves as the second output terminal of the potential generating circuit.
  • the potential of the substrate terminal of the first transistor T1 is the potential output by the first output terminal
  • the potential of the substrate terminal of the second transistor T2 is the potential output by the second output terminal.
  • the potential of the substrate end of the first transistor T1 changes with the change of the first parameter
  • the potential of the substrate end of the second transistor T2 changes with the change of the first parameter. Therefore, the potential generating circuit provided in this embodiment can output the output voltage that varies with the supply voltage, Potential that changes with any change in operating temperature and manufacturing process.
  • the potential of the substrate end of the first transistor T1 changes with the change of the first parameter
  • the potential of the substrate end of the second transistor T2 changes with the first parameter
  • the change can be specifically: the potential of the substrate end of the first transistor T1 increases as the first parameter increases, and the potential of the substrate end of the first transistor T1 decreases as the first parameter decreases, that is, the two are in a proportional relationship ;
  • the potential of the substrate end of the second transistor T2 decreases as the first parameter increases, and the potential of the substrate end of the second transistor T2 increases as the first parameter decreases.
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor.
  • the source terminal of the first transistor T1 is connected to the first voltage node
  • the source terminal of the second transistor T2 is connected to the second voltage node
  • the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2 .
  • FIG. 5 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • the potential generating circuit of this embodiment is based on the circuit shown in FIG. 4 , and further, It may further include: a constant current source 11, the first end of the constant current source 11 is connected to the second voltage node, and the second end of the constant current source 11 is connected to the third voltage node.
  • FIG. 6 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • the potential generating circuit of this embodiment is based on the circuit shown in FIG. 5 , and may further include: a first The error amplifier 12, the second error amplifier 13 and the third transistor T3, wherein,
  • the first error amplifier 12 and the second transistor T2 form a first feedback loop, and the substrate terminal of the second transistor T2 is connected to a voltage node of the first feedback loop.
  • the second error amplifier 13 and the third transistor T3 form a second feedback loop, and the substrate terminal of the first transistor is connected to a voltage node of the second feedback loop.
  • the negative input terminal of the first error amplifier 12 is connected to the second voltage node
  • the positive input terminal of the first error amplifier 12 is connected to the first reference voltage V 1
  • the output terminal of the first error amplifier 12 is connected to the first reference voltage V 1 .
  • the substrate terminal of the second transistor T2 is connected.
  • the negative input terminal of the second error amplifier 13 is connected to the second reference voltage V 2
  • the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node
  • the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3 .
  • the source terminal of the three transistors T3 is connected to the first voltage node
  • the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the first resistor R1
  • the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the second resistor R2 .
  • the first voltage node may be connected to the power supply terminal, the first reference voltage V1 may be connected to the ground terminal, and the potential of the third voltage node is lower than the potential of the first reference voltage V1.
  • the first voltage node is connected to the power supply terminal, the first reference voltage V1 is connected to the ground terminal, and the potential of the third voltage node is less than the potential of V1, that is, the potential of the third voltage node is less than 0.
  • the potential of the first voltage node is greater than the potential of the third voltage node.
  • FIG. 7 and FIG. 8 Another potential generating circuit is shown below with reference to FIG. 7 and FIG. 8 , and will be described in detail below with reference to FIG. 7 and FIG. 8 .
  • FIG. 7 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • the potential generating circuit of this embodiment is based on the circuit shown in FIG. 4 , and may further include: a constant current For the source 11, the first end of the constant current source 11 is connected to the third voltage node, and the second end of the constant current source 11 is connected to the first voltage node.
  • FIG. 8 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • the potential generating circuit of this embodiment is based on the circuit shown in FIG. 7 , and may further include: a first The error amplifier 12 and the first transistor T1 form a first feedback loop, and the substrate terminal of the first transistor T1 is connected to a voltage node of the first feedback loop.
  • the second error amplifier 13 and the third transistor T3 constitute a second feedback loop, and the substrate terminal of the second transistor T2 is connected to a voltage node of the second feedback loop.
  • the negative input end of the first error amplifier 12 is connected to the first voltage node, the positive input end of the first error amplifier is connected to the first reference voltage V 1 , and the output end of the first error amplifier 12 is connected to the first reference voltage V 1 .
  • the negative input terminal of the second error amplifier 13 is connected to the second reference voltage V 2
  • the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node
  • the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3 .
  • the source terminal of the three transistors T3 is connected to the second voltage node
  • the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the second resistor R2
  • the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the first resistor R1 .
  • the second voltage node may be connected to the ground terminal
  • the first reference voltage V1 may be connected to the power terminal
  • the potential of the third voltage node is greater than the potential of the first reference voltage V1.
  • the second voltage node is connected to the ground terminal, the first reference voltage V1 is connected to the power supply terminal, and the potential of the third voltage node is greater than the potential of V1, that is, the potential of the third voltage node is greater than Power terminal potential.
  • the potential of the first voltage node is smaller than the potential of the third voltage node.
  • the gate terminal of the first transistor is connected to the drain terminal of the first transistor, and the substrate terminal of the first transistor is used as the potential generating circuit.
  • the first output terminal, the gate terminal of the second transistor is connected to the drain terminal of the second transistor, and the substrate terminal of the second transistor is used as the second output terminal of the potential generating circuit, because the potential of the substrate terminal of the first transistor varies with the first parameter
  • the potential of the substrate terminal of the second transistor changes with the change of the first parameter, so that the output of the first output terminal and the second output terminal can respectively change with any one of the power supply voltage, the operating temperature and the manufacturing process. the potential.
  • FIG. 9 is a potential generating circuit provided by an embodiment of the application.
  • 10 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application, and the potential generating circuit shown in FIG. 9 may further include: a first buffer 14 and The second buffer 15 , the potential generating circuit shown in FIG. 10 , based on the circuit shown in FIG. 8 , may further include: a first buffer 14 and a second buffer 15 .
  • the first buffer 14 is connected to the first output terminal, and outputs a first substrate potential, and the value of the first substrate potential is equal to the potential value of the substrate terminal of the first transistor T1 .
  • the input potential and output potential of the first buffer 14 are the same.
  • the first buffer 14 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the first The potential of the substrate terminal of the transistor T1 is disturbed.
  • the second buffer 15 is connected to the second output terminal, and outputs a second substrate potential whose value is equal to the potential value of the substrate terminal of the second transistor T2.
  • the input potential and output potential of the second buffer 15 are the same.
  • the second buffer 15 is used to enhance the driving capability of the potential of the substrate end of the second transistor T2, and can also isolate the substrate end of the second transistor T2 to avoid the second The potential of the substrate terminal of the transistor T2 is disturbed.
  • the structure of the potential generating circuit of the present application will be described below with reference to specific embodiments.
  • the specific structure of the potential generating circuit of the present application is not limited to any of the following structures.
  • the potential generating circuit of this embodiment may include: a first transistor T1, a second transistor T2, a constant current source 11, a first error amplifier 12, a Two error amplifiers 13 , a first resistor R1 , a second resistor R2 , a third transistor T3 , a first buffer 14 and a second buffer 15 .
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor.
  • the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1
  • the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2
  • the source terminal of the first transistor T1 is connected to the power supply terminal Vcc
  • the source terminal of the second transistor T2 The terminal is connected to the first terminal of the constant current source 11, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2.
  • the second end of the constant current source 11 is connected to Vkb, and the potential of Vkb is less than 0.
  • the first error amplifier 12 and the second transistor T2 form a first feedback loop, the negative input terminal of the first error amplifier 12 is connected to the source terminal of the second transistor T2 and the first terminal of the constant current source 11, and the first error amplifier 12 The positive input terminal of the first error amplifier 12 is connected to the ground terminal, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the second transistor T2.
  • the negative input terminal of the second error amplifier 13 is connected to the power supply terminal (for example, Vcc/2), the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node, and the output terminal of the second error amplifier 13 is connected to the third transistor.
  • the gate terminal of T3, the source terminal of the third transistor T3 is connected to the power supply terminal Vcc, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the first resistor R1, and the output terminal of the first error amplifier 12 is coupled through the second resistor R2 to the fourth voltage node.
  • the first buffer 14 is connected to the substrate terminal of the first transistor and outputs a first substrate potential, and the value of the first substrate potential is equal to the potential value of the substrate terminal of the first transistor T1.
  • the second buffer 15 is connected to the substrate terminal of the second transistor, and outputs a second substrate potential whose value is equal to the potential value of the substrate terminal of the second transistor T2.
  • the resistance values of the first resistor R1 and the second resistor R2 can be set to be larger, for example, set to 100M ⁇ .
  • the resistance values of the first resistor R1 and the second resistor R2 can be set to be larger, the resistance of the first error amplifier 12 The output only affects the input of the second error amplifier 13 slowly, and has little effect on the potential of the first substrate.
  • the potential of the substrate end of the first transistor T1 increases as the first parameter increases, and the potential of the substrate end of the first transistor T1 decreases as the first parameter decreases; the potential of the substrate end of the second transistor T2 Decrease as the first parameter increases, the potential of the substrate end of the second transistor T2 increases as the first parameter decreases, and the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.
  • the following describes in detail the principle that the potential of the substrate end of the first transistor T1 changes with the change of the first parameter, and the change of the potential of the substrate end of the second transistor T2 with the change of the first parameter. principle.
  • the current flowing through the first transistor T1 Id ⁇ *Cox*(W/L)*(Vgs-Vth) 2 , where ⁇ is the electron mobility, Cox is the gate capacitance, and Vgs is the gap between the gate and the source Vth is the threshold voltage.
  • ⁇ is the electron mobility
  • Cox is the gate capacitance
  • Vgs is the gap between the gate
  • the source Vth is the threshold voltage.
  • the first substrate needs to be The potential increases, eg, becomes Vcc+100mV, while the potential of the second substrate needs to be decreased, eg, becomes -100mV.
  • the current Id flowing through the first transistor T1 and the second transistor T2 decreases.
  • the current supplied from the top decreases, but the current flowing to the bottom remains unchanged, so that the first error
  • the potential of the negative input terminal of the amplifier 12 decreases, and then the potential of the second substrate decreases.
  • the output of the first error amplifier 12 will gradually become -100mV, and then the positive input terminal of the second error amplifier 13 will decrease, resulting in The output voltage of the second error amplifier 13 becomes smaller, and then the pull-up capability of the third transistor T3 is enhanced, thereby making the voltage of the first substrate potential higher, and the first substrate potential gradually becomes Vcc+100mV.
  • the first parameter is the power supply voltage and the manufacturing process
  • the changes in the power supply voltage and the manufacturing process will cause the current Id flowing through the first transistor T1 to change, which in turn causes the delay time to change.
  • the principle of compensation is similar to the above principle, here No longer.
  • the potential generating circuit in this embodiment may include: a first transistor T1, a second transistor T2, a constant current source 11, a first error amplifier 12, a Two error amplifiers 13 , a first resistor R1 , a second resistor R2 , a third transistor T3 , a first buffer 14 and a second buffer 15 .
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor.
  • the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1
  • the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2
  • the source terminal of the first transistor T1 is connected to the first terminal of the constant current source 11.
  • the source terminal of the two transistors T2 is connected to the ground terminal
  • the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2.
  • the second terminal of the constant current source 11 is connected to the power terminal Vdd.
  • the first error amplifier 12 and the first transistor T1 form a first feedback loop, the negative input end of the first error amplifier 12 is connected to the first end of the constant current source 11, the positive input end of the first error amplifier is connected to the power supply end Vcc, The output terminal of the first error amplifier 12 is connected to the substrate terminal of the first transistor T1.
  • Vdd is greater than Vcc.
  • the negative input terminal of the second error amplifier 13 is connected to the power supply terminal (for example, Vcc/2), the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node, and the output terminal of the second error amplifier 13 is connected to the third transistor.
  • the gate terminal of T3, the source terminal of the third transistor T3 is connected to the ground terminal, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the second resistor R2, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the first resistor R1 fourth voltage node.
  • the first buffer 14 is connected to the substrate terminal of the first transistor and outputs a first substrate potential, and the value of the first substrate potential is equal to the potential value of the substrate terminal of the first transistor T1.
  • the second buffer 15 is connected to the substrate terminal of the second transistor, and outputs a second substrate potential whose value is equal to the potential value of the substrate terminal of the second transistor T2.
  • the potential of the substrate end of the first transistor T1 increases as the first parameter increases, and the potential of the substrate end of the first transistor T1 decreases as the first parameter decreases; the potential of the substrate end of the second transistor T2 Decrease as the first parameter increases, the potential of the substrate end of the second transistor T2 increases as the first parameter decreases, and the first parameter is any one of the power supply voltage, operating temperature and manufacturing process of the potential generating circuit.
  • the following describes in detail the principle that the potential of the substrate end of the first transistor T1 changes with the change of the first parameter, and the change of the potential of the substrate end of the second transistor T2 with the change of the first parameter. principle.
  • the current flowing through the first transistor T1 Id ⁇ *Cox*(W/L)*(Vgs-Vth) 2 , where ⁇ is the electron mobility, and Vth is the threshold voltage.
  • ⁇ is the electron mobility
  • Vth is the threshold voltage.
  • Vgs-Vth is adjusted to increase, it can compensate the current change caused by the decrease of electron mobility ⁇ , the specific adjustment value can be set according to actual needs.
  • the potential generation circuit shown in FIG. 12 if the temperature increases, the electron mobility ⁇ decreases, and the current Id flowing through the first transistor T1 decreases.
  • the second substrate In order to keep the current of the constant current source unchanged, the second substrate needs to be When the potential decreases, for example, it becomes -100mV, and at the same time, the potential of the first substrate needs to be increased, for example, it becomes Vcc+100mV. If the temperature increases, the current provided above the constant current source remains unchanged, the current flowing from the constant current source to the bottom is equal to the current Id flowing through the first transistor T1 and the second transistor T2, and Id becomes smaller, so the negative value of the first error amplifier 12 The potential of the input terminal increases, and the potential of the first substrate increases. At this time, the output of the first error amplifier 12 will gradually become Vcc+100mV, and then the positive input terminal of the second error amplifier 13 will increase, resulting in the second error amplifier. The output voltage of 13 becomes larger, and then the pull-down capability of the third transistor T3 is enhanced, so that the voltage of the second substrate potential becomes smaller.
  • the first parameter is the power supply voltage and the manufacturing process
  • the changes in the power supply voltage and the manufacturing process will cause the current Id flowing through the first transistor T1 to change, which in turn causes the delay time to change.
  • the principle of compensation is similar to the above principle, here No longer.
  • An embodiment of the present application further provides a delay circuit, including the potential generating circuit shown in any of FIG. 4 to FIG. 12 and a delay unit, the delay unit includes a first inverter, and the first inverter includes a fourth transistor and a delay unit. Five transistors, the substrate terminal of the fourth transistor is connected to the potential of the substrate terminal of the first transistor T1, and the substrate terminal of the fifth transistor is connected to the potential of the substrate terminal of the second transistor T2.
  • the potential of the substrate end of the first transistor in the potential generating circuit can vary with any one of the power supply voltage, the operating temperature and the manufacturing process, it can be used as the substrate of the fourth transistor.
  • the bottom end provides the first substrate potential that varies with the change of the first parameter, and the potential of the substrate end of the second transistor can vary with any one of the supply voltage, the operating temperature and the manufacturing process, so that the fifth
  • the substrate terminal of the transistor provides a second substrate potential that varies with the first parameter, so the current flowing through the two transistors of the first inverter can be adjusted to the change in the current flowing through the two transistors of the inverter. The value is compensated, so that the change of the delay time T of the delay circuit is small, and the control ability of the delay circuit on the accuracy of the delay time is improved.
  • the first transistor is a P-type transistor
  • the second transistor is an N-type transistor
  • the fourth transistor is a P-type transistor
  • the fifth transistor is an N-type transistor
  • the changing first substrate potential can adjust the change value of the rising edge delay time of the delay circuit, so that the change of the rising edge delay time of the delay circuit is small.
  • the variation value of the falling edge delay time of the delay circuit can be adjusted, so that the variation of the falling edge delay time of the delay circuit is small.
  • connection relationship between the potential generating circuit and the inverter can be set according to the number of inverters included in the delay circuit and the requirements of delay time compensation, for example, two inverters are connected in series,
  • the substrate terminal of the P-type transistor in the inverter is connected to the substrate terminal of the P-type transistor in the potential generation circuit, and the change value of the rising edge delay time of the delay circuit can be adjusted.
  • the substrate terminal of the N-type transistor in the inverter is connected to The substrate end of the N-type transistor in the potential generation circuit can adjust the change value of the falling edge delay time of the delay circuit.
  • the potential generation circuit can be set according to the change value of the rising edge and/or falling edge delay time to be adjusted.
  • the potential generating circuit provided in the embodiment of the present application can be applied to a delay circuit in which both the rising edge and/or the falling edge are delayed, and can reduce the delay time T of the delay circuit caused by the manufacturing process, power supply voltage and operating temperature of the delay circuit.
  • the influence of the delay time T is small, and the control ability of the delay circuit on the accuracy of the delay time is improved.
  • FIG. 13 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • the delay circuit of this embodiment includes a potential Generation circuit 1 and delay unit 2, the potential generation circuit 1 is the circuit shown in FIG. 11, the specific structure description can refer to the description in the embodiment shown in FIG.
  • the potential generation circuit 1 outputs the first substrate The potential BP and the second substrate potential BN
  • the delay unit 2 includes an inverter and a capacitor C1
  • the inverter includes a P-type transistor TP1 and an N-type transistor TN1
  • the substrate end of the P-type transistor TP1 is connected to the first substrate potential BP
  • the substrate end of the N-type transistor TN1 is connected to the second substrate potential BN.
  • the potential generating circuit 1 provides the substrate terminal of the P-type transistor in the delay unit 2 with a first substrate potential that varies with the change of the first parameter.
  • the first substrate potential BP can adjust the change value of the rising edge delay time of the delay circuit, so that the change of the rising edge delay time of the delay circuit is small, and the potential generating circuit 1 is an N-type transistor in the delay unit 2
  • the substrate end of BN provides the second substrate potential that changes with the change of the first parameter.
  • the second substrate potential BN can adjust the change value of the delay time of the falling edge of the delay circuit.
  • FIG. 14 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • the delay circuit of this embodiment includes a potential generating circuit 1 and a delay unit 2 , and the potential generating circuit 1 is shown in FIG. 11 .
  • the potential generating circuit 1 outputs the first substrate potential BP and the second substrate potential BN, and the delay unit 2 includes a first inverter.
  • An inverter, a second inverter and a capacitor C1 the first inverter includes a P-type transistor TP1 and an N-type transistor TN1
  • the second inverter includes a P-type transistor TP2 and an N-type transistor TN2.
  • the substrate end of the N-type transistor TN1 in the delay unit 2 is connected to the second substrate potential BN
  • the substrate end of the N-type transistor TN2 is connected to the second substrate potential BN.
  • the potential generating circuit 1 provides the substrate terminals of the N-type transistor TN1 and the N-type transistor TN2 in the delay unit 2 with a second substrate potential BN that changes with the change of the first parameter.
  • the change value of the delay time of the falling edge of the delay circuit can be adjusted, so that the change of the delay time of the rising edge of the delay circuit is small, so that the manufacturing process and power supply voltage of the delay circuit can be reduced. and the influence of working temperature on the rising edge delay time T of the delay circuit, so that the change of the rising edge delay time T is small, and the control ability of the delay circuit on the accuracy of the delay time is improved.
  • the substrate end of the P-type transistor TP1 in the delay unit 2 may also be connected to the first substrate potential BP, and the substrate end of the P-type transistor TP2 may be connected to the first substrate.
  • the potential BP can adjust the change value of the falling edge delay time of the delay circuit, so that the change of the falling edge delay time of the delay circuit is small.
  • FIG. 15 is a schematic structural diagram of a delay circuit provided by an embodiment of the application. As shown in FIG. 15 , the difference between the delay circuit in this embodiment and the delay circuit shown in FIG. 13 is that the The potential generating circuit 1 is the circuit shown in FIG. 12 , other structures are the same, and the achieved effects are also the same, which will not be repeated here.
  • An embodiment of the present application further provides a delay circuit, including the potential generating circuit shown in any of FIG. 9 to FIG. 12 and a delay unit, the delay unit includes a first inverter, and the first inverter includes a fourth transistor and a delay unit. Five transistors, the substrate terminal of the fourth transistor is connected to the first substrate potential, and the substrate terminal of the fifth transistor is connected to the second substrate potential.
  • the potential of the first substrate in the potential generating circuit can change with any one of the power supply voltage, the operating temperature and the manufacturing process, it can provide a variable with the first parameter.
  • the first substrate potential is applied to the substrate terminal of the fourth transistor, and the second substrate potential can be varied with any one of supply voltage, operating temperature, and manufacturing process, so as to provide a variation of the first parameter.
  • the second substrate potential is given to the substrate terminal of the fifth transistor, so the current flowing through the two transistors of the first inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the extension The change of the delay time T of the time circuit is small, and the control ability of the delay circuit to the accuracy of the delay time is improved.
  • the ratio of the channel length of the first transistor T1 to the channel length of the fourth transistor as H
  • the ratio of the channel length of the second transistor T2 to the channel length of the fifth transistor denote L
  • L denote the ratio of the channel width of the first transistor T1 to the channel width of the fourth transistor as M
  • N denote the ratio of the channel width of the second transistor T2 to the channel width of the fifth transistor as N
  • H is equal to L
  • M is equal to N
  • H, L, M and N can be 1.
  • the first transistor and the fourth transistor may be of the same type
  • the second transistor and the fifth transistor may be of the same type.
  • FIG. 16 is a schematic structural diagram of an inverter provided by an embodiment of the present application. As shown in FIG. 16 , the inverter includes:
  • the source terminal of P-type transistor TP1 is connected to the power supply terminal
  • the drain terminal of P-type transistor TP1 is connected to the drain terminal of N-type transistor TN1
  • the source terminal of N-type transistor TN1 is connected to the ground terminal.
  • the gate terminal of the transistor TP1 is connected to the gate terminal of the N-type transistor TN1 and serves as the input terminal of the inverter
  • the drain terminal of the P-type transistor serves as the output terminal of the inverter.
  • the substrate terminal of the P-type transistor TP1 is connected to the first substrate potential, and the substrate terminal of the N-type transistor TN1 is connected to the second substrate potential.
  • the first substrate potential varies with the first parameter, and the second substrate potential varies with the first substrate potential.
  • a parameter varies depending on the change.
  • the first parameter is any one of the inverter's power supply voltage, operating temperature and manufacturing process.
  • the potential of the first substrate increases as the first parameter increases, and the potential of the first substrate decreases as the first parameter decreases; the potential of the second substrate increases Decrease as the first parameter increases, and the second substrate potential increases as the first parameter decreases.
  • the inverter since the potential of the first substrate can be changed with any one of the power supply voltage, the operating temperature and the manufacturing process, it can provide the first substrate that changes with the change of the first parameter
  • the potential is given to the substrate terminal of TP1
  • the potential of the second substrate can be changed with any one of the supply voltage, operating temperature and manufacturing process, so that the second substrate potential that varies with the change of the first parameter can be provided to The substrate end of TN1, so the current flowing through the P-type transistor TP1 and the N-type transistor TN1 of the inverter can be adjusted, and the change value of the current flowing through the two transistors of the inverter can be compensated, so that the delay of the inverter
  • the change of time T is small, which improves the control ability of the inverter to the delay time precision.
  • FIG. 17 is a schematic structural diagram of a delay circuit provided by an embodiment of the present application.
  • the delay circuit of this embodiment may include the delay circuit shown in FIG. 16 .
  • the inverter and the capacitor C1 one end of the capacitor C1 is connected to the ground terminal.
  • the capacitor C1 may be a capacitor array.
  • the delay circuit provided in this embodiment can compensate the change value of the current flowing through the two transistors of the inverter, so that the change of the delay time T of the inverter is small, and thus the delay time of the delay circuit can be reduced.
  • the change of T is small, which improves the control ability of the delay circuit to the accuracy of the delay time.
  • Embodiments of the present application further provide a logic gate circuit, including: a P-type transistor and an N-type transistor, the substrate end of the P-type transistor is connected to a first substrate potential, and the substrate end of the N-type transistor is connected to a second substrate potential,
  • the first substrate potential and the second substrate potential vary with the change of the first parameter, so that the change value of the delay time of the logic gate circuit from the input end to the output end with the change of the first parameter is within the first range, and the first parameter includes the logic Any of the power supply voltage, operating temperature and manufacturing process of the gate circuit.
  • the first range is a relatively small range, such as a range close to 0, for example, the first range is 1%, 3% or 5%, which can make the delay time of the logic gate circuit from the input terminal to the output terminal in the power supply When any one of voltage, operating temperature and manufacturing process changes, the change is small, and the control ability of the logic gate circuit on the accuracy of the delay time is improved.
  • FIG. 18 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • the potential generating circuit of this embodiment may include: a first transistor T1 and a second transistor T2, wherein the first transistor T1 The potential of the substrate end of the 2 varies with the change of the first parameter, and the first parameter is any one of the power supply voltage, the working temperature and the manufacturing process of the potential generating circuit.
  • the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the substrate terminal of the first transistor T1 serves as the output terminal of the potential generating circuit, and the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2.
  • the potential of the substrate terminal of the first transistor T1 is the potential output by the output terminal, and the potential of the substrate terminal of the first transistor T1 changes with the change of the first parameter. Therefore, the potential generating circuit provided in this embodiment can output A potential that varies with any one of supply voltage, operating temperature, and manufacturing process.
  • the potential of the substrate end of the first transistor T1 changes with the change of the first parameter.
  • the potential of the substrate end of the first transistor T1 may vary with the change of the first parameter.
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor.
  • the source terminal of the first transistor T1 is connected to the first voltage node
  • the source terminal of the second transistor T2 is connected to the second voltage node
  • the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2
  • the substrate terminal of the second transistor T2 is connected to the second voltage node.
  • FIG. 19 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • the potential generating circuit of this embodiment is based on the circuit shown in FIG. 18 , and further, It may further include: a constant current source 21, the first end of the constant current source 21 is connected to the first voltage node, and the second end of the constant current source 21 is connected to the third voltage node.
  • FIG. 20 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application. As shown in FIG. 20 , the potential generating circuit of this embodiment is based on the circuit shown in FIG. 19 , and may further include: an error amplifier 22. Form a feedback loop with the first transistor T1, and the substrate end of the first transistor T1 is connected to a voltage node of the first feedback loop.
  • the negative input terminal of the error amplifier 22 is connected to the first voltage node
  • the positive input terminal of the error amplifier 22 is connected to the first reference voltage V 1
  • the output terminal of the error amplifier 22 is connected to the first reference voltage V 1 . substrate end.
  • the first reference voltage V 1 may be connected to the power supply terminal, and the potential of the third voltage node is greater than the potential of the first reference voltage V 1 .
  • the potential of the third voltage node is greater than the potential of the first reference voltage V1
  • the potential of the first voltage node is less than the potential of the third voltage node
  • the voltage of the third voltage node may be Vdd
  • the first reference voltage V 1 may be equal to Vcc
  • Vdd is greater than Vcc.
  • the gate terminal of the first transistor is connected to the drain terminal of the first transistor, and the substrate terminal of the first transistor is used as the potential generating circuit.
  • the output terminal, the gate terminal of the second transistor is connected to the drain terminal of the second transistor. Since the potential of the substrate terminal of the first transistor changes with the change of the first parameter, the output terminal can output the output terminal according to the power supply voltage, operating temperature and manufacturing process. The potential that changes with any change in .
  • FIG. 21 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application. As shown in FIG. 21 , on the basis of the potential generating circuit shown in FIG. 20 , it may further include: a buffer 23 , a buffer 23 The output terminal is connected, and the substrate potential is output, and the value of the substrate potential is equal to the potential value of the substrate terminal of the first transistor T1. The input potential and output potential of the buffer 23 are the same.
  • the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the lining of the first transistor T1. The potential at the bottom end is disturbed.
  • FIG. 22 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • the potential generating circuit of this embodiment may include: The first transistor T1 and the second transistor T2, wherein the potential of the substrate end of the second transistor T2 changes with the change of the first parameter, and the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process of the potential generating circuit .
  • the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1
  • the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2
  • the substrate terminal of the second transistor serves as the output terminal of the potential generating circuit.
  • the potential of the substrate terminal of the second transistor T2 is the potential output by the output terminal, and the potential of the substrate terminal of the second transistor T2 changes with the change of the first parameter. Therefore, the potential generating circuit provided in this embodiment can output A potential that varies with any one of supply voltage, operating temperature, and manufacturing process.
  • the potential of the substrate end of the second transistor T2 changes with the change of the first parameter. Specifically, the potential of the substrate end of the second transistor T2 changes with the change of the first parameter.
  • the first parameter increases and decreases, and the potential of the substrate terminal of the second transistor T2 increases as the first parameter decreases.
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor.
  • the source terminal of the first transistor T1 is connected to the first voltage node
  • the source terminal of the second transistor T2 is connected to the second voltage node
  • the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2
  • the substrate terminal of the first transistor T1 is connected to the first voltage node.
  • FIG. 23 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • the potential generating circuit of this embodiment is based on the circuit shown in FIG. 22 , and further, It may further include: a constant current source 21, the first end of the constant current source 21 is connected to the third voltage node, and the second end of the constant current source 21 is connected to the second voltage node.
  • FIG. 24 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application. As shown in FIG. 24 , the potential generating circuit of this embodiment is based on the circuit shown in FIG. 23 , and may further include: an error amplifier 22. A feedback loop is formed with the second transistor T2, and the substrate end of the second transistor T2 is connected to a voltage node of the first feedback loop.
  • the negative input terminal of the error amplifier 22 is connected to the second voltage node
  • the positive input terminal of the error amplifier 22 is connected to the first reference voltage V 1
  • the output terminal of the error amplifier 22 is connected to the second voltage node of the transistor T2. substrate end.
  • the first voltage node may be connected to the power supply terminal Vcc
  • the first reference voltage V1 may be connected to the ground terminal Vss
  • the potential of the third voltage node is lower than the potential of the first reference voltage V1.
  • the first voltage node is connected to the power supply terminal Vcc, the first reference voltage V1 is connected to the ground terminal Vss, and the potential of the third voltage node is smaller than the potential of V1, for example, the potential of the third voltage node Less than 0, the potential of the second voltage node is greater than the potential of the third voltage node.
  • FIG. 25 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application. As shown in FIG. 25 , on the basis of the potential generating circuit shown in FIG. 24 , it may further include: a buffer 23 , a buffer 23 The output terminal is connected, and the substrate potential is output, and the value of the substrate potential is equal to the potential value of the substrate terminal of the second transistor T2. The input potential and output potential of the buffer 23 are the same.
  • the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the second transistor T2, and can also isolate the substrate end of the second transistor T2 to avoid the lining of the second transistor T2. The potential at the bottom end is disturbed.
  • the structure of the potential generating circuit of the present application will be described below with reference to specific embodiments.
  • the specific structure of the potential generating circuit of the present application is not limited to any of the following structures.
  • FIG. 26 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the application.
  • the potential generating circuit of this embodiment may include: a first transistor T1, a second transistor T2, a constant current source 21, an error Amplifier 22 and buffer 23.
  • the error amplifier 22 and the second transistor T2 form a first feedback loop, the negative input end of the error amplifier 22 is connected to the source end of the second transistor T2 and the first end of the constant current source 21, and the positive input end of the error amplifier 22 is connected to ground terminal, the output terminal of the error amplifier 22 is connected to the substrate terminal of the second transistor T2.
  • the potential of the substrate end of the second transistor T2 changes with the change of the first parameter. Specifically, the potential of the substrate end of the second transistor T2 decreases as the first parameter increases, and the substrate of the second transistor T2 The potential of the terminal increases as the first parameter decreases, and the first parameter is any one of the power supply voltage, the working temperature and the manufacturing process of the potential generating circuit.
  • the first parameter as the operating temperature as an example, the following describes in detail the principle that the potential of the substrate end of the second transistor T2 changes with the change of the first parameter.
  • the current flowing through the second transistor T2 Id ⁇ *Cox*(W/L)*(Vgs-Vth) 2 , where ⁇ is the electron mobility, and Vth is the threshold voltage.
  • ⁇ is the electron mobility
  • Vth is the threshold voltage.
  • Vgs-Vth is adjusted to increase, the current change caused by the decrease of electron mobility ⁇ can be compensated , the specific adjustment value can be set according to actual needs.
  • the potential generation circuit shown in FIG. 26 if the temperature increases, the electron mobility ⁇ decreases, and the current Id flowing through the second transistor T2 decreases. In order to keep the current of the constant current source unchanged, the second transistor T2 needs to be The substrate potential decreases, at this time the substrate potential decreases with the increase of temperature.
  • the first parameter is the power supply voltage and the manufacturing process
  • the changes in the power supply voltage and the manufacturing process will cause the current Id flowing through the second transistor T2 to change, which in turn causes the delay time to change.
  • the principle of compensation is similar to the above principle, here No longer.
  • FIG. 27 is a schematic structural diagram of a potential generating circuit provided by an embodiment of the present application.
  • the potential generating circuit of this embodiment may include: a first transistor T1, a second transistor T2, a constant current source 21, an error Amplifier 22 and buffer 23.
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is an N-type transistor.
  • the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1
  • the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2
  • the source terminal of the first transistor T1 is connected to the first terminal of the constant current source 21.
  • the source terminal of the two transistors T2 is connected to the ground terminal
  • the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2.
  • the second end of the constant current source 21 is connected to Vdd.
  • the error amplifier 22 and the first transistor T1 form a first feedback loop, the negative input terminal of the error amplifier 22 is connected to the source terminal of the first transistor T1 and the first terminal of the constant current source 21, and the positive input terminal of the error amplifier 22 is connected to the power supply
  • the terminal Vcc, the output terminal of the error amplifier 22 is connected to the substrate terminal of the first transistor T1.
  • Vdd is greater than Vcc.
  • the buffer 23 is connected to the substrate terminal of the first transistor T1, and outputs the substrate potential, and the value of the substrate potential is equal to the potential value of the substrate terminal of the first transistor T1.
  • the potential of the substrate end of the first transistor T1 changes with the change of the first parameter. Specifically, the potential of the substrate end of the first transistor T1 increases as the first parameter increases, and the substrate end of the first transistor T1 increases. The potential of the bottom end decreases as the first parameter decreases, and the first parameter is any one of the power supply voltage, the working temperature and the manufacturing process of the potential generating circuit.
  • the first parameter as the operating temperature as an example, the following describes in detail the principle that the potential of the substrate end of the first transistor T1 changes with the change of the first parameter.
  • the current flowing through the first transistor T1 Id ⁇ *Cox*(W/L)*(Vgs-Vth) 2 , where ⁇ is the electron mobility, and Vth is the threshold voltage.
  • ⁇ is the electron mobility
  • Vth is the threshold voltage.
  • Vgs-Vth is adjusted to increase, it can compensate the current change caused by the decrease of electron mobility ⁇ , the specific adjustment value can be set according to actual needs.
  • the potential generation circuit shown in FIG. 26 if the temperature increases, the electron mobility ⁇ decreases, and the current Id flowing through the first transistor T1 decreases. In order to keep the current of the constant current source unchanged, the first transistor T1 needs to be The substrate potential decreases, at this time the substrate potential decreases with the increase of temperature.
  • the first parameter is the power supply voltage and the manufacturing process
  • the changes in the power supply voltage and the manufacturing process will cause the current Id flowing through the second transistor T2 to change, which in turn causes the delay time to change.
  • the principle of compensation is similar to the above principle, here No longer.
  • the embodiment of the present application further provides a delay circuit, including the potential generating circuit and the delay unit shown in FIG. 18 or FIG. 19 or FIG. 20, FIG. 21 or FIG. 27, the delay unit includes a first inverter, the first inverter It includes a fourth transistor and a fifth transistor, the substrate terminal of the fourth transistor is connected to the potential of the substrate terminal of the first transistor, the substrate terminal of the fifth transistor is connected to the ground terminal, the fourth transistor is a P-type transistor, and the fifth transistor is N type transistor.
  • the ratio of the channel length of the first transistor to the channel length of the fourth transistor H
  • the ratio of the channel length of the second transistor to the channel length of the fifth transistor L
  • denote the ratio of the channel length of the second transistor to the channel length of the fifth transistor L
  • the ratio of the channel width of a transistor to the channel width of the fourth transistor is M
  • the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N
  • H equals L
  • M equals N.
  • H, L, M and N may be 1.
  • the first transistor and the fourth transistor may be of the same type
  • the second transistor and the fifth transistor may be of the same type.
  • the delay circuit since the potential of the substrate end of the first transistor in the potential generating circuit can vary with any one of the power supply voltage, the operating temperature and the manufacturing process, it can be used for the inverter in the inverter.
  • the substrate terminal of the P-type transistor provides a substrate potential that changes with the change of the first parameter, so the current flowing through the P-type transistor in the inverter can be adjusted to the change of the current flowing through the P-type transistor in the inverter. The value is compensated, so that the change of the rising edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the accuracy of the rising edge delay time is improved.
  • the delay circuit provided in this embodiment can be applied to a scenario where the rising edge delay time of the delay circuit needs to be precisely controlled, for example, it can be applied to a DRAM, and can simultaneously compensate for any of the power supply voltage, operating temperature, and manufacturing process.
  • the influence of the change on the rising edge delay time makes the change of the rising edge delay time T smaller, which improves the control ability of the delay circuit on the precision of the rising edge delay time.
  • An embodiment of the present application further provides a delay circuit, including the potential generating circuit shown in any of FIG. 22 to FIG. 26 and a delay unit, the delay unit includes a first inverter, and the first inverter includes a fourth transistor and a delay unit. Five transistors, the substrate terminal of the fourth transistor is connected to the potential of the substrate terminal of the first transistor, the substrate terminal of the fifth transistor is connected to the power supply terminal, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.
  • the ratio of the channel length of the first transistor to the channel length of the fourth transistor H
  • the ratio of the channel length of the second transistor to the channel length of the fifth transistor L
  • denote the ratio of the channel length of the second transistor to the channel length of the fifth transistor L
  • the ratio of the channel width of a transistor to the channel width of the fourth transistor is M
  • the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N
  • H equals L
  • M equals N.
  • H, L, M and N may be 1.
  • the first transistor and the fourth transistor may be of the same type
  • the second transistor and the fifth transistor may be of the same type.
  • the delay circuit since the potential of the substrate end of the second transistor in the potential generating circuit can vary with any one of the power supply voltage, the operating temperature and the manufacturing process, it can be used for the inverter in the inverter.
  • the substrate terminal of the N-type transistor provides a substrate potential that changes with the change of the first parameter, so the current flowing through the N-type transistor in the inverter can be adjusted to the change of the current flowing through the N-type transistor in the inverter. The value is compensated, so that the change of the falling edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the precision of the falling edge delay time is improved.
  • the delay circuit provided in this embodiment can be applied to scenarios where precise control of the falling edge delay time of the delay circuit is required.
  • it can be applied to a DRAM, and can simultaneously compensate for any one of the power supply voltage, operating temperature, and manufacturing process.
  • the influence of the change on the falling edge delay time makes the change of the falling edge delay time T smaller, which improves the control ability of the delay circuit on the precision of the falling edge delay time.
  • the embodiment of the present application further provides a delay circuit, including: a first potential generating circuit, a second potential generating circuit and a delay unit, wherein,
  • the first potential generating circuit is the potential generating circuit shown in Figure 18 or Figure 19 or 20 or Figure 21 or Figure 27;
  • the second potential generating circuit is the potential generating circuit shown in any one of FIG. 22 to FIG. 26 ;
  • the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, and the substrate terminal of the fourth transistor is connected to the potential of the substrate terminal of the first transistor in the first potential generating circuit, The substrate terminal of the fifth transistor is connected to the potential of the substrate terminal of the second transistor in the second potential generating circuit, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.
  • H1 denote the ratio of the channel length of the first transistor in the first potential generating circuit to the channel length of the fourth transistor as H1
  • H2 denote the channel length of the second transistor in the first potential generating circuit and
  • the ratio of the channel length of the fifth transistor is L1
  • the ratio of the channel width of the first transistor in the first potential generating circuit to the channel width of the fourth transistor is M1
  • the second The ratio of the channel width of the transistor to the channel width of the fifth transistor is N1
  • H1 is equal to L1
  • M1 is equal to N1.
  • H1, L1, M1 and N1 may be 1.
  • H2 Denote the ratio of the channel length of the first transistor to the channel length of the fourth transistor in the second potential generating circuit as H2
  • H2 denote the channel length of the second transistor in the second potential generating circuit and the channel length of the fifth transistor
  • the ratio of the lengths is L2
  • the ratio of the channel width of the first transistor in the second potential generating circuit to the channel width of the fourth transistor is M2
  • the channel width of the second transistor in the second potential generating circuit and The ratio of the channel widths of the fifth transistor is N2
  • H2 is equal to L
  • M2 is equal to N2.
  • H2, L2, M2 and N2 can be 1.
  • the delay circuit provided in this embodiment can be applied to scenarios where precise control of the rising edge delay time and falling edge delay time of the delay circuit is required.
  • it can be applied to DRAM, which can simultaneously compensate for power supply voltage, operating temperature, and manufacturing process.
  • the influence of any change in the rising edge delay time and the falling edge delay time makes the change of the rising edge delay time T and the falling edge delay time T smaller, and improves the delay circuit's effect on the rising edge delay time and the falling edge delay time.
  • the ability to control the accuracy of the falling edge delay time can be applied to scenarios where precise control of the rising edge delay time and falling edge delay time of the delay circuit is required.
  • DRAM which can simultaneously compensate for power supply voltage, operating temperature, and manufacturing process.
  • the influence of any change in the rising edge delay time and the falling edge delay time makes the change of the rising edge delay time T and the falling edge delay time T smaller, and improves the delay circuit's effect on the rising edge delay time and the falling edge delay time.
  • the ability to control the accuracy of the falling edge delay time is
  • the potential generating circuit shown in the above two embodiments and the delay unit in the delay unit can be set according to the rising edge delay and/or the falling edge delay realized by the delay unit.
  • a delay circuit implements a rising edge delay
  • the delay circuit includes an inverter
  • the inverter includes a P-type transistor and an N-type transistor
  • the delay circuit is set a first potential generating circuit
  • the first potential generating circuit can provide the substrate terminal of the P-type transistor in the inverter with the substrate potential that changes with the change of the first parameter, so that the P-type flowing through the inverter can be adjusted
  • the current of the transistor compensates the change value of the current flowing through the P-type transistor in the inverter, so that the change of the rising edge delay time T of the delay circuit is small.
  • a certain delay circuit implements a falling edge delay
  • the delay circuit includes an inverter
  • the inverter includes a P-type transistor and an N-type transistor
  • a second potential generating circuit is set in the delay circuit
  • the second potential generating circuit can provide the substrate terminal of the N-type transistor in the inverter with a substrate potential that varies with the change of the first parameter, so that the current flowing through the N-type transistor in the inverter can be adjusted.
  • the change value of the current of the N-type transistor in the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is small.
  • the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor, then the first delay circuit is set.
  • a potential generating circuit and a second potential generating circuit, the first potential generating circuit can provide the substrate terminal of the P-type transistor in the inverter with the substrate potential that changes with the change of the first parameter, so that the flow through the inverter can be adjusted
  • the current of the P-type transistor in the inverter compensates the change value of the current flowing through the P-type transistor in the inverter, so that the change of the rising edge delay time T of the delay circuit is small, and the second potential generation circuit can be inverted.
  • the substrate terminal of the N-type transistor in the inverter provides a substrate potential that changes with the change of the first parameter, so that the current flowing through the N-type transistor in the inverter can be adjusted, and the current flowing through the N-type transistor in the inverter can be adjusted.
  • the change value of the current is compensated, so that the change of the falling edge delay time T of the delay circuit is small. Therefore, the variation of the rising edge delay time T and the falling edge delay time T of the delay circuit can be made smaller. Improve the ability of the delay circuit to control the accuracy of the delay time (including the rising edge delay time and the falling edge delay time).
  • FIG. 28 is a schematic structural diagram of a delay circuit provided by an embodiment of the present application.
  • the delay circuit of this embodiment includes a potential Generation circuit 1 and delay unit 2, the potential generation circuit 1 is the circuit shown in FIG. 26, the specific structure description can refer to the description in the embodiment shown in FIG.
  • the potential generation circuit 1 outputs the substrate potential BN
  • the delay unit 2 includes an inverter and a capacitor C1
  • the inverter includes a P-type transistor TP1 and an N-type transistor TN1
  • the substrate terminal of the P-type transistor TP1 is connected to the power supply terminal Vcc
  • the substrate terminal of the N-type transistor TN1 is connected to the substrate Potential BN.
  • the potential generating circuit 1 provides the substrate terminal of the N-type transistor in the delay unit 2 with a substrate potential that changes with the change of the first parameter, which can adjust the falling edge delay time of the delay circuit.
  • the change value makes the change of the falling edge delay time of the delay circuit smaller, so that the influence of the manufacturing process, power supply voltage and working temperature of the delay circuit on the falling edge delay time T of the delay circuit can be reduced, so that the falling edge delay
  • the change of time T is small, which improves the control ability of the delay circuit to the precision of the falling edge delay time.
  • FIG. 29 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • the delay circuit of this embodiment includes a potential generating circuit 1 and a delay unit 2, and the potential generating circuit 1 is shown in FIG. 27 .
  • the potential generating circuit 1 outputs the substrate potential BP
  • the delay unit 2 includes an inverter and a capacitor C1
  • the inverter includes P Type transistor TP1 and N-type transistor TN1, the substrate terminal of the P-type transistor TP1 is connected to the substrate potential BP, and the substrate terminal of the N-type transistor TN1 is connected to the ground terminal.
  • the potential generating circuit 1 provides the substrate terminal of the P-type transistor in the delay unit 2 with a substrate potential that changes with the change of the first parameter, and can adjust the rising edge delay time of the delay circuit.
  • the change value makes the change of the rising edge delay time of the delay circuit smaller, so that the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the rising edge delay time T of the delay circuit can be reduced, so that the rising edge delay time
  • the change of time T is small, which improves the control ability of the delay circuit to the accuracy of the delay time of the rising edge.
  • FIG. 30 is a schematic structural diagram of a delay circuit provided by an embodiment of the application.
  • the delay circuit of this embodiment includes a first potential generating circuit 1 , a second potential generating circuit 3 and a delay unit 2 ,
  • the first potential generating circuit 1 is the circuit shown in FIG. 27 .
  • the first potential generating circuit 1 outputs the substrate potential BN.
  • the second potential generating circuit 3 is the circuit shown in FIG. 28 .
  • the second potential generating circuit 3 outputs the substrate potential BP.
  • the delay unit 2 includes an inverter and a capacitor C1.
  • the inverter includes a P-type transistor TP1 and an N-type transistor TN1.
  • the substrate end of the P-type transistor TP1 is connected to the substrate potential BP output by the second potential generating circuit 3.
  • the N-type transistor The substrate terminal of TN1 is connected to the substrate potential BN output by the first potential generating circuit 1 .
  • the potential generation circuit 1 provides the substrate terminal of the N-type transistor in the delay unit 2 with a substrate potential that changes with the change of the first parameter, and can adjust the rising edge delay time of the delay circuit. The change value makes the change of the delay time of the rising edge of the delay circuit small.
  • the potential generation circuit 3 provides the substrate terminal of the P-type transistor in the delay unit 2 with the substrate potential that changes with the change of the first parameter, and the delay can be adjusted.
  • the change value of the falling edge delay time of the delay circuit makes the change of the falling edge delay time of the delay circuit smaller, thereby reducing the delay time T( Including the influence of the rising edge delay time and the falling edge delay time), the change of the delay time T is small, and the control ability of the delay circuit on the accuracy of the delay time is improved.
  • FIG. 31 is a schematic structural diagram of an inverter provided by an embodiment of the present application. As shown in FIG. 31 , the inverter includes:
  • the source terminal of the P-type transistor TP2 is connected to the power supply terminal
  • the drain terminal of the P-type transistor TP2 is connected to the drain terminal of the N-type transistor TN2
  • the source terminal of the N-type transistor TN2 is connected to the ground terminal.
  • the gate terminal of the transistor TP2 is connected to the gate terminal of the N-type transistor TN2 and serves as the input terminal of the inverter
  • the drain terminal of the P-type transistor TP2 serves as the output terminal of the inverter.
  • the substrate terminal of the P-type transistor TP2 is connected to the substrate potential, and the substrate terminal of the N-type transistor TN2 is connected to the ground terminal.
  • the substrate potential changes with the change of the first parameter.
  • the first parameter is the power supply voltage, operating temperature and any of the manufacturing processes.
  • the substrate potential increases as the first parameter increases, and the substrate potential decreases as the first parameter decreases.
  • the substrate potential can be changed with any one of the power supply voltage, the operating temperature and the manufacturing process, it can provide the P-type substrate potential that changes with the change of the first parameter.
  • the substrate end of the transistor TP2 can adjust the current flowing through the P-type transistor TP2 of the inverter, and compensate the change value of the current flowing through the P-type transistor TP2, so that the change of the rising edge delay time T of the inverter is relatively Small, improve the inverter's ability to control the accuracy of the rising edge delay time.
  • FIG. 32 is a schematic structural diagram of an inverter provided by an embodiment of the present application.
  • the inverter includes: a P-type transistor TP2 and an N-type transistor TN2, and the source terminal of the P-type transistor TP2 is connected to a power supply terminal , the drain terminal of the P-type transistor TP2 is connected to the drain terminal of the N-type transistor TN2, the source terminal of the N-type transistor TN2 is connected to the ground terminal, and the gate terminal of the P-type transistor TP2 is connected to the gate terminal of the N-type transistor TN2.
  • the input terminal, the drain terminal of the P-type transistor TP2 is used as the output terminal of the inverter.
  • the substrate terminal of the N-type transistor TN2 is connected to the substrate potential, and the substrate terminal of the P-type transistor TP2 is connected to the power supply terminal.
  • the substrate potential changes with the change of the first parameter.
  • the first parameter is the power supply voltage, operating temperature and any of the manufacturing processes.
  • the substrate potential decreases as the first parameter increases, and the substrate potential increases as the first parameter decreases.
  • the substrate potential can be changed with any one of the power supply voltage, the operating temperature and the manufacturing process, it can provide the N-type substrate potential that changes with the change of the first parameter.
  • the substrate end of the transistor TN2 so the current flowing through the N-type transistor TN2 of the inverter can be adjusted, and the change value of the current flowing through the N-type transistor TN2 can be compensated, so that the change of the falling edge delay time T of the inverter is relatively Small, improving the inverter's ability to control the accuracy of the falling edge delay time.
  • FIG. 33 is a schematic structural diagram of a delay circuit provided by an embodiment of the present application.
  • the delay circuit of this embodiment may include the delay circuit shown in FIG. 31 .
  • the inverter and the capacitor C1 one end of the capacitor C1 is connected to the ground terminal.
  • the capacitor C1 may be a capacitor array.
  • the delay circuit provided in this embodiment can compensate the change value of the current flowing through the P-type transistor TP2 of the inverter, so that the change of the delay time T of the rising edge of the inverter is small, which can make the delay circuit The change of the rising edge delay time T is small, which improves the control ability of the delay circuit on the accuracy of the rising edge delay time.
  • FIG. 34 is a schematic structural diagram of a delay circuit provided by an embodiment of the present application.
  • the delay circuit of this embodiment may include the delay circuit shown in FIG. 32 .
  • the inverter and the capacitor C1 one end of the capacitor C1 is connected to the ground terminal.
  • the capacitor C1 may be a capacitor array.
  • the delay circuit provided in this embodiment can compensate the change value of the current flowing through the N-type transistor TN2 of the inverter, so that the change of the delay time T of the falling edge of the inverter is small, which can make the delay circuit The change of the falling edge delay time T of , is small, which improves the control ability of the delay circuit on the precision of the falling edge delay time.
  • An embodiment of the present application further provides a logic gate circuit, including: a P-type transistor and an N-type transistor, the substrate terminal of the P-type transistor is connected to the substrate potential, the substrate terminal of the N-type transistor is connected to the ground terminal, and the substrate potential varies with the A parameter changes, so that the delay time from the input terminal to the output terminal of the logic gate circuit changes with the change value of the first parameter within a first range, and the first parameter includes the power supply voltage of the logic gate circuit, the operating temperature and the manufacturing process. either.
  • the first range is a relatively small range, such as a range close to 0, for example, the first range is 1%, 3% or 5%, which can make the logic gate circuit delay time from the input end to the output end of the rising edge
  • the change is small, and the control ability of the logic gate circuit on the accuracy of the rising edge delay time is improved.
  • Embodiments of the present application further provide a logic gate circuit, including: a P-type transistor and an N-type transistor, the substrate terminal of the N-type transistor is connected to a substrate potential, the substrate terminal of the P-type transistor is connected to a power supply terminal, and the substrate potential varies with the A parameter changes, so that the delay time from the input terminal to the output terminal of the logic gate circuit changes with the change value of the first parameter within a first range, and the first parameter includes the power supply voltage of the logic gate circuit, the operating temperature and the manufacturing process. either.
  • the first range is a relatively small range, such as a range close to 0, for example, the first range is 1%, 3% or 5%, which can make the logic gate circuit fall from the input end to the output end of the delay time of the falling edge
  • the change is small, and the control ability of the logic gate circuit on the precision of the falling edge delay time is improved.
  • FIG. 35 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • the control circuit of this embodiment may include: a control unit 41 , a first feedback unit 42 and a second feedback unit 43 , wherein , the first feedback unit 42 is used to output the first feedback signal according to the voltage of the control unit 41 and the first reference voltage, the first end of the first feedback unit 42 is connected to the first end of the control unit, and the first end of the first feedback unit 42 is connected to the first end of the control unit.
  • the second terminal is the input terminal of the first reference voltage, and the output terminal of the first feedback unit 42 is connected to the second terminal of the control unit 41 and the first terminal of the second feedback unit 43 .
  • the second feedback unit 43 is configured to output a second feedback signal according to the voltage output by the first feedback unit 42 and the second reference voltage, the second end of the second feedback unit 43 is the input end of the second reference voltage, and the second feedback unit The output terminal of 43 is connected to the third terminal of the control unit 41 .
  • the control unit 41 is configured to adjust the voltage of the second end of the control unit 41 according to the first feedback signal, and adjust the voltage of the third end of the control unit 41 according to the second feedback signal, so that the current of the control unit 41 varies with the first parameter.
  • the change value is within the first range
  • the first parameter includes at least one of the manufacturing process, power supply voltage and operating temperature of the control circuit
  • the fourth end of the control unit 41 is connected to the first power supply end
  • the fifth end of the control unit 41 is connected to the Negative power supply terminal.
  • the first range is a relatively small range, such as a range close to 0, for example, the first range is 1%, 3% or 5%, so that the current of the control unit 41 can be changed with the first parameter changes are small.
  • FIG. 36 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 36 , the difference between this embodiment and the embodiment shown in FIG. 35 is that the fourth terminal of the control unit 41 is connected to the second power terminal. The fifth terminal of the control unit 41 is connected to the ground terminal Vgg.
  • a control unit In the control circuits shown in Fig. 35 and Fig. 36, a control unit, a first feedback unit and a second feedback unit are provided.
  • the first end of the first feedback unit is connected to the first end of the control unit, and the second end of the first feedback unit is connected to the control unit.
  • the terminal is the input terminal of the first reference voltage
  • the output terminal of the first feedback unit is connected to the second terminal of the control unit and the first terminal of the second feedback unit
  • the second terminal of the second feedback unit is the input terminal of the second reference voltage terminal
  • the output terminal of the second feedback unit is connected with the third terminal of the control unit.
  • the first feedback unit is used for outputting the first feedback signal according to the voltage of the control unit and the first reference voltage
  • the second feedback unit is used for outputting the second feedback signal according to the voltage output by the first feedback unit and the second reference voltage
  • control The unit is used to adjust the voltage of the second end of the control unit according to the first feedback signal, and adjust the voltage of the third end of the control unit according to the second feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within the first Within the range
  • the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process, so that the second terminal of the control unit and the third terminal of the control unit can respectively output the power supply voltage, the operating temperature and the manufacturing process.
  • the voltage varies with any change.
  • FIG. 37 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 37 , the control circuit of this embodiment is based on the circuit shown in FIG. 35 . Further, the control unit 41 may include an inverter inverter 411 and constant current source 412, wherein the first end of the inverter 411 is connected to the first power supply end;
  • the first end of the constant current source 412 is connected to the second end of the inverter 411, and the second end of the constant current source 412 is connected to the negative power supply end;
  • the input terminal of the inverter 411 is short-circuited with the output terminal of the inverter 411 .
  • FIG. 38 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 38 , the control circuit of this embodiment is based on the circuit shown in FIG. 37 . Further, the inverter 411 includes a first For the transistor T1 and the second transistor T2, the substrate end of the first transistor T1 is connected to the output end of the second feedback unit 43, and the substrate end of the second transistor T2 is connected to the output end of the first feedback unit 42;
  • the first end of the first transistor T1 is connected to the first power supply end
  • the second end of the first transistor T1 is connected to the first end of the second transistor T2
  • the control end of the first transistor T1 is connected to the control end of the second transistor T2
  • the first end of the first transistor T1 is connected to the control end of the second transistor T2.
  • the second end of the two transistors T2 is connected to the first end of the constant current source 412 .
  • control unit 41 is configured to adjust the voltage of the substrate terminal of the second transistor T2 according to the first feedback signal, and adjust the voltage of the substrate terminal of the first transistor T1 according to the second feedback signal.
  • control unit is configured to adjust the voltage of the substrate terminal of the second transistor according to the first feedback signal, and adjust the voltage of the substrate terminal of the first transistor according to the second feedback signal, so that the current of the control unit is adjusted.
  • the change value with the change of the first parameter is in the first range, and the first parameter is any one of the supply voltage, the operating temperature and the manufacturing process, so that the substrate end of the first transistor and the substrate end of the second transistor can be Outputs voltages that vary with any one of supply voltage, operating temperature, and manufacturing process, respectively.
  • FIG. 39 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 39 , the control circuit of this embodiment is based on the circuit shown in FIG. 36 . Further, the control unit 41 may include an inverter Inverter 411 and constant current source 412, the first end of inverter 411 is connected to the ground terminal;
  • the first end of the constant current source 412 is connected to the second end of the inverter 411, and the second end of the constant current source 412 is connected to the second power supply end;
  • the input terminal of the inverter 411 is short-circuited with the output terminal of the inverter 411 .
  • FIG. 40 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 40 , the control circuit of this embodiment is based on the circuit shown in FIG. 39 . Further, the inverter 411 includes a first For the transistor T1 and the second transistor T2, the substrate terminal of the first transistor T1 is connected to the output terminal of the first feedback unit, and the substrate terminal of the second transistor T2 is connected to the output terminal of the second feedback unit 43.
  • the first end of the first transistor T1 is connected to the first end of the constant current source, the second end of the first transistor T1 is connected to the first end of the second transistor T2, the control end of the first transistor T1 and the control end of the second transistor T2 connected, the second terminal of the second transistor T2 is connected to the ground terminal.
  • control unit 41 is configured to adjust the voltage of the substrate terminal of the second transistor T2 according to the first feedback signal, and adjust the voltage of the substrate terminal of the first transistor T1 according to the second feedback signal.
  • control unit is configured to adjust the voltage of the substrate terminal of the second transistor according to the first feedback signal, and adjust the voltage of the substrate terminal of the first transistor according to the second feedback signal, so that the current of the control unit is adjusted.
  • the change value with the change of the first parameter is in the first range, and the first parameter is any one of the supply voltage, the operating temperature and the manufacturing process, so that the substrate end of the first transistor and the substrate end of the second transistor can be Outputs voltages that vary with any one of supply voltage, operating temperature, and manufacturing process, respectively.
  • the first transistor is a P-type transistor
  • the second transistor is an N-type transistor
  • the first feedback unit 42 includes a first feedback unit 42 .
  • An error amplifier 421 the negative input terminal of the first error amplifier 421 is connected to the first terminal of the control unit 41, the positive input terminal of the first error amplifier 421 is the input terminal of the first reference voltage, and the output terminal of the first error amplifier 421 It is connected to the second end of the control unit 41 and the first end of the second feedback unit 43 .
  • the second feedback unit 43 includes a second error amplifier 431 , a first resistor R1 , a second resistor R2 and a third transistor T3 , wherein the negative input terminal of the second error amplifier 431 is the second The input terminal of the reference voltage, the positive input terminal of the second error amplifier 431 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, and the output terminal of the second error amplifier 431 is connected to the control of the third transistor T3 end;
  • the second end of the first resistor R1 is connected to the first end of the third transistor T3 and the third end of the control unit 41;
  • the second end of the second resistor R2 is connected to the output end of the first feedback unit and the second end of the control unit 41;
  • the second terminal of the third transistor is connected to the first power terminal.
  • FIG. 42 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 42 , the control circuit of this embodiment is based on the circuit shown in FIG. 40 . Further, the first feedback unit 42 includes a first feedback unit 42 . An error amplifier 421, the negative input terminal of the first error amplifier 421 is connected to the first terminal of the control unit 41, the positive input terminal of the first error amplifier 421 is the input terminal of the first reference voltage, and the output terminal of the first error amplifier 421 It is connected to the second end of the control unit 41 and the first end of the second feedback unit 43 .
  • the second feedback unit 43 includes a second error amplifier 431 , a first resistor R1 , a second resistor R2 and a third transistor T3 , wherein the negative input terminal of the second error amplifier 431 is the second The input terminal of the reference voltage, the positive input terminal of the second error amplifier 431 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, and the output terminal of the second error amplifier 431 is connected to the control of the third transistor T3 end;
  • the second end of the first resistor R1 is connected to the output end of the first feedback unit and the second end of the control unit 41;
  • the second end of the second resistor R2 is connected to the first end of the third transistor T3 and the third end of the control unit 41;
  • the second terminal of the third transistor is connected to the ground terminal.
  • the control circuit shown in FIG. 41 or FIG. 42 may further include a first buffer and a second buffer.
  • FIG. 43 is a schematic structural diagram of a control circuit provided by an embodiment of the application
  • FIG. 44 is a schematic diagram of the structure of the control circuit.
  • the first buffer 44 may further include: a first buffer 44 and The second buffer 45, wherein the first buffer 44 is connected to the substrate terminal of the first transistor T1, and outputs a first substrate voltage, and the value of the first substrate voltage is equal to the voltage value of the substrate terminal of the first transistor T1,
  • the input voltage and output voltage of the first buffer 44 are the same.
  • the first buffer 44 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the first The potential of the substrate terminal of the transistor T1 is disturbed.
  • the second buffer 45 is connected to the substrate terminal of the second transistor T2, and outputs a second substrate voltage.
  • the value of the second substrate voltage is equal to the voltage value of the substrate terminal of the first transistor T1.
  • the second buffer 45 is used for enhancing The driving capability of the potential of the substrate end of the second transistor T2 can also isolate the substrate end of the second transistor T2, so as to prevent the potential of the substrate end of the second transistor T2 from being disturbed.
  • the voltage of the first power supply terminal is, for example, Vcc
  • the second reference voltage may be Vcc/2
  • the voltage of the negative power supply terminal may be a voltage value less than 0.
  • a reference voltage may be zero.
  • the voltage of the second power supply terminal is greater than the voltage of the first reference voltage, and the value of the second reference voltage may be half of the first reference voltage.
  • the voltage of the second power supply terminal is Vdd
  • the first reference voltage is Vcc
  • Vdd is greater than Vcc.
  • the value of the two reference voltages may be Vcc/2.
  • control circuit of the present application will be described below with reference to specific embodiments.
  • the specific structure of the control circuit of the present application is not limited to any of the following structures.
  • control circuit in this embodiment can refer to the circuit structures shown in FIG. 11 and FIG. 12 .
  • the potential generating circuit shown in FIG. 11 and FIG. 12 is the control circuit in this embodiment, and the working principle is the same.
  • the descriptions of the embodiments shown in FIG. 11 and FIG. 12 which are not repeated here.
  • the embodiment of the application also provides a delay circuit, including the control circuit and the delay unit shown in any one of FIG. 35 to FIG. 44 , wherein the second end of the control unit in the control circuit is connected to the first end of the delay unit, and the control circuit controls the delay unit.
  • the third end of the unit is connected to the second end of the delay unit, and the control circuit is used for controlling the rising edge delay time and/or the falling edge delay time of the delay unit to have a change value with the change of the first parameter within a first range.
  • the delay unit includes an inverter, the inverter includes a fourth transistor and a fifth transistor, the third end of the control unit is connected to the substrate end of the fourth transistor, and the second end of the control unit is connected to the fifth transistor. Substrate end connections.
  • the fourth transistor is a P-type transistor
  • the fifth transistor is an N-type transistor.
  • the control circuit in the delay circuit is the control circuit shown in FIG. 38 or FIG. 40 or any one of FIG. 41-FIG. 44
  • the ratio of the channel length is H
  • the ratio of the channel length of the second transistor to the channel length of the fifth transistor is L
  • the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M
  • the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M.
  • the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N
  • H is equal to L
  • M is equal to N.
  • the second terminal of the control unit and the third terminal of the control unit can respectively output the output voltage which changes with the change of the first parameter (any one of the power supply voltage, the working temperature and the manufacturing process) Voltage. Therefore, the substrate terminal of the fourth transistor can be provided with a first substrate voltage that varies with the change of the first parameter, and the substrate terminal of the fifth transistor can be provided with a second substrate voltage that varies with the change of the first parameter. Therefore, The change value of the current flowing through the two transistors of the inverter with the change of the first parameter can be adjusted within the first range, and the change value of the current flowing through the two transistors of the inverter can be compensated to make the delay of the delay circuit. The change of the time T is small, which improves the control ability of the delay circuit to the accuracy of the delay time.
  • connection relationship between the control circuit and the inverter can be set according to the number of inverters included in the delay circuit and the requirements for delay time compensation.
  • the lining of the P-type transistor in the inverter The bottom end is connected to the substrate end of the P-type transistor in the control circuit, and the change value of the rising edge delay time of the delay circuit can be adjusted.
  • the substrate end of the N-type transistor in the inverter is connected to the substrate end of the N-type transistor in the control circuit.
  • the change value of the falling edge delay time of the delay circuit can be adjusted.
  • the connection relationship between the control circuit and the inverter can be set according to the change value of the rising edge and/or falling edge delay time to be adjusted.
  • the control circuit provided by the embodiment of the present application can be applied to a delay circuit in which both the rising edge and/or the falling edge are delayed, and can reduce the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the delay time T of the delay circuit. Influence, the change of the delay time T (including the rising edge and/or the falling edge) is small, and the control ability of the delay circuit on the accuracy of the delay time is improved.
  • Figures 13 to 15 show examples of two kinds of delay circuits, which are also applicable to this embodiment.
  • the potential generating circuits shown in Figures 13 to 15 are the specific control circuits in this embodiment, and please refer to Figure 13 - The specific description in FIG. 15 will not be repeated here.
  • FIG. 45 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 45 , the control circuit of this embodiment may include: a control unit 51 and a feedback unit 52 , wherein,
  • the feedback unit 52 is used for outputting a feedback signal according to the voltage of the control unit 51 and the reference voltage.
  • the second end of 51 is connected.
  • the control unit 51 is used to adjust the voltage of the second end of the control unit 51 according to the feedback signal, so that the change value of the current of the control unit 51 with the change of the first parameter is within the first range, and the first parameter includes the manufacturing process of the control circuit, At least one of the power supply voltage and the working temperature, the third terminal of the control unit 51 is connected to the first power terminal, and the fourth terminal of the control unit 51 is connected to the negative power terminal.
  • the first range is a relatively small range, such as a range close to 0, for example, the first range is 1%, 3% or 5%, so that the current of the control unit 41 can be changed with the change of the first parameter smaller.
  • FIG. 46 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 46 , the difference between this embodiment and the embodiment shown in FIG. 45 is that the third terminal of the control unit 51 is connected to the second power terminal. The fourth terminal of the control unit 51 is connected to the ground terminal Vgg.
  • the feedback unit is used to output a feedback signal according to the voltage and reference voltage of the control unit, and the control unit is used to adjust the second control unit according to the feedback signal.
  • the voltage of the terminal so that the change value of the current of the control unit with the change of the first parameter is within the first range, and the first parameter is any one of the power supply voltage, the working temperature and the manufacturing process, so that the second terminal of the control unit can be Outputs a voltage that varies with any of supply voltage, operating temperature, and manufacturing process.
  • FIG. 47 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 47 , the control circuit of this embodiment is based on the circuit shown in FIG. 45 . Further, the control unit 51 may include an inverter Inverter 511 and constant current source 512, the first end of the inverter 511 is connected to the first power supply end, the first end of the constant current source 512 is connected to the second end of the inverter 511, and the second end of the constant current source 512 is connected The negative power supply terminal, the input terminal of the inverter 511 is short-circuited with the output terminal of the inverter 511 .
  • FIG. 48 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 48 , the control circuit of this embodiment is based on the circuit shown in FIG. 47 . Further, the inverter 411 includes a first The transistor T1 and the second transistor T2, the substrate terminal of the first transistor T1 is connected to the first power supply terminal, and the substrate terminal of the second transistor T2 is connected to the output terminal of the feedback unit 52;
  • the first end of the first transistor T1 is connected to the first power supply end
  • the second end of the first transistor T1 is connected to the first end of the second transistor T2
  • the control end of the first transistor T1 is connected to the control end of the second transistor T2
  • the first end of the first transistor T1 is connected to the control end of the second transistor T2.
  • the second end of the two transistors T2 is connected to the first end of the constant current source.
  • control unit 41 is configured to adjust the voltage of the substrate terminal of the second transistor T2 according to the feedback signal.
  • control unit is configured to adjust the voltage of the substrate terminal of the second transistor according to the feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within the first range, and the first parameter is Any one of the power supply voltage, the operating temperature and the manufacturing process, so that the substrate terminal of the second transistor can output a voltage that varies with any one of the power supply voltage, the operating temperature and the manufacturing process, respectively.
  • FIG. 49 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 49 , the control circuit of this embodiment is based on the circuit shown in FIG. 46 . Further, the control unit 51 may include an inverter Inverter 511 and constant current source 512, wherein the first end of the inverter 511 is connected to the ground terminal, the first end of the constant current source 512 is connected to the second end of the inverter 511, and the second end of the constant current source 512 is connected The second power supply terminal, the input terminal of the inverter 511 is short-circuited with the output terminal of the inverter 511 .
  • FIG. 50 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 50 , the control circuit of this embodiment is based on the circuit shown in FIG. 49 . Further, the inverter 511 includes a first Transistor T1 and second transistor T2, the substrate terminal of the first transistor T1 is connected to the output terminal of the feedback unit, and the substrate terminal of the second transistor is connected to the ground terminal;
  • the first end of the first transistor T1 is connected to the first end of the constant current source, the second end of the first transistor T1 is connected to the first end of the second transistor T2, the control end of the first transistor T1 and the control end of the second transistor T2 connected, the second terminal of the second transistor T2 is connected to the ground terminal.
  • control unit 51 is configured to adjust the voltage of the substrate terminal of the first transistor T1 according to the feedback signal.
  • control unit is configured to adjust the voltage of the substrate terminal of the first transistor according to the feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within the first range, and the first parameter is Any one of the power supply voltage, the operating temperature and the manufacturing process, so that the substrate terminal of the first transistor can output a voltage that varies with any one of the power supply voltage, the operating temperature and the manufacturing process, respectively.
  • the first transistor is a P-type transistor
  • the second transistor is an N-type transistor
  • FIG. 51 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 51 , the control circuit of this embodiment is based on the circuit shown in FIG. 48 . Further, the feedback unit 52 includes an error amplifier 521 , the negative input terminal of the error amplifier 521 is connected to the first terminal of the constant current source 512 and the second terminal of the second transistor T2, the positive input terminal of the error amplifier 521 is the reference voltage input terminal, and the output terminal of the error amplifier 521 is connected to the second terminal of the second transistor T2. The substrate terminal of the transistor T2 is connected.
  • FIG. 52 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 52 , the control circuit of this embodiment is based on the circuit shown in FIG. 51 , and may further include:
  • Buffer 53 the buffer 53 is connected to the substrate terminal of the second transistor T2, and outputs a first substrate voltage, and the value of the first substrate voltage is equal to the voltage value of the substrate terminal of the second transistor T2.
  • FIG. 54 is a schematic structural diagram of a control circuit provided by an embodiment of the application. As shown in FIG. 54 , the control circuit of this embodiment is based on the circuit shown in FIG. 53 , and may further include: a buffer 53 , the buffer 53 is connected to the substrate terminal of the first transistor T1, and outputs a second substrate voltage, the value of which is equal to the voltage value of the substrate terminal of the first transistor T1.
  • the voltage of the first power supply terminal is, for example, Vcc
  • the second reference voltage can be Vcc/2
  • the voltage of the negative power supply terminal can be 0 or less than 0, the first The reference voltage can be 0.
  • the voltage of the second power supply terminal is greater than the voltage of the first reference voltage, and the value of the second reference voltage may be half of the first reference voltage.
  • the voltage of the second power supply terminal is Vdd
  • the first reference voltage is Vcc
  • Vdd is greater than Vcc.
  • the value of the two reference voltages may be Vcc/2.
  • control circuit of the present application will be described below with reference to specific embodiments.
  • the specific structure of the control circuit of the present application is not limited to any of the following structures.
  • control circuit in this embodiment can refer to the circuit structures shown in FIG. 26 and FIG. 27 .
  • the potential generating circuit shown in FIG. 26 and FIG. 27 is the control circuit in this embodiment, and the working principle is the same.
  • the description of the embodiments shown in FIG. 26 and FIG. 27 and details are not repeated here.
  • An embodiment of the present application further provides a delay circuit, including the control circuit and the delay unit shown in any one of FIG. 45 to FIG. 54 , wherein the second end of the control unit is connected to the first end of the delay unit, and the control circuit is used for The change value of the rising edge delay time and/or the falling edge delay time of the control delay unit with the change of the first parameter is within the first range.
  • the delay unit includes an inverter, the inverter includes a fourth transistor and a fifth transistor, and the second end of the control unit is connected to the substrate end of the fourth transistor or the substrate end of the fifth transistor.
  • the fourth transistor is a P-type transistor
  • the fifth transistor is an N-type transistor.
  • the second terminal of the control unit is connected to the substrate terminal of the fifth transistor.
  • the second terminal of the control unit is connected to the substrate terminal of the fourth transistor.
  • the control circuit in the delay circuit is the control circuit shown in FIG. 48 or FIG. 50 or any one of FIG. 51-FIG. 54
  • the ratio of the channel length is H
  • the ratio of the channel length of the second transistor to the channel length of the fifth transistor is L
  • the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M
  • the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M.
  • the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N
  • H is equal to L
  • M is equal to N.
  • the second terminal of the control unit can output a voltage that changes with the change of the first parameter (which is any one of the power supply voltage, the operating temperature, and the manufacturing process). Therefore, the substrate terminal of the fourth transistor can be provided with the first substrate voltage that varies with the change of the first parameter, so the change value of the current flowing through the fourth transistor of the inverter with the change of the first parameter can be adjusted within the first parameter. Within the range, the change value of the current flowing through the fourth transistor of the inverter is compensated, so that the change of the rising edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the accuracy of the rising edge delay time is improved.
  • the substrate terminal of the fifth transistor can be provided with a first substrate voltage that changes with the change of the first parameter, so the change value of the current flowing through the fifth transistor of the inverter with the change of the first parameter can be adjusted in the first Within the range, the change value of the current flowing through the fifth transistor of the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the precision of the falling edge delay time is improved.
  • the control circuit shown in the above two embodiments and the inverse delay unit in the delay unit can be set according to the rising edge delay and/or the falling edge delay realized by the delay unit.
  • the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor
  • the delay circuit is set to A control circuit
  • the first control circuit can adjust the voltage of the substrate terminal of the P-type transistor in the inverter, so that the current flowing through the P-type transistor in the inverter can be adjusted so that the P-type transistor in the inverter flows
  • the change value of the transistor current with the change of the first parameter is within the first range, and the change value of the current flowing through the P-type transistor in the inverter is compensated, so that the change of the rising edge delay time T of the delay circuit is small.
  • a certain delay circuit implements a falling edge delay
  • the delay circuit includes an inverter
  • the inverter includes a P-type transistor and an N-type transistor
  • a second control circuit is set in the delay circuit, and the first The second control circuit can adjust the voltage of the substrate terminal of the N-type transistor in the inverter, so that the current flowing through the N-type transistor in the inverter can be adjusted, so that the current flowing through the N-type transistor in the inverter varies with the first
  • the variation value of a parameter variation is within the first range, and the variation value of the current flowing through the N-type transistor in the inverter is compensated, so that the variation of the falling edge delay time T of the delay circuit is small.
  • the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor, then the first delay circuit is set.
  • the first control circuit can adjust the voltage of the substrate terminal of the P-type transistor in the inverter, so that the current flowing through the P-type transistor in the inverter can be adjusted so that it flows through the inverter
  • the change value of the current of the P-type transistor in the inverter with the change of the first parameter is within the first range, and the change value of the current flowing through the P-type transistor in the inverter is compensated, so that the rising edge of the delay circuit delay time T
  • the second control circuit can adjust the voltage of the substrate terminal of the N-type transistor in the inverter, so that the current flowing through the N-type transistor in the inverter can be adjusted, so that the N-type transistor in the inverter can be adjusted.
  • the change value of the transistor current with the change of the first parameter is within the first range, and the change value of the current flowing through the N-type transistor in the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is small. Therefore, the variation of the rising edge delay time T and the falling edge delay time T of the delay circuit can be made smaller. Improve the ability of the delay circuit to control the accuracy of the delay time (including the rising edge delay time and the falling edge delay time).
  • Figures 28 to 30 show examples of two kinds of delay circuits, which are also applicable to this embodiment.
  • the potential generation circuits shown in Figures 28 to 30 are the specific control circuits in this embodiment. Please refer to Figure 28 - The specific description in Figure 30 will not be repeated here.
  • the constant current source in the above embodiment can use a mirror current source, and the current at the mirror end can be a current independent of the temperature coefficient, or the current is independent of temperature, voltage, etc.; the constant current source in the above embodiment can also use other way to achieve.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)

Abstract

一种电位产生电路、反相器、延时电路和逻辑门电路。该电位产生电路包括：第一晶体管(T1)和第二晶体管(T2)，第一晶体管(T1)的衬底端的电位随第一参数变化而变化，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项，其中，第一晶体管(T1)的栅极端连接第一晶体管(T1)的漏极端，第一晶体管(T1)的衬底端作为电位产生电路的输出端，第二晶体管(T2)的栅极端连接第二晶体管(T2)的漏极端。从而，第一晶体管(T1)的衬底端可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。

Description

电位产生电路、反相器、延时电路和逻辑门电路
本申请要求于2020年11月25日提交中国专利局、申请号为202011340770.2、申请名称为“电位产生电路、反相器、延时电路和逻辑门电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种电位产生电路、反相器、延时电路和逻辑门电路。
背景技术
目前，在半导体元件中常使用到延时电路，延时电路为能够使脉冲信号延迟一定时间的电路。延时电路应用在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中时，常常需要精确控制延时电路的延迟时间，延迟电路需要满足在电源电压、工作温度以及制造工艺等参数发生变化时，延迟时间的变化较小。
图1为一种输入信号和经过延时电路的输出信号的示意图，输入信号经过延时电路后，输出延时信号，如图1所示，输出信号为输入信号延迟时间T后的信号。图1所示的是输入信号的上升沿和下降沿均延迟时间T的情况，还有一种情况是只有输入信号的上升沿延迟时间T或只有输入信号的下降沿延迟时间T。
现有的延时电路中，延时时间T会随着电源电压、工作温度以及制造工艺的变化发生较大的变化(变大或变小)，会影响延时时间的精度。如何降低上述参数的变化对延时电路的延迟时间T的影响，使得延迟时间T的变化较小，是亟需解决的问题。
发明内容
本申请提供一种电位产生电路，可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
本申请提供一种反相器，可使得反向器的上升沿延迟时间或下降沿延迟时间的变化较小，提高反相器对延迟时间精度的控制能力。
本申请提供一种延时电路，以降低延时电路的制造工艺、供电电压和工作温度对延时电路的上升沿延迟时间和/或下降沿延迟时间的影响，使得上升沿延迟时间和/或下降沿延迟时间的变化较小。
本申请提供一种逻辑门电路，以降低逻辑门电路的制造工艺、供电电压和工作温度对逻辑门电路的上升沿延迟时间和/或下降沿延迟时间的影响，使得上升沿延迟时间和/或下降沿延迟时间的变化较小。
第一方面，本申请提供一种电位产生电路，包括：
第一晶体管和第二晶体管，所述第一晶体管的衬底端的电位随第一参数变化而变化，所述第一参数为所述电位产生电路的供电电压、工作温度和制造工艺中的任一项；
其中，所述第一晶体管的栅极端连接所述第一晶体管的漏极端，所述第一晶体管的衬底端作为所述电位产生电路的输出端；所述第二晶体管的栅极端连接所述第二晶体管的漏极端。
本申请提供的电位产生电路，通过设置第一晶体管和第二晶体管，第一晶体管的栅极端连接第一晶体管的漏极端，第一晶体管的衬底端作为电位产生电路的输出端，第二晶体管的栅极端连接第二晶体管的漏极端，由于第一晶体管的衬底端的电位随第一参数变化而变化，从而，输出端可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
可选的，所述第一参数为所述电位产生电路的供电电压或工作温度，
所述第一晶体管的衬底端的电位随所述第一参数升高而升高，所述第一晶体管的衬底端的电位随所述第一参数降低而降低。
可选的，所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管。
可选的，所述第一晶体管的源极端连接第一电压节点，所述第二晶体管的源极端连接第二电压节点，所述第一晶体管的漏极端连接所述第二晶体管的漏极端，所述第二晶体管的衬底端连接所述第二电压节点。
可选的，还包括：
恒流源，所述恒流源的第一端连接所述第一电压节点，所述恒流源的第二端连接第三电压节点。
可选的，还包括：
误差放大器，与所述第一晶体管构成反馈回路，所述第一晶体管的衬底端连接所述第一反馈回路的一个电压节点。
可选的，所述误差放大器的负输入端连接所述第一电压节点，所述误差放大器的正输入端连接第一参考电压，所述误差放大器的输出端连接所述第一晶体管的衬底端。
可选的，所述第三电压节点连接电源端，所述第一参考电压连接电源端，所述第三电压节点的电位大于所述第一参考电压的电位。
可选的，还包括：
缓冲器，所述缓冲器连接所述输出端，并输出衬底电位，所述衬底电位的值等于所述第一晶体管的衬底端的电位值。
第二方面，本申请提供一种电位产生电路，包括：
第一晶体管和第二晶体管，所述第二晶体管的衬底端的电位随第一参数变化而变化，所述第一参数为所述电位产生电路的供电电压、工作温度和制造工艺中的任一项；
其中，所述第一晶体管的栅极端连接所述第一晶体管的漏极端，所述第二晶体管的栅极端连接所述第二晶体管的漏极端，所述第二晶体管的衬底端作为所述电位产生电路的输出端。
本申请提供的电位产生电路，通过设置第一晶体管和第二晶体管，第一晶体管的栅极端连接第一晶体管的漏极端，第二晶体管的栅极端连接第二晶体管的漏极端，第二晶体管T2的衬底端的电位随第一参数变化而变化，第二晶体管的衬底端作为所述电位产生电路的输出端，由于第二晶体管的衬底端的电位随第一参数变化而变化，从而，输出端可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
可选的，所述第一参数为所述电位产生电路的供电电压或工作温度，所述第二晶体管的衬底端的电位随所述第一参数升高而降低，所述第二晶体管的衬底端的电位随所述第一参数降低而升高。
可选的，所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管。
可选的，所述第一晶体管的源极端连接第一电压节点，所述第二晶体管的源极端连接第二电压节点，所述第一晶体管的漏极端连接所述第二晶体管的漏极端，所述第一晶体管的衬底端连接所述第一电压节点。
可选的，还包括：
恒流源，所述恒流源的第一端连接第三电压节点，所述恒流源的第二端连接所述第二电压节点。
可选的，还包括：
误差放大器，与所述第二晶体管构成反馈回路，所述第二晶体管的衬底端连接所述第一反馈回路的一个电压节点。
可选的，所述误差放大器的负输入端连接所述第二电压节点，所述误差放大器的正输入端连接第一参考电压，所述误差放大器的输出端连接所述第二晶体管的衬底端。
可选的，所述第一电压节点连接电源端，所述第一参考电压连接接地端，所述第三电压节点的电位小于所述第一参考电压的电位。
可选的，还包括：
缓冲器，所述缓冲器连接所述输出端，并输出衬底电位，所述衬底电位的值等于所述第二晶体管的衬底端的电位值。
第三方面，本申请提供一种延时电路，包括：
如第一方面及第一方面的实施方式中任一所述的电位产生电路；
延迟单元，所述延迟单元包括第一反相器，所述第一反相器包括第四晶体管和第五晶体管，所述第四晶体管的衬底端连接所述第一晶体管的衬底端的电位，所述第五晶体管的衬底端连接接地端，所述第四晶体管为P型晶体管，所述第五晶体管为N型晶体管。
可选的，记所述第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H，记所述第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L，记所述第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M，记所述第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N，所述H等于所述L，所述M等于所述N。
本申请提供的延时电路，由于电位产生电路中第一晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可为反相器中的P型晶体管的衬底端提供随第一参数变化而变化的衬底电位，因此可调节流经反相器中的P型晶体管的电流，对流经反相器中的P型晶体管的电流的变化值进行补偿，使得延时电路的上升沿延迟时间T的变化较小，提高延时电路对上升沿延迟时间精度的控制能力。
第四方面，本申请提供一种延时电路，包括：
如第二方面及第二方面的实施方式中任一所述的电位产生电路；
延迟单元，所述延迟单元包括第一反相器，所述第一反相器包括第四晶体管和第 五晶体管，所述第四晶体管的衬底端连接所述第一晶体管的衬底端的电位，所述第五晶体管的衬底端连接电源端，所述第四晶体管为P型晶体管，所述第五晶体管为N型晶体管。
本申请提供的延时电路，由于电位产生电路中第二晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可为反相器中的N型晶体管的衬底端提供随第一参数变化而变化的衬底电位，因此可调节流经反相器中的N型晶体管的电流，对流经反相器中的N型晶体管的电流的变化值进行补偿，使得延时电路的下降沿延迟时间T的变化较小，提高延时电路对下降沿延迟时间精度的控制能力。
可选的，记所述第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H，记所述第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L，记所述第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M，记所述第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N，所述H等于所述L，所述M等于所述N。
第五方面，本申请提供一种延时电路，包括：
第一电位产生电路，所述第一电位产生电路为如第一方面及第一方面的实施方式中任一所述的电位产生电路；
第二电位产生电路，所述第二电位产生电路为如第二方面及第二方面的实施方式中任一所述的电位产生电路；
延迟单元，所述延迟单元包括第一反相器，所述第一反相器包括第四晶体管和第五晶体管，所述第四晶体管的衬底端连接所述第一电位产生电路中的第一晶体管的衬底端的电位，所述第五晶体管的衬底端连接所述第二电位产生电路中的第二晶体管的衬底端的电位，所述第四晶体管为P型晶体管，所述第五晶体管为N型晶体管。
本申请提供的延时电路，可同时补偿电源电压、工作温度以及制造工艺中的任一项的变化对上升沿延时时间和下降沿延迟时间的影响，使得上升沿延时时间T和下降沿延迟时间T的变化较小，提高延时电路对上升沿延时时间和下降沿延迟时间精度的控制能力。
可选的，记所述第一电位产生电路中的第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H1，记所述第一电位产生电路中的第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L1，记所述第一电位产生电路中的第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M1，记所述第一电位产生电路中的第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N1，所述H1等于所述L1，所述M1等于所述N1；
记所述第二电位产生电路中的第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H2，记所述第二电位产生电路中的第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L2，记所述第二电位产生电路中的第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M2，记所述第二电位产生电路中的第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N2，所述H2等于所述L2，所述M2等于所述N2。
第六方面，本申请提供一种反相器，包括：
P型晶体管和N型晶体管，所述P型晶体管的源极端连接电源端，所述P型晶体管的漏极端连接所述N型晶体管的漏极端，所述N型晶体管的源极端连接接地端，所述P型晶体管的栅极端连接所述N型晶体管的栅极端，并作为所述反相器的输入端，所述P型晶体管的漏极端作为所述反相器的输出端；
所述P型晶体管的衬底端连接衬底电位，所述N型晶体管的衬底端连接接地端，所述衬底电位随第一参数变化而变化，所述第一参数为所述反相器的供电电压、工作温度和制造工艺中的任一项。
可选的，所述第一参数为所述反相器的供电电压或工作温度，
所述衬底电位随所述第一参数升高而升高，所述衬底电位随所述第一参数升高而降低。
本申请提供的反相器，由于衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的衬底电位给P型晶体管TP2的衬底端，因此可调节流经反相器的P型晶体管TP2的电流，对流经P型晶体管TP2的电流的变化值进行补偿，使得反向器的上升沿延迟时间T的变化较小，提高反相器对上升沿延迟时间精度的控制能力。
第七方面，本申请提供一种反相器，包括：
P型晶体管和N型晶体管，所述P型晶体管的源极端连接电源端，所述P型晶体管的漏极端连接所述N型晶体管的漏极端，所述N型晶体管的源极端连接接地端，所述P型晶体管的栅极端连接所述N型晶体管的栅极端，并作为所述反相器的输入端，所述P型晶体管的漏极端作为所述反相器的输出端；
所述N型晶体管的衬底端连接衬底电位，所述P型晶体管的衬底端连接电源端，所述衬底电位随第一参数变化而变化，所述第一参数为所述反相器的供电电压、工作温度和制造工艺中的任一项。
本申请提供的反相器，由于衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的衬底电位给N型晶体管TN2的衬底端，因此可调节流经反相器的N型晶体管TN2的电流，对流经N型晶体管TN2的电流的变化值进行补偿，使得反向器的下降沿延迟时间T的变化较小，提高反相器对下降沿延迟时间精度的控制能力。
可选的，所述第一参数为所述反相器的供电电压或工作温度，
所述第一衬底电位随所述第一参数降低而降低，所述第二衬底电位随所述第一参数降低而升高。
第八方面，本申请提供一种延时电路，包括：
如第五方面及第五方面的实施方式中和第六方面及第六方面的实施方式中任一所述的反相器；
电容，其一端与所述反相器的输出端连接，其另一端连接所述电源端或所述接地端。
可选的，所述电容为电容阵列。
本申请提供的延时电路，由于可对流经反相器的P型晶体管TP2的电流的变化值进行补偿，使得反向器的上升沿延迟时间T的变化较小，进而可使得延时电路的上升 沿延迟时间T的变化较小，提高延时电路对上升沿延迟时间精度的控制能力。
第九方面，本申请提供一种逻辑门电路，包括：
P型晶体管和N型晶体管，所述P型晶体管的衬底端连接衬底电位，所述N型晶体管的衬底端连接接地端，所述衬底电位随第一参数变化而变化，使得所述逻辑门电路从输入端到输出端的延迟时间随所述第一参数变化的变化值在第一范围内，所述第一参数包括所述逻辑门电路的供电电压、工作温度和制造工艺中的任一项。
本申请提供的逻辑门电路，可以使得逻辑门电路从输入端到输出端的上升沿延迟时间在电源电压、工作温度和制造工艺中的任一项发生变化时的变化较小，提高逻辑门电路对上升沿延迟时间精度的控制能力。
第十方面，本申请提供一种逻辑门电路，包括：
P型晶体管和N型晶体管，所述N型晶体管的衬底端连接衬底电位，所述P型晶体管的衬底端连接电源端，所述衬底电位随第一参数变化而变化，使得所述逻辑门电路从输入端到输出端的延迟时间随所述第一参数变化的变化值在第一范围内，所述第一参数包括所述逻辑门电路的供电电压、工作温度和制造工艺中的任一项。
本申请提供的逻辑门电路，可以使得逻辑门电路从输入端到输出端的下降沿延迟时间在电源电压、工作温度和制造工艺中的任一项发生变化时的变化较小，提高逻辑门电路对下降沿延迟时间精度的控制能力。
附图说明
为了更清楚地说明本申请或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为一种输入信号和经过延时电路的输出信号的示意图；
图2为一种输入信号和经过延时电路的输出信号的示意图；
图3为一种输入信号和经过延时电路的输出信号的示意图；
图4为本申请实施例提供的一种电位产生电路的结构示意图；
图5为本申请实施例提供的一种电位产生电路的结构示意图；
图6为本申请实施例提供的一种电位产生电路的结构示意图；
图7为本申请实施例提供的一种电位产生电路的结构示意图；
图8为本申请实施例提供的一种电位产生电路的结构示意图；
图9为本申请实施例提供的一种电位产生电路的结构示意图；
图10为本申请实施例提供的一种电位产生电路的结构示意图；
图11为本申请实施例提供的一种电位产生电路的结构示意图；
图12为本申请实施例提供的一种电位产生电路的结构示意图；
图13为本申请实施例提供的一种延时电路的结构示意图；
图14为本申请实施例提供的一种延时电路的结构示意图；
图15为本申请实施例提供的一种延时电路的结构示意图；
图16为本申请实施例提供的一种反相器的结构示意图；
图17为本申请实施例提供的一种延时电路的结构示意图；
图18为本申请实施例提供的一种电位产生电路的结构示意图；
图19为本申请实施例提供的一种电位产生电路的结构示意图；
图20为本申请实施例提供的一种电位产生电路的结构示意图；
图21为本申请实施例提供的一种电位产生电路的结构示意图；
图22为本申请实施例提供的一种电位产生电路的结构示意图；
图23为本申请实施例提供的一种电位产生电路的结构示意图；
图24为本申请实施例提供的一种电位产生电路的结构示意图；
图25为本申请实施例提供的一种电位产生电路的结构示意图；
图26为本申请实施例提供的一种电位产生电路的结构示意图；
图27为本申请实施例提供的一种电位产生电路的结构示意图；
图28为本申请实施例提供的一种延时电路的结构示意图；
图29为本申请实施例提供的一种延时电路的结构示意图；
图30为本申请实施例提供的一种延时电路的结构示意图；
图31为本申请实施例提供的一种反相器的结构示意图；
图32为本申请实施例提供的一种反相器的结构示意图；
图33为本申请实施例提供的一种延时电路的结构示意图；
图34为本申请实施例提供的一种延时电路的结构示意图；
图35为本申请实施例提供的一种控制电路的结构示意图；
图36为本申请实施例提供的一种控制电路的结构示意图；
图37为本申请实施例提供的一种控制电路的结构示意图；
图38为本申请实施例提供的一种控制电路的结构示意图；
图39为本申请实施例提供的一种控制电路的结构示意图；
图40为本申请实施例提供的一种控制电路的结构示意图；
图41为本申请实施例提供的一种控制电路的结构示意图；
图42为本申请实施例提供的一种控制电路的结构示意图；
图43为本申请实施例提供的一种控制电路的结构示意图；
图44为本申请实施例提供的一种控制电路的结构示意图；
图45为本申请实施例提供的一种控制电路的结构示意图；
图46为本申请实施例提供的一种控制电路的结构示意图；
图47为本申请实施例提供的一种控制电路的结构示意图；
图48为本申请实施例提供的一种控制电路的结构示意图；
图49为本申请实施例提供的一种控制电路的结构示意图；
图50为本申请实施例提供的一种控制电路的结构示意图；
图51为本申请实施例提供的一种控制电路的结构示意图；
图52为本申请实施例提供的一种控制电路的结构示意图；
图53为本申请实施例提供的一种控制电路的结构示意图；
图54为本申请实施例提供的一种控制电路的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
首先对本申请中涉及到的上升沿延迟时间和下降沿延迟时间进行解释，以便于理解。
1、上升沿延迟时间，图1为一种输入信号和经过延时电路的输出信号的示意图，如图1所示，输出信号的上升沿与输入信号的上升沿之间的延迟时间T为上升沿延迟时间。
2、下降沿延迟时间，如图1所示，输出信号的下降沿与输入信号的下降沿之间的延迟时间T为下降沿延迟时间。
本申请提供的延时电路，可以实现对输入信号的上升沿和下降沿均延迟时间T，脉冲信号的宽度不变，如图1中所示，也可以实现对输入信号的上升沿延迟时间T，还可以实现对输入信号的下降沿延迟时间T。图2为一种输入信号和经过延时电路的输出信号的示意图，如图2所示，输入信号的上升沿被延迟时间T得到输出信号，脉冲信号的宽度被缩短了时间T。图3为一种输入信号和经过延时电路的输出信号的示意图，如图3所示，输入信号的下降沿被延迟时间T得到输出信号，脉冲信号的宽度被延长了时间T。需要说明的是，图1-图3中仅示出了脉冲信号的一个周期。
本申请提供的延时电路，可应用于需要精确控制延时电路的延迟时间的场景，例如可应用于DRAM中，可同时补偿电源电压、工作温度以及制造工艺中的任一项的变化对延迟时间的影响，使得延迟时间T的变化较小，提高延时电路对延迟时间精度的控制能力。
现有的延时电路中的延迟单元包括反相器，反向器由两个晶体管(P型晶体管和N型晶体管)组成，经过延时电路的输出信号的延时时间T会随着电源电压、工作温度以及制造工艺的变化发生较大的变化，会影响延时时间的精度。为解决这一问题，本申请从延迟单元的结构出发，由于电源电压、工作温度以及制造工艺发生变化时，均会导致流经反相器的两个晶体管的电流发生变化，才会导致延时时间发生变化，因此本申请提供一种延时电路，延时电路包括电位产生电路和延迟单元，该电位产生电路包括第一晶体管和第二晶体管，第一晶体管的衬底端的电位随第一参数变化而变化，第二晶体管的衬底端的电位随第一参数变化而变化，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项。延迟单元包括第一反相器，第一反相器包括第四晶体管和第五晶体管，第四晶体管的衬底端连接第一晶体管的衬底端的电位，第五晶体管的衬底端连接第二晶体管的衬底端的电位。
由于第一晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的衬底电位给第四晶体管的衬底端，第二晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的衬底电位给第五晶体管的衬底端，因此可调节流经第一反相器的两个晶体管的电流，对流经反相器的两个晶体管的电流的变化值进行补偿，使得延时电路的延迟时间T的变化较小，提高延时电路对延迟时间精度 的控制能力。
下面通过具体实施例，对本申请提供的电位产生电路、反相器、延时电路和逻辑门电路的具体结构进行详细说明。
实施例一
图4为本申请实施例提供的一种电位产生电路的结构示意图，如图4所示，本实施例的电位产生电路可以包括：第一晶体管T1和第二晶体管T2，其中，第一晶体管T1的衬底端的电位随第一参数变化而变化，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项，第二晶体管T2的衬底端的电位随第一参数变化而变化。
其中，第一晶体管T1的栅极端连接第一晶体管T1的漏极端，第一晶体管T1的衬底端作为电位产生电路的第一输出端，第二晶体管T2的栅极端连接第二晶体管T2的漏极端，第二晶体管T2的衬底端作为电位产生电路的第二输出端。
具体地，第一晶体管T1的衬底端的电位即为第一输出端输出的电位，第二晶体管T2的衬底端的电位即为第二输出端输出的电位。第一晶体管T1的衬底端的电位随第一参数变化而变化，第二晶体管T2的衬底端的电位随第一参数变化而变化，因此，本实施例提供的电位产生电路可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
具体来说，若第一参数为电位产生电路的供电电压或工作温度，第一晶体管T1的衬底端的电位随第一参数变化而变化，第二晶体管T2的衬底端的电位随第一参数变化而变化，具体可以是：第一晶体管T1的衬底端的电位随第一参数升高而升高，第一晶体管T1的衬底端的电位随第一参数降低而降低，即二者是正比的关系；第二晶体管T2的衬底端的电位随第一参数升高而降低，第二晶体管T2的衬底端的电位随第一参数降低而升高。
在一种可实施的方式中，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。
在一种可实施的方式中，第一晶体管T1的源极端连接第一电压节点，第二晶体管T2的源极端连接第二电压节点，第一晶体管T1的漏极端连接第二晶体管T2的漏极端。
在该实施方式中，图5为本申请实施例提供的一种电位产生电路的结构示意图，如图5所示，本实施例的电位产生电路在图4所示电路的基础上，进一步地，还可以包括：恒流源11，恒流源11的第一端连接第二电压节点，恒流源11的第二端连接第三电压节点。
图6为本申请实施例提供的一种电位产生电路的结构示意图，如图6所示，本实施例的电位产生电路在图5所示电路的基础上，进一步地，还可以包括：第一误差放大器12、第二误差放大器13和第三晶体管T3，其中，
第一误差放大器12与第二晶体管T2构成第一反馈回路，第二晶体管T2的衬底端连接第一反馈回路的一个电压节点。
第二误差放大器13和第三晶体管T3构成第二反馈回路，第一晶体管的衬底端连接第二反馈回路的一个电压节点。
如图6所示，可选的，第一误差放大器12的负输入端连接第二电压节点，第一误差放大器12的正输入端连接第一参考电压V 1，第一误差放大器12的输出端连接第二 晶体管T2的衬底端。
第二误差放大器13的负输入端连接第二参考电压V 2，第二误差放大器13的正输入端连接第四电压节点，第二误差放大器13的输出端连接第三晶体管T3的栅极端，第三晶体管T3的源极端连接第一电压节点，第三晶体管T3的漏极端通过第一电阻R1耦合到第四电压节点，第一误差放大器12的输出端通过第二电阻R2耦合到第四电压节点。
本实施例中，第一电压节点可以是连接电源端，第一参考电压V 1可以是连接接地端，第三电压节点的电位小于第一参考电压V 1的电位。
图6所示的电位产生电路中，第一电压节点连接电源端，第一参考电压V 1连接接地端，第三电压节点的电位小于V 1的电位，也即就是第三电压节点的电位小于0。第一电压节点的电位大于第三电压节点的电位。
下面结合图7和图8示出另一种电位产生电路，下面结合图7和图8进行详细说明。
图7为本申请实施例提供的一种电位产生电路的结构示意图，如图7所示，本实施例的电位产生电路在图4所示电路的基础上，进一步地，还可以包括：恒流源11，恒流源11的第一端连接第三电压节点，恒流源11的第二端连接第一电压节点。
图8为本申请实施例提供的一种电位产生电路的结构示意图，如图8所示，本实施例的电位产生电路在图7所示电路的基础上，进一步地，还可以包括：第一误差放大器12，与第一晶体管T1构成第一反馈回路，第一晶体管T1的衬底端连接第一反馈回路的一个电压节点。
第二误差放大器13和第三晶体管T3，第二误差放大器13和第三晶体管T3构成第二反馈回路，第二晶体管T2的衬底端连接第二反馈回路的一个电压节点。
如图8所示，可选的，第一误差放大器12的负输入端连接第一电压节点，第一误差放大器的正输入端连接第一参考电压V 1，第一误差放大器12的输出端连接第一晶体管T1的衬底端。
第二误差放大器13的负输入端连接第二参考电压V 2，第二误差放大器13的正输入端连接第四电压节点，第二误差放大器13的输出端连接第三晶体管T3的栅极端，第三晶体管T3的源极端连接第二电压节点，第三晶体管T3的漏极端通过第二电阻R2耦合到第四电压节点，第一误差放大器12的输出端通过第一电阻R1耦合到第四电压节点。
本实施例中，第二电压节点可以是连接接地端，第一参考电压V 1可以是连接电源端，第三电压节点的电位大于第一参考电压V 1的电位。
图8所示的电位产生电路中，第二电压节点连接接地端，第一参考电压V 1连接电源端，第三电压节点的电位大于V 1的电位，也即就是第三电压节点的电位大于电源端电位。第一电压节点的电位小于第三电压节点的电位。
图4至图8任一所示的电位产生电路，通过设置第一晶体管和第二晶体管，第一晶体管的栅极端连接第一晶体管的漏极端，第一晶体管的衬底端作为电位产生电路的第一输出端，第二晶体管的栅极端连接第二晶体管的漏极端，第二晶体管的衬底端作为电位产生电路的第二输出端，由于第一晶体管的衬底端的电位随第一参数变化而变 化，第二晶体管的衬底端的电位随第一参数变化而变化，从而，第一输出端和第二输出端可分别输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
进一步地，在图4至图8任一所示电位产生电路的基础上，还可以包括：第一缓冲器14和第二缓冲器15，图9为本申请实施例提供的一种电位产生电路的结构示意图，图10为本申请实施例提供的一种电位产生电路的结构示意图，图9所示的电位产生电路在图6所示电路的基础上，还可以包括：第一缓冲器14和第二缓冲器15，图10所示的电位产生电路在图8所示电路的基础上，还可以包括：第一缓冲器14和第二缓冲器15。
参见图9和图10，第一缓冲器14连接第一输出端，并输出第一衬底电位，第一衬底电位的值等于第一晶体管T1的衬底端的电位值。第一缓冲器14的输入电位和输出电位相同，第一缓冲器14用于增强第一晶体管T1的衬底端的电位的驱动能力，还可以对第一晶体管T1的衬底端隔离，避免第一晶体管T1的衬底端的电位受到干扰。
第二缓冲器15连接第二输出端，并输出第二衬底电位，第二衬底电位的值等于第二晶体管T2的衬底端的电位值。第二缓冲器15的输入电位和输出电位相同，第二缓冲器15用于增强第二晶体管T2的衬底端的电位的驱动能力，还可以对第二晶体管T2的衬底端隔离，避免第二晶体管T2的衬底端的电位受到干扰。
下面结合具体实施例对本申请的电位产生电路的结构进行说明，本申请的电位产生电路的具体结构并不局限于下面任一种结构。
图11为本申请实施例提供的一种电位产生电路的结构示意图，本实施例的电位产生电路可以包括：第一晶体管T1、第二晶体管T2、恒流源11、第一误差放大器12、第二误差放大器13、第一电阻R1、第二电阻R2、第三晶体管T3、第一缓冲器14和第二缓冲器15。
本实施例中，其中，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。第一晶体管T1的栅极端连接第一晶体管T1的漏极端，第二晶体管T2的栅极端连接第二晶体管T2的漏极端，第一晶体管T1的源极端连接电源端Vcc，第二晶体管T2的源极端连接恒流源11的第一端，第一晶体管T1的漏极端连接第二晶体管T2的漏极端。恒流源11第二端连接Vkb，Vkb的电位小于0。
其中，第一误差放大器12与第二晶体管T2构成第一反馈回路，第一误差放大器12的负输入端连接第二晶体管T2的源极端和恒流源11的第一端，第一误差放大器12的正输入端连接接地端，第一误差放大器12的输出端连接第二晶体管T2的衬底端。
其中，第二误差放大器13的负输入端连接电源端(例如可以为Vcc/2)，第二误差放大器13的正输入端连接第四电压节点，第二误差放大器13的输出端连接第三晶体管T3的栅极端，第三晶体管T3的源极端连接电源端Vcc，第三晶体管T3的漏极端通过第一电阻R1耦合到第四电压节点，第一误差放大器12的输出端通过第二电阻R2耦合到第四电压节点。
其中，第一缓冲器14连接第一晶体管的衬底端，并输出第一衬底电位，第一衬底电位的值等于第一晶体管T1的衬底端的电位值。第二缓冲器15连接第二晶体管的衬底端，并输出第二衬底电位，第二衬底电位的值等于第二晶体管T2的衬底端的电位值。
可选的，第一电阻R1和第二电阻R2的阻值可以设置较大，例如设置为100MΩ， 通过将第一电阻R1和第二电阻R2的阻值设置较大，第一误差放大器12的输出只会缓慢的影响第二误差放大器13的输入，而对第一衬底电位的影响较小。
本实施例中，第一晶体管T1的衬底端的电位随第一参数升高而升高，第一晶体管T1的衬底端的电位随第一参数降低而降低；第二晶体管T2的衬底端的电位随第一参数升高而降低，第二晶体管T2的衬底端的电位随第一参数降低而升高，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项。
以第一参数为工作温度为例，下面详细介绍第一晶体管T1的衬底端的电位随第一参数变化而变化的原理，以及第二晶体管T2的衬底端的电位随第一参数变化而变化的原理。
流经第一晶体管T1的电流Id＝μ*Cox*(W/L)*(Vgs-Vth) 2，其中，μ为电子迁移率，Cox为栅极电容，Vgs为栅极与源极之间的电压差，Vth为阈值电压，例如工作温度升高时，电子迁移率μ变小，会导致流经第一晶体管T1的电流Id变小，对应的反相器的延迟时间变长，此时若调整Vgs-Vth变大可以补偿电子迁移率μ变小导致的电流变化，具体调整的数值可根据实际需求设置。图11所示的电位产生电路中，若温度升高，电子迁移率μ变小，流经第一晶体管T1的电流Id变小，为了保持恒流源的电流不变，需要将第一衬底电位增大，例如变成Vcc+100mV，同时需要将第二衬底电位减小，例如变成-100mV。当温度升高，流经第一晶体管T1和第二晶体管T2的电流Id减小，对于恒流源11而言，上方提供的电流减小，而流向下方的电流不变，从而使得第一误差放大器12的负输入端电位减小，进而第二衬底电位减小，这时候会导致第一误差放大器12的输出逐渐变为-100mV，然后第二误差放大器13的正输入端减小，导致第二误差放大器13的输出电压变小，然后再导致第三晶体管T3的上拉能力增强，进而使得第一衬底电位的电压变高，第一衬底电位逐渐变为Vcc+100mV。
第一参数为供电电压和制造工艺时，供电电压和制造工艺的变化均会导致流经第一晶体管T1的电流Id发生变化，进而导致延迟时间发生变化，补偿的原理和上述原理类似，此处不再赘述。
图12为本申请实施例提供的一种电位产生电路的结构示意图，本实施例的电位产生电路可以包括：第一晶体管T1、第二晶体管T2、恒流源11、第一误差放大器12、第二误差放大器13、第一电阻R1、第二电阻R2、第三晶体管T3、第一缓冲器14和第二缓冲器15。
本实施例中，其中，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。第一晶体管T1的栅极端连接第一晶体管T1的漏极端，第二晶体管T2的栅极端连接第二晶体管T2的漏极端，第一晶体管T1的源极端连接恒流源11的第一端，第二晶体管T2的源极端连接接地端，第一晶体管T1的漏极端连接第二晶体管T2的漏极端。恒流源11第二端连接电源端Vdd。
其中，第一误差放大器12与第一晶体管T1构成第一反馈回路，第一误差放大器12的负输入端连接恒流源11的第一端，第一误差放大器的正输入端连接电源端Vcc，第一误差放大器12的输出端连接第一晶体管T1的衬底端。
其中，Vdd大于Vcc。
其中，第二误差放大器13的负输入端连接电源端(例如可以为Vcc/2)，第二误 差放大器13的正输入端连接第四电压节点，第二误差放大器13的输出端连接第三晶体管T3的栅极端，第三晶体管T3的源极端连接接地端，第三晶体管T3的漏极端通过第二电阻R2耦合到第四电压节点，第一误差放大器12的输出端通过第一电阻R1耦合到第四电压节点。
其中，第一缓冲器14连接第一晶体管的衬底端，并输出第一衬底电位，第一衬底电位的值等于第一晶体管T1的衬底端的电位值。第二缓冲器15连接第二晶体管的衬底端，并输出第二衬底电位，第二衬底电位的值等于第二晶体管T2的衬底端的电位值。
本实施例中，第一晶体管T1的衬底端的电位随第一参数升高而升高，第一晶体管T1的衬底端的电位随第一参数降低而降低；第二晶体管T2的衬底端的电位随第一参数升高而降低，第二晶体管T2的衬底端的电位随第一参数降低而升高，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项。
以第一参数为工作温度为例，下面详细介绍第一晶体管T1的衬底端的电位随第一参数变化而变化的原理，以及第二晶体管T2的衬底端的电位随第一参数变化而变化的原理。
流经第一晶体管T1的电流Id＝μ*Cox*(W/L)*(Vgs-Vth) 2，其中，μ为电子迁移率，Vth为阈值电压，例如工作温度升高时，电子迁移率μ变小，会导致流经第一晶体管T1的电流Id变小，对应的反相器的延迟时间变长，此时若调整Vgs-Vth变大可以补偿电子迁移率μ变小导致的电流变化，具体调整的数值可根据实际需求设置。图12所示的电位产生电路中，若温度升高，电子迁移率μ变小，流经第一晶体管T1的电流Id变小，为了保持恒流源的电流不变，需要将第二衬底电位减小，例如变成-100mV，同时需要把第一衬底电位增大，例如变成Vcc+100mV。若温度升高，恒流源上方提供的电流不变，恒流源流向下方的电流等于流经第一晶体管T1和第二晶体管T2的电流Id，Id变小，因此第一误差放大器12的负输入端电位增大，第一衬底电位增大，这时候会导致第一误差放大器12的输出逐渐变为Vcc+100mV，然后第二误差放大器13的正输入端增大，导致第二误差放大器13的输出电压变大，然后再导致第三晶体管T3的下拉能力增强，使得第二衬底电位的电压变小。
第一参数为供电电压和制造工艺时，供电电压和制造工艺的变化均会导致流经第一晶体管T1的电流Id发生变化，进而导致延迟时间发生变化，补偿的原理和上述原理类似，此处不再赘述。
本申请实施例还提供一种延时电路，包括图4至图12任一所示的电位产生电路和延迟单元，延迟单元包括第一反相器，第一反相器包括第四晶体管和第五晶体管，第四晶体管的衬底端连接第一晶体管T1的衬底端的电位，第五晶体管的衬底端连接第二晶体管T2的衬底端的电位。
本实施例提供的延时电路，由于电位产生电路中第一晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可为第四晶体管的衬底端提供随第一参数变化而变化的第一衬底电位，第二晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可为第五晶体管的衬底端提供随第一参数变化而变化的第二衬底电位，因此可调节流经第一反相器的两个晶体管的电流，对流经反相器的两个晶体管的电流的变化值进行补偿，使得延时电路的 延迟时间T的变化较小，提高延时电路对延迟时间精度的控制能力。
当第一晶体管为P型晶体管，第二晶体管为N型晶体管，第四晶体管为P型晶体管，第五晶体管为N型晶体管时，通过为P型晶体管的衬底端提供随第一参数变化而变化的第一衬底电位，可调节延时电路的上升沿延迟时间的变化值，使得延时电路的上升沿延迟时间的变化较小，通过为N型晶体管的衬底端提供随第一参数变化而变化的第二衬底电位时，可调节延时电路的下降沿延迟时间的变化值，使得延时电路的下降沿延迟时间的变化较小。
需要说明的是，本申请实施例中可根据延时电路所包括的反相器的个数及延迟时间补偿的需求设置电位产生电路与反相器的连接关系，例如两个反相器串联，反相器中P型晶体管的衬底端连接电位产生电路中P型晶体管的衬底端，可调节延时电路的上升沿延迟时间的变化值，反相器中N型晶体管的衬底端连接电位产生电路中N型晶体管的衬底端，可调节延时电路的下降沿延迟时间的变化值，具体可根据所需调节的上升沿和/或下降沿延迟时间的变化值，设置电位产生电路与反相器的连接关系。本申请实施例提供的电位产生电路，可应用于上升沿和/或下降沿均延迟的延时电路中，可降低延时电路的制造工艺、供电电压和工作温度对延时电路的延迟时间T的影响，使得延迟时间T(包括上升沿和/或下降沿)的变化较小，提高延时电路对延迟时间精度的控制能力。
下面结合图13至图15给出三种延时电路的示例，图13为本申请实施例提供的一种延时电路的结构示意图，如图13所示，本实施例的延时电路包括电位产生电路1和延迟单元2，电位产生电路1为图11所示的电路，具体结构描述可参见图11所示实施例中的描述，此处不再赘述，电位产生电路1输出第一衬底电位BP和第二衬底电位BN，延迟单元2包括反相器和电容C1，反相器包括P型晶体管TP1和N型晶体管TN1，P型晶体管TP1的衬底端连接第一衬底电位BP，N型晶体管TN1的衬底端连接第二衬底电位BN。本实施例的延时电路中，电位产生电路1为延迟单元2中的P型晶体管的衬底端提供随第一参数变化而变化的第一衬底电位，当延迟单元2的输入端为下降沿时，第一衬底电位BP可调节延时电路的上升沿延迟时间的变化值，使得延时电路的上升沿延迟时间的变化较小，电位产生电路1为延迟单元2中的N型晶体管的衬底端提供随第一参数变化而变化的第二衬底电位，当延迟单元2的输入端为上升沿时，第二衬底电位BN可调节延时电路的下降沿延迟时间的变化值，使得延时电路的下降沿延迟时间的变化较小，从而，可降低延时电路的制造工艺、供电电压和工作温度对延时电路的延迟时间T的影响，使得延迟时间T(包括上升沿和下降沿)的变化较小，提高延时电路对延迟时间精度的控制能力。
图14为本申请实施例提供的一种延时电路的结构示意图，如图14所示，本实施例的延时电路包括电位产生电路1和延迟单元2，电位产生电路1为图11所示的电路，具体结构描述可参见图11所示实施例中的描述，此处不再赘述，电位产生电路1输出第一衬底电位BP和第二衬底电位BN，延迟单元2包括第一反相器、第二反相器和电容C1，第一反相器包括P型晶体管TP1和N型晶体管TN1，第二反相器包括P型晶体管TP2和N型晶体管TN2。其中，延迟单元2中N型晶体管TN1的衬底端连接第二衬底电位BN，N型晶体管TN2的衬底端连接第二衬底电位BN。本实施例的延时电路 中，电位产生电路1为延迟单元2中N型晶体管TN1和N型晶体管TN2的衬底端提供随第一参数变化而变化的第二衬底电位BN，当延迟单元2的输入端为上升沿时，可调节延时电路的下降沿延迟时间的变化值，使得延时电路的上升沿延迟时间的变化较小，从而，可降低延时电路的制造工艺、供电电压和工作温度对延时电路的上升沿延迟时间T的影响，使得上升沿延迟时间T的变化较小，提高延时电路对延迟时间精度的控制能力。
可以理解的是，在另一中延时电路中，还可以是延迟单元2中P型晶体管TP1的衬底端连接第一衬底电位BP，P型晶体管TP2的衬底端连接第一衬底电位BP，可调节延时电路的下降沿延迟时间的变化值，使得延时电路的下降沿延迟时间的变化较小。
图15为本申请实施例提供的一种延时电路的结构示意图，如图15所示，本实施例中的延时电路和图13所示的延时电路的区别在于，本实施例中的电位产生电路1为图12所示的电路，其它结构相同，所达到的效果也相同，此处不再赘述。
本申请实施例还提供一种延时电路，包括图9至图12任一所示的电位产生电路和延迟单元，延迟单元包括第一反相器，第一反相器包括第四晶体管和第五晶体管，第四晶体管的衬底端连接第一衬底电位，第五晶体管的衬底端连接第二衬底电位。
本实施例提供的延时电路，由于电位产生电路中第一衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的第一衬底电位给第四晶体管的衬底端，第二衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的第二衬底电位给第五晶体管的衬底端，因此可调节流经第一反相器的两个晶体管的电流，对流经反相器的两个晶体管的电流的变化值进行补偿，使得延时电路的延迟时间T的变化较小，提高延时电路对延迟时间精度的控制能力。
在上述两种延时电路中，记第一晶体管T1的沟道长度与第四晶体管的沟道长度之比为H，记第二晶体管T2的沟道长度与第五晶体管的沟道长度之比为L，记第一晶体管T1的沟道宽度与第四晶体管的沟道宽度之比为M，记第二晶体管T2的沟道宽度与第五晶体管的沟道宽度之比为N，H等于L，M等于N，可选的，H、L、M和N可以是1。可选的，第一晶体管和第四晶体管的类型可以相同，第二晶体管和第五晶体管的类型可以相同。
本申请实施例还提供一种反相器，图16为本申请实施例提供的一种反相器的结构示意图，如图16所示，该反相器包括：
P型晶体管TP1和N型晶体管TN1，P型晶体管TP1的源极端连接电源端，P型晶体管TP1的漏极端连接N型晶体管TN1的漏极端，N型晶体管TN1的源极端连接接地端，P型晶体管TP1的栅极端连接N型晶体管TN1的栅极端，并作为反相器的输入端，P型晶体管的漏极端作为反相器的输出端。
P型晶体管TP1的衬底端连接第一衬底电位，N型晶体管TN1的衬底端连接第二衬底电位，第一衬底电位随第一参数变化而变化，第二衬底电位随第一参数变化而变化，第一参数为反相器的供电电压、工作温度和制造工艺中的任一项。
其中，第一参数为反相器的供电电压或工作温度时，第一衬底电位随第一参数升高而升高，第一衬底电位随第一参数降低而降低；第二衬底电位随第一参数升高而降 低，第二衬底电位随第一参数降低而升高。
本实施例提供的反相器，由于第一衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的第一衬底电位给TP1的衬底端，第二衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的第二衬底电位给TN1的衬底端，因此可调节流经反相器的P型晶体管TP1和N型晶体管TN1的电流，对流经反相器的两个晶体管的电流的变化值进行补偿，使得反向器的延迟时间T的变化较小，提高反相器对延迟时间精度的控制能力。
本申请实施例还提供一种延时电路，图17为本申请实施例提供的一种延时电路的结构示意图，如图17所示，本实施例的延时电路可以包括图16所示的反相器和电容C1，电容C1的一端连接接地端。在一种可实施的方式中，电容C1可以为电容阵列。
本实施例提供的延时电路，由于可对流经反相器的两个晶体管的电流的变化值进行补偿，使得反向器的延迟时间T的变化较小，进而可使得延时电路的延迟时间T的变化较小，提高延时电路对延迟时间精度的控制能力。
本申请实施例还提供一种逻辑门电路，包括：P型晶体管和N型晶体管，P型晶体管的衬底端连接第一衬底电位，N型晶体管的衬底端连接第二衬底电位，第一衬底电位和第二衬底电位随第一参数变化而变化，使得逻辑门电路从输入端到输出端的延迟时间随第一参数变化的变化值在第一范围内，第一参数包括逻辑门电路的供电电压、工作温度和制造工艺中的任一项。
具体来说，第一范围为一个较小的范围，例如为接近0的范围，如第一范围为1％或3％或5％，可以使得逻辑门电路从输入端到输出端的延迟时间在电源电压、工作温度和制造工艺中的任一项发生变化时的变化较小，提高逻辑门电路对延迟时间精度的控制能力。
实施例二
图18为本申请实施例提供的一种电位产生电路的结构示意图，如图18所示，本实施例的电位产生电路可以包括：第一晶体管T1和第二晶体管T2，其中，第一晶体管T1的衬底端的电位随第一参数变化而变化，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项。
其中，第一晶体管T1的栅极端连接第一晶体管T1的漏极端，第一晶体管T1的衬底端作为电位产生电路的输出端，第二晶体管T2的栅极端连接第二晶体管T2的漏极端。
具体地，第一晶体管T1的衬底端的电位即为输出端输出的电位，第一晶体管T1的衬底端的电位随第一参数变化而变化，因此，本实施例提供的电位产生电路可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
具体来说，若第一参数为电位产生电路的供电电压或工作温度，第一晶体管T1的衬底端的电位随第一参数变化而变化，具体可以是：第一晶体管T1的衬底端的电位随第一参数升高而升高，第一晶体管T1的衬底端的电位随第一参数降低而降低，即二者是正比的关系。
在一种可实施的方式中，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。
在一种可实施的方式中，第一晶体管T1的源极端连接第一电压节点，第二晶体管T2的源极端连接第二电压节点，第一晶体管T1的漏极端连接第二晶体管T2的漏极端，第二晶体管T2的衬底端连接第二电压节点。
在该实施方式中，图19为本申请实施例提供的一种电位产生电路的结构示意图，如图19所示，本实施例的电位产生电路在图18所示电路的基础上，进一步地，还可以包括：恒流源21，恒流源21的第一端连接第一电压节点，恒流源21的第二端连接第三电压节点。
图20为本申请实施例提供的一种电位产生电路的结构示意图，如图20所示，本实施例的电位产生电路在图19所示电路的基础上，进一步地，还可以包括：误差放大器22，与第一晶体管T1构成反馈回路，第一晶体管T1的衬底端连接第一反馈回路的一个电压节点。
如图20所示，可选的，误差放大器22的负输入端连接第一电压节点，误差放大器22的正输入端连接第一参考电压V 1，误差放大器22的输出端连接第一晶体管T1的衬底端。
本实施例中，第一参考电压V 1可以是连接电源端，第三电压节点的电位大于第一参考电压V 1的电位。
图20所示的电位产生电路中，第三电压节点的电位大于第一参考电压V 1的电位，第一电压节点的电位小于第三电压节点的电位，例如第三电压节点电压可以为Vdd，第一参考电压V 1可以等于Vcc，Vdd大于Vcc。
图18至图20任一所示的电位产生电路，通过设置第一晶体管和第二晶体管，第一晶体管的栅极端连接第一晶体管的漏极端，第一晶体管的衬底端作为电位产生电路的输出端，第二晶体管的栅极端连接第二晶体管的漏极端，由于第一晶体管的衬底端的电位随第一参数变化而变化，从而，输出端可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
图21为本申请实施例提供的一种电位产生电路的结构示意图，如图21所示，在图20所示电位产生电路的基础上，进一步地，还可以包括：缓冲器23，缓冲器23连接输出端，并输出衬底电位，衬底电位的值等于第一晶体管T1的衬底端的电位值。缓冲器23的输入电位和输出电位相同，缓冲器23用于增强第一晶体管T1的衬底端的电位的驱动能力，还可以对第一晶体管T1的衬底端隔离，避免第一晶体管T1的衬底端的电位受到干扰。
下面结合图22至图25示出另一种电位产生电路，图22为本申请实施例提供的一种电位产生电路的结构示意图，如图22所示，本实施例的电位产生电路可以包括：第一晶体管T1和第二晶体管T2，其中，第二晶体管T2的衬底端的电位随第一参数变化而变化，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项。
其中，第一晶体管T1的栅极端连接第一晶体管T1的漏极端,第二晶体管T2的栅极端连接第二晶体管T2的漏极端，第二晶体管的衬底端作为电位产生电路的输出端。
具体地，第二晶体管T2的衬底端的电位即为输出端输出的电位，第二晶体管T2 的衬底端的电位随第一参数变化而变化，因此，本实施例提供的电位产生电路可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
具体来说，若第一参数为电位产生电路的供电电压或工作温度，第二晶体管T2的衬底端的电位随第一参数变化而变化，具体可以是：第二晶体管T2的衬底端的电位随第一参数升高而降低，第二晶体管T2的衬底端的电位随第一参数降低而升高。
在一种可实施的方式中，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。
在一种可实施的方式中，第一晶体管T1的源极端连接第一电压节点，第二晶体管T2的源极端连接第二电压节点，第一晶体管T1的漏极端连接第二晶体管T2的漏极端，第一晶体管T1的衬底端连接第一电压节点。
在该实施方式中，图23为本申请实施例提供的一种电位产生电路的结构示意图，如图23所示，本实施例的电位产生电路在图22所示电路的基础上，进一步地，还可以包括：恒流源21，恒流源21的第一端连接第三电压节点，恒流源21的第二端连接第二电压节点。
图24为本申请实施例提供的一种电位产生电路的结构示意图，如图24所示，本实施例的电位产生电路在图23所示电路的基础上，进一步地，还可以包括：误差放大器22，与第二晶体管T2构成反馈回路，第二晶体管T2的衬底端连接第一反馈回路的一个电压节点。
如图24所示，可选的，误差放大器22的负输入端连接第二电压节点，误差放大器22的正输入端连接第一参考电压V 1，误差放大器22的输出端连接第二晶体管T2的衬底端。
本实施例中，第一电压节点可以是连接电源端Vcc，第一参考电压V 1可以是连接接地端Vss，第三电压节点的电位小于第一参考电压V 1的电位。
图24所示的电位产生电路中，第一电压节点连接电源端Vcc，第一参考电压V 1连接接地端Vss，第三电压节点的电位小于V 1的电位，例如，第三电压节点的电位小于0，第二电压节点的电位大于第三电压节点的电位。
图22至图24任一所示的电位产生电路，通过设置第一晶体管和第二晶体管，第一晶体管的栅极端连接第一晶体管的漏极端，第二晶体管的栅极端连接第二晶体管的漏极端，第二晶体管T2的衬底端的电位随第一参数变化而变化，第二晶体管的衬底端作为电位产生电路的输出端，由于第二晶体管的衬底端的电位随第一参数变化而变化，从而，输出端可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电位。
图25为本申请实施例提供的一种电位产生电路的结构示意图，如图25所示，在图24所示电位产生电路的基础上，进一步地，还可以包括：缓冲器23，缓冲器23连接输出端，并输出衬底电位，衬底电位的值等于第二晶体管T2的衬底端的电位值。缓冲器23的输入电位和输出电位相同，缓冲器23用于增强第二晶体管T2的衬底端的电位的驱动能力，还可以对第二晶体管T2的衬底端隔离，避免第二晶体管T2的衬底端的电位受到干扰。
下面结合具体实施例对本申请的电位产生电路的结构进行说明，本申请的电位产生电路的具体结构并不局限于下面任一种结构。
图26为本申请实施例提供的一种电位产生电路的结构示意图，如图26所示，本实施例的电位产生电路可以包括：第一晶体管T1、第二晶体管T2、恒流源21、误差放大器22和缓冲器23。
本实施例中，其中，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。第一晶体管T1的栅极端连接第一晶体管T1的漏极端，第二晶体管T2的栅极端连接第二晶体管T2的漏极端，第一晶体管T1的源极端连接电源端Vcc，第二晶体管T2的源极端连接恒流源21的第一端，第一晶体管T1的漏极端连接第二晶体管T2的漏极端。恒流源21的第二端连接Vkb，Vkb的电位小于0。
其中，误差放大器22与第二晶体管T2构成第一反馈回路，误差放大器22的负输入端连接第二晶体管T2的源极端和恒流源21的第一端，误差放大器22的正输入端连接接地端，误差放大器22的输出端连接第二晶体管T2的衬底端。
其中，缓冲器23连接第二晶体管T2的衬底端，并输出衬底电位，衬底电位的值等于第二晶体管T2的衬底端的电位值。
本实施例中，第二晶体管T2的衬底端的电位随第一参数变化而变化，具体地，第二晶体管T2的衬底端的电位随第一参数升高而降低，第二晶体管T2的衬底端的电位随第一参数降低而升高，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项。
以第一参数为工作温度为例，下面详细介绍第二晶体管T2的衬底端的电位随第一参数变化而变化的原理。
流经第二晶体管T2的电流Id＝μ*Cox*(W/L)*(Vgs-Vth) 2，其中，μ为电子迁移率，Vth为阈值电压，例如工作温度升高时，电子迁移率μ变小，会导致流经第二晶体管T2的电流Id变小，对应的反相器的延迟时间变长，此时若调整Vgs-Vth变大可以补偿电子迁移率μ变小导致的电流变化，具体调整的数值可根据实际需求设置。图26所示的电位产生电路中，若温度升高，电子迁移率μ变小，流经第二晶体管T2的电流Id变小，为了保持恒流源的电流不变，需要将第二晶体管T2的衬底电位减小，此时衬底电位是随着温度升高而降低的。
第一参数为供电电压和制造工艺时，供电电压和制造工艺的变化均会导致流经第二晶体管T2的电流Id发生变化，进而导致延迟时间发生变化，补偿的原理和上述原理类似，此处不再赘述。
图27为本申请实施例提供的一种电位产生电路的结构示意图，如图27所示，本实施例的电位产生电路可以包括：第一晶体管T1、第二晶体管T2、恒流源21、误差放大器22和缓冲器23。
本实施例中，其中，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管。第一晶体管T1的栅极端连接第一晶体管T1的漏极端，第二晶体管T2的栅极端连接第二晶体管T2的漏极端，第一晶体管T1的源极端连接恒流源21的第一端，第二晶体管T2的源极端连接接地端，第一晶体管T1的漏极端连接第二晶体管T2的漏极端。恒流源21的第二端连接Vdd。
其中，误差放大器22与第一晶体管T1构成第一反馈回路，误差放大器22的负输入端连接第一晶体管T1的源极端和恒流源21的第一端，误差放大器22的正输入端连 接电源端Vcc，误差放大器22的输出端连接第一晶体管T1的衬底端。
其中，Vdd大于Vcc。
其中，缓冲器23连接第一晶体管T1的衬底端，并输出衬底电位，衬底电位的值等于第一晶体管T1的衬底端的电位值。
本实施例中，第一晶体管T1的衬底端的电位随第一参数变化而变化，具体地，第一晶体管T1的衬底端的电位随第一参数升高而升高，第一晶体管T1的衬底端的电位随第一参数降低而降低，第一参数为电位产生电路的供电电压、工作温度和制造工艺中的任一项。
以第一参数为工作温度为例，下面详细介绍第一晶体管T1的衬底端的电位随第一参数变化而变化的原理。
流经第一晶体管T1的电流Id＝μ*Cox*(W/L)*(Vgs-Vth) 2，其中，μ为电子迁移率，Vth为阈值电压，例如工作温度升高时，电子迁移率μ变小，会导致流经第一晶体管T1的电流Id变小，对应的反相器的延迟时间变长，此时若调整Vgs-Vth变大可以补偿电子迁移率μ变小导致的电流变化，具体调整的数值可根据实际需求设置。图26所示的电位产生电路中，若温度升高，电子迁移率μ变小，流经第一晶体管T1的电流Id变小，为了保持恒流源的电流不变，需要将第一晶体管T1的衬底电位减小，此时衬底电位是随着温度升高而降低的。
第一参数为供电电压和制造工艺时，供电电压和制造工艺的变化均会导致流经第二晶体管T2的电流Id发生变化，进而导致延迟时间发生变化，补偿的原理和上述原理类似，此处不再赘述。
本申请实施例还提供一种延时电路，包括图18或图19或图20图21或图27所示的电位产生电路和延迟单元，延迟单元包括第一反相器，第一反相器包括第四晶体管和第五晶体管，第四晶体管的衬底端连接第一晶体管的衬底端的电位，第五晶体管的衬底端连接接地端，第四晶体管为P型晶体管，第五晶体管为N型晶体管。
其中，可选的，记第一晶体管的沟道长度与第四晶体管的沟道长度之比为H，记第二晶体管的沟道长度与第五晶体管的沟道长度之比为L，记第一晶体管的沟道宽度与第四晶体管的沟道宽度之比为M，记第二晶体管的沟道宽度与第五晶体管的沟道宽度之比为N，H等于L，M等于N。可选的，H、L、M和N可以是1。可选的，第一晶体管和第四晶体管的类型可以相同，第二晶体管和第五晶体管的类型可以相同。
本实施例提供的延时电路，由于电位产生电路中第一晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可为反相器中的P型晶体管的衬底端提供随第一参数变化而变化的衬底电位，因此可调节流经反相器中的P型晶体管的电流，对流经反相器中的P型晶体管的电流的变化值进行补偿，使得延时电路的上升沿延迟时间T的变化较小，提高延时电路对上升沿延迟时间精度的控制能力。
本实施例提供的延时电路，可应用于需要精确控制延时电路的上升沿延迟时间的场景，例如可应用于DRAM中，可同时补偿电源电压、工作温度以及制造工艺中的任一项的变化对上升沿延迟时间的影响，使得上升沿延迟时间T的变化较小，提高延时电路对上升沿延迟时间精度的控制能力。
本申请实施例还提供一种延时电路，包括图22至图26任一所示的电位产生电路和延迟单元，延迟单元包括第一反相器，第一反相器包括第四晶体管和第五晶体管，第四晶体管的衬底端连接第一晶体管的衬底端的电位，第五晶体管的衬底端连接电源端，第四晶体管为P型晶体管，第五晶体管为N型晶体管。
其中，可选的，记第一晶体管的沟道长度与第四晶体管的沟道长度之比为H，记第二晶体管的沟道长度与第五晶体管的沟道长度之比为L，记第一晶体管的沟道宽度与第四晶体管的沟道宽度之比为M，记第二晶体管的沟道宽度与第五晶体管的沟道宽度之比为N，H等于L，M等于N。可选的，H、L、M和N可以是1。可选的，第一晶体管和第四晶体管的类型可以相同，第二晶体管和第五晶体管的类型可以相同。
本实施例提供的延时电路，由于电位产生电路中第二晶体管的衬底端的电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可为反相器中的N型晶体管的衬底端提供随第一参数变化而变化的衬底电位，因此可调节流经反相器中的N型晶体管的电流，对流经反相器中的N型晶体管的电流的变化值进行补偿，使得延时电路的下降沿延迟时间T的变化较小，提高延时电路对下降沿延迟时间精度的控制能力。
本实施例提供的延时电路，可应用于需要精确控制延时电路的下降沿延迟时间的场景，例如可应用于DRAM中，可同时补偿电源电压、工作温度以及制造工艺中的任一项的变化对下降沿延迟时间的影响，使得下降沿延迟时间T的变化较小，提高延时电路对下降沿延迟时间精度的控制能力。
本申请实施例还提供一种延时电路，包括：第一电位产生电路、第二电位产生电路和延迟单元，其中，
第一电位产生电路为如图18或图19或20或图21或图27所示的电位产生电路；
第二电位产生电路为如图22至图26任一所示的电位产生电路；
延迟单元，延迟单元包括第一反相器，第一反相器包括第四晶体管和第五晶体管，第四晶体管的衬底端连接第一电位产生电路中的第一晶体管的衬底端的电位，第五晶体管的衬底端连接第二电位产生电路中的第二晶体管的衬底端的电位，第四晶体管为P型晶体管，第五晶体管为N型晶体管。
其中，可选的，记第一电位产生电路中的第一晶体管的沟道长度与第四晶体管的沟道长度之比为H1，记第一电位产生电路中的第二晶体管的沟道长度与第五晶体管的沟道长度之比为L1，记第一电位产生电路中的第一晶体管的沟道宽度与第四晶体管的沟道宽度之比为M1，记第一电位产生电路中的第二晶体管的沟道宽度与第五晶体管的沟道宽度之比为N1，H1等于L1，M1等于N1。可选的，H1、L1、M1和N1可以是1。
记第二电位产生电路中的第一晶体管的沟道长度与第四晶体管的沟道长度之比为H2，记第二电位产生电路中的第二晶体管的沟道长度与第五晶体管的沟道长度之比为L2，记第二电位产生电路中的第一晶体管的沟道宽度与第四晶体管的沟道宽度之比为M2，记第二电位产生电路中的第二晶体管的沟道宽度与第五晶体管的沟道宽度之比为N2，H2等于L2，M2等于N2。可选的，H2、L2、M2和N2可以是1。
本实施例提供的延时电路，可应用于需要精确控制延时电路的上升沿延时时间和 下降沿延迟时间的场景，例如可应用于DRAM中，可同时补偿电源电压、工作温度以及制造工艺中的任一项的变化对上升沿延时时间和下降沿延迟时间的影响，使得上升沿延时时间T和下降沿延迟时间T的变化较小，提高延时电路对上升沿延时时间和下降沿延迟时间精度的控制能力。
需要说明的是，本申请实施例提供的延时电路，可根据延迟单元所实现的上升沿延迟和/或下降沿延迟来设置上述两个实施例中所示的电位产生电路与延迟单元中的反相器的连接关系，例如，某一延时电路实现的是上升沿延迟，该延时电路包括反相器，反相器包括P型晶体管和N型晶体管，则在该延时电路中设置第一电位产生电路，第一电位产生电路可为反相器中的P型晶体管的衬底端提供随第一参数变化而变化的衬底电位，从而可调节流经反相器中的P型晶体管的电流，对流经反相器中的P型晶体管的电流的变化值进行补偿，使得延时电路的上升沿延迟时间T的变化较小。又例如，某一延时电路实现的是下降沿延迟，该延时电路包括反相器，反相器包括P型晶体管和N型晶体管，则在该延时电路中设置第二电位产生电路，第二电位产生电路可为反相器中的N型晶体管的衬底端提供随第一参数变化而变化的衬底电位，从而可调节流经反相器中的N型晶体管的电流，对流经反相器中的N型晶体管的电流的变化值进行补偿，使得延时电路的下降沿延迟时间T的变化较小。又例如，某一延时电路实现的是上升沿和下降沿均延迟，该延时电路包括反相器，反相器包括P型晶体管和N型晶体管，则在该延时电路中设置第一电位产生电路和第二电位产生电路，第一电位产生电路可为反相器中的P型晶体管的衬底端提供随第一参数变化而变化的衬底电位，从而可调节流经反相器中的P型晶体管的电流，对流经反相器中的P型晶体管的电流的变化值进行补偿，使得延时电路的上升沿延迟时间T的变化较小，第二电位产生电路可为反相器中的N型晶体管的衬底端提供随第一参数变化而变化的衬底电位，从而可调节流经反相器中的N型晶体管的电流，对流经反相器中的N型晶体管的电流的变化值进行补偿，使得延时电路的下降沿延迟时间T的变化较小。从而，可使得延时电路的上升沿延迟时间T和下降沿延迟时间T的变化较小。提高延时电路对延迟时间(包括上升沿延迟时间和下降沿延迟时间)精度的控制能力。
下面结合图28-图30给出三种延时电路的示例，图28为本申请实施例提供的一种延时电路的结构示意图，如图28所示，本实施例的延时电路包括电位产生电路1和延迟单元2，电位产生电路1为图26所示的电路，具体结构描述可参见图26所示实施例中的描述，此处不再赘述，电位产生电路1输出衬底电位BN，延迟单元2包括反相器和电容C1，反相器包括P型晶体管TP1和N型晶体管TN1，P型晶体管TP1的衬底端连接电源端Vcc，N型晶体管TN1的衬底端连接衬底电位BN。本实施例的延时电路中，电位产生电路1为延迟单元2中的N型晶体管的衬底端提供随第一参数变化而变化的衬底电位，可调节延时电路的下降沿延迟时间的变化值，使得延时电路的下降沿延迟时间的变化较小，从而，可降低延时电路的制造工艺、供电电压和工作温度对延时电路的下降沿延迟时间T的影响，使得下降沿延迟时间T的变化较小，提高延时电路对下降沿延迟时间精度的控制能力。
图29为本申请实施例提供的一种延时电路的结构示意图，如图29所示，本实施例的延时电路包括电位产生电路1和延迟单元2，电位产生电路1为图27所示的电路， 具体结构描述可参见图27所示实施例中的描述，此处不再赘述，电位产生电路1输出衬底电位BP，延迟单元2包括反相器和电容C1，反相器包括P型晶体管TP1和N型晶体管TN1，P型晶体管TP1的衬底端连接衬底电位BP，N型晶体管TN1的衬底端连接接地端。本实施例的延时电路中，电位产生电路1为延迟单元2中的P型晶体管的衬底端提供随第一参数变化而变化的衬底电位，可调节延时电路的上升沿延迟时间的变化值，使得延时电路的上升沿延迟时间的变化较小，从而，可降低延时电路的制造工艺、供电电压和工作温度对延时电路的上升沿延迟时间T的影响，使得上升沿延迟时间T的变化较小，提高延时电路对上升沿延迟时间精度的控制能力。
图30为本申请实施例提供的一种延时电路的结构示意图，如图30所示，本实施例的延时电路包括第一电位产生电路1、第二电位产生电路3和延迟单元2，第一电位产生电路1为图27所示的电路，具体结构描述可参见图27所示实施例中的描述，此处不再赘述，第一电位产生电路1输出衬底电位BN。第二电位产生电路3为图28所示的电路，具体结构描述可参见图28所示实施例中的描述，此处不再赘述，第二电位产生电路3输出衬底电位BP。延迟单元2包括反相器和电容C1，反相器包括P型晶体管TP1和N型晶体管TN1，P型晶体管TP1的衬底端连接第二电位产生电路3输出的衬底电位BP，N型晶体管TN1的衬底端连接第一电位产生电路1输出的衬底电位BN。本实施例的延时电路中，电位产生电路1为延迟单元2中的N型晶体管的衬底端提供随第一参数变化而变化的衬底电位，可调节延时电路的上升沿延迟时间的变化值，使得延时电路的上升沿延迟时间的变化较小，电位产生电路3为延迟单元2中的P型晶体管的衬底端提供随第一参数变化而变化的衬底电位，可调节延时电路的下降沿延迟时间的变化值，使得延时电路的下降沿延迟时间的变化较小，从而，可降低延时电路的制造工艺、供电电压和工作温度对延时电路的延迟时间T(包括上升沿延迟时间和下降沿延迟时间)的影响，使得延迟时间T的变化较小，提高延时电路对延迟时间精度的控制能力。
本申请实施例还提供一种反相器，图31为本申请实施例提供的一种反相器的结构示意图，如图31所示，该反相器包括：
P型晶体管TP2和N型晶体管TN2，P型晶体管TP2的源极端连接电源端，P型晶体管TP2的漏极端连接N型晶体管TN2的漏极端，N型晶体管TN2的源极端连接接地端，P型晶体管TP2的栅极端连接N型晶体管TN2的栅极端，并作为反相器的输入端，P型晶体管TP2的漏极端作为反相器的输出端。
P型晶体管TP2的衬底端连接衬底电位，N型晶体管TN2的衬底端连接接地端，衬底电位随第一参数变化而变化，第一参数为反相器的供电电压、工作温度和制造工艺中的任一项。
若第一参数为反相器的供电电压或工作温度，衬底电位随第一参数升高而升高，衬底电位随第一参数降低而降低。
本实施例提供的反相器，由于衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的衬底电位给P型晶体管TP2的衬底端，因此可调节流经反相器的P型晶体管TP2的电流，对流经P型晶体管TP2的电流的变化值进行补偿，使得反向器的上升沿延迟时间T的变化较小，提高反相器 对上升沿延迟时间精度的控制能力。
图32为本申请实施例提供的一种反相器的结构示意图，如图32所示，该反相器包括：P型晶体管TP2和N型晶体管TN2，P型晶体管TP2的源极端连接电源端，P型晶体管TP2的漏极端连接N型晶体管TN2的漏极端，N型晶体管TN2的源极端连接接地端，P型晶体管TP2的栅极端连接N型晶体管TN2的栅极端，并作为反相器的输入端，P型晶体管TP2的漏极端作为反相器的输出端。
N型晶体管TN2的衬底端连接衬底电位，P型晶体管TP2的衬底端连接电源端，衬底电位随第一参数变化而变化，第一参数为反相器的供电电压、工作温度和制造工艺中的任一项。
若第一参数为反相器的供电电压或工作温度，衬底电位随第一参数升高而降低，衬底电位随第一参数降低而升高。
本实施例提供的反相器，由于衬底电位可随供电电压、工作温度和制造工艺中的任一项的变化而变化，从而可提供随第一参数变化而变化的衬底电位给N型晶体管TN2的衬底端，因此可调节流经反相器的N型晶体管TN2的电流，对流经N型晶体管TN2的电流的变化值进行补偿，使得反向器的下降沿延迟时间T的变化较小，提高反相器对下降沿延迟时间精度的控制能力。
本申请实施例还提供一种延时电路，图33为本申请实施例提供的一种延时电路的结构示意图，如图33所示，本实施例的延时电路可以包括图31所示的反相器和电容C1，电容C1的一端连接接地端。在一种可实施的方式中，电容C1可以为电容阵列。
本实施例提供的延时电路，由于可对流经反相器的P型晶体管TP2的电流的变化值进行补偿，使得反向器的上升沿延迟时间T的变化较小，进而可使得延时电路的上升沿延迟时间T的变化较小，提高延时电路对上升沿延迟时间精度的控制能力。
本申请实施例还提供一种延时电路，图34为本申请实施例提供的一种延时电路的结构示意图，如图34所示，本实施例的延时电路可以包括图32所示的反相器和电容C1，电容C1的一端连接接地端。在一种可实施的方式中，电容C1可以为电容阵列。
本实施例提供的延时电路，由于可对流经反相器的N型晶体管TN2的电流的变化值进行补偿，使得反向器的下降沿延迟时间T的变化较小，进而可使得延时电路的下降沿延迟时间T的变化较小，提高延时电路对下降沿延迟时间精度的控制能力。
本申请实施例还提供一种逻辑门电路，包括：P型晶体管和N型晶体管，P型晶体管的衬底端连接衬底电位，N型晶体管的衬底端连接接地端，衬底电位随第一参数变化而变化，使得逻辑门电路从输入端到输出端的延迟时间随第一参数变化的变化值在第一范围内，第一参数包括逻辑门电路的供电电压、工作温度和制造工艺中的任一项。
具体来说，第一范围为一个较小的范围，例如为接近0的范围，如第一范围为1％或3％或5％，可以使得逻辑门电路从输入端到输出端的上升沿延迟时间在电源电压、工作温度和制造工艺中的任一项发生变化时的变化较小，提高逻辑门电路对上升沿延迟时间精度的控制能力。
本申请实施例还提供一种逻辑门电路，包括：P型晶体管和N型晶体管，N型晶体管的衬底端连接衬底电位，P型晶体管的衬底端连接电源端，衬底电位随第一参数 变化而变化，使得逻辑门电路从输入端到输出端的延迟时间随第一参数变化的变化值在第一范围内，第一参数包括逻辑门电路的供电电压、工作温度和制造工艺中的任一项。
具体来说，第一范围为一个较小的范围，例如为接近0的范围，如第一范围为1％或3％或5％，可以使得逻辑门电路从输入端到输出端的下降沿延迟时间在电源电压、工作温度和制造工艺中的任一项发生变化时的变化较小，提高逻辑门电路对下降沿延迟时间精度的控制能力。
实施例三
图35为本申请实施例提供的一种控制电路的结构示意图，如图35所示，本实施例的控制电路电路可以包括：控制单元41、第一反馈单元42和第二反馈单元43，其中，第一反馈单元42用于根据控制单元41的电压和第一参考电压，输出第一反馈信号，第一反馈单元42的第一端与控制单元的第一端连接，第一反馈单元42的第二端为第一参考电压的输入端，第一反馈单元42的输出端与控制单元41的第二端及第二反馈单元43的第一端连接。
第二反馈单元43用于根据第一反馈单元42输出的电压和第二参考电压，输出第二反馈信号，第二反馈单元43的第二端为第二参考电压的输入端，第二反馈单元43的输出端与控制单元41的第三端连接。
控制单元41用于根据第一反馈信号，调节控制单元41的第二端的电压，根据第二反馈信号，调节控制单元41的第三端的电压，以使控制单元41的电流随第一参数变化的变化值在第一范围内，第一参数包括控制电路的制造工艺、供电电压和工作温度中的至少一项，控制单元41的第四端连接第一电源端，控制单元41的第五端连接负电源端。其中，具体来说，第一范围为一个较小的范围，例如为接近0的范围，如第一范围为1％或3％或5％，从而可使得控制单元41的电流随第一参数变化的变化较小。
图36为本申请实施例提供的一种控制电路的结构示意图，如图36所示，本实施例与图35所示实施例的区别在于，控制单元41的第四端连接第二电源端，控制单元41的第五端连接接地端Vgg。
图35和图36所示的控制电路，通过设置控制单元、第一反馈单元和第二反馈单元，第一反馈单元的第一端与控制单元的第一端连接，第一反馈单元的第二端为第一参考电压的输入端，第一反馈单元的输出端与控制单元的第二端及第二反馈单元的第一端连接，第二反馈单元的第二端为第二参考电压的输入端，第二反馈单元的输出端与控制单元的第三端连接。第一反馈单元用于根据控制单元的电压和第一参考电压，输出第一反馈信号，第二反馈单元用于根据第一反馈单元输出的电压和第二参考电压，输出第二反馈信号，控制单元用于根据第一反馈信号，调节控制单元的第二端的电压，根据第二反馈信号，调节控制单元的第三端的电压，以使控制单元的电流随第一参数变化的变化值在第一范围内，第一参数为供电电压、工作温度和制造工艺中的任一项，从而，控制单元的第二端和控制单元的第三端可分别输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电压。
图37为本申请实施例提供的一种控制电路的结构示意图，如图37所示，本实施 例的控制电路电路在图35所示电路的基础上，进一步地，控制单元41可以包括反相器411和恒流源412，其中，反相器411的第一端连接第一电源端；
恒流源412的第一端与反相器411的第二端连接，恒流源412的第二端连接负电源端；
反相器411的输入端与反相器411的输出端短接。
图38为本申请实施例提供的一种控制电路的结构示意图，如图38所示，本实施例的控制电路电路在图37所示电路的基础上，进一步地，反相器411包括第一晶体管T1和第二晶体管T2，第一晶体管T1的衬底端连接第二反馈单元43的输出端，第二晶体管T2的衬底端连接第一反馈单元42的输出端；
第一晶体管T1的第一端接第一电源端，第一晶体管T1的第二端接第二晶体管T2的第一端，第一晶体管T1的控制端和第二晶体管T2的控制端连接，第二晶体管T2的第二端与恒流源412的第一端连接。
本实施例中，控制单元41用于根据第一反馈信号，调节第二晶体管T2的衬底端的电压，根据第二反馈信号，调节第一晶体管T1的衬底端的电压。
本实施例提供的控制电路，控制单元用于根据第一反馈信号，调节第二晶体管的衬底端的电压，根据第二反馈信号，调节第一晶体管的衬底端的电压，以使控制单元的电流随第一参数变化的变化值在第一范围内，第一参数为供电电压、工作温度和制造工艺中的任一项，从而，第一晶体管的衬底端和第二晶体管的衬底端可分别输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电压。
图39为本申请实施例提供的一种控制电路的结构示意图，如图39所示，本实施例的控制电路电路在图36所示电路的基础上，进一步地，控制单元41可以包括反相器411和恒流源412，反相器411的第一端连接接地端；
恒流源412的第一端与反相器411的第二端连接，恒流源412的第二端连接第二电源端；
反相器411的输入端与反相器411的输出端短接。
图40为本申请实施例提供的一种控制电路的结构示意图，如图40所示，本实施例的控制电路电路在图39所示电路的基础上，进一步地，反相器411包括第一晶体管T1和第二晶体管T2，第一晶体管T1的衬底端连接第一反馈单元的输出端，第二晶体管T2的衬底端连接第二反馈单元43的输出端。
第一晶体管T1的第一端接恒流源的第一端，第一晶体管T1的第二端接第二晶体管T2的第一端，第一晶体管T1的控制端和第二晶体管T2的控制端连接，第二晶体管T2的第二端连接接地端。
本实施例中，控制单元41用于根据第一反馈信号，调节第二晶体管T2的衬底端的电压，根据第二反馈信号，调节第一晶体管T1的衬底端的电压。
本实施例提供的控制电路，控制单元用于根据第一反馈信号，调节第二晶体管的衬底端的电压，根据第二反馈信号，调节第一晶体管的衬底端的电压，以使控制单元的电流随第一参数变化的变化值在第一范围内，第一参数为供电电压、工作温度和制造工艺中的任一项，从而，第一晶体管的衬底端和第二晶体管的衬底端可分别输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电压。
在图38和图40所示的控制电路中，第一晶体管为P型晶体管，第二晶体管为N型晶体管。
下面结合附图详细说明第一反馈单元和第二反馈单元的具体可实施的结构。
图41为本申请实施例提供的一种控制电路的结构示意图，如图41所示，本实施例的控制电路电路在图38所示电路的基础上，进一步地，第一反馈单元42包括第一误差放大器421，第一误差放大器421的负输入端与控制单元41的第一端连接，第一误差放大器421的正输入端为第一参考电压的输入端，第一误差放大器421的输出端与控制单元41的第二端及第二反馈单元43的第一端连接。
如图41所示，进一步地，第二反馈单元43包括第二误差放大器431、第一电阻R1、第二电阻R2和第三晶体管T3，其中，第二误差放大器431的负输入端为第二参考电压的输入端，第二误差放大器431的正输入端与第一电阻R1的第一端和第二电阻R2的第一端连接，第二误差放大器431的输出端连接第三晶体管T3的控制端；
第一电阻R1的第二端连接第三晶体管T3的第一端与控制单元41的第三端；
第二电阻R2的第二端连接第一反馈单元的输出端与控制单元41的第二端；
第三晶体管的第二端连接第一电源端。
图42为本申请实施例提供的一种控制电路的结构示意图，如图42所示，本实施例的控制电路电路在图40所示电路的基础上，进一步地，第一反馈单元42包括第一误差放大器421，第一误差放大器421的负输入端与控制单元41的第一端连接，第一误差放大器421的正输入端为第一参考电压的输入端，第一误差放大器421的输出端与控制单元41的第二端及第二反馈单元43的第一端连接。
如图42所示，进一步地，第二反馈单元43包括第二误差放大器431、第一电阻R1、第二电阻R2和第三晶体管T3，其中，第二误差放大器431的负输入端为第二参考电压的输入端，第二误差放大器431的正输入端与第一电阻R1的第一端和第二电阻R2的第一端连接，第二误差放大器431的输出端连接第三晶体管T3的控制端；
第一电阻R1的第二端连接第一反馈单元的输出端与控制单元41的第二端；
第二电阻R2的第二端连接第三晶体管T3的第一端与控制单元41的第三端；
第三晶体管的第二端连接接地端。
在图41或图42所示的控制电路中，进一步地，还可以包括第一缓冲器和第二缓冲器，图43为本申请实施例提供的一种控制电路的结构示意图，图44为本申请实施例提供的一种控制电路的结构示意图，如图43和图44所示，在图41或图42所示的控制电路的基础上，进一步地，还可以包括：第一缓冲器44和第二缓冲器45，其中，第一缓冲器44连接第一晶体管T1的衬底端，并输出第一衬底电压，第一衬底电压的值等于第一晶体管T1的衬底端的电压值，第一缓冲器44的输入电压和输出电压相同，第一缓冲器44用于增强第一晶体管T1的衬底端的电位的驱动能力，还可以对第一晶体管T1的衬底端隔离，避免第一晶体管T1的衬底端的电位受到干扰。
第二缓冲器45连接第二晶体管T2的衬底端，并输出第二衬底电压，第二衬底电压的值等于第一晶体管T1的衬底端的电压值，第二缓冲器45用于增强第二晶体管T2的衬底端的电位的驱动能力，还可以对第二晶体管T2的衬底端隔离，避免第二晶体管T2的衬底端的电位受到干扰。
需要说明的是，在图35-图44所示的控制电路中，第一电源端的电压例如为Vcc，第二参考电压可以为Vcc/2，负电源端的电压可以为小于0的电压值，第一参考电压可以为0。
第二电源端的电压大于第一参考电压的电压，第二参考电压的值可以为第一参考电压的一半，例如，第二电源端的电压为Vdd，第一参考电压为Vcc，Vdd大于Vcc，第二参考电压的值可以为Vcc/2。
下面结合具体实施例对本申请的控制电路的结构进行说明，本申请的控制电路的具体结构并不局限于下面任一种结构。
具体地，本实施例的控制电路的具体结构可参见图11和图12所示的电路结构，图11和图12所示的电位产生电路即为本实施例中的控制电路，工作原理相同，详细可参见图11和图12所示实施例的描述，此处不再赘述。
申请实施例还提供一种延时电路，包括图35-图44任一所示的控制电路和延迟单元，其中，控制电路中的控制单元的第二端与延迟单元的第一端连接，控制单元的第三端与延迟单元的第二端连接，控制电路用于控制延迟单元的上升沿延迟时间和/或下降沿延迟时间随第一参数变化的变化值在第一范围内。
可选的，延迟单元包括反相器，反相器包括第四晶体管和第五晶体管，控制单元的第三端与第四晶体管的衬底端连接，控制单元的第二端与第五晶体管的衬底端连接。
可选的，第四晶体管为P型晶体管，第五晶体管为N型晶体管。
本实施例中，可选的，延时电路中控制电路为图38或图40或图41-图44任一所示的控制电路时，记第一晶体管的沟道长度与第四晶体管的沟道长度之比为H，记第二晶体管的沟道长度与第五晶体管的沟道长度之比为L，记第一晶体管的沟道宽度与第四晶体管的沟道宽度之比为M，记第二晶体管的沟道宽度与第五晶体管的沟道宽度之比为N，H等于L，M等于N。
本实施例提供的延时电路，由于控制单元的第二端和控制单元的第三端可分别输出随第一参数(为供电电压、工作温度和制造工艺中的任一项)变化而变化的电压。从而可为第四晶体管的衬底端提供随第一参数变化而变化的第一衬底电压，可为第五晶体管的衬底端提供随第一参数变化而变化的第二衬底电压，因此可调节流经反相器的两个晶体管的电流随第一参数变化的变化值在第一范围内，对流经反相器的两个晶体管的电流的变化值进行补偿，使得延时电路的延迟时间T的变化较小，提高延时电路对延迟时间精度的控制能力。
需要说明的是，本申请实施例中可根据延时电路所包括的反相器的个数及延迟时间补偿的需求设置控制电路与反相器的连接关系，反相器中P型晶体管的衬底端连接控制电路中P型晶体管的衬底端，可调节延时电路的上升沿延迟时间的变化值，反相器中N型晶体管的衬底端连接控制电路中N型晶体管的衬底端，可调节延时电路的下降沿延迟时间的变化值，具体可根据所需调节的上升沿和/或下降沿延迟时间的变化值，设置控制电路与反相器的连接关系。本申请实施例提供的控制电路，可应用于上升沿和/或下降沿均延迟的延时电路中，可降低延时电路的制造工艺、供电电压和工作温度对延时电路的延迟时间T的影响，使得延迟时间T(包括上升沿和/或下降沿)的变化较小，提高延时电路对延迟时间精度的控制能力。
图13-图15给出两种延时电路的示例，也适用于本实施例中，图13-图15中所示的电位产生电路即为本实施例中具体的控制电路，可参见图13-图15中具体的描述，此处不再赘述。
实施例四
图45为本申请实施例提供的一种控制电路的结构示意图，如图45所示，本实施例的控制电路电路可以包括：控制单元51和反馈单元52，其中，
反馈单元52用于根据控制单元51的电压和参考电压，输出反馈信号，其第一端与控制单元51的第一端连接，其第二端为参考电压的输入端，其输出端与控制单元51的第二端连接。
控制单元51用于根据反馈信号，调节控制单元51的第二端的电压，以使控制单元51的电流随第一参数变化的变化值在第一范围内，第一参数包括控制电路的制造工艺、供电电压和工作温度中的至少一项，控制单元51的第三端连接第一电源端，控制单元51的第四端连接负电源端。
具体来说，第一范围为一个较小的范围，例如为接近0的范围，如第一范围为1％或3％或5％，从而可使得控制单元41的电流随第一参数变化的变化较小。
图46为本申请实施例提供的一种控制电路的结构示意图，如图46所示，本实施例与图45所示实施例的区别在于，控制单元51的第三端连接第二电源端，控制单元51的第四端连接接地端Vgg。
图45和图46所示的控制电路，通过设置控制单元和反馈单元，反馈单元用于根据控制单元的电压和参考电压，输出反馈信号，控制单元用于根据反馈信号，调节控制单元的第二端的电压，以使控制单元的电流随第一参数变化的变化值在第一范围内，第一参数为供电电压、工作温度和制造工艺中的任一项，从而，控制单元的第二端可输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电压。
图47为本申请实施例提供的一种控制电路的结构示意图，如图47所示，本实施例的控制电路电路在图45所示电路的基础上，进一步地，控制单元51可以包括反相器511和恒流源512，反相器511的第一端连接第一电源端，恒流源512的第一端与反相器511的第二端连接，恒流源512的第二端连接负电源端，反相器511的输入端与反相器511的输出端短接。
图48为本申请实施例提供的一种控制电路的结构示意图，如图48所示，本实施例的控制电路电路在图47所示电路的基础上，进一步地，反相器411包括第一晶体管T1和第二晶体管T2，第一晶体管T1的衬底端连接第一电源端，第二晶体管T2的衬底端连接反馈单元52的输出端；
第一晶体管T1的第一端接第一电源端，第一晶体管T1的第二端接第二晶体管T2的第一端，第一晶体管T1的控制端和第二晶体管T2的控制端连接，第二晶体管T2的第二端与恒流源的第一端连接。
本实施例中，控制单元41用于根据反馈信号，调节第二晶体管T2的衬底端的电压。
本实施例提供的控制电路，控制单元用于根据反馈信号，调节第二晶体管的衬底 端的电压，以使控制单元的电流随第一参数变化的变化值在第一范围内，第一参数为供电电压、工作温度和制造工艺中的任一项，从而，第二晶体管的衬底端可分别输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电压。
图49为本申请实施例提供的一种控制电路的结构示意图，如图49所示，本实施例的控制电路电路在图46所示电路的基础上，进一步地，控制单元51可以包括反相器511和恒流源512，其中，反相器511的第一端连接接地端，恒流源512的第一端与反相器511的第二端连接，恒流源512的第二端连接第二电源端，反相器511的输入端与反相器511的输出端短接。
图50为本申请实施例提供的一种控制电路的结构示意图，如图50所示，本实施例的控制电路电路在图49所示电路的基础上，进一步地，反相器511包括第一晶体管T1和第二晶体管T2，第一晶体管T1的衬底端连接反馈单元的输出端，第二晶体管的衬底端连接接地端；
第一晶体管T1的第一端连接恒流源的第一端，第一晶体管T1的第二端连接第二晶体管T2的第一端，第一晶体管T1的控制端和第二晶体管T2的控制端连接，第二晶体管T2的第二端连接接地端。
本实施例中，控制单元51用于根据反馈信号，调节第一晶体管T1的衬底端的电压。
本实施例提供的控制电路，控制单元用于根据反馈信号，调节第一晶体管的衬底端的电压，以使控制单元的电流随第一参数变化的变化值在第一范围内，第一参数为供电电压、工作温度和制造工艺中的任一项，从而，第一晶体管的衬底端可分别输出随供电电压、工作温度和制造工艺中的任一项变化而变化的电压。
在图48和图50所示的控制电路中，第一晶体管为P型晶体管，第二晶体管为N型晶体管。
下面结合附图详细说明反馈单元的具体可实施的结构。
图51为本申请实施例提供的一种控制电路的结构示意图，如图51所示，本实施例的控制电路电路在图48所示电路的基础上，进一步地，反馈单元52包括误差放大器521，误差放大器521的负输入端与恒流源512的第一端和第二晶体管T2的第二端连接，误差放大器521的正输入端为参考电压输入端，误差放大器521的输出端与第二晶体管T2的衬底端连接。
图52为本申请实施例提供的一种控制电路的结构示意图，如图52所示，本实施例的控制电路电路在图51所示电路的基础上，进一步地，还可以包括：
缓冲器53，缓冲器53连接第二晶体管T2的衬底端，并输出第一衬底电压，第一衬底电压的值等于第二晶体管T2的衬底端的电压值。
图53为本申请实施例提供的一种控制电路的结构示意图，如图53所示，本实施例的控制电路电路在图50所示电路的基础上，进一步地，反馈单元52包括误差放大器521，误差放大器521的负输入端与恒流源512的第一端和第一晶体管T1的第一端连接，误差放大器521的负输入端为参考电压输入端，误差放大器521的输出端与述第一晶体管T1的衬底端连接。
图54为本申请实施例提供的一种控制电路的结构示意图，如图54所示，本实施 例的控制电路电路在图53所示电路的基础上，进一步地，还可以包括：缓冲器53，缓冲器53连接第一晶体管T1的衬底端，并输出第二衬底电压，第二衬底电压的值等于第一晶体管T1的衬底端的电压值。
需要说明的是，在图45-图54所示的控制电路中，第一电源端的电压例如为Vcc，第二参考电压可以为Vcc/2，负电源端的电压可以为0或小于0，第一参考电压可以为0。
第二电源端的电压大于第一参考电压的电压，第二参考电压的值可以为第一参考电压的一半，例如，第二电源端的电压为Vdd，第一参考电压为Vcc，Vdd大于Vcc，第二参考电压的值可以为Vcc/2。
下面结合具体实施例对本申请的控制电路的结构进行说明，本申请的控制电路的具体结构并不局限于下面任一种结构。
具体地，本实施例的控制电路的具体结构可参见图26和图27所示的电路结构，图26和图27所示的电位产生电路即为本实施例中的控制电路，工作原理相同，详细可参见图26和图27所示实施例的描述，此处不再赘述。
本申请实施例还提供一种延时电路，包括图45-图54任一所示的控制电路和延迟单元，其中，控制单元的第二端与延迟单元的第一端连接，控制电路用于控制延迟单元的上升沿延迟时间和/或下降沿延迟时间随第一参数变化的变化值在第一范围内。
可选的，延迟单元包括反相器，反相器包括第四晶体管和第五晶体管，控制单元的第二端与第四晶体管的衬底端或第五晶体管的衬底端连接。
可选的，第四晶体管为P型晶体管，第五晶体管为N型晶体管。
控制单元的第五端连接负电源端时，控制单元的第二端与第五晶体管的衬底端连接。
控制单元的第三端连接第二电源端，控制单元的第四端连接接地端时，控制单元的第二端与第四晶体管的衬底端连接。
本实施例中，可选的，延时电路中控制电路为图48或图50或图51-图54任一所示的控制电路时，记第一晶体管的沟道长度与第四晶体管的沟道长度之比为H，记第二晶体管的沟道长度与第五晶体管的沟道长度之比为L，记第一晶体管的沟道宽度与第四晶体管的沟道宽度之比为M，记第二晶体管的沟道宽度与第五晶体管的沟道宽度之比为N，H等于L，M等于N。
本实施例提供的延时电路，由于控制单元的第二端可输出随第一参数(为供电电压、工作温度和制造工艺中的任一项)变化而变化的电压。从而可为第四晶体管的衬底端提供随第一参数变化而变化的第一衬底电压，因此可调节流经反相器的第四晶体管的电流随第一参数变化的变化值在第一范围内，对流经反相器的第四晶体管的电流的变化值进行补偿，使得延时电路的上升沿延迟时间T的变化较小，提高延时电路对上升沿延迟时间精度的控制能力。
或者可为第五晶体管的衬底端提供随第一参数变化而变化的第一衬底电压，因此可调节流经反相器的第五晶体管的电流随第一参数变化的变化值在第一范围内，对流经反相器的第五晶体管的电流的变化值进行补偿，使得延时电路的下降沿延迟时间T的变化较小，提高延时电路对下降沿延迟时间精度的控制能力。
需要说明的是，本申请实施例提供的延时电路，可根据延迟单元所实现的上升沿延迟和/或下降沿延迟来设置上述两个实施例中所示的控制电路与延迟单元中的反相器的连接关系，例如，某一延时电路实现的是上升沿延迟，该延时电路包括反相器，反相器包括P型晶体管和N型晶体管，则在该延时电路中设置第一控制电路，第一控制电路可调节反相器中的P型晶体管的衬底端的电压，从而可调节流经反相器中的P型晶体管的电流，使得流经反相器中的P型晶体管的电流随第一参数变化的变化值在第一范围内，对流经反相器中的P型晶体管的电流的变化值进行补偿，使得延时电路的上升沿延迟时间T的变化较小。又例如，某一延时电路实现的是下降沿延迟，该延时电路包括反相器，反相器包括P型晶体管和N型晶体管，则在该延时电路中设置第二控制电路，第二控制电路可调节反相器中的N型晶体管的衬底端的电压，从而可调节流经反相器中的N型晶体管的电流，使得流经反相器中的N型晶体管的电流随第一参数变化的变化值在第一范围内，对流经反相器中的N型晶体管的电流的变化值进行补偿，使得延时电路的下降沿延迟时间T的变化较小。又例如，某一延时电路实现的是上升沿和下降沿均延迟，该延时电路包括反相器，反相器包括P型晶体管和N型晶体管，则在该延时电路中设置第一控制电路和第二控制电路，第一控制电路可调节反相器中的P型晶体管的衬底端的电压，从而可调节流经反相器中的P型晶体管的电流，使得流经反相器中的P型晶体管的电流随第一参数变化的变化值在第一范围内，对流经反相器中的P型晶体管的电流的变化值进行补偿，使得延时电路的上升沿延迟时间T的变化较小，第二控制电路可调节反相器中的N型晶体管的衬底端的电压，从而可调节流经反相器中的N型晶体管的电流，使得流经反相器中的N型晶体管的电流随第一参数变化的变化值在第一范围内，对流经反相器中的N型晶体管的电流的变化值进行补偿，使得延时电路的下降沿延迟时间T的变化较小。从而，可使得延时电路的上升沿延迟时间T和下降沿延迟时间T的变化较小。提高延时电路对延迟时间(包括上升沿延迟时间和下降沿延迟时间)精度的控制能力。
图28-图30给出两种延时电路的示例，也适用于本实施例中，图28-图30中所示的电位产生电路即为本实施例中具体的控制电路，可参见图28-图30中具体的描述，此处不再赘述。
上述实施例中的恒流源例如可以用镜像电流源，镜像端的电流可以是与温度系数无关的电流，或者该电流与温度、电压等均无关；上述实施例中的恒流源也可以采用其他方式实现。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (32)

  1. 一种电位产生电路，包括：
    第一晶体管和第二晶体管，所述第一晶体管的衬底端的电位随第一参数变化而变化，所述第一参数为所述电位产生电路的供电电压、工作温度和制造工艺中的任一项；
    其中，所述第一晶体管的栅极端连接所述第一晶体管的漏极端，所述第一晶体管的衬底端作为所述电位产生电路的输出端；所述第二晶体管的栅极端连接所述第二晶体管的漏极端。
  2. 根据权利要求1所述的电位产生电路，所述第一参数为所述电位产生电路的供电电压或工作温度，所述第一晶体管的衬底端的电位随所述第一参数升高而升高，所述第一晶体管的衬底端的电位随所述第一参数降低而降低。
  3. 根据权利要求1所述的电位产生电路，所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管。
  4. 根据权利要求3所述的电位产生电路，所述第一晶体管的源极端连接第一电压节点，所述第二晶体管的源极端连接第二电压节点，所述第一晶体管的漏极端连接所述第二晶体管的漏极端，所述第二晶体管的衬底端连接所述第二电压节点。
  5. 根据权利要求4所述的电位产生电路，还包括：
    恒流源，所述恒流源的第一端连接所述第一电压节点，所述恒流源的第二端连接第三电压节点。
  6. 根据权利要求5所述的电位产生电路，还包括：
    误差放大器，与所述第一晶体管构成第一反馈回路，所述第一晶体管的衬底端连接所述第一反馈回路的一个电压节点。
  7. 根据权利要求6所述的电位产生电路，所述误差放大器的负输入端连接所述第一电压节点，所述误差放大器的正输入端连接第一参考电压，所述误差放大器的输出端连接所述第一晶体管的衬底端。
  8. 根据权利要求7所述的电位产生电路，所述第三电压节点连接电源端，所述第一参考电压连接电源端，所述第三电压节点的电位大于所述第一参考电压的电位。
  9. 根据权利要求1-7任一项所述的电位产生电路，还包括：
    缓冲器，所述缓冲器连接所述输出端，并输出衬底电位，所述衬底电位的值等于所述第一晶体管的衬底端的电位值。
  10. 一种电位产生电路，包括：
    第一晶体管和第二晶体管，所述第二晶体管的衬底端的电位随第一参数变化而变化，所述第一参数为所述电位产生电路的供电电压、工作温度和制造工艺中的任一项；
    其中，所述第一晶体管的栅极端连接所述第一晶体管的漏极端，所述第二晶体管的栅极端连接所述第二晶体管的漏极端，所述第二晶体管的衬底端作为所述电位产生电路的输出端。
  11. 根据权利要求10所述的电位产生电路，所述第一参数为所述电位产生电路的供电电压或工作温度，所述第二晶体管的衬底端的电位随所述第一参数升高而降低，所述第二晶体管的衬底端的电位随所述第一参数降低而升高。
  12. 根据权利要求10所述的电位产生电路，所述第一晶体管为P型晶体管，所述 第二晶体管为N型晶体管。
  13. 根据权利要求12所述的电位产生电路，所述第一晶体管的源极端连接第一电压节点，所述第二晶体管的源极端连接第二电压节点，所述第一晶体管的漏极端连接所述第二晶体管的漏极端，所述第一晶体管的衬底端连接所述第一电压节点。
  14. 根据权利要求13所述的电位产生电路，还包括：
    恒流源，所述恒流源的第一端连接第三电压节点，所述恒流源的第二端连接所述第二电压节点。
  15. 根据权利要求14所述的电位产生电路，还包括：
    误差放大器，与所述第二晶体管构成第一反馈回路，所述第二晶体管的衬底端连接所述第一反馈回路的一个电压节点。
  16. 根据权利要求15所述的电位产生电路，所述误差放大器的负输入端连接所述第二电压节点，所述误差放大器的正输入端连接第一参考电压，所述误差放大器的输出端连接所述第二晶体管的衬底端。
  17. 根据权利要求16所述的电位产生电路，所述第一电压节点连接电源端，所述第一参考电压连接接地端，所述第三电压节点的电位小于所述第一参考电压的电位。
  18. 根据权利要求10-16任一项所述的电位产生电路，还包括：
    缓冲器，所述缓冲器连接所述输出端，并输出衬底电位，所述衬底电位的值等于所述第二晶体管的衬底端的电位值。
  19. 一种延时电路，包括：
    如权利要求1-9任一项所述的电位产生电路；
    延迟单元，所述延迟单元包括第一反相器，所述第一反相器包括第四晶体管和第五晶体管，所述第四晶体管的衬底端连接所述第一晶体管的衬底端的电位，所述第五晶体管的衬底端连接接地端，所述第四晶体管为P型晶体管，所述第五晶体管为N型晶体管。
  20. 根据权利要求19所述的延时电路，记所述第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H，记所述第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L，记所述第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M，记所述第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N，所述H等于所述L，所述M等于所述N。
  21. 一种延时电路，包括：
    如权利要求10-18任一项所述的电位产生电路；
    延迟单元，所述延迟单元包括第一反相器，所述第一反相器包括第四晶体管和第五晶体管，所述第四晶体管的衬底端连接所述第一晶体管的衬底端的电位，所述第五晶体管的衬底端连接电源端，所述第四晶体管为P型晶体管，所述第五晶体管为N型晶体管。
  22. 根据权利要求21所述的延时电路，记所述第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H，记所述第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L，记所述第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M，记所述第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N，所述H等于所 述L，所述M等于所述N。
  23. 一种延时电路，包括：
    第一电位产生电路，所述第一电位产生电路为如权利要求1-9任一项所述的电位产生电路；
    第二电位产生电路，所述第二电位产生电路为如权利要求10-18任一项所述的电位产生电路；
    延迟单元，所述延迟单元包括第一反相器，所述第一反相器包括第四晶体管和第五晶体管，所述第四晶体管的衬底端连接所述第一电位产生电路中的第一晶体管的衬底端的电位，所述第五晶体管的衬底端连接所述第二电位产生电路中的第二晶体管的衬底端的电位，所述第四晶体管为P型晶体管，所述第五晶体管为N型晶体管。
  24. 根据权利要求23所述的延时电路，记所述第一电位产生电路中的第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H1，记所述第一电位产生电路中的第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L1，记所述第一电位产生电路中的第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M1，记所述第一电位产生电路中的第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N1，所述H1等于所述L1，所述M1等于所述N1；
    记所述第二电位产生电路中的第一晶体管的沟道长度与所述第四晶体管的沟道长度之比为H2，记所述第二电位产生电路中的第二晶体管的沟道长度与所述第五晶体管的沟道长度之比为L2，记所述第二电位产生电路中的第一晶体管的沟道宽度与所述第四晶体管的沟道宽度之比为M2，记所述第二电位产生电路中的第二晶体管的沟道宽度与所述第五晶体管的沟道宽度之比为N2，所述H2等于所述L2，所述M2等于所述N2。
  25. 一种反相器，包括：
    P型晶体管和N型晶体管，所述P型晶体管的源极端连接电源端，所述P型晶体管的漏极端连接所述N型晶体管的漏极端，所述N型晶体管的源极端连接接地端，所述P型晶体管的栅极端连接所述N型晶体管的栅极端，并作为所述反相器的输入端，所述P型晶体管的漏极端作为所述反相器的输出端；
    所述P型晶体管的衬底端连接衬底电位，所述N型晶体管的衬底端连接接地端，所述衬底电位随第一参数变化而变化，所述第一参数为所述反相器的供电电压、工作温度和制造工艺中的任一项。
  26. 根据权利要求25所述的反相器，所述第一参数为所述反相器的供电电压或工作温度，所述衬底电位随所述第一参数升高而升高，所述衬底电位随所述第一参数降低而降低。
  27. 一种反相器，包括：
    P型晶体管和N型晶体管，所述P型晶体管的源极端连接电源端，所述P型晶体管的漏极端连接所述N型晶体管的漏极端，所述N型晶体管的源极端连接接地端，所述P型晶体管的栅极端连接所述N型晶体管的栅极端，并作为所述反相器的输入端，所述P型晶体管的漏极端作为所述反相器的输出端；
    所述N型晶体管的衬底端连接衬底电位，所述P型晶体管的衬底端连接电源端， 所述衬底电位随第一参数变化而变化，所述第一参数为所述反相器的供电电压、工作温度和制造工艺中的任一项。
  28. 根据权利要求27所述的反相器，所述第一参数为所述反相器的供电电压或工作温度，所述衬底电位随所述第一参数升高而降低，所述衬底电位随所述第一参数降低而升高。
  29. 一种延时电路，包括：
    如权利要求25-28任一项所述的反相器；
    电容，其一端与所述反相器的输出端连接，其另一端连接所述电源端或所述接地端。
  30. 根据权利要求29所述的延时电路，所述电容为电容阵列。
  31. 一种逻辑门电路，包括：
    P型晶体管和N型晶体管，所述P型晶体管的衬底端连接衬底电位，所述N型晶体管的衬底端连接接地端，所述衬底电位随第一参数变化而变化，使得所述逻辑门电路从输入端到输出端的延迟时间随所述第一参数变化的变化值在第一范围内，所述第一参数包括所述逻辑门电路的供电电压、工作温度和制造工艺中的任一项。
  32. 一种逻辑门电路，包括：
    P型晶体管和N型晶体管，所述N型晶体管的衬底端连接衬底电位，所述P型晶体管的衬底端连接电源端，所述衬底电位随第一参数变化而变化，使得所述逻辑门电路从输入端到输出端的延迟时间随所述第一参数变化的变化值在第一范围内，所述第一参数包括所述逻辑门电路的供电电压、工作温度和制造工艺中的任一项。
PCT/CN2021/098722 2020-11-25 2021-06-07 电位产生电路、反相器、延时电路和逻辑门电路 Ceased WO2022110757A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/446,302 US11681313B2 (en) 2020-11-25 2021-08-29 Voltage generating circuit, inverter, delay circuit, and logic gate circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011340770.2A CN114553196B (zh) 2020-11-25 2020-11-25 电位产生电路、反相器、延时电路和逻辑门电路
CN202011340770.2 2020-11-25

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/446,302 Continuation US11681313B2 (en) 2020-11-25 2021-08-29 Voltage generating circuit, inverter, delay circuit, and logic gate circuit

Publications (1)

Publication Number Publication Date
WO2022110757A1 true WO2022110757A1 (zh) 2022-06-02

Family

ID=81659612

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/098722 Ceased WO2022110757A1 (zh) 2020-11-25 2021-06-07 电位产生电路、反相器、延时电路和逻辑门电路

Country Status (2)

Country Link
CN (1) CN114553196B (zh)
WO (1) WO2022110757A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1216880A (zh) * 1997-11-01 1999-05-19 Lg半导体株式会社 延迟电路
US20080211572A1 (en) * 2007-01-23 2008-09-04 Elpida Memory Inc. Reference voltage generating circuit and semiconductor integrated circuit device
CN104038201A (zh) * 2013-03-07 2014-09-10 德克萨斯仪器股份有限公司 补偿保持违规的方法和设备
CN106301346A (zh) * 2016-08-08 2017-01-04 成都华微电子科技有限公司 具有稳定输入翻转电平的接收器控制方法
CN109379060A (zh) * 2014-08-30 2019-02-22 意法半导体国际有限公司 对于过程、温度和电压变化而具有稳定频率的cmos振荡器
CN109450415A (zh) * 2018-09-28 2019-03-08 湖南国科微电子股份有限公司 一种延迟电路
CN110377088A (zh) * 2019-07-10 2019-10-25 深圳市锐能微科技有限公司 一种集成电路、低压差线性稳压电路及其控制方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3311133B2 (ja) * 1994-02-16 2002-08-05 株式会社東芝 出力回路
JP4084872B2 (ja) * 1997-08-28 2008-04-30 株式会社リコー ボルテージレギュレータ
JP3593486B2 (ja) * 2000-01-28 2004-11-24 株式会社東芝 電圧比較回路およびこれを用いた基板バイアス調整回路
CN100352059C (zh) * 2002-10-21 2007-11-28 松下电器产业株式会社 半导体集成电路装置
JP2006134268A (ja) * 2004-11-09 2006-05-25 Nec Electronics Corp レギュレータ回路
US7525391B2 (en) * 2007-05-17 2009-04-28 Finisar Corporation Linear transimpedance amplifier with multiplexed gain stage
JP2009188904A (ja) * 2008-02-08 2009-08-20 Seiko Epson Corp 遅延回路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1216880A (zh) * 1997-11-01 1999-05-19 Lg半导体株式会社 延迟电路
US20080211572A1 (en) * 2007-01-23 2008-09-04 Elpida Memory Inc. Reference voltage generating circuit and semiconductor integrated circuit device
CN104038201A (zh) * 2013-03-07 2014-09-10 德克萨斯仪器股份有限公司 补偿保持违规的方法和设备
CN109379060A (zh) * 2014-08-30 2019-02-22 意法半导体国际有限公司 对于过程、温度和电压变化而具有稳定频率的cmos振荡器
CN106301346A (zh) * 2016-08-08 2017-01-04 成都华微电子科技有限公司 具有稳定输入翻转电平的接收器控制方法
CN109450415A (zh) * 2018-09-28 2019-03-08 湖南国科微电子股份有限公司 一种延迟电路
CN110377088A (zh) * 2019-07-10 2019-10-25 深圳市锐能微科技有限公司 一种集成电路、低压差线性稳压电路及其控制方法

Also Published As

Publication number Publication date
CN114553196A (zh) 2022-05-27
CN114553196B (zh) 2026-01-16

Similar Documents

Publication Publication Date Title
US11528020B2 (en) Control circuit and delay circuit
US11681313B2 (en) Voltage generating circuit, inverter, delay circuit, and logic gate circuit
US20180292854A1 (en) Voltage regulator
US11887652B2 (en) Control circuit and delay circuit
US10574221B2 (en) Comparator, integrated circuit, and method
TWI773214B (zh) 振盪電路以及半導體積體電路
KR101948223B1 (ko) 차동 증폭기 회로
US7768307B2 (en) Current mode logic-complementary metal oxide semiconductor converter
WO2022110696A1 (zh) 电位产生电路、反相器、延时电路和逻辑门电路
WO2022110697A1 (zh) 控制电路和延时电路
US6377095B1 (en) Digital-edge-rate control LVDS driver
WO2022110698A1 (zh) 控制电路和延时电路
TW202232900A (zh) 接收器電路以及資料接收器
KR100718044B1 (ko) 반도체 장치의 입력회로
WO2022110757A1 (zh) 电位产生电路、反相器、延时电路和逻辑门电路
US6930530B1 (en) High-speed receiver for high I/O voltage and low core voltage
JP2872058B2 (ja) 出力バッファ回路
US11550350B2 (en) Potential generating circuit, inverter, delay circuit, and logic gate circuit
CN113452332B (zh) 差分放大器
CN212032037U (zh) 一种恒流源电路和电源
TWI781598B (zh) 放大器以及lpddr3輸入緩衝器
CN116455339A (zh) 运算放大器
CN114914785A (zh) 一种驱动eml型激光器的输出级电路
CN115314040A (zh) 放大器以及lpddr3输入缓冲器
TW202211628A (zh) 緩衝電路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21896266

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21896266

Country of ref document: EP

Kind code of ref document: A1