WO2022105059A1 - 示波器的触发系统、触发方法、示波器以及存储介质 - Google Patents

示波器的触发系统、触发方法、示波器以及存储介质 Download PDF

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Publication number
WO2022105059A1
WO2022105059A1 PCT/CN2021/074271 CN2021074271W WO2022105059A1 WO 2022105059 A1 WO2022105059 A1 WO 2022105059A1 CN 2021074271 W CN2021074271 W CN 2021074271W WO 2022105059 A1 WO2022105059 A1 WO 2022105059A1
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trigger
module
signal
oscilloscope
signals
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PCT/CN2021/074271
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English (en)
French (fr)
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史慧
张宁强
王悦
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北京普源精电科技有限公司
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Publication of WO2022105059A1 publication Critical patent/WO2022105059A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0218—Circuits therefor
    • G01R13/0254—Circuits therefor for triggering, synchronisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form

Definitions

  • the present application relates to the technical field of test and measurement, for example, to a trigger system of an oscilloscope, a trigger method, an oscilloscope, and a storage medium.
  • Triggering is one of the core functions of an oscilloscope and is very important for stable waveform display. If there is no trigger function, the oscilloscope may acquire the waveform in any time position of the signal to be sampled in the current sampling, and in the next sampling, the oscilloscope may acquire the waveform in another time position of the signal to be sampled. The waveform seen on the screen is unstable.
  • the trigger system of the oscilloscope includes interconnected trigger comparators and trigger control modules, and the oscilloscope also includes: a sampling storage module and a display module.
  • the trigger comparator compares the trigger signal and the trigger level, generates a reference trigger signal, and sends the reference trigger signal to the trigger control module.
  • the trigger control module determines the trigger position according to the reference trigger signal and the trigger mode, and sends the trigger position to the sampling storage module of the oscilloscope.
  • the sampling storage module samples the signal input to the oscilloscope at the trigger position to obtain the sampled signal, stores the sampled signal, and sends the sampled signal to the display module of the oscilloscope.
  • the display module displays the sampled signal.
  • the time resolution of the trigger is the reciprocal of the period of the trigger signal, and when the period of the trigger signal is larger, the time resolution of the trigger is lower.
  • the present application provides a triggering system for an oscilloscope, a triggering method, an oscilloscope and a storage medium, so as to solve the problem of low time resolution of triggering in the triggering system.
  • a trigger system for an oscilloscope comprising: a reference trigger signal generation module and a trigger control module connected to each other;
  • the reference trigger signal generation module is configured to generate N reference trigger signals according to the initial trigger signal, and send the N reference trigger signals to the trigger control module; wherein, N is an integer greater than 1;
  • the trigger control module is configured to sequentially delay the N reference trigger signals to form N target trigger signals, wherein the maximum delay among the respective delays corresponding to the N target trigger signals is smaller than the initial delay.
  • Period T of the trigger signal pre-sampling the to-be-sampled signal input to the oscilloscope based on each target trigger signal to obtain N pieces of pre-sampled data, determine the trigger position according to the N pieces of pre-sampled data, and send all the data to the sampling module. the trigger position, so that the sampling module samples the to-be-sampled signal input to the oscilloscope based on the trigger position to obtain a sampling signal.
  • N reference trigger signals sent by the reference trigger signal generation module; wherein, the N reference trigger signals are signals generated by the reference trigger signal generation module according to the initial trigger signal, and N is an integer greater than 1;
  • the N reference trigger signals are sequentially delayed to form N target trigger signals; wherein, the maximum delay among the respective delays corresponding to the N target trigger signals is smaller than the period T of the initial trigger signal;
  • a trigger position is determined according to the N pieces of pre-sampled data, and the trigger position is sent to the sampling module of the oscilloscope.
  • An oscilloscope comprising: the above trigger system of the oscilloscope and a sampling module connected to the trigger control module in the trigger system.
  • a computer-readable storage medium is also provided, on which a computer program is stored, and when the program is executed by a processor, the above-mentioned triggering method of an oscilloscope is provided.
  • FIG. 1 is a schematic structural diagram of a trigger system of an oscilloscope provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a trigger system of another oscilloscope provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another trigger system of an oscilloscope provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of pre-sampling a to-be-sampled signal to obtain pre-sampled data based on N-way target trigger signals according to an embodiment of the present application;
  • FIG. 5 is another schematic diagram of pre-sampling a to-be-sampled signal to obtain pre-sampled data based on N target trigger signals according to an embodiment of the present application;
  • FIG. 6 is a schematic flowchart of a triggering method for an oscilloscope provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a trigger device of an oscilloscope according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another trigger device of an oscilloscope according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a trigger system of an oscilloscope according to an embodiment of the present application.
  • the trigger system of the oscilloscope provided in this embodiment includes the following modules: a reference trigger signal generation module 11 and a trigger control module 12 that are connected to each other.
  • the oscilloscope includes a sampling module 13 .
  • the reference trigger signal generating module 11 is configured to generate N reference trigger signals according to the initial trigger signal, and send the N reference trigger signals to the trigger control module 12 .
  • N is an integer greater than 1.
  • the trigger control module 12 is set to sequentially delay the N reference trigger signals to form N target trigger signals, the maximum delay of the N target trigger signals is less than the period T of the initial trigger signal, and the input oscilloscope is based on each target trigger signal.
  • the signal to be sampled is pre-sampled to obtain N pre-sampled data, the optimal trigger position is determined according to the N pre-sampled data, and the optimal trigger position is sent to the sampling module 13 of the oscilloscope, so that the sampling module 13 is based on the optimal trigger position. Sampling the signal to be sampled input to the oscilloscope to obtain the sampled signal.
  • the trigger system of the oscilloscope provided in this embodiment can be applied to the oscilloscope.
  • the oscilloscope here can be a digital oscilloscope.
  • the time resolution of the trigger is the reciprocal of the period of the trigger signal, and the time resolution of the trigger is low.
  • the time resolution of triggering can be improved, that is, the precision of triggering can be improved.
  • the functions of the reference trigger signal generation module 11 and the trigger control module 12 are described below.
  • the trigger system provided in this embodiment includes three trigger signals: an initial trigger signal, a reference trigger signal, and a target trigger signal.
  • the initial trigger signal in this embodiment is the same as the trigger signal in the trigger system of the oscilloscope.
  • the period of the initial trigger signal is T.
  • the reference trigger signal generating module 11 may generate N reference trigger signals according to the initial trigger signal, and send the N reference trigger signals to the trigger control module 12 .
  • the N reference trigger signals are all the same signal.
  • the trigger control module 12 receives the N reference trigger signals, and sequentially delays the N reference trigger signals to form N target trigger signals.
  • the maximum time delay of the N target trigger signals is less than the period T of the initial trigger signals.
  • the trigger control module 12 pre-samples the to-be-sampled signal input to the oscilloscope based on each target trigger signal, so as to obtain N pieces of pre-sampled data.
  • the trigger control module 12 determines the optimum trigger position according to the N pre-sampled data, and sends the optimum trigger position to the sampling module 13 .
  • the sampling module 13 samples the to-be-sampled signal based on the optimal trigger position to obtain the sampled signal.
  • the oscilloscope may further include a display module.
  • the sampling module 13 may send sampling signals to the display module.
  • the display module receives the sampling signal sent by the sampling module 13 and displays the sampling signal.
  • the display module may perform necessary processing such as interpolation and compression on the sampled signal, and then display the sampled signal.
  • the trigger control module 12 can pre-sample the to-be-sampled signal input to the oscilloscope based on each target trigger signal to obtain N pieces of pre-sampled data, and since the maximum time delay of the N target trigger signals is smaller than the initial trigger signal Therefore, the trigger system of the oscilloscope provided in this embodiment can collect the to-be-sampled signal N times within the period T of the initial trigger signal to determine the optimal trigger position.
  • the time resolution of the trigger system of the oscilloscope provided in this embodiment is N/T. The temporal resolution is improved by a factor of N.
  • FIG. 2 is a schematic structural diagram of another trigger system of an oscilloscope according to an embodiment of the present application.
  • the reference trigger signal generation module 11 in the trigger system of the oscilloscope provided in this embodiment includes: a comparator module 112 , a trigger level module 111 , and a fan-out module 113 .
  • the first input terminal of the comparator module 112 is connected to the trigger level module 111 , and the second input terminal of the comparator module 112 is connected to the analog link module 15 of the oscilloscope.
  • the output terminal of the comparator module 112 is connected to the input terminal of the fan-out module 113 .
  • the output terminal of the fan-out module 113 is connected to the input terminal of the trigger control module 12 .
  • the comparator module 112 is configured to generate an initial reference trigger signal according to the trigger level input by the trigger level module 111 and the initial trigger signal input by the analog link module 15 , and send the initial reference trigger signal to the fan-out module 113 .
  • the fan-out module 113 is configured to receive the initial reference trigger signal, fan out the initial reference trigger signal into N reference trigger signals, and send the N reference trigger signals to the trigger control module 12 .
  • the analog link module 15 refers to a module composed of circuits such as attenuation circuits and programmable gain amplifiers in the oscilloscope, or the analog link module 15 is a coaxial connector directly inputting an external initial trigger signal, for example, an ultra-small type A (SubMiniature version A, SMA) interface, Bayonet Neill-Concelman (BNC) interface, etc.
  • the analog link module 15 may input an initial trigger signal into the comparator module 112 .
  • the initial trigger signal in this embodiment may be implemented in two ways: the initial trigger signal may be an externally input signal, or the initial trigger signal may be a signal output by the analog front-end circuit of the oscilloscope .
  • the trigger level module 111 in this embodiment may be a digital-to-analog converter (Digital To Analog Converter, DAC).
  • the trigger level module 111 can output a DC level signal as a trigger comparison level value of the comparator module 112 .
  • the comparator module 112 in this embodiment can generate an initial reference trigger signal according to the trigger level and the initial trigger signal.
  • the comparator module 112 can compare the trigger level and the initial trigger signal with hysteresis to generate an initial reference trigger signal.
  • An initial reference trigger signal here refers to a channel of initial reference trigger signal.
  • the first input terminal of the comparator module 112 in this embodiment may be a non-inverting input terminal, and the second input terminal may be an inverting input terminal.
  • the first input terminal of the comparator module 112 may be an inverting input terminal, and the second input terminal may be a non-inverting input terminal. This embodiment does not limit this.
  • the comparator module 112 in this embodiment may be a high-speed differential comparator with a current mode logic (Current Mode Logic, CML) high-speed logic level.
  • the high-speed differential comparator of CML high-speed logic level can output CML high-speed digital logic level.
  • the initial reference trigger signal output by the comparator module 112 in this embodiment is a differential edge signal.
  • the fan-out module 113 in this embodiment may be a differential clock fan-out circuit.
  • the differential clock fan-out circuit is a differential clock fan-out circuit of 1:L (L ⁇ N).
  • the N reference trigger signals in this embodiment refer to N channels of reference trigger signals.
  • L refers to the fan-out number.
  • the value of N depends on the rise time of the edge of the reference trigger signal and the accuracy that the trigger system needs to achieve.
  • the following describes how the trigger control module 12 sequentially delays the N reference trigger signals to form N target trigger signals.
  • the trigger control module 12 only needs to perform different delays on the N reference trigger signals, and the delay mode is not limited. However, it needs to be ensured that the maximum time delay of the N target trigger signals is smaller than the period T of the initial trigger signals. This implementation is more flexible.
  • the trigger control module 12 sequentially delays the N reference trigger signals equal to the first time interval.
  • the delay of the first reference trigger signal is 0 seconds, and the delay of the Nth reference trigger signal is seconds, the first time interval is: second.
  • This implementation manner can facilitate implementation and reduce the cost of the triggering system.
  • the fan-out module 113 fans out one channel of the initial reference trigger signal into 8 channels of reference trigger signals, and sends the 8 channels of reference trigger signals to the trigger control module 12 .
  • the trigger control module 12 performs the following steps on the eight reference trigger signals: 0 second delay, T/8 second delay, 2T/8 second delay, 3T/8 second delay, 4T/8 Second delay, 5T/8 second delay, 6T/8 second delay and 7T/8 second delay.
  • the trigger control module 12 sequentially delays the M reference trigger signals among the N reference trigger signals at equal second time intervals, and performs delays on the remaining N-M reference trigger signals except the M reference trigger signals.
  • the signal is sequentially delayed for a third time interval, and M is less than N.
  • the second time interval is seconds
  • the third time interval is second.
  • the trigger control module 12 in this embodiment may be implemented by a field programmable gate array (Field Programmable Gate Array, FPGA).
  • FPGA Field Programmable Gate Array
  • the trigger control module 12 After the trigger control module 12 in this embodiment sequentially delays the N reference trigger signals to form N target trigger signals, it needs to pre-sample the to-be-sampled signals input to the oscilloscope based on each target trigger signal to obtain N target trigger signals. Presampled data.
  • the trigger control module 12 pre-samples the to-be-sampled signal input to the oscilloscope at the edge position of each target trigger signal.
  • the edge position here can be a rising edge or a falling edge. That is, the trigger control module 12 pre-samples the to-be-sampled signal at the rising edge (or falling edge) of each target trigger signal.
  • the trigger control module 12 may acquire N pieces of pre-sampled data after pre-sampling the signal to be sampled. In this embodiment, the trigger control module 12 determines the optimal trigger position based on the N pieces of pre-sampled data. The more trigger control module 12 determines the optimal trigger position according to the N pre-sampled data and the target trigger mode.
  • the trigger control module 12 determines the edge position of the signal to be sampled input to the oscilloscope according to the N pre-sampled data, and determines the edge position as the best trigger position.
  • the edge trigger here can be a rising edge trigger or a falling edge trigger.
  • the target triggering mode in this embodiment may also be triggering modes such as pulse width triggering, slope triggering, and pattern triggering.
  • FIG. 4 is a schematic diagram of obtaining pre-sampled data by pre-sampling a to-be-sampled signal based on N target trigger signals according to an embodiment of the present application.
  • the trigger control module 12 pre-samples the to-be-sampled signal at the rising edge position of the first target trigger signal, and the obtained pre-sampled data is 0; the trigger control module 12 is at the rising edge of the second target trigger signal.
  • the trigger control module 12 pre-samples the signal to be sampled at the rising edge position of the third target trigger signal, and the obtained pre-sampling data is 1; ... ...; the trigger control module 12 pre-samples the to-be-sampled signal at the rising edge position of the Nth target trigger signal, and the obtained pre-sampled data is 0. Therefore, in this example, the N pre-sampled data are (011...0).
  • the target trigger mode is rising edge triggering, it can be determined that the optimal trigger position is the position between the rising edge position of the first target trigger signal and the rising edge position of the second target trigger signal.
  • the position at which the N pre-sampled data (011...0) changes from a high level to a low level for the first time can be determined, and this position is taken as the best trigger position.
  • FIG. 5 is another schematic diagram of obtaining pre-sampled data by pre-sampling a to-be-sampled signal based on N target trigger signals according to an embodiment of the present application.
  • the trigger control module 12 pre-samples the to-be-sampled signal at the rising edge position of the first target trigger signal, and the obtained pre-sampled data is 0; the trigger control module 12 is at the rising edge of the second target trigger signal.
  • the trigger control module 12 pre-samples the signal to be sampled at the rising edge position of the third target trigger signal, and the obtained pre-sampling data is 1; ... ...; the trigger control module 12 pre-samples the to-be-sampled signal at the rising edge position of the Nth target trigger signal, and the obtained pre-sampled data is 0. Therefore, in this example, the N pre-sampled data are (001...0).
  • the optimal trigger position is the position between the rising edge position of the second target trigger signal and the rising edge position of the third target trigger signal.
  • the position where the N pre-sampled data (001...0) changes from high level to low level for the first time can be determined, and this position is taken as the best trigger position.
  • the period of the initial trigger signal is T, that is to say, sampling is performed every time T elapses, and at the same time, the minimum time unit of sampling of the trigger control module is T. Since the sampling is performed asynchronously, the minimum sampling error that may be generated by the sampling is T, and since the asynchronous sampling of the measured signal may be ahead or behind, the edge of the initial trigger signal is affected by the trigger control module when sampling.
  • the time error is ⁇ T.
  • the actual rising edge of the signal to be sampled occurs at the rising edge position of the first target trigger signal and the rising edge of the second target trigger signal.
  • the position between the positions; in FIG. 5 the actual rising edge of the signal to be sampled occurs at the position between the rising edge position of the second target trigger signal and the rising edge position of the third target trigger signal. Therefore, at this time, the time that the trigger control module 12 can distinguish when sampling is the position between the rising edge positions of the two adjacent target trigger signals. Therefore, the time error of the edge of the initial trigger signal when the trigger control module 12 samples has been reduced to T/N.
  • the equivalent sampling rate is increased from the original 1/T to N/T. Therefore, based on the triggering system, the triggering precision of the oscilloscope, the equivalent sampling rate of the oscilloscope's triggering, and the time resolution of the oscilloscope's triggering can be improved.
  • the trigger jitter When the period of the initial trigger signal is T, the trigger jitter is ⁇ T, so the best trigger accuracy is ⁇ T.
  • the reference trigger signal generated by the initial trigger signal is fan-out to N channels, the corresponding sampling period becomes T/N, then the trigger jitter is ⁇ T/N, so the trigger accuracy becomes ⁇ T /N, which is N times higher than before the improvement.
  • the sampling module 13 in this embodiment samples the signal to be sampled input to the oscilloscope based on the optimal trigger position to obtain the sampled signal, and sends the sampled signal to the display module, the sampled signal can also be stored.
  • FIG. 3 is a schematic structural diagram of yet another trigger system of an oscilloscope according to an embodiment of the present application.
  • the trigger system of the oscilloscope provided in this embodiment includes: a comparator module 312 , a fan-out module 313 , a trigger level module 311 , and a trigger control module 32 .
  • the oscilloscope includes a sampling module 33 .
  • the oscilloscope may further include a display module 34 .
  • the first input terminal of the comparator module 312 is connected to the trigger level module 311 , and the second input terminal of the comparator module 312 is connected to the analog link module 35 .
  • the output terminal of the comparator module 312 is connected to the input terminal of the fan-out module 313 .
  • the output terminal of the fan-out module 313 is connected to the input terminal of the trigger control module 32 .
  • the comparator module 312 is set to generate an initial reference trigger signal according to the trigger level input by the trigger level module 311 and the initial trigger signal input by the analog link module 35, and send the initial reference trigger signal to the fan-out module 313 .
  • ADC Analog to Digital Converter
  • ADC36 Analog to Digital Converter
  • AFE Analog Front End
  • FIG. 3 the oscilloscope has four channels and corresponding four AFEs for illustration.
  • Input ends of ADC36 are respectively connected to one end of AFE1, AFE2, AFE3 and AFE4.
  • the other end of AFE1 is connected to channel (CHannel, CH)1.
  • the other end of AFE2 is connected to CH2.
  • the other end of AFE3 is connected to CH3.
  • the other end of AFE4 is connected to CH4.
  • the trigger control module 32 is set to sequentially delay the 8 reference trigger signals to form 8 target trigger signals, and the maximum delay of the 8 target trigger signals is less than the period T of the initial trigger signal.
  • the to-be-sampled signal of the oscilloscope is pre-sampled to obtain 8 pre-sampled data, the optimal trigger position is determined according to the 8 pre-sampled data, and the optimal trigger position is sent to the sampling module 33 .
  • the sampling module 33 is configured to sample the to-be-sampled signal input to the oscilloscope based on the optimal trigger position to obtain the sampled signal.
  • the sampling module 33 may also send a sampling signal to the display module 34 .
  • the display module 34 receives the sampling signal and displays the sampling signal.
  • the sampling module 33 and the display module 34 in the oscilloscope shown in FIG. 3 may be implemented as digital modules.
  • the trigger control module 32 can also be implemented as a digital module.
  • This embodiment provides a trigger system for an oscilloscope, including: a reference trigger signal generation module and a trigger control module connected to each other; wherein, the reference trigger signal generation module is configured to generate N reference trigger signals according to an initial trigger signal, and send N reference trigger signals to the trigger control module.
  • the module sends N reference trigger signals, where N is an integer greater than 1; the trigger control module is set to sequentially delay the N reference trigger signals to form N target trigger signals, and the maximum delay of the N target trigger signals is less than
  • the trigger system of the oscilloscope can increase the equivalent sampling rate from the original 1/T to N/T, and increase the time resolution of the trigger system to N/T. Therefore, based on the triggering system, the triggering precision of the oscilloscope, the equivalent sampling rate of the oscilloscope's triggering, and the time resolution of the oscilloscope's triggering can be improved.
  • This embodiment also provides an oscilloscope, including the trigger system shown in FIG. 1 to FIG. 3 and various optional implementation manners. The technical principle and technical effect thereof are similar, and are not repeated here.
  • FIG. 6 is a schematic flowchart of a triggering method for an oscilloscope according to an embodiment of the present application. This embodiment is applicable to the scenario of triggering the oscilloscope.
  • the triggering method of the oscilloscope can be performed by a trigger control module, which can be implemented by software and/or hardware, and the trigger control module can be integrated in the oscilloscope.
  • the triggering method of the oscilloscope provided in this embodiment includes the following steps:
  • Step 601 Receive N reference trigger signals sent by the reference trigger signal generation module.
  • the N reference trigger signals are signals generated by the reference trigger signal generation module according to the initial trigger signal, and N is an integer greater than 1.
  • the reference trigger signal generating module is configured to generate N reference trigger signals according to the initial trigger signal, and send the N reference trigger signals to the trigger control module.
  • the trigger control module receives N reference trigger signals sent by the reference trigger signal generation module.
  • Step 602 Delay the N reference trigger signals in sequence to form N target trigger signals.
  • the maximum time delay of the N target trigger signals is less than the period T of the initial trigger signals.
  • the trigger control module can sequentially delay the N reference trigger signals in three ways to form N target trigger signals.
  • the trigger control module only needs to perform different delays on the N reference trigger signals, and the delay mode is not limited. However, it needs to be ensured that the maximum time delay of the N target trigger signals is smaller than the period T of the initial trigger signals. This implementation is more flexible.
  • the trigger control module sequentially delays the N reference trigger signals equal to the first time interval.
  • the delay of the first reference trigger signal is 0 seconds, and the delay of the Nth reference trigger signal is seconds, the first time interval is: second.
  • This implementation manner can facilitate implementation and reduce the cost of the triggering system.
  • the trigger control module performs 0-second delay, T/8-second delay, 2T/8-second delay, and 3T/8-second delay on the eight reference trigger signals respectively. time, 4T/8 second delay, 5T/8 second delay, 6T/8 second delay and 7T/8 second delay.
  • the trigger control module performs sequential delays of M reference trigger signals in the N reference trigger signals equal to the second time interval, and delays the remaining N-M reference trigger signals except the M reference trigger signals. Perform sequential delays waiting for a third time interval, where M is less than N.
  • the second time interval is seconds
  • the third time interval is second.
  • Step 603 Pre-sampling the to-be-sampled signal input to the oscilloscope based on each target trigger signal to acquire N pieces of pre-sampled data.
  • the trigger control module pre-samples the to-be-sampled signal input to the oscilloscope at the edge position of each target trigger signal.
  • the edge position here can be a rising edge or a falling edge.
  • Step 604 Determine the best trigger position according to the N pre-sampled data, and send the best trigger position to the sampling module of the oscilloscope.
  • the trigger control module can acquire N pieces of pre-sampled data.
  • the trigger control module determines the optimal trigger position based on the N pre-sampled data.
  • the trigger control module determines the optimal trigger position according to the N pre-sampled data and the target trigger mode.
  • the trigger control module determines the edge position of the signal to be sampled input to the oscilloscope according to the N pre-sampled data, and determines the edge position as the best trigger position.
  • the edge trigger here can be a rising edge trigger or a falling edge trigger.
  • This embodiment provides a triggering method for an oscilloscope, including: receiving N reference trigger signals sent by a reference trigger signal generation module, wherein the N reference trigger signals are signals generated by the reference trigger signal generation module according to the initial trigger signals, and N is An integer greater than 1; N reference trigger signals are sequentially delayed to form N target trigger signals, and the maximum delay of the N target trigger signals is less than the period T of the initial trigger signal; The signal to be sampled is pre-sampled to obtain N pre-sampled data; the optimal trigger position is determined according to the N pre-sampled data, and the optimal trigger position is sent to the sampling module of the oscilloscope.
  • the trigger method of the oscilloscope can increase the equivalent sampling rate from the original 1/T to N/T, and increase the time resolution of the trigger system to N/T. Therefore, based on the triggering system, the triggering precision of the oscilloscope, the equivalent sampling rate of the oscilloscope's triggering, and the time resolution of the oscilloscope's triggering can be improved.
  • FIG. 7 is a schematic structural diagram of a trigger device of an oscilloscope according to an embodiment of the present application.
  • the triggering device of the oscilloscope provided in this embodiment includes the following modules: a receiving module 71 , a delay module 72 , an obtaining module 73 and a sending module 74 .
  • the receiving module 71 is configured to receive N reference trigger signals sent by the reference trigger signal generating module.
  • the N reference trigger signals are signals generated by the reference trigger signal generation module according to the initial trigger signal, and N is an integer greater than 1.
  • the delay module 72 is configured to sequentially delay the N reference trigger signals to form N target trigger signals.
  • the maximum time delay of the N target trigger signals is less than the period T of the initial trigger signals.
  • the acquisition module 73 is configured to pre-sample the to-be-sampled signal input to the oscilloscope based on each target trigger signal, and acquire N pieces of pre-sampled data.
  • the sending module 74 is configured to determine the optimal trigger position according to the N pieces of pre-sampled data, and send the optimal trigger position to the sampling module of the oscilloscope.
  • the triggering device of the oscilloscope provided by the embodiment of the present application can execute the triggering method of the oscilloscope provided by any embodiment of the present application, and has functional modules and effects corresponding to the execution method.
  • FIG. 8 is a schematic structural diagram of another trigger device of an oscilloscope according to an embodiment of the present application.
  • the trigger device of the oscilloscope includes a processor 80 and a memory 81 .
  • the number of processors 80 in the trigger device of the oscilloscope can be one or more, and one processor 80 is taken as an example in FIG. In 8, the connection through the bus is used as an example.
  • the memory 81 can be configured to store software programs, computer-executable programs, and modules, such as program instructions and modules corresponding to the triggering method of the oscilloscope in the embodiments of the present application (for example, in the triggering device of the oscilloscope).
  • the processor 80 executes various functional applications of the triggering device of the oscilloscope and the triggering method of the oscilloscope by running the software programs, instructions and modules stored in the memory 81 , that is, realizes the triggering method of the oscilloscope.
  • the memory 81 may mainly include a stored program area and a stored data area, wherein the stored program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the trigger device of the oscilloscope, and the like. Additionally, memory 81 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 81 may include memory located remotely from processor 80, which may be connected to the oscilloscope's triggering means via a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the present application also provides a storage medium containing computer-executable instructions, the computer-executable instructions, when executed by a computer processor, are used to execute an oscilloscope triggering method, the method comprising:
  • Receive N reference trigger signals sent by the reference trigger signal generation module wherein, the N reference trigger signals are signals generated by the reference trigger signal generation module according to the initial trigger signal, and N is an integer greater than 1;
  • the reference trigger signals are sequentially delayed to form N target trigger signals; the maximum time delay of the N target trigger signals is less than the period T of the initial trigger signal; based on each target trigger signal, the signal to be sampled input to the oscilloscope is analyzed.
  • Pre-sampling is performed to obtain N pieces of pre-sampling data; an optimum trigger position is determined according to the N pieces of pre-sampling data, and the optimum trigger position is sent to the sampling module of the oscilloscope.
  • a storage medium containing computer-executable instructions provided by an embodiment of the present application the computer-executable instructions of the computer-executable instructions are not limited to the above-mentioned method operations, and can also execute the related functions in the triggering method of an oscilloscope provided by any embodiment of the present application. operate.
  • the present application can be implemented by software and necessary general-purpose hardware, and can also be implemented by hardware.
  • the technical solution of the present application can be embodied in the form of a software product in essence, and the computer software product can be stored in a computer-readable storage medium, such as a floppy disk of a computer, a read-only memory (Read-Only Memory, ROM), a random access A memory (Random Access Memory, RAM), a flash memory (FLASH), a hard disk or an optical disk, etc., includes a plurality of instructions to make the triggering device of an oscilloscope execute the triggering method of the oscilloscope described in the embodiments of the present application.
  • a computer-readable storage medium such as a floppy disk of a computer, a read-only memory (Read-Only Memory, ROM), a random access A memory (Random Access Memory, RAM), a flash memory (FLASH), a hard disk or an optical disk, etc.
  • the multiple units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be realized; in addition, the names of the functional units It is only for the convenience of distinguishing from each other, and is not used to limit the protection scope of the present application.

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Abstract

一种示波器的触发系统、触发方法、示波器以及存储介质。示波器的触发系统包括：相互连接的参考触发信号生成模块(11)以及触发控制模块(12)；其中，参考触发信号生成模块(11)设置为根据初始触发信号生成N个参考触发信号；触发控制模块(12)设置为对N个参考触发信号进行依次延时，形成N个目标触发信号，其中， N个目标触发信号分别对应的时延中的最大时延小于初始触发信号的周期T，基于每个目标触发信号对输入示波器的待采样信号进行预采样以获取N个预采样数据，根据N个预采样数据确定触发位置，并向示波器的采样模块(13)发送触发位置，以使采样模块(13)基于触发位置对输入示波器的待采样信号进行采样以获取采样信号。

Description

示波器的触发系统、触发方法、示波器以及存储介质
本申请要求在2020年11月17日提交中国专利局、申请号为202011286702.2的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及测试测量技术领域，例如涉及一种示波器的触发系统、触发方法、示波器以及存储介质。
背景技术
触发是示波器的核心功能之一，对于波形的稳定显示非常重要。如果没有触发功能，示波器可能在当前采样中采集到待采样信号的任何一个时间位置中的波形，而在下一次采样中，示波器可能又采集到待采样信号的另一个时间位置中的波形，这样在屏幕上看到的波形就是不稳定的。
示波器的触发系统包括相互连接的触发比较器以及触发控制模块，示波器还包括：采样存储模块以及显示模块。触发比较器对触发信号以及触发电平进行比较，生成参考触发信号，向触发控制模块发送参考触发信号。触发控制模块根据参考触发信号以及触发方式，确定触发位置，并向示波器的采样存储模块发送该触发位置。采样存储模块在触发位置处对输入示波器的信号进行采样，得到采样信号，存储该采样信号，并向示波器的显示模块发送采样信号。显示模块显示采样信号。
但是，触发系统中，触发的时间分辨率为触发信号的周期的倒数，在触发信号的周期较大时，触发的时间分辨率较低。
发明内容
本申请提供一种示波器的触发系统、触发方法、示波器以及存储介质，以解决触发系统中触发的时间分辨率较低的问题。
提供一种示波器的触发系统，包括：相互连接的参考触发信号生成模块以及触发控制模块；
其中，所述参考触发信号生成模块设置为根据初始触发信号生成N个参考触发信号，并向所述触发控制模块发送所述N个参考触发信号；其中，N为大于1的整数；
所述触发控制模块设置为对所述N个参考触发信号进行依次延时，形成N 个目标触发信号，其中，所述N个目标触发信号分别对应的时延中的最大时延小于所述初始触发信号的周期T，基于每个目标触发信号对输入示波器的待采样信号进行预采样以获取N个预采样数据，根据所述N个预采样数据确定触发位置，并向所述采样模块发送所述触发位置，以使所述采样模块基于所述触发位置对输入所述示波器的待采样信号进行采样以获取采样信号。
还提供一种示波器的触发方法，包括：
接收参考触发信号生成模块发送的N个参考触发信号；其中，所述N个参考触发信号为所述参考触发信号生成模块根据初始触发信号生成的信号，N为大于1的整数；
对所述N个参考触发信号进行依次延时，形成N个目标触发信号；其中，所述N个目标触发信号分别对应的时延中的最大时延小于所述初始触发信号的周期T；
基于每个目标触发信号对输入示波器的待采样信号进行预采样，获取N个预采样数据；
根据所述N个预采样数据确定触发位置，并向所述示波器的采样模块发送所述触发位置。
还提供了一种示波器，包括：上述的示波器的触发系统以及与所述触发系统中的触发控制模块连接的采样模块。
还提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时上述的示波器的触发方法。
附图说明
图1为本申请实施例提供的一种示波器的触发系统的结构示意图；
图2为本申请实施例提供的另一种示波器的触发系统的结构示意图；
图3为本申请实施例提供的又一种示波器的触发系统的结构示意图；
图4为本申请实施例提供的一种基于N路目标触发信号对待采样信号进行预采样获取预采样数据的示意图；
图5为本申请实施例提供的另一种基于N路目标触发信号对待采样信号进行预采样获取预采样数据的示意图；
图6为本申请实施例提供的一种示波器的触发方法的流程示意图；
图7为本申请实施例提供的一种示波器的触发装置的结构示意图；
图8为本申请实施例提供的另一种示波器的触发装置的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。
图1为本申请实施例提供的一种示波器的触发系统的结构示意图。如图1所示，本实施例提供的示波器的触发系统包括如下模块：相互连接的参考触发信号生成模块11以及触发控制模块12。示波器包括采样模块13。
参考触发信号生成模块11设置为根据初始触发信号生成N个参考触发信号，并向触发控制模块12发送N个参考触发信号。其中，N为大于1的整数。
触发控制模块12设置为对N个参考触发信号进行依次延时，形成N个目标触发信号，N个目标触发信号的最大时延小于初始触发信号的周期T，基于每路目标触发信号对输入示波器的待采样信号进行预采样以获取N个预采样数据，根据N个预采样数据确定最佳触发位置，并向示波器的采样模块13发送最佳触发位置，以使采样模块13基于最佳触发位置对输入示波器的待采样信号进行采样以获取采样信号。
本实施例提供的示波器的触发系统可以应用于示波器中。这里的示波器可以为数字示波器。
由于示波器的触发系统中，触发的时间分辨率为触发信号的周期的倒数，触发的时间分辨率较低。本实施例提供的示波器的触发系统中，通过参考触发信号生成模块11以及触发控制模块12的作用，可以提高触发的时间分辨率，也即，提高触发的精度。下面介绍参考触发信号生成模块11以及触发控制模块12的作用。
本实施例提供的触发系统中，包括三种触发信号：初始触发信号、参考触发信号以及目标触发信号。本实施例中的初始触发信号与示波器的触发系统中的触发信号相同。初始触发信号的周期为T。参考触发信号生成模块11可以根据初始触发信号生成N个参考触发信号，并向触发控制模块12发送这N个参考触发信号。这N个参考触发信号均为相同的信号。之后，触发控制模块12接收这N个参考触发信号，对这N个参考触发信号进行依次延时，形成N个目标触发信号。N个目标触发信号的最大时延小于初始触发信号的周期T。
在形成N个目标触发信号之后，触发控制模块12基于每路目标触发信号对输入示波器的待采样信号进行预采样，可以得到N个预采样数据。触发控制模块12根据这N个预采样数据，确定最佳触发位置，并向采样模块13发送该最佳触发位置。
采样模块13基于最佳触发位置对待采样信号进行采样以获取采样信号。
可选地，示波器还可以包括显示模块。采样模块13可以向显示模块发送采样信号。相对应地，显示模块接收采样模块13发送的采样信号，并显示采样信号。
可选地，显示模块在显示采样信号之前，可以对采样信号进行内插、压缩等必要的处理后，再进行显示。
在上述过程中，触发控制模块12可以基于每路目标触发信号对输入示波器的待采样信号进行预采样，得到N个预采样数据，并且，由于N个目标触发信号的最大时延小于初始触发信号的周期T，因此，本实施例提供的示波器的触发系统可以在初始触发信号的周期T内，对待采样信号采集N次，以确定最佳触发位置。相较于在初始触发信号的周期T内，只能对待采样信号采集一次的触发系统，本实施例提供的示波器的触发系统的时间分辨率为N/T，本实施例提供的示波器的触发系统的时间分辨率提高了N倍。
以下介绍参考触发信号生成模块11的一种可能的组成结构。图2为本申请实施例提供的另一种示波器的触发系统的结构示意图。如图2所示，本实施例提供的示波器的触发系统中的参考触发信号生成模块11包括：比较器模块112、触发电平模块111以及扇出模块113。
比较器模块112的第一输入端与触发电平模块111连接，比较器模块112的第二输入端与示波器的模拟链路模块15连接。比较器模块112的输出端与扇出模块113的输入端连接。扇出模块113的输出端与触发控制模块12的输入端连接。
比较器模块112设置为根据触发电平模块111输入的触发电平，以及，模拟链路模块15输入的初始触发信号，生成初始参考触发信号，并向扇出模块113发送该初始参考触发信号。
扇出模块113设置为接收初始参考触发信号，将初始参考触发信号扇出为N个参考触发信号，并向触发控制模块12发送N个参考触发信号。
模拟链路模块15指的是示波器中的衰减电路和程控增益放大器等电路组成的模块，或者，模拟链路模块15为外部的初始触发信号直接输入的同轴连接器，例如，超小型A型(SubMiniature version A，SMA)接口、尼尔-康塞曼卡口(Bayonet Neill-Concelman，BNC)接口等。模拟链路模块15可以将初始触发信号输入比较器模块112中。基于模拟链路模块15的不同实现方式，本实施例中的初始触发信号可以有两种实现方式：初始触发信号可以是外部输入的信号，或者，初始触发信号可以为示波器模拟前端电路输出的信号。
本实施例中的触发电平模块111可以为数模转换器(Digital To Analog Converter，DAC)。触发电平模块111可以输出直流电平信号，作为比较器模块112的触发比较电平值。
本实施例中的比较器模块112可以根据触发电平以及初始触发信号，生成一个初始参考触发信号。比较器模块112可以将触发电平以及初始触发信号进行迟滞比较，生成一个初始参考触发信号。这里的一个初始参考触发信号指的是一路初始参考触发信号。
可选地，本实施例中的比较器模块112的第一输入端可以为同相输入端，第二输入端可以为反相输入端。或者，比较器模块112的第一输入端可以为反向输入端，第二输入端可以为同相输入端。本实施例对此不作限制。
可选地，本实施例中的比较器模块112可以为电流模式逻辑(Current Mode Logic，CML)高速逻辑电平的高速差分比较器。CML高速逻辑电平的高速差分比较器可以输出CML高速数字逻辑电平。通过设置CML高速逻辑电平的高速差分比较器，可以使得输出的初始参考触发信号的边沿更加陡、上升时间更短，同时，保证了输出的初始参考触发信号的抖动性能，进而，可以进一步提高触发系统的触发精度，同时，降低了触发的抖动和触发延迟。
本实施例中的比较器模块112输出的初始参考触发信号为差分边沿信号。
可选地，本实施例中的扇出模块113可以为差分时钟扇出电路。差分时钟扇出电路为1：L(L≥N)的差分时钟扇出电路，设置为将输入的一路初始参考触发信号，扇出为L个参考触发信号，并向触发控制模块12发送这L个参考触发信号中的N个参考触发信号。本实施例中的N个参考触发信号指的是N路参考触发信号。L指的是扇出数。N的取值取决于参考触发信号的边沿的上升时间以及触发系统需要达到的精度。采用差分时钟扇出电路，可以实现高效地将一路初始参考触发信号扇出为N路参考触发信号，进而降低了触发延迟。
以下介绍触发控制模块12如何对N个参考触发信号进行依次延时，形成N个目标触发信号。
第一种实现方式，触发控制模块12只要对这N个参考触发信号进行不同的延时即可，不限定延时方式。但是，需要保证N个目标触发信号的最大时延小于初始触发信号的周期T。这种实现方式的灵活性较高。
第二种实现方式，为了便于实现，触发控制模块12对N个参考触发信号进行等第一时间间隔的依次延时。
第1个参考触发信号的时延为0秒，第N个参考触发信号的时延为
Figure PCTCN2021074271-appb-000001
秒， 第一时间间隔为：
Figure PCTCN2021074271-appb-000002
秒。
这种实现方式，可以便于实现，可以降低触发系统的成本。
在N为8时，扇出模块113将一路初始参考触发信号扇出为8路参考触发信号，并向触发控制模块12发送这8路参考触发信号。
基于第二种实现方式，触发控制模块12对这8路参考触发信号分别进行：0秒延时、T/8秒延时、2T/8秒延时、3T/8秒延时、4T/8秒延时、5T/8秒延时、6T/8秒延时以及7T/8秒延时。
第三种实现方式，触发控制模块12对N个参考触发信号中的M个参考触发信号进行等第二时间间隔的依次延时，对除M个参考触发信号之外的剩余的N-M个参考触发信号进行等第三时间间隔的依次延时，M小于N。
第二时间间隔为
Figure PCTCN2021074271-appb-000003
秒，第三时间间隔为
Figure PCTCN2021074271-appb-000004
秒。
在这种实现方式中，进行了二次等分，先对M个参考触发信号进行等第二时间间隔的依次延时，再对剩余的N-M个参考触发信号进行等第三时间间隔的依次延时，这种实现方式中，可以结合第一种实现方式和第二种实现方式的优点，便于实现的同时，灵活性也较高。
在第二种实现方式和第三种实现方式中，也需要保证N个目标触发信号的最大时延小于初始触发信号的周期T。
本实施例中的触发控制模块12可以通过现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)实现。
本实施例中的触发控制模块12在对N个参考触发信号进行依次延时，形成N个目标触发信号后，需要基于每路目标触发信号对输入示波器的待采样信号进行预采样以获取N个预采样数据。触发控制模块12在每路目标触发信号的边沿位置，对输入示波器的待采样信号进行预采样。这里的边沿位置可以为上升沿或者下降沿。也即，触发控制模块12在每个目标触发信号的上升沿(或下降沿)，对待采样信号进行预采样。
触发控制模块12在对待采样信号预采样后，可以获取到N个预采样数据。本实施例中，触发控制模块12基于这N个预采样数据，确定最佳触发位置。更触发控制模块12根据N个预采样数据以及目标触发方式，确定最佳触发位置。
可选地，在目标触发方式为边沿触发的场景中，触发控制模块12根据N个预采样数据，确定输入示波器的待采样信号的边沿位置，将边沿位置确定为最佳触发位置。这里的边沿触发可以为上升沿触发或者下降沿触发。
本实施例中的目标触发方式除了可以为边沿触发之外，还可以为脉宽触发、斜率触发、码型触发等触发方式。
以下以两个具体的例子说明触发控制模块12基于N个预采样数据，确定最佳触发位置的过程。
图4为本申请实施例提供的一种基于N路目标触发信号对待采样信号进行预采样获取预采样数据的示意图。如图4所示，触发控制模块12在第1路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为0；触发控制模块12在第2路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为1；触发控制模块12在第3路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为1；……；触发控制模块12在第N路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为0。因此，在该示例中，N个预采样数据为(011……0)。当目标触发方式为上升沿触发时，可以确定出最佳触发位置为第1路目标触发信号的上升沿位置与第2路目标触发信号的上升沿位置之间的位置。
当目标触发方式为下降沿触发时，可以确定出N个预采样数据(011……0)中第一次由高电平变为低电平的位置，将该位置作为最佳触发位置。
图5为本申请实施例提供的另一种基于N路目标触发信号对待采样信号进行预采样获取预采样数据的示意图。如图5所示，触发控制模块12在第1路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为0；触发控制模块12在第2路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为0；触发控制模块12在第3路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为1；……；触发控制模块12在第N路目标触发信号的上升沿位置，对待采样信号进行预采样，得到的预采样数据为0。因此，在该示例中，N个预采样数据为(001……0)。当目标触发方式为上升沿触发时，可以确定出最佳触发位置为第2路目标触发信号的上升沿位置与第3路目标触发信号的上升沿位置之间的位置。
当目标触发方式为下降沿触发时，可以确定出N个预采样数据(001……0)中第一次由高电平变为低电平的位置，将该位置作为最佳触发位置。
在背景技术中的触发系统中，初始触发信号的周期为T，也就是说每经过T时间进行一次采样，同时，也就是说触发控制模块的采样最小时间单位是T。由于采样是异步进行的，因此采样可能产生的最小的采样误差为T，又由于异步采样被测信号可能是超前的，也可能是落后的，因此触发控制模块采样时对初始触发信号的边沿的时间误差为±T。
从图4和图5所示的例子中可以看出：在图4中，待采样信号的实际的上升沿发生在第1路目标触发信号的上升沿位置与第2路目标触发信号的上升沿位置之间的位置；在图5中，待采样信号的实际的上升沿发生在第2路目标触发信号的上升沿位置与第3路目标触发信号的上升沿位置之间的位置。因此，此时触发控制模块12采样时可以分辨的时间为相邻两路目标触发信号的上升沿位置之间的位置。所以，触发控制模块12采样时对初始触发信号的边沿的时间误差已经减小为T/N了。等效采样率由原来的1/T，提高到了N/T。因此，基于该触发系统，可以提高示波器的触发精度、提高示波器的触发的等效采样率和提高示波器的触发的时间分辨率。
当初始触发信号的周期为T时，触发抖动就是±T，所以触发精度最高最好也就是±T。当把由初始触发信号生成的参考触发信号扇出为N路后，相对应的采样周期就变成了T/N，那么触发抖动就是±T/N，所以触发精度也就变成了±T/N了，相比改进之前提升了N倍。
本实施例中的采样模块13基于最佳触发位置对输入示波器的待采样信号进行采样以获取采样信号后，并向显示模块发送采样信号之后，还可以存储该采样信号。
以下再以一个具体的例子说明本实施例提供的示波器的触发系统的结构。图3为本申请实施例提供的又一种示波器的触发系统的结构示意图。如图3所示，本实施例提供的示波器的触发系统包括：比较器模块312、扇出模块313、触发电平模块311以及触发控制模块32。
示波器包括采样模块33。可选地，示波器还可以包括显示模块34。
比较器模块312的第一输入端与触发电平模块311连接，比较器模块312的第二输入端与模拟链路模块35连接。比较器模块312的输出端与扇出模块313的输入端连接。扇出模块313的输出端与触发控制模块32的输入端连接。
比较器模块312设置为根据触发电平模块311输入的触发电平，以及，模拟链路模块35输入的初始触发信号，生成一个初始参考触发信号，并向扇出模块313发送该初始参考触发信号。
扇出模块313设置为接收初始参考触发信号，将初始参考触发信号扇出为N个参考触发信号。示例性地，图3中N＝8。也即，扇出模块313将初始参考触发信号扇出为8个参考触发信号，并向触发控制模块32发送这8个参考触发信号。
图3中的采样模块33的一端连接模拟数字转换器(Analog to Digital Converter，ADC)36的输出端。ADC36的输入端连接示波器的模拟前端(Analog  Front End，AFE)。图3中以该示波器具有四个通道以及对应的四个AFE进行举例说明。ADC36的输入端分别连接AFE1、AFE2、AFE3以及AFE4的一端。AFE1的另一端连接通道(CHannel，CH)1。AFE2的另一端连接CH2。AFE3的另一端连接CH3。AFE4的另一端连接CH4。
触发控制模块32设置为对8个参考触发信号进行依次延时，形成8个目标触发信号，该8个目标触发信号的最大时延小于初始触发信号的周期T，基于每路目标触发信号对输入示波器的待采样信号进行预采样以获取8个预采样数据，根据8个预采样数据确定最佳触发位置，并向采样模块33发送最佳触发位置。
采样模块33设置为基于最佳触发位置对输入示波器的待采样信号进行采样以获取采样信号。可选地，采样模块33还可以向显示模块34发送采样信号。相对应地，显示模块34接收采样信号，并显示采样信号。
图3所示的示波器中的采样模块33以及显示模块34可以均为数字模块实现。触发控制模块32也可以为数字模块实现。
本实施例提供一种示波器的触发系统，包括：相互连接的参考触发信号生成模块以及触发控制模块；其中，参考触发信号生成模块设置为根据初始触发信号生成N个参考触发信号，并向触发控制模块发送N个参考触发信号，其中，N为大于1的整数；触发控制模块设置为对N个参考触发信号进行依次延时，形成N个目标触发信号，N个目标触发信号的最大时延小于初始触发信号的周期T，基于每路目标触发信号对输入示波器的待采样信号进行预采样以获取N个预采样数据，根据N个预采样数据确定最佳触发位置，并向示波器的采样模块发送最佳触发位置，以使采样模块基于最佳触发位置对输入示波器的待采样信号进行采样以获取采样信号。该示波器的触发系统，可以使得等效采样率由原来的1/T，提高到N/T，将触发系统的时间分辨率提高至N/T。因此，基于该触发系统，可以提高示波器的触发精度、提高示波器的触发的等效采样率和提高示波器的触发的时间分辨率。
本实施例还提供一种示波器，包括如图1至图3及多种可选的实现方式所示的触发系统。其技术原理和技术效果类似，此处不再赘述。
图6为本申请实施例提供的一种示波器的触发方法的流程示意图。本实施例适用于对示波器进行触发的场景中。该示波器的触发方法可以由触发控制模块来执行，该触发控制模块可以由软件和/或硬件的方式实现，该触发控制模块可以集成于示波器中。如图6所示，本实施例提供的示波器的触发方法包括如下步骤：
步骤601：接收参考触发信号生成模块发送的N个参考触发信号。
N个参考触发信号为参考触发信号生成模块根据初始触发信号生成的信号，N为大于1的整数。
参考触发信号生成模块设置为根据初始触发信号生成N个参考触发信号，并向触发控制模块发送N个参考触发信号。触发控制模块接收参考触发信号生成模块发送的N个参考触发信号。
步骤602：对N个参考触发信号进行依次延时，形成N个目标触发信号。
N个目标触发信号的最大时延小于初始触发信号的周期T。
触发控制模块可以按照三种方式，对N个参考触发信号进行依次延时，形成N个目标触发信号。
第一种实现方式，触发控制模块只要对这N个参考触发信号进行不同的延时即可，不限定延时方式。但是，需要保证N个目标触发信号的最大时延小于初始触发信号的周期T。这种实现方式的灵活性较高。
第二种实现方式，为了便于实现，触发控制模块对N个参考触发信号进行等第一时间间隔的依次延时。
第1个参考触发信号的时延为0秒，第N个参考触发信号的时延为
Figure PCTCN2021074271-appb-000005
秒，第一时间间隔为：
Figure PCTCN2021074271-appb-000006
秒。
这种实现方式，可以便于实现，可以降低触发系统的成本。
在N为8时，基于第二种实现方式，触发控制模块对这8路参考触发信号分别进行：0秒延时、T/8秒延时、2T/8秒延时、3T/8秒延时、4T/8秒延时、5T/8秒延时、6T/8秒延时以及7T/8秒延时。
第三种实现方式，触发控制模块对N个参考触发信号中的M个参考触发信号进行等第二时间间隔的依次延时，对除M个参考触发信号之外的剩余的N-M个参考触发信号进行等第三时间间隔的依次延时，M小于N。
第二时间间隔为
Figure PCTCN2021074271-appb-000007
秒，第三时间间隔为
Figure PCTCN2021074271-appb-000008
秒。
在这种实现方式中，进行了二次等分，先对M个参考触发信号进行等第二时间间隔的依次延时，再对剩余的N-M个参考触发信号进行等第三时间间隔的依次延时，这种实现方式中，可以结合第一种实现方式和第二种实现方式的优点，便于实现的同时，灵活性也较高。
在第二种实现方式和第三种实现方式中，也需要保证N个目标触发信号的 最大时延小于初始触发信号的周期T。
步骤603：基于每路目标触发信号对输入示波器的待采样信号进行预采样，获取N个预采样数据。
可选地，触发控制模块在每路目标触发信号的边沿位置，对输入示波器的待采样信号进行预采样。这里的边沿位置可以为上升沿或者下降沿。
步骤604：根据N个预采样数据确定最佳触发位置，并向示波器的采样模块发送最佳触发位置。
触发控制模块在对待采样信号预采样后，可以获取到N个预采样数据。本实施例中，触发控制模块基于这N个预采样数据，确定最佳触发位置。触发控制模块根据N个预采样数据以及目标触发方式，确定最佳触发位置。
可选地，在目标触发方式为边沿触发的场景中，触发控制模块根据N个预采样数据，确定输入示波器的待采样信号的边沿位置，将边沿位置确定为最佳触发位置。这里的边沿触发可以为上升沿触发或者下降沿触发。
本实施例提供一种示波器的触发方法，包括：接收参考触发信号生成模块发送的N个参考触发信号，其中，N个参考触发信号为参考触发信号生成模块根据初始触发信号生成的信号，N为大于1的整数；对N个参考触发信号进行依次延时，形成N个目标触发信号，N个目标触发信号的最大时延小于初始触发信号的周期T；基于每路目标触发信号对输入示波器的待采样信号进行预采样，获取N个预采样数据；根据N个预采样数据确定最佳触发位置，并向示波器的采样模块发送最佳触发位置。该示波器的触发方法，可以使得等效采样率由原来的1/T，提高到N/T，将触发系统的时间分辨率提高至N/T。因此，基于该触发系统，可以提高示波器的触发精度、提高示波器的触发的等效采样率和提高示波器的触发的时间分辨率。
图7为本申请实施例提供的一种示波器的触发装置的结构示意图。如图7所示，本实施例提供的示波器的触发装置包括如下模块：接收模块71、延时模块72、获取模块73以及发送模块74。
接收模块71，设置为接收参考触发信号生成模块发送的N个参考触发信号。
N个参考触发信号为参考触发信号生成模块根据初始触发信号生成的信号，N为大于1的整数。
延时模块72，设置为对N个参考触发信号进行依次延时，形成N个目标触发信号。
N个目标触发信号的最大时延小于初始触发信号的周期T。
获取模块73，设置为基于每路目标触发信号对输入示波器的待采样信号进行预采样，获取N个预采样数据。
发送模块74，设置为根据N个预采样数据确定最佳触发位置，并向示波器的采样模块发送最佳触发位置。
本申请实施例所提供的示波器的触发装置可执行本申请任意实施例所提供的示波器的触发方法，具备执行方法相应的功能模块和效果。
图8为本申请实施例提供的另一种示波器的触发装置的结构示意图。如图8所示，该示波器的触发装置包括处理器80和存储器81。该示波器的触发装置中处理器80的数量可以是一个或多个，图8中以一个处理器80为例；该示波器的触发装置的处理器80和存储器81可以通过总线或其他方式连接，图8中以通过总线连接为例。
存储器81作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请实施例中的示波器的触发方法对应的程序指令以及模块(例如，示波器的触发装置中的接收模块71、延时模块72、获取模块73以及发送模块74)。处理器80通过运行存储在存储器81中的软件程序、指令以及模块，从而执行示波器的触发装置的各种功能应用以及示波器的触发方法，即实现上述的示波器的触发方法。
存储器81可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据示波器的触发装置的使用所创建的数据等。此外，存储器81可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实施例中，存储器81可包括相对于处理器80远程设置的存储器，这些远程存储器可以通过网络连接至示波器的触发装置。上述网络的实施例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
本申请还提供一种包含计算机可执行指令的存储介质，所述计算机可执行指令在由计算机处理器执行时用于执行一种示波器的触发方法，该方法包括：
接收参考触发信号生成模块发送的N个参考触发信号；其中，所述N个参考触发信号为所述参考触发信号生成模块根据初始触发信号生成的信号，N为大于1的整数；对所述N个参考触发信号进行依次延时，形成N个目标触发信号；所述N个目标触发信号的最大时延小于所述初始触发信号的周期T；基于每路目标触发信号对输入示波器的待采样信号进行预采样，获取N个预采样数据；根据所述N个预采样数据确定最佳触发位置，并向示波器的采样模块发送 所述最佳触发位置。
本申请实施例所提供的一种包含计算机可执行指令的存储介质，其计算机可执行指令不限于如上所述的方法操作，还可以执行本申请任意实施例所提供的示波器的触发方法中的相关操作。
通过以上关于实施方式的描述，本申请可借助软件及必需的通用硬件来实现，也可以通过硬件实现。本申请的技术方案本质上可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如计算机的软盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、闪存(FLASH)、硬盘或光盘等，包括多个指令用以使得一台示波器的触发装置执行本申请实施例所述的示波器的触发方法。
上述示波器的触发装置的实施例中，所包括的多个单元和模块只是按照功能逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，功能单元的名称也只是为了便于相互区分，并不用于限制本申请的保护范围。

Claims (14)

  1. 一种示波器的触发系统，包括：相互连接的参考触发信号生成模块以及触发控制模块；
    其中，所述参考触发信号生成模块设置为根据初始触发信号生成N个参考触发信号，并向所述触发控制模块发送所述N个参考触发信号；其中，N为大于1的整数；
    所述触发控制模块设置为对所述N个参考触发信号进行依次延时，形成N个目标触发信号，其中，所述N个目标触发信号分别对应的时延中的最大时延小于所述初始触发信号的周期T，基于每个目标触发信号对输入示波器的待采样信号进行预采样以获取N个预采样数据，根据所述N个预采样数据确定触发位置，并向所述示波器的采样模块发送所述触发位置，以使所述采样模块基于所述触发位置对输入所述示波器的待采样信号进行采样以获取采样信号。
  2. 根据权利要求1所述的触发系统，其中，所述参考触发信号生成模块包括：比较器模块、触发电平模块以及扇出模块；
    其中，所述比较器模块的第一输入端与所述触发电平模块连接，所述比较器模块的第二输入端与所述示波器的模拟链路模块连接，所述比较器模块的输出端与所述扇出模块的输入端连接，所述扇出模块的输出端与所述触发控制模块的输入端连接；
    所述比较器模块设置为根据所述触发电平模块输入的触发电平，以及，所述模拟链路模块输入的所述初始触发信号，生成初始参考触发信号，并向所述扇出模块发送所述初始参考触发信号；
    所述扇出模块设置为接收所述初始参考触发信号，将所述初始参考触发信号扇出为所述N个参考触发信号，并向所述触发控制模块发送所述N个参考触发信号。
  3. 根据权利要求2所述的触发系统，其中，所述比较器模块为电流模式逻辑CML高速逻辑电平的高速差分比较器。
  4. 根据权利要求2所述的触发系统，其中，所述扇出模块为差分时钟扇出电路。
  5. 根据权利要求1至4任一项所述的触发系统，其中，所述触发控制模块是设置为通过如下方式对所述N个参考触发信号进行依次延时：对所述N个参考触发信号进行等第一时间间隔的依次延时。
  6. 根据权利要求5所述的触发系统，其中，第1个参考触发信号的时延为0秒，第N个参考触发信号的时延为
    Figure PCTCN2021074271-appb-100001
    秒，所述第一时间间隔为：
    Figure PCTCN2021074271-appb-100002
    秒。
  7. 根据权利要求1至4任一项所述的触发系统，其中，所述触发控制模块是设置为通过如下方式对所述N个参考触发信号进行依次延时：对所述N个参考触发信号中的M个参考触发信号进行等第二时间间隔的依次延时，对除所述M个参考触发信号之外的N-M个参考触发信号进行等第三时间间隔的依次延时，其中，M小于N。
  8. 根据权利要求7所述的触发系统，其中，所述第二时间间隔为
    Figure PCTCN2021074271-appb-100003
    秒，所述第三时间间隔为
    Figure PCTCN2021074271-appb-100004
    秒。
  9. 根据权利要求1至4任一项所述的触发系统，其中，所述触发控制模块是设置为通过如下方式基于每个目标触发信号对输入示波器的待采样信号进行预采样：在每个目标触发信号的边沿位置，对输入所述示波器的待采样信号进行预采样。
  10. 根据权利要求1至4任一项所述的触发系统，其中，所述触发控制模块是设置为通过如下方式根据所述N个预采样数据确定触发位置：根据所述N个预采样数据以及目标触发方式，确定所述触发位置。
  11. 根据权利要求10所述的触发系统，其中，所述目标触发方式为边沿触发；
    所述触发控制模块是设置为通过如下方式根据所述N个预采样数据以及目标触发方式，确定所述触发位置：根据所述N个预采样数据，确定输入所述示波器的待采样信号的边沿位置，将所述边沿位置确定为所述触发位置。
  12. 一种示波器的触发方法，包括：
    接收参考触发信号生成模块发送的N个参考触发信号；其中，所述N个参考触发信号为所述参考触发信号生成模块根据初始触发信号生成的信号，N为大于1的整数；
    对所述N个参考触发信号进行依次延时，形成N个目标触发信号；其中，所述N个目标触发信号分别对应的时延中的最大时延小于所述初始触发信号的周期T；
    基于每个目标触发信号对输入示波器的待采样信号进行预采样，获取N个预采样数据；
    根据所述N个预采样数据确定触发位置，并向所述示波器的采样模块发送所述触发位置。
  13. 一种示波器，包括如权利要求1至11任一项所述的触发系统以及与所 述触发系统中的触发控制模块连接的采样模块。
  14. 一种计算机可读存储介质，存储有计算机程序，其中，所述程序被处理器执行时实现如权利要求12所述的示波器的触发方法。
PCT/CN2021/074271 2020-11-17 2021-01-29 示波器的触发系统、触发方法、示波器以及存储介质 WO2022105059A1 (zh)

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