WO2022095159A1 - Goa 电路及其驱动方法、显示面板 - Google Patents

Goa 电路及其驱动方法、显示面板 Download PDF

Info

Publication number
WO2022095159A1
WO2022095159A1 PCT/CN2020/131755 CN2020131755W WO2022095159A1 WO 2022095159 A1 WO2022095159 A1 WO 2022095159A1 CN 2020131755 W CN2020131755 W CN 2020131755W WO 2022095159 A1 WO2022095159 A1 WO 2022095159A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
signal
gate
node
Prior art date
Application number
PCT/CN2020/131755
Other languages
English (en)
French (fr)
Inventor
吕京
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/280,909 priority Critical patent/US11798511B2/en
Publication of WO2022095159A1 publication Critical patent/WO2022095159A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit, a driving method thereof, and a display panel.
  • GOA Gate Driver On Array
  • array the existing thin film transistor liquid crystal display array (array) process to fabricate the Gate (gate) line scanning drive signal circuit on the array substrate to realize the gate progressive scanning. item technology.
  • the GOA circuit contains multiple transistors. If a transistor is turned on for a long time, its threshold voltage will easily shift, which will cause the transistor to fail to work normally, resulting in the failure of the GOA circuit output and abnormal display.
  • a transistor is turned on for a long time, its threshold voltage will easily shift, which will cause the transistor to fail to work normally, resulting in the failure of the GOA circuit output and abnormal display.
  • the gate of the transistor T6 is connected to a high-potential signal, and the transistor T6 is in an on state for a long time, and its threshold voltage will shift; especially in The threshold voltage will be shifted and accelerated under high temperature working conditions such as on-board displays, resulting in abnormal thin film transistor (TFT) characteristics of transistor T6, resulting in failure of the GOA circuit output and abnormal display.
  • TFT thin film transistor
  • the GOA circuit, its driving method, and the display panel provided by the present invention can solve the problem that the existing GOA circuit includes a plurality of transistors. If a transistor is in an on state for a long time, its threshold voltage is easily shifted, so that the transistor cannot work normally. The technical problem of abnormal display caused by GOA circuit output failure.
  • An embodiment of the present invention provides a GOA circuit, including M cascaded GOA units, wherein the Nth-level GOA unit includes:
  • the forward and reverse scanning control module is used to control the GOA circuit to perform forward scanning or reverse scanning according to the forward scanning control signal or the reverse scanning control signal;
  • the node signal control module is connected to the forward and reverse scanning control module, and is used for controlling the gate driving of the GOA circuit to output a low potential in the non-working phase according to the N+2 stage clock signal and the N-2 stage clock signal Signal;
  • a voltage regulator module connected to the forward and reverse scanning control module through a first node, for maintaining the potential of the first node under the control of the forward and reverse scanning control module;
  • the output control module is connected to the voltage regulator module through the second node, and is used for controlling the output of the gate driving signal of the current stage according to the clock signal of the current stage;
  • a first pull-down module connected to the node signal control module through a third node, for pulling down the potential of the gate driving signal of the current stage under the control of the node signal control module;
  • the second pull-down module is connected to the output control module and the voltage regulator module through the second node, and is used to pull down the potential of the second node. Under the control of the node signal control module, when the When the second pull-down module is in a working state, the forward and reverse scanning control module controls the voltage regulator module to be in an off state.
  • the forward and reverse scanning control module includes a first transistor and a second transistor, the first electrode of the first transistor is connected to the forward scanning control signal, and the first The gate of the transistor is connected to the gate driving signal of the N-2th stage; the first electrode of the second transistor is connected to the reverse scanning control signal, and the gate of the second transistor is connected to the gate of the N+2th stage The second electrode of the second transistor is connected to the second electrode of the first transistor.
  • the node control module includes a third transistor, a fourth transistor, and a fifth transistor
  • the first electrode of the third transistor is connected to the N+2 th clock signal
  • the The gates of the three transistors are connected to the first electrodes of the first transistors
  • the first electrodes of the fourth transistors are connected to the N-2 th clock signal
  • the gates of the fourth transistors are connected to the second transistors
  • the first electrode of the fifth transistor is connected to a high-potential signal
  • the second electrode of the fifth transistor is connected to the first pull-down module through the third node
  • the fifth The gate of the transistor is connected to the second electrode of the third transistor and the second electrode of the fourth transistor.
  • the voltage regulator module includes a sixth transistor and a first storage capacitor, and the gate of the sixth transistor passes through the first node and the second electrode of the first transistor and The first electrode plate of the first storage capacitor is connected to the high potential signal, the gate of the sixth transistor is connected to the high potential signal, and the second electrode plate of the first storage capacitor is connected to the low potential signal.
  • the output control module includes a seventh transistor, a first electrode of the seventh transistor is connected to the clock signal of the current stage, and a second electrode of the seventh transistor is connected to the clock signal of the current stage.
  • the gate driving signal of the current stage is connected, and the gate of the seventh transistor is connected to the second electrode of the sixth transistor through the second node.
  • the first pull-down module includes an eighth transistor, a ninth transistor, a tenth transistor, and a second storage capacitor, and a first electrode of the eighth transistor is connected to the low-potential signal , the gate of the eighth transistor is connected to the second electrode of the second transistor; the first electrode of the ninth transistor is connected to the low-potential signal, and the second electrode of the ninth transistor passes through the A node is connected to the gate of the seventh transistor and the first plate of the first storage capacitor; the first electrode of the tenth transistor is connected to the low-potential signal, and the first electrode of the tenth transistor is connected to the low-potential signal.
  • the low potential signal is connected, the gate of the tenth transistor is connected to the second electrode of the fifth transistor through the third node, and the second electrode of the tenth transistor is connected to the gate of the current stage a driving signal; the second plate of the second storage capacitor is connected to the low-potential signal.
  • the second pull-down module includes an eleventh transistor, and the gate of the eleventh transistor passes through the third node and the second electrode of the fifth transistor, the The gate of the ninth transistor is connected to the first plate of the second storage capacitor, the first electrode of the eleventh transistor is connected to the low-potential signal, and the second electrode of the eleventh transistor passes through the The second node is connected to the second electrode of the sixth transistor and the gate of the seventh transistor.
  • the GOA circuit further includes a reset module, the reset module includes a twelfth transistor, and the gate of the twelfth transistor is connected to the first electrode of the twelfth transistor And both are connected to a reset signal, and the second electrode of the twelfth transistor is connected to the gate of the tenth transistor through the third node.
  • the reset module includes a twelfth transistor, and the gate of the twelfth transistor is connected to the first electrode of the twelfth transistor And both are connected to a reset signal, and the second electrode of the twelfth transistor is connected to the gate of the tenth transistor through the third node.
  • the plurality of transistors in the GOA circuit are low temperature polysilicon thin film transistors.
  • An embodiment of the present invention provides a display panel, including the above-mentioned GOA circuit, where the GOA circuit includes M cascaded GOA units, wherein the Nth-level GOA unit includes:
  • the forward and reverse scanning control module is used to control the GOA circuit to perform forward scanning or reverse scanning according to the forward scanning control signal or the reverse scanning control signal;
  • the node signal control module is connected to the forward and reverse scanning control module, and is used for controlling the gate driving of the GOA circuit to output a low potential in the non-working phase according to the N+2 stage clock signal and the N-2 stage clock signal Signal;
  • a voltage regulator module connected to the forward and reverse scanning control module through a first node, for maintaining the potential of the first node under the control of the forward and reverse scanning control module;
  • the output control module is connected to the voltage regulator module through the second node, and is used for controlling the output of the gate driving signal of the current stage according to the clock signal of the current stage;
  • a first pull-down module connected to the node signal control module through a third node, for pulling down the potential of the gate driving signal of the current stage under the control of the node signal control module;
  • the second pull-down module is connected to the output control module and the voltage regulator module through the second node, and is used to pull down the potential of the second node. Under the control of the node signal control module, when the When the second pull-down module is in a working state, the forward and reverse scanning control module controls the voltage regulator module to be in an off state.
  • the forward and reverse scanning control module includes a first transistor and a second transistor, the first electrode of the first transistor is connected to the forward scanning control signal, and the first The gate of the transistor is connected to the gate driving signal of the N-2th stage; the first electrode of the second transistor is connected to the reverse scanning control signal, and the gate of the second transistor is connected to the gate of the N+2th stage The second electrode of the second transistor is connected to the second electrode of the first transistor.
  • the node control module includes a third transistor, a fourth transistor, and a fifth transistor
  • the first electrode of the third transistor is connected to the N+2 th clock signal
  • the The gates of the three transistors are connected to the first electrodes of the first transistors
  • the first electrodes of the fourth transistors are connected to the N-2 th clock signal
  • the gates of the fourth transistors are connected to the second transistors
  • the first electrode of the fifth transistor is connected to a high-potential signal
  • the second electrode of the fifth transistor is connected to the first pull-down module through the third node
  • the fifth The gate of the transistor is connected to the second electrode of the third transistor and the second electrode of the fourth transistor.
  • the voltage stabilization module includes a sixth transistor and a first storage capacitor, and the gate of the sixth transistor passes through the first node and the second electrode of the first transistor and The first electrode plate of the first storage capacitor is connected to the high potential signal, the gate of the sixth transistor is connected to the high potential signal, and the second electrode plate of the first storage capacitor is connected to the low potential signal.
  • the output control module includes a seventh transistor, the first electrode of the seventh transistor is connected to the clock signal of the current stage, and the second electrode of the seventh transistor is connected to the The gate driving signal of the current stage is connected, and the gate of the seventh transistor is connected to the second electrode of the sixth transistor through the second node.
  • the first pull-down module includes an eighth transistor, a ninth transistor, a tenth transistor, and a second storage capacitor, and a first electrode of the eighth transistor is connected to the low-potential signal , the gate of the eighth transistor is connected to the second electrode of the second transistor; the first electrode of the ninth transistor is connected to the low-potential signal, and the second electrode of the ninth transistor passes through the A node is connected to the gate of the seventh transistor and the first plate of the first storage capacitor; the first electrode of the tenth transistor is connected to the low-potential signal, and the first electrode of the tenth transistor is connected to the low-potential signal.
  • the low potential signal is connected, the gate of the tenth transistor is connected to the second electrode of the fifth transistor through the third node, and the second electrode of the tenth transistor is connected to the gate of the current stage a driving signal; the second plate of the second storage capacitor is connected to the low-potential signal.
  • the second pull-down module includes an eleventh transistor, and the gate of the eleventh transistor passes through the third node and the second electrode of the fifth transistor, the The gate of the ninth transistor is connected to the first plate of the second storage capacitor, the first electrode of the eleventh transistor is connected to the low-potential signal, and the second electrode of the eleventh transistor passes through the The second node is connected to the second electrode of the sixth transistor and the gate of the seventh transistor.
  • the GOA circuit further includes a reset module, the reset module includes a twelfth transistor, and the gate of the twelfth transistor is connected to the first electrode of the twelfth transistor And both are connected to a reset signal, and the second electrode of the twelfth transistor is connected to the gate of the tenth transistor through the third node.
  • the reset module includes a twelfth transistor, and the gate of the twelfth transistor is connected to the first electrode of the twelfth transistor And both are connected to a reset signal, and the second electrode of the twelfth transistor is connected to the gate of the tenth transistor through the third node.
  • the plurality of transistors in the GOA circuit are low temperature polysilicon thin film transistors.
  • An embodiment of the present invention provides a GOA circuit driving method, comprising the following steps:
  • the forward scanning control signal connected to the forward and reverse scanning control module in the GOA circuit makes the voltage regulator module and the output control module work, and the node signal control module keeps the first pull-down module and the second pull-down module in off state, the output control module writes the gate drive signal of the current stage;
  • the clock signal of the current stage causes the output control module to generate a bootstrap effect
  • the output control module writes the gate drive signal of the current stage
  • the gate drive signal of the current stage drives the pixel drive circuit.
  • the drive transistor works;
  • the output control module writes the gate drive signal of the current stage
  • the first pull-down module and the second pull-down module are in the working state, and the potential of the gate driving signal of the current stage is pulled down, and the forward and reverse scanning control module controls the voltage regulator module to be in In the off state, the output control module is in the off state, and a low-level signal is written to the output terminal of the output control module.
  • the GOA circuit driving method provided according to the embodiment of the present invention further includes a reset stage, wherein the reset stage is before the input stage, the first pull-down module and the second pull-down module are in a working state, and the output control The output terminal of the module writes the low-level signal.
  • the beneficial effects of the present invention are as follows: in the GOA circuit, the driving method thereof, and the display panel provided by the present invention, by adding a second pull-down module, the second pull-down module is connected to the output control module and the voltage-stabilizing module through the second node, and is used to pull down the first pull-down module.
  • the potential of the two nodes under the control of the node signal control module, when the second pull-down module is in the working state, the forward and reverse scanning control module controls the voltage regulator module to be in an off state, thereby preventing the voltage regulator module from being turned on for a long time. state, so that there is no transistor in the GOA circuit that is in the open state for a long time, thereby suppressing the threshold voltage shift of the transistor and improving the reliability of the GOA circuit.
  • FIG. 1 is a schematic diagram of the circuit structure of a GOA circuit in the prior art
  • FIG. 2 is a schematic diagram of a circuit structure of a GOA circuit provided by an embodiment of the present invention.
  • FIG. 3 is a working sequence diagram of a GOA circuit according to an embodiment of the present invention.
  • the present invention is aimed at the GOA circuit, liquid crystal display panel and display device of the prior art, so as to solve the problem that the existing GOA circuit includes a plurality of transistors. If a transistor is in an on state for a long time, its threshold voltage is easily shifted, so that the transistor cannot be It works normally, causing the output of the GOA circuit to fail and cause abnormal display. This embodiment can solve the defect.
  • the GOA circuit provided by the embodiment of the present invention includes M cascaded GOA units, wherein the N-th GOA unit includes: a forward and reverse scan control module 100, a node signal control module 200, a voltage stabilization module 300, The output control module 400 , the first pull-down module 500 and the second pull-down module 600 are output.
  • the forward and reverse scan control module 100 is configured to control the GOA circuit to perform forward scan or reverse scan according to the forward scan control signal U2D or the reverse scan control signal D2U.
  • the node signal control module 200 is connected to the forward and reverse scanning control module 100, and is used for according to the N+2 stage clock signal CK(N+2) and the N-2 stage clock signal CK(N-2)
  • the GOA circuit is controlled to output a gate driving signal with a low potential in a non-working phase.
  • the voltage stabilization module 300 is connected to the forward and reverse scanning control module 100 through the first node Q1 , and is used for maintaining the potential of the first node Q1 under the control of the forward and reverse scanning control module 100 .
  • the output control module 400 is connected to the voltage regulator module 300 through the second node Q2, and is used for controlling the output of the gate driving signal Gate(N) of the current stage according to the clock signal CK(N) of the current stage.
  • the first pull-down module 500 is connected to the node signal control module 200 through the third node P, for pulling down the potential of the gate driving signal Gate(N) of the current stage under the control of the node signal control module 200 .
  • the second pull-down module 600 is connected to the output control module 400 and the voltage regulator module 300 through the second node Q2, for pulling down the potential of the second node Q2, at the node signal control module 200 Under the control of , when the second pull-down module 600 is in the working state, the forward and reverse scanning control module 100 controls the voltage regulator module 300 to be in the off state, thereby suppressing the threshold voltage shift of the transistor and improving the Describe the reliability of the GOA circuit.
  • the GOA circuit includes an input stage t1 , an output stage t2 , a first pull-down stage t3 and a second pull-down stage t4 .
  • the forward scanning control signal U2D When the display panel is in the forward scanning stage, the forward scanning control signal U2D is at a high potential, and the reverse scanning control signal D2U is at a low potential, at this time the GOA circuit scans line by line from top to bottom, otherwise,
  • the forward scan control signal U2D When the display panel is in the reverse scan phase, the forward scan control signal U2D is at a low level, and the reverse scan control signal D2U is at a high level, and the GOA circuit scans line by line from bottom to top.
  • the forward and reverse scan control module 100 includes a first transistor T1 and a second transistor T2, a first electrode of the first transistor T1 is connected to the forward scan control signal U2D, and a gate of the first transistor T1 is connected to the forward scan control signal U2D.
  • the first electrode of the second transistor T2 is connected to the reverse scanning control signal D2U, and the gate of the second transistor T2 is connected to the first electrode N+2-level gate driving signal Gate(N+2), the second electrode of the second transistor T2 is connected to the second electrode of the first transistor T1; wherein, the first transistor T1 is used for the During the input stage t1, the node signal control module 200, the voltage regulator module 300 and the output control module 400 are made to work, so that the output terminal of the output control module 400 writes the gate drive signal Gate ( N); the second transistor T2 is used to make the first pull-down module 500 and the second pull-down module 600 work in the second pull-down stage t4.
  • the node signal control module 200 includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5, and the first electrode of the third transistor T3 is connected to the N+2 th clock signal Gate(N+2), so The gate of the third transistor T3 is connected to the first electrode of the first transistor T1; the first electrode of the fourth transistor T4 is connected to the N-2 th clock signal CK(N-2), the The gate of the fourth transistor T4 is connected to the first electrode of the second transistor T2; the first electrode of the fifth transistor T5 is connected to the high potential signal VGH, and the second electrode of the fifth transistor T5 passes through the first electrode of the fifth transistor T5.
  • the three nodes P are connected to the first pull-down module 500, and the gate of the fifth transistor T5 is connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4.
  • the voltage regulator module 300 includes a sixth transistor T6 and a first storage capacitor C1, the gate of the sixth transistor T6 passes through the first node Q1 and the second electrode of the first transistor T1 and the first The first electrode plate of the storage capacitor C1 is connected, the first electrode of the sixth transistor T6 is connected to the high potential signal VGH, and the second electrode plate of the first storage capacitor C1 is connected to the low potential signal VGL;
  • the storage capacitor C1 is used to maintain the output control module 400 to work during the input stage t1, the output stage t2 and the first pull-down stage t3, so that the output terminal of the output control module 400 writes the stage clock signal CK(N).
  • the output control module 400 includes a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the clock signal CK(N) of the current stage, and the second electrode of the seventh transistor T7 is connected to the current stage
  • the gate driving signal is connected to Gate(N), and the gate of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 through the second node Q2.
  • the first pull-down module 500 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 and a second storage capacitor C2.
  • the first electrode of the eighth transistor T8 is connected to the low-level signal VGL, and the The gate of the eighth transistor T8 is connected to the second electrode of the second transistor T2; the first electrode of the ninth transistor T9 is connected to the low potential signal VGL, and the second electrode of the ninth transistor T9 passes through the
  • the first node Q1 is connected to the gate of the sixth transistor T6 and the first plate of the first storage capacitor C1; the first electrode of the tenth transistor T10 is connected to the low potential signal VGL, the The gate of the tenth transistor T10 is connected to the second electrode of the fifth transistor T5 through the third node P, and the second electrode of the tenth transistor T10 is connected to the gate driving signal Gate (N ); the second plate of the second storage capacitor C2 is connected to the low potential signal VGL, and the second storage capacitor C2 is used to maintain the gate voltages
  • the second pull-down module 600 includes an eleventh transistor T11, and the gate of the eleventh transistor T11 passes through the third node P and the second electrode of the fifth transistor T5 and the gate of the ninth transistor T9.
  • the gate is connected to the first plate of the second storage capacitor C2, the first electrode of the eleventh transistor T11 is connected to the low-capacitance signal VGL, and the second electrode of the eleventh transistor T11 passes through the
  • the second node Q2 is connected to the second electrode of the sixth transistor T6 and the gate of the seventh transistor T7;
  • the present application adds the second pull-down module 600, specifically adding For the eleventh transistor T11, since the gate of the sixth transistor T6 in the voltage stabilization module 300 in the prior art is connected to the high-potential signal VGH, the sixth transistor T6 is always in an on state;
  • the gate of the sixth transistor T6 in the voltage stabilization module 300 is connected to the first node Q1, and the first electrode of the sixth transistor T6 is connected to the high-potential
  • the GOA circuit further includes a reset module 700, the reset module 700 includes a twelfth transistor T12, the gate of the twelfth transistor T12 is connected to the first electrode of the twelfth transistor T12 and both are connected to reset signal, the second electrode of the twelfth transistor T12 is connected to the gate of the tenth transistor T10 through the third node P.
  • the reset module 700 includes a twelfth transistor T12, the gate of the twelfth transistor T12 is connected to the first electrode of the twelfth transistor T12 and both are connected to reset signal, the second electrode of the twelfth transistor T12 is connected to the gate of the tenth transistor T10 through the third node P.
  • the transistors located in the GOA circuit are field effect transistors; further, the transistors located in the GOA circuit are thin film transistors; further, the transistors located in the GOA circuit are The transistor is a low temperature polysilicon thin film transistor.
  • the first electrode of the present invention can be one of the drain electrode or the source electrode; correspondingly, the second electrode is the source electrode or the drain electrode. the other.
  • an embodiment of the present invention further provides a driving method for a GOA circuit, which is used in the above-mentioned GOA driving circuit, and includes the following steps:
  • the forward scanning control signal U2D connected to the forward and reverse scanning control module 100 in the GOA circuit makes the voltage regulator module 300 and the output control module 400 work, and the node signal control module 200 maintains the first pull-down module 500 and the output control module 400.
  • the second pull-down module 600 is in an off state, and the output control module 400 writes the gate driving signal Gate(N) of the current stage;
  • the first transistor T1 in the forward and reverse scanning control module 100 is turned on, and the first transistor T1 is turned on.
  • the first electrode of a transistor T1 writes the forward scan control signal U2D and charges the first storage capacitor C1, the potential of the first node Q1 is pulled up to a high level, because the voltage stabilization module 300
  • the first electrode of the sixth transistor T6 in the output control module 400 writes the high potential signal VGH, the potential of the second node Q2 also becomes a high level, and the seventh transistor T7 in the output control module 400 is turned on, the output terminal of the output control module 400 writes the clock signal CK(N) of the current stage; at the same time, the eighth transistor T8 in the first pull-down module 500 is turned on.
  • the first electrode of the eighth transistor T8 writes the low potential signal VGL, the potential of the third node P is pulled down, the ninth transistor T9 and the tenth transistor T10, And the eleventh transistor T11 in
  • the first transistor T1 in the forward and reverse scanning control module 100 is turned off, and the first storage capacitor is turned off.
  • the signal stored in C1 maintains the potential of the first node Q1 at a high level
  • the sixth transistor T6 in the voltage regulator module 300 is turned on, and the first electrode of the six transistors writes a high potential signal VGH
  • the potential of the second node Q2 remains at a high level
  • the seventh transistor T7 in the output control module 400 is turned on, and the output terminal of the output control module 400 writes the clock signal CK ( N).
  • the clock signal CK(N) of the current stage causes the output control module 400 to generate a bootstrap effect, and the output control module 400 writes the gate driving signal Gate(N) of the current stage.
  • the stage gate driving signal Gate(N) drives the driving transistors in the pixel driving circuit to work.
  • the seventh transistor T7 since the signal stored in the first storage capacitor C1 maintains the potentials at the first node Q1 and the second node Q2, the seventh transistor T7 remains on; at the same time, the The ninth transistor T9 and the tenth transistor T10 in the first pull-down module 500, and the eleventh transistor T11 in the second pull-down module 600 continue to write the low-level signal VGL, so The ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are turned off; the seventh transistor T7 is kept on so that the Nth level clock signal CK(N) is at a high level, A bootstrap effect occurs at the gate of the seventh transistor T7 (that is, at the second potential), and the potential at the second potential is pulled up to 2*VGH-VGL; the seventh transistor T7 is fully turned on, At this time, the output terminal Gate(N) of the output control module 400 is a full swing output, and the output terminal Gate(N) of the output control module 400 is written into the N-th stage clock signal CK(N
  • the output control module 400 writes the gate driving signal Gate(N) of the current stage.
  • the N-th stage clock signal CK(N) changes from a high level to a low level, the bootstrap effect disappears at the gate of the seventh transistor T7 (that is, at the second potential), and the The signal stored in the first storage capacitor C1 continues to maintain the potentials at the first node Q1 and the second node Q2, the seventh transistor T7 is still fully turned on, and the node signal controls all the signals in the module 200.
  • the second transistor T2 is still turned on; the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are still turned off; the output terminal Gate(N) of the output control module 400 writes The low-level signal VGL loaded by the N-th stage clock signal CK(N) is input, and at this time, the output terminal Gate(N) of the output control module 400 is rapidly pulled down to a low level.
  • the first pull-down module 500 and the second pull-down module 600 are in the working state, the potential of the gate driving signal Gate(N) of the current stage is pulled down, and the forward and reverse scanning control module 100 controls the voltage regulator module 300 to be in an off state, the output control module 400 is in an off state, and the output terminal of the output control module 400 writes a low-level signal VGL.
  • the N+2 stage clock signal CK(N+2) and the N+2 stage gate driving signal Gate(N+2) both change from high level to low level, and the forward and reverse scanning control
  • the second transistor T2 in the module 100 and the fifth transistor T5 in the node signal control module 200 are turned on, the potential of the first node Q1 is pulled down to a low level, and the third node The potential of P is pulled up to a high level, therefore, the ninth transistor T9 and the tenth transistor T10 in the first pull-down module 500 and the tenth transistor in the second pull-down module 600
  • a transistor T11 is turned on, the potentials at the first node Q1 and the second node Q2 are both pulled down to a low level, and the sixth transistor T6 in the voltage regulator module 300 is turned off, so
  • the seventh transistor T7 in the output control module 400 is turned off, and the output terminal Gate (N) of the output control module 400 writes the low-level signal VGL, thereby preventing the sixth transistor T6 from being in the At the
  • the GOA circuit further includes a reset module 700.
  • the driving method of the GOA circuit further includes a reset phase, and the reset phase is before the input phase t1, and before the start of a frame, the reset signal For the high-level signal VGH, the twelfth transistor T12 in the reset module 700 is turned on, and the potential at the third node P is pre-pulled to a high level.
  • the first pull-down module and the The second pull-down module is in a working state, wherein the ninth transistor T9 and the tenth transistor T10 in the first pull-down module 500 and the eleventh transistor in the second pull-down module 600 T11 is turned on, and the output terminal Gate(N) of the output control module 400 writes the low-level signal VGL loaded by the N-th clock signal CK(N); after that, the reset signal changes from the high-level signal VGH to the low-level signal VGL.
  • the twelfth transistor T12 in the reset module 700 is turned off, and at this time, the input stage t1 is awaited.
  • the present invention also provides a display panel, which includes any of the above GOA circuits, and the display panel can be a liquid crystal display panel.
  • the beneficial effects are as follows: in the GOA circuit, the driving method thereof, and the display panel provided by the embodiment of the present invention, by adding a second pull-down module, the second pull-down module is connected to the output control module and the voltage-stabilizing module through the second node, and is used to pull down the second pull-down module.
  • the forward and reverse scanning control module controls the voltage regulator module to be in the off state, so as to avoid the voltage regulator module being in the on state for a long time , so that there is no transistor in the GOA circuit that is in the open state for a long time, thereby suppressing the threshold voltage shift of the transistor and improving the reliability of the GOA circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路及其驱动方法、显示面板，GOA电路包括GOA单元，GOA单元包括正反向扫描控制模块(100)、节点信号控制模块(200)、稳压模块(300)、输出控制模块(400)、第一下拉模块(500)以及第二下拉模块(600)，当第二下拉模块(600)处于工作状态时，正反向扫描控制模块(100)控制稳压模块(300)处于关断状态，使得GOA电路无长期处于开态的晶体管，抑制晶体管的阈值电压偏移。

Description

GOA电路及其驱动方法、显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路及其驱动方法、显示面板。
 背景技术
GOA（Gate Driver On Array）电路是指利用现有薄膜晶体管液晶显示器array(阵列)制程将Gate（栅极）行扫描驱动信号电路制作在array基板上，实现对Gate逐行扫描的驱动方式的一项技术。
GOA电路包含多个晶体管，若某个晶体管长期处于开启状态，其阈值电压容易偏移，从而导致该晶体管无法正常工作，造成GOA电路输出失效引起显示异常。例如，以正向扫描为例，在图1所示的GOA电路单元中，晶体管T6的栅极连接的是高电位信号，此晶体管T6长期处于开启状态，其阈值电压会发生偏移；尤其在车载显示等高温工作状态下该阈值电压则会偏移加速，从而导致晶体管T6的薄膜晶体管(Thin Film Transistor, TFT)特性异常，造成GOA电路输出失效引起显示异常。
因此，亟需一种GOA电路及其驱动方法、显示面板以解决上述技术问题。
 技术问题
本发明提供的GOA电路及其驱动方法、显示面板，以解决现有的GOA电路包含多个晶体管，若某个晶体管长期处于开启状态，其阈值电压容易偏移，从而导致该晶体管无法正常工作，造成GOA电路输出失效引起显示异常的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种GOA电路，包括M个级联的GOA单元，其中第N级GOA单元包括：
正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制所述GOA电路进行正向扫描或反向扫描；
节点信号控制模块，与所述正反向扫描控制模块连接，用于根据第N+2级时钟信号和第N-2级时钟信号控制所述GOA电路在非工作阶段输出低电位的栅极驱动信号；
稳压模块，通过第一节点与所述正反向扫描控制模块连接，用于在所述正反向扫描控制模块的控制下，维持所述第一节点的电位；
输出控制模块，通过第二节点与所述稳压模块连接，用于根据本级时钟信号控制本级栅极驱动信号的输出；
第一下拉模块，通过第三节点与所述节点信号控制模块连接，用于在所述节点信号控制模块的控制下，下拉本级栅极驱动信号的电位；以及
第二下拉模块，通过所述第二节点与所述输出控制模块和所述稳压模块连接，用于下拉所述第二节点的电位，在所述节点信号控制模块的控制下，当所述第二下拉模块处于工作状态时，所述正反向扫描控制模块控制所述稳压模块处于关断状态。
根据本发明实施例提供的GOA电路，所述正反向扫描控制模块包括第一晶体管和第二晶体管，所述第一晶体管的第一电极接入所述正向扫描控制信号，所述第一晶体管的栅极连接第N-2级栅极驱动信号；所述第二晶体管的第一电极接入所述反向扫描控制信号，所述第二晶体管的栅极接入第N+2级栅极驱动信号，所述第二晶体管的第二电极连接所述第一晶体管的第二电极。
根据本发明实施例提供的GOA电路，所述节点控制模块包括第三晶体管、第四晶体管以及第五晶体管，所述第三晶体管的第一电极接入第N+2级时钟信号，所述第三晶体管的栅极与所述第一晶体管的第一电极连接；所述第四晶体管的第一电极接入第N-2级时钟信号，所述第四晶体管的栅极与所述第二晶体管的第一电极连接；所述第五晶体管的第一电极接入高电位信号，所述第五晶体管的第二电极通过所述第三节点与所述第一下拉模块连接，所述第五晶体管的栅极与所述第三晶体管的第二电极以及所述第四晶体管的第二电极连接。
根据本发明实施例提供的GOA电路，所述稳压模块包括第六晶体管和第一存储电容，所述第六晶体管的栅极通过所述第一节点与所述第一晶体管的第二电极以及所述第一存储电容的第一极板连接，所述第六晶体管的栅极连接所述高电位信号，所述第一存储电容的第二极板连接低电位信号。
根据本发明实施例提供的GOA电路，所述输出控制模块包括第七晶体管，所述第七晶体管的第一电极与所述本级时钟信号连接，所述第七晶体管的第二电极与所述本级栅极驱动信号连接，所述第七晶体管的栅极通过所述第二节点与所述第六晶体管的第二电极连接。
根据本发明实施例提供的GOA电路，所述第一下拉模块包括第八晶体管、第九晶体管、第十晶体管以及第二存储电容，所述第八晶体管的第一电极连接所述低电位信号，所述第八晶体管的栅极与所述第二晶体管的第二电极连接；所述第九晶体管的第一电极连接所述低电位信号，所述第九晶体管的第二电极通过所述第一节点与所述第七晶体管的栅极以及所述第一存储电容的第一极板连接；所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极连接，所述第十晶体管的第二电极接入所述本级栅极驱动信号；所述第二存储电容的第二极板连接所述低电位信号。
根据本发明实施例提供的GOA电路，所述第二下拉模块包括第十一晶体管，所述第十一晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极、所述第九晶体管的栅极以及所述第二存储电容的第一极板连接，所述第十一晶体管的第一电极连接所述低电位信号，所述第十一晶体管的第二电极通过所述第二节点与所述第六晶体管的第二电极以及所述第七晶体管的栅极连接。
根据本发明实施例提供的GOA电路，所述GOA电路还包括复位模块，所述复位模块包括第十二晶体管，所述第十二晶体管的栅极与所述第十二晶体管的第一电极连接且均接入复位信号，所述第十二晶体管的第二电极通过所述第三节点与所述第十晶体管的栅极连接。
根据本发明实施例提供的GOA电路，所述GOA电路中的多个晶体管为低温多晶硅薄膜晶体管。
本发明实施例提供一种显示面板，包括上述GOA电路，所述GOA电路包括M个级联的GOA单元，其中第N级GOA单元包括：
正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制所述GOA电路进行正向扫描或反向扫描；
节点信号控制模块，与所述正反向扫描控制模块连接，用于根据第N+2级时钟信号和第N-2级时钟信号控制所述GOA电路在非工作阶段输出低电位的栅极驱动信号；
稳压模块，通过第一节点与所述正反向扫描控制模块连接，用于在所述正反向扫描控制模块的控制下，维持所述第一节点的电位；
输出控制模块，通过第二节点与所述稳压模块连接，用于根据本级时钟信号控制本级栅极驱动信号的输出；
第一下拉模块，通过第三节点与所述节点信号控制模块连接，用于在所述节点信号控制模块的控制下，下拉本级栅极驱动信号的电位；以及
第二下拉模块，通过所述第二节点与所述输出控制模块和所述稳压模块连接，用于下拉所述第二节点的电位，在所述节点信号控制模块的控制下，当所述第二下拉模块处于工作状态时，所述正反向扫描控制模块控制所述稳压模块处于关断状态。
根据本发明实施例提供的显示面板，所述正反向扫描控制模块包括第一晶体管和第二晶体管，所述第一晶体管的第一电极接入所述正向扫描控制信号，所述第一晶体管的栅极连接第N-2级栅极驱动信号；所述第二晶体管的第一电极接入所述反向扫描控制信号，所述第二晶体管的栅极接入第N+2级栅极驱动信号，所述第二晶体管的第二电极连接所述第一晶体管的第二电极。
根据本发明实施例提供的显示面板，所述节点控制模块包括第三晶体管、第四晶体管以及第五晶体管，所述第三晶体管的第一电极接入第N+2级时钟信号，所述第三晶体管的栅极与所述第一晶体管的第一电极连接；所述第四晶体管的第一电极接入第N-2级时钟信号，所述第四晶体管的栅极与所述第二晶体管的第一电极连接；所述第五晶体管的第一电极接入高电位信号，所述第五晶体管的第二电极通过所述第三节点与所述第一下拉模块连接，所述第五晶体管的栅极与所述第三晶体管的第二电极以及所述第四晶体管的第二电极连接。
根据本发明实施例提供的显示面板，所述稳压模块包括第六晶体管和第一存储电容，所述第六晶体管的栅极通过所述第一节点与所述第一晶体管的第二电极以及所述第一存储电容的第一极板连接，所述第六晶体管的栅极连接所述高电位信号，所述第一存储电容的第二极板连接低电位信号。
根据本发明实施例提供的显示面板，所述输出控制模块包括第七晶体管，所述第七晶体管的第一电极与所述本级时钟信号连接，所述第七晶体管的第二电极与所述本级栅极驱动信号连接，所述第七晶体管的栅极通过所述第二节点与所述第六晶体管的第二电极连接。
根据本发明实施例提供的显示面板，所述第一下拉模块包括第八晶体管、第九晶体管、第十晶体管以及第二存储电容，所述第八晶体管的第一电极连接所述低电位信号，所述第八晶体管的栅极与所述第二晶体管的第二电极连接；所述第九晶体管的第一电极连接所述低电位信号，所述第九晶体管的第二电极通过所述第一节点与所述第七晶体管的栅极以及所述第一存储电容的第一极板连接；所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极连接，所述第十晶体管的第二电极接入所述本级栅极驱动信号；所述第二存储电容的第二极板连接所述低电位信号。
根据本发明实施例提供的显示面板，所述第二下拉模块包括第十一晶体管，所述第十一晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极、所述第九晶体管的栅极以及所述第二存储电容的第一极板连接，所述第十一晶体管的第一电极连接所述低电位信号，所述第十一晶体管的第二电极通过所述第二节点与所述第六晶体管的第二电极以及所述第七晶体管的栅极连接。
根据本发明实施例提供的显示面板，所述GOA电路还包括复位模块，所述复位模块包括第十二晶体管，所述第十二晶体管的栅极与所述第十二晶体管的第一电极连接且均接入复位信号，所述第十二晶体管的第二电极通过所述第三节点与所述第十晶体管的栅极连接。
根据本发明实施例提供的显示面板，所述GOA电路中的多个晶体管为低温多晶硅薄膜晶体管。
本发明实施例提供一种GOA电路驱动方法，包括以下步骤：
输入阶段，所述GOA电路中的正反向扫描控制模块连接的正向扫描控制信号使稳压模块和输出控制模块工作，节点信号控制模块保持第一下拉模块和第二下拉模块处于关断状态，所述输出控制模块写入本级栅极驱动信号；
输出阶段，所述本级时钟信号使所述输出控制模块发生自举效应，所述输出控制模块写入所述本级栅极驱动信号，所述本级栅极驱动信号驱动像素驱动电路中的驱动晶体管工作；
第一下拉阶段，所述输出控制模块写入所述本级栅极驱动信号；以及
第二下拉阶段，所述第一下拉模块和所述第二下拉模块处于工作状态，下拉所述本级栅极驱动信号的电位，所述正反向扫描控制模块控制所述稳压模块处于关断状态，所述输出控制模块处于关断状态，所述输出控制模块的输出端写入低电位信号。
根据本发明实施例提供的GOA电路驱动方法，还包括复位阶段，所述复位阶段在所述输入阶段之前，所述第一下拉模块和所述第二下拉模块处于工作状态，所述输出控制模块的输出端写入所述低电位信号。
 有益效果
本发明的有益效果为：本发明提供的GOA电路及其驱动方法、显示面板，通过增加第二下拉模块，第二下拉模块通过第二节点与输出控制模块和稳压模块连接，用于下拉第二节点的电位，在节点信号控制模块的控制下，当第二下拉模块处于工作状态时，正反向扫描控制模块控制所述稳压模块处于关断状态，从而避免稳压模块长期处于接通状态，使得GOA电路中无长期处于开态的晶体管，从而抑制晶体管的阈值电压偏移，提高GOA电路的信赖性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的GOA电路的电路结构示意图；
图2为本发明实施例提供的一种GOA电路的电路结构示意图；
图3为本发明实施例提供的一种GOA电路的工作时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的GOA电路、液晶显示面板及显示装置，以解决现有的GOA电路包含多个晶体管，若某个晶体管长期处于开启状态，其阈值电压容易偏移，从而导致该晶体管无法正常工作，造成GOA电路输出失效引起显示异常，本实施例能够解决该缺陷。
请参阅图2，本发明实施例提供的GOA电路，包括M个级联的GOA单元，其中第N级GOA单元包括：正反向扫描控制模块100、节点信号控制模块200、稳压模块300、输出控制模块400、第一下拉模块500以及第二下拉模块600。
所述正反向扫描控制模块100，用于根据正向扫描控制信号U2D或反向扫描控制信号D2U控制所述GOA电路进行正向扫描或反向扫描。
所述节点信号控制模块200，与所述正反向扫描控制模块100连接，用于根据第N+2级时钟信号CK(N+2)和第N-2级时钟信号CK(N-2)控制所述GOA电路在非工作阶段输出低电位的栅极驱动信号。
所述稳压模块300通过第一节点Q1与所述正反向扫描控制模块100连接，用于在所述正反向扫描控制模块100的控制下，维持所述第一节点Q1的电位。
所述输出控制模块400通过第二节点Q2与所述稳压模块300连接，用于根据本级时钟信号CK(N)控制本级栅极驱动信号Gate(N)的输出。
所述第一下拉模块500通过第三节点P与所述节点信号控制模块200连接，用于在所述节点信号控制模块200的控制下，下拉本级栅极驱动信号Gate(N)的电位。
所述第二下拉模块600通过所述第二节点Q2与所述输出控制模块400和所述稳压模块300连接，用于下拉所述第二节点Q2的电位，在所述节点信号控制模块200的控制下，当所述第二下拉模块600处于工作状态时，所述正反向扫描控制模块100控制所述稳压模块300处于关断状态，从而抑制晶体管的阈值电压偏移，提高了所述GOA电路的信赖性。
在本发明中，请参阅图2和图3，所述GOA电路包括输入阶段t1、输出阶段t2、第一下拉阶段t3以及第二下拉阶段t4。
当显示面板处于正向扫描阶段时，所述正向扫描控制信号U2D为高电位，所述反向扫描控制信号D2U为低电位，此时所述GOA电路由上向下逐行扫描，反之，当显示面板处于反向扫描阶段时，所述正向扫描控制信号U2D为低电位，所述反向扫描控制信号D2U为高电位，此时所述GOA电路由下向上逐行扫描。
所述正反向扫描控制模块100包括第一晶体管T1和第二晶体管T2，所述第一晶体管T1的第一电极接入所述正向扫描控制信号U2D，所述第一晶体管T1的栅极连接第N-2级栅极驱动信号Gate(N-2)；所述第二晶体管T2的第一电极接入所述反向扫描控制信号D2U，所述第二晶体管T2的栅极接入第N+2级栅极驱动信号Gate(N+2)，所述第二晶体管T2的第二电极连接所述第一晶体管T1的第二电极；其中，所述第一晶体管T1用于在所述输入阶段t1时使得所述节点信号控制模块200、所述稳压模块300以及所述输出控制模块400工作，使得所述输出控制模块400的输出端写入所述本级栅极驱动信号Gate(N)；所述第二晶体管T2用于在所述第二下拉阶段t4使所述第一下拉模块500和所述第二下拉模块600工作。
所述节点信号控制模块200包括第三晶体管T3、第四晶体管T4以及第五晶体管T5，所述第三晶体管T3的第一电极接入第N+2级时钟信号Gate(N+2)，所述第三晶体管T3的栅极与所述第一晶体管T1的第一电极连接；所述第四晶体管T4的第一电极接入第N-2级时钟信号CK(N-2)，所述第四晶体管T4的栅极与所述第二晶体管T2的第一电极连接；所述第五晶体管T5的第一电极接入高电位信号VGH，所述第五晶体管T5的第二电极通过所述第三节点P与所述第一下拉模块500连接，所述第五晶体管T5的栅极与所述第三晶体管T3的第二电极以及所述第四晶体管T4的第二电极连接。
所述稳压模块300包括第六晶体管T6和第一存储电容C1，所述第六晶体管T6的栅极通过所述第一节点Q1与所述第一晶体管T1的第二电极以及所述第一存储电容C1的第一极板连接，所述第六晶体管T6的第一电极连接所述高电位信号VGH，所述第一存储电容C1的第二极板连接低电位信号VGL；所述第一存储电容C1用于在所述输入阶段t1、所述输出阶段t2以及所述第一下拉阶段t3维持所述输出控制模块400工作，使得所述输出控制模块400的输出端写入所述本级时钟信号CK(N)。
所述输出控制模块400包括第七晶体管T7，所述第七晶体管T7的第一电极与所述本级时钟信号CK(N)连接，所述第七晶体管T7的第二电极与所述本级栅极驱动信号连接Gate(N)，所述第七晶体管T7的栅极通过所述第二节点Q2与所述第六晶体管T6的第二电极连接。
所述第一下拉模块500包括第八晶体管T8、第九晶体管T9、第十晶体管T10以及第二存储电容C2，所述第八晶体管T8的第一电极连接所述低电位信号VGL，所述第八晶体管T8的栅极与所述第二晶体管T2的第二电极连接；所述第九晶体管T9的第一电极连接所述低电位信号VGL，所述第九晶体管T9的第二电极通过所述第一节点Q1与所述第六晶体管T6的栅极以及所述第一存储电容C1的第一极板连接；所述第十晶体管T10的第一电极连接所述低电位信号VGL，所述第十晶体管T10的栅极通过所述第三节点P与所述第五晶体管T5的第二电极连接，所述第十晶体管T10的第二电极接入所述本级栅极驱动信号Gate(N)；所述第二存储电容C2的第二极板连接所述低电位信号VGL，所述第二存储电容C2用于维持所述第九晶体管T9和所述第十晶体管T10的栅极电压。
所述第二下拉模块600包括第十一晶体管T11，所述第十一晶体管T11的栅极通过所述第三节点P与所述第五晶体管T5的第二电极、所述第九晶体管T9的栅极以及所述第二存储电容C2的第一极板连接，所述第十一晶体管T11的第一电极连接所述低电容信号VGL，所述第十一晶体管T11的第二电极通过所述第二节点Q2与所述第六晶体管T6的第二电极以及所述第七晶体管T7的栅极连接；本申请相比现有的GOA电路增加了该所述第二下拉模块600，具体增加了所述第十一晶体管T11，由于现有技术中的所述稳压模块300中的所述第六晶体管T6的栅极接入高电位信号VGH，因此所述第六晶体管T6一直处于开启状态；而本申请中的所述稳压模块300中的所述第六晶体管T6的栅极连接所述第一节点Q1，所述第六晶体管T6的第一电极接入高电位信号VGH，从而通过所述第十一晶体管T11的设计使得所述第六晶体管T6被关断时，所述第二节点Q2处的电位接入低电位信号VGL，所述输出控制模块400中的所述第七晶体管T7被关断。
所述GOA电路还包括复位模块700，所述复位模块700包括第十二晶体管T12，所述第十二晶体管T12的栅极与所述第十二晶体管T12的第一电极连接且均接入复位信号，所述第十二晶体管T12的第二电极通过所述第三节点P与所述第十晶体管T10的栅极连接。
需要说明的是，位于所述GOA电路中的多个晶体管为场效应晶体管；进一步地，位于所述GOA电路中的多个晶体管为薄膜晶体管；更进一步地，位于所述GOA电路中的多个晶体管为低温多晶硅薄膜晶体管。为区分晶体管中除栅极以外的源极与漏极，本发明的所述第一电极可以为漏极或源极的一者；相应地，所述第二电极为源极或漏极中的另一者。
请参阅图2和图3，本发明实施例还提供一种GOA电路的驱动方法，用于上述GOA驱动电路，包括以下步骤：
输入阶段t1，所述GOA电路中的正反向扫描控制模块100连接的正向扫描控制信号U2D使稳压模块300和输出控制模块400工作，节点信号控制模块200保持第一下拉模块500和第二下拉模块600处于关断状态，所述输出控制模块400写入本级栅极驱动信号Gate(N)；
具体地，在所述输入阶段t1，在所述第N-2级栅极驱动信号为高电平时，所述正反向扫描控制模块100中的所述第一晶体管T1导通，所述第一晶体管T1的第一电极写入所述正向扫描控制信号U2D并对所述第一存储电容C1充电，所述第一节点Q1的电位被拉高至高电平，由于所述稳压模块300中的所述第六晶体管T6的第一电极写入所述高电位信号VGH，所述第二节点Q2的电位也变为高电平，所述输出控制模块400中的所述第七晶体管T7导通，所述输出控制模块400的输出端写入所述本级时钟信号CK(N)；与此同时，所述第一下拉模块500中的所述第八晶体管T8导通，由于所述第八晶体管T8的第一电极写入所述低电位信号VGL，所述第三节点P的电位被拉低，所述第一下拉模块500中的第九晶体管T9和第十晶体管T10、以及所述第二下拉模块600中的第十一晶体管T11被关断。
在所述第N-2级栅极驱动信号Gate(N-2)为低电平时，所述正反向扫描控制模块100中的所述第一晶体管T1被关断，所述第一存储电容C1中存储的信号维持所述第一节点Q1的电位为高电平，所述稳压模块300中的所述第六晶体管T6导通，所述六晶体管的第一电极写入高电位信号VGH，所述第二节点Q2的电位保持高电平，所述输出控制模块400中的所述第七晶体管T7导通，所述输出控制模块400的输出端写入所述本级时钟信号CK(N)。
输出阶段t2，所述本级时钟信号CK(N)使所述输出控制模块400发生自举效应，所述输出控制模块400写入所述本级栅极驱动信号Gate(N)，所述本级栅极驱动信号Gate(N)驱动像素驱动电路中的驱动晶体管工作。
具体地，由于所述第一存储电容C1中存储的信号维持所述第一节点Q1和所述第二节点Q2处的电位，所以所述第七晶体管T7维持导通；与此同时，所述第一下拉模块500中的所述第九晶体管T9和所述第十晶体管T10、以及所述第二下拉模块600中的所述第十一晶体管T11继续写入所述低电位信号VGL，所述第九晶体管T9、所述第十晶体管T10以及所述第十一晶体管T11被关断；所述第七晶体管T7维持导通使得所述第N级时钟信号CK(N)为高电平时，所述第七晶体管T7的栅极(即所述第二电位处)发生自举效应，所述第二电位处的电位被拉高至2*VGH-VGL；所述第七晶体管T7充分打开，此时所述输出控制模块400的输出端Gate(N)为全摆幅输出，所述输出控制模块400的输出端Gate(N)写入所述第N级时钟信号CK(N)载入的高电位信号VGH，从而为像素驱动电路的驱动晶体管提供栅极驱动信号。
第一下拉阶段t3，所述输出控制模块400写入所述本级栅极驱动信号Gate(N)。
具体地，所述第N级时钟信号CK(N)由高电平变为低电平，所述第七晶体管T7的栅极(即所述第二电位处)处自举效应消失，所述第一存储电容C1中存储的信号继续维持所述第一节点Q1与所述第二节点Q2处的电位，所述第七晶体管T7仍维持充分打开状态，所述节点信号控制模块200中的所述第二晶体管T2仍维持导通；所述第九晶体管T9、所述第十晶体管T10以及所述第十一晶体管T11仍被关断；所述输出控制模块400的输出端Gate(N)写入所述第N级时钟信号CK(N)载入的低电位信号VGL，此时所述输出控制模块400的输出端Gate(N)被迅速拉低至低电平。
第二下拉阶段t4，所述第一下拉模块500和所述第二下拉模块600处于工作状态，下拉所述本级栅极驱动信号Gate(N)的电位，所述正反向扫描控制模块100控制所述稳压模块300处于关断状态，所述输出控制模块400处于关断状态，所述输出控制模块400的输出端写入低电位信号VGL。
具体地，第N+2级时钟信号CK(N+2)以及第N+2级栅极驱动信号Gate(N+2)均由高电平变为低电平，所述正反向扫描控制模块100中的所述第二晶体管T2和所述节点信号控制模块200中的所述第五晶体管T5导通，所述第一节点Q1的电位被拉低至低电平，所述第三节点P的电位被拉高至高电平，因此，所述第一下拉模块500中的所述第九晶体管T9和所述第十晶体管T10，以及所述第二下拉模块600中的所述第十一晶体管T11导通，所述第一节点Q1和所述第二节点Q2处的电位均被拉低至低电平，所述稳压模块300中的所述第六晶体管T6被关断，所述输出控制模块400中的所述第七晶体管T7被关断，所述输出控制模块400的输出端Gate(N)写入所述低电位信号VGL，从而避免了所述第六晶体管T6一直处于开启状态；与此同时，所述第二存储电容C2进行充电，所述第九晶体管T9、所述第十晶体管T10以及所述第十一晶体管T11仍保持导通，以维持输出稳定性。
进一步地，所述GOA电路还包括复位模块700，相应地，所述GOA电路的驱动方法还包括复位阶段，所述复位阶段在所述输入阶段t1之前，在一帧开始之前，所述复位信号为高电位信号VGH，所述复位模块700中的所述第十二晶体管T12打开，所述第三节点P处的电位被预拉高至高电位，因此，所述第一下拉模块和所述第二下拉模块处于工作状态，其中，所述第一下拉模块500中的所述第九晶体管T9和所述第十晶体管T10、以及所述第二下拉模块600中的所述第十一晶体管T11导通，所述输出控制模块400的输出端Gate(N)写入所述第N级时钟信号CK(N)载入的低电位信号VGL；之后，所述复位信号由高电位信号VGH变为低电位信号VGL，所述复位模块700中的所述第十二晶体管T12被关断，此时等待所述输入阶段t1的到来。
本发明还提供一种显示面板，其包括上述任意一种GOA电路，该显示面板可以为液晶显示面板。
有益效果为：本发明实施例提供的GOA电路及其驱动方法、显示面板，通过增加第二下拉模块，第二下拉模块通过第二节点与输出控制模块和稳压模块连接，用于下拉第二节点的电位，在节点信号控制模块的控制下，当第二下拉模块处于工作状态时，正反向扫描控制模块控制所述稳压模块处于关断状态，从而避免稳压模块长期处于接通状态，使得GOA电路中无长期处于开态的晶体管，从而抑制晶体管的阈值电压偏移，提高GOA电路的信赖性。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种GOA电路，包括M个级联的GOA单元，其中第N级GOA单元包括：
    正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制所述GOA电路进行正向扫描或反向扫描；
    节点信号控制模块，与所述正反向扫描控制模块连接，用于根据第N+2级时钟信号和第N-2级时钟信号控制所述GOA电路在非工作阶段输出低电位的栅极驱动信号；
    稳压模块，通过第一节点与所述正反向扫描控制模块连接，用于在所述正反向扫描控制模块的控制下，维持所述第一节点的电位；
    输出控制模块，通过第二节点与所述稳压模块连接，用于根据本级时钟信号控制本级栅极驱动信号的输出；
    第一下拉模块，通过第三节点与所述节点信号控制模块连接，用于在所述节点信号控制模块的控制下，下拉本级栅极驱动信号的电位；以及
    第二下拉模块，通过所述第二节点与所述输出控制模块和所述稳压模块连接，用于下拉所述第二节点的电位，在所述节点信号控制模块的控制下，当所述第二下拉模块处于工作状态时，所述正反向扫描控制模块控制所述稳压模块处于关断状态。
  2. 根据权利要求1所述的GOA电路，其中所述正反向扫描控制模块包括第一晶体管和第二晶体管，所述第一晶体管的第一电极接入所述正向扫描控制信号，所述第一晶体管的栅极连接第N-2级栅极驱动信号；所述第二晶体管的第一电极接入所述反向扫描控制信号，所述第二晶体管的栅极接入第N+2级栅极驱动信号，所述第二晶体管的第二电极连接所述第一晶体管的第二电极。
  3. 根据权利要求2所述的GOA电路，其中所述节点控制模块包括第三晶体管、第四晶体管以及第五晶体管，所述第三晶体管的第一电极接入第N+2级时钟信号，所述第三晶体管的栅极与所述第一晶体管的第一电极连接；所述第四晶体管的第一电极接入第N-2级时钟信号，所述第四晶体管的栅极与所述第二晶体管的第一电极连接；所述第五晶体管的第一电极接入高电位信号，所述第五晶体管的第二电极通过所述第三节点与所述第一下拉模块连接，所述第五晶体管的栅极与所述第三晶体管的第二电极以及所述第四晶体管的第二电极连接。
  4. 根据权利要求3所述的GOA电路，其中所述稳压模块包括第六晶体管和第一存储电容，所述第六晶体管的栅极通过所述第一节点与所述第一晶体管的第二电极以及所述第一存储电容的第一极板连接，所述第六晶体管的栅极连接所述高电位信号，所述第一存储电容的第二极板连接低电位信号。
  5. 根据权利要求4所述的GOA电路，其中所述输出控制模块包括第七晶体管，所述第七晶体管的第一电极与所述本级时钟信号连接，所述第七晶体管的第二电极与所述本级栅极驱动信号连接，所述第七晶体管的栅极通过所述第二节点与所述第六晶体管的第二电极连接。
  6. 根据权利要求5所述的GOA电路，其中所述第一下拉模块包括第八晶体管、第九晶体管、第十晶体管以及第二存储电容，所述第八晶体管的第一电极连接所述低电位信号，所述第八晶体管的栅极与所述第二晶体管的第二电极连接；所述第九晶体管的第一电极连接所述低电位信号，所述第九晶体管的第二电极通过所述第一节点与所述第七晶体管的栅极以及所述第一存储电容的第一极板连接；所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极连接，所述第十晶体管的第二电极接入所述本级栅极驱动信号；所述第二存储电容的第二极板连接所述低电位信号。
  7. 根据权利要求6所述的GOA电路，其中所述第二下拉模块包括第十一晶体管，所述第十一晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极、所述第九晶体管的栅极以及所述第二存储电容的第一极板连接，所述第十一晶体管的第一电极连接所述低电位信号，所述第十一晶体管的第二电极通过所述第二节点与所述第六晶体管的第二电极以及所述第七晶体管的栅极连接。
  8. 根据权利要求7所述的GOA电路，其中所述GOA电路还包括复位模块，所述复位模块包括第十二晶体管，所述第十二晶体管的栅极与所述第十二晶体管的第一电极连接且均接入复位信号，所述第十二晶体管的第二电极通过所述第三节点与所述第十晶体管的栅极连接。
  9. 根据权利要求1所述的GOA电路，其中所述GOA电路中的多个晶体管为低温多晶硅薄膜晶体管。
  10. 一种显示面板，包括上述GOA电路，所述GOA电路包括M个级联的GOA单元，其中第N级GOA单元包括：
    正反向扫描控制模块，用于根据正向扫描控制信号或反向扫描控制信号控制所述GOA电路进行正向扫描或反向扫描；
    节点信号控制模块，与所述正反向扫描控制模块连接，用于根据第N+2级时钟信号和第N-2级时钟信号控制所述GOA电路在非工作阶段输出低电位的栅极驱动信号；
    稳压模块，通过第一节点与所述正反向扫描控制模块连接，用于在所述正反向扫描控制模块的控制下，维持所述第一节点的电位；
    输出控制模块，通过第二节点与所述稳压模块连接，用于根据本级时钟信号控制本级栅极驱动信号的输出；
    第一下拉模块，通过第三节点与所述节点信号控制模块连接，用于在所述节点信号控制模块的控制下，下拉本级栅极驱动信号的电位；以及
    第二下拉模块，通过所述第二节点与所述输出控制模块和所述稳压模块连接，用于下拉所述第二节点的电位，在所述节点信号控制模块的控制下，当所述第二下拉模块处于工作状态时，所述正反向扫描控制模块控制所述稳压模块处于关断状态。
  11. 根据权利要求10所述的显示面板，其中所述正反向扫描控制模块包括第一晶体管和第二晶体管，所述第一晶体管的第一电极接入所述正向扫描控制信号，所述第一晶体管的栅极连接第N-2级栅极驱动信号；所述第二晶体管的第一电极接入所述反向扫描控制信号，所述第二晶体管的栅极接入第N+2级栅极驱动信号，所述第二晶体管的第二电极连接所述第一晶体管的第二电极。
  12. 根据权利要求11所述的显示面板，其中所述节点控制模块包括第三晶体管、第四晶体管以及第五晶体管，所述第三晶体管的第一电极接入第N+2级时钟信号，所述第三晶体管的栅极与所述第一晶体管的第一电极连接；所述第四晶体管的第一电极接入第N-2级时钟信号，所述第四晶体管的栅极与所述第二晶体管的第一电极连接；所述第五晶体管的第一电极接入高电位信号，所述第五晶体管的第二电极通过所述第三节点与所述第一下拉模块连接，所述第五晶体管的栅极与所述第三晶体管的第二电极以及所述第四晶体管的第二电极连接。
  13. 根据权利要求12所述的显示面板，其中所述稳压模块包括第六晶体管和第一存储电容，所述第六晶体管的栅极通过所述第一节点与所述第一晶体管的第二电极以及所述第一存储电容的第一极板连接，所述第六晶体管的栅极连接所述高电位信号，所述第一存储电容的第二极板连接低电位信号。
  14. 根据权利要求13所述的显示面板，其中所述输出控制模块包括第七晶体管，所述第七晶体管的第一电极与所述本级时钟信号连接，所述第七晶体管的第二电极与所述本级栅极驱动信号连接，所述第七晶体管的栅极通过所述第二节点与所述第六晶体管的第二电极连接。
  15. 根据权利要求14所述的显示面板，其中所述第一下拉模块包括第八晶体管、第九晶体管、第十晶体管以及第二存储电容，所述第八晶体管的第一电极连接所述低电位信号，所述第八晶体管的栅极与所述第二晶体管的第二电极连接；所述第九晶体管的第一电极连接所述低电位信号，所述第九晶体管的第二电极通过所述第一节点与所述第七晶体管的栅极以及所述第一存储电容的第一极板连接；所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的第一电极连接所述低电位信号，所述第十晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极连接，所述第十晶体管的第二电极接入所述本级栅极驱动信号；所述第二存储电容的第二极板连接所述低电位信号。
  16. 根据权利要求15所述的显示面板，其中所述第二下拉模块包括第十一晶体管，所述第十一晶体管的栅极通过所述第三节点与所述第五晶体管的第二电极、所述第九晶体管的栅极以及所述第二存储电容的第一极板连接，所述第十一晶体管的第一电极连接所述低电位信号，所述第十一晶体管的第二电极通过所述第二节点与所述第六晶体管的第二电极以及所述第七晶体管的栅极连接。
  17. 根据权利要求16所述的显示面板，其中所述GOA电路还包括复位模块，所述复位模块包括第十二晶体管，所述第十二晶体管的栅极与所述第十二晶体管的第一电极连接且均接入复位信号，所述第十二晶体管的第二电极通过所述第三节点与所述第十晶体管的栅极连接。
  18. 根据权利要求10所述的显示面板，其中所述GOA电路中的多个晶体管为低温多晶硅薄膜晶体管。
  19. 一种GOA电路驱动方法，包括以下步骤：
    输入阶段，所述GOA电路中的正反向扫描控制模块连接的正向扫描控制信号使稳压模块和输出控制模块工作，节点信号控制模块保持第一下拉模块和第二下拉模块处于关断状态，所述输出控制模块写入本级栅极驱动信号；
    输出阶段，所述本级时钟信号使所述输出控制模块发生自举效应，所述输出控制模块写入所述本级栅极驱动信号，所述本级栅极驱动信号驱动像素驱动电路中的驱动晶体管工作；
    第一下拉阶段，所述输出控制模块写入所述本级栅极驱动信号；以及
    第二下拉阶段，所述第一下拉模块和所述第二下拉模块处于工作状态，下拉所述本级栅极驱动信号的电位，所述正反向扫描控制模块控制所述稳压模块处于关断状态，所述输出控制模块处于关断状态，所述输出控制模块的输出端写入低电位信号。
  20. 根据权利要求19所述的GOA电路驱动方法，其中还包括复位阶段，所述复位阶段在所述输入阶段之前，所述第一下拉模块和所述第二下拉模块处于工作状态，所述输出控制模块的输出端写入所述低电位信号。
PCT/CN2020/131755 2020-11-03 2020-11-26 Goa 电路及其驱动方法、显示面板 WO2022095159A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/280,909 US11798511B2 (en) 2020-11-03 2020-11-26 GOA circuit and driving method therefor, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011211809.0 2020-11-03
CN202011211809.0A CN112289275B (zh) 2020-11-03 2020-11-03 Goa电路及其驱动方法、显示面板

Publications (1)

Publication Number Publication Date
WO2022095159A1 true WO2022095159A1 (zh) 2022-05-12

Family

ID=74350525

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/131755 WO2022095159A1 (zh) 2020-11-03 2020-11-26 Goa 电路及其驱动方法、显示面板

Country Status (3)

Country Link
US (1) US11798511B2 (zh)
CN (1) CN112289275B (zh)
WO (1) WO2022095159A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI830491B (zh) * 2022-11-09 2024-01-21 友達光電股份有限公司 斜波電壓產生器及其操作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114170987B (zh) * 2021-12-09 2022-11-08 武汉华星光电技术有限公司 栅极驱动电路及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104992661A (zh) * 2015-07-29 2015-10-21 京东方科技集团股份有限公司 移位寄存电路及其驱动方法、栅极驱动电路及显示装置
CN106098003A (zh) * 2016-08-08 2016-11-09 武汉华星光电技术有限公司 Goa电路
US20170018245A1 (en) * 2015-07-17 2017-01-19 Samsung Display Co., Ltd. Gate driving circuit and display apparatus having the same
CN106782389A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 一种阵列基板行驱动电路
CN107749281A (zh) * 2017-10-31 2018-03-02 武汉华星光电技术有限公司 一种栅极驱动电路
CN108962168A (zh) * 2018-07-24 2018-12-07 武汉华星光电技术有限公司 单型goa电路
CN109036304A (zh) * 2018-07-26 2018-12-18 武汉华星光电技术有限公司 一种goa电路、显示面板及显示装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103258494B (zh) * 2013-04-16 2015-10-14 合肥京东方光电科技有限公司 一种移位寄存器、栅极驱动装置和液晶显示装置
US9626928B2 (en) * 2014-12-31 2017-04-18 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid crystal display device comprising gate driver on array circuit
CN105336302B (zh) * 2015-12-07 2017-12-01 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN105489180B (zh) * 2016-01-04 2018-06-01 武汉华星光电技术有限公司 Goa电路
CN107221279B (zh) * 2017-05-19 2020-11-27 南京中电熊猫液晶显示科技有限公司 一种双向扫描驱动电路
US10431178B2 (en) * 2017-10-31 2019-10-01 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA driving circuit
US10490151B2 (en) * 2017-10-31 2019-11-26 Wuhan China Star Optotelectronics Technology Co., Ltd. Gate driving circuit
CN107799083B (zh) * 2017-11-17 2020-02-07 武汉华星光电技术有限公司 一种goa电路
US10302985B1 (en) * 2017-11-28 2019-05-28 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit, liquid crystal panel and display device
CN107958656B (zh) * 2018-01-08 2019-07-02 武汉华星光电技术有限公司 Goa电路
CN108399899A (zh) * 2018-01-29 2018-08-14 南京中电熊猫平板显示科技有限公司 一种双向扫描栅极驱动电路
CN108389554B (zh) * 2018-01-29 2020-11-06 南京中电熊猫液晶显示科技有限公司 栅极扫描驱动电路及液晶显示装置
CN108538268B (zh) * 2018-04-20 2020-08-04 南京中电熊猫液晶显示科技有限公司 一种双向扫描栅极驱动电路
CN108630167A (zh) * 2018-07-26 2018-10-09 武汉华星光电技术有限公司 一种goa电路、显示面板及显示装置
CN110875002B (zh) * 2018-08-30 2021-04-13 合肥鑫晟光电科技有限公司 栅极驱动单元及其驱动方法、栅极驱动电路、显示装置
CN109326261B (zh) * 2018-11-30 2020-10-27 武汉华星光电技术有限公司 Goa电路和显示面板
CN110782855A (zh) * 2019-10-12 2020-02-11 武汉华星光电技术有限公司 G0a电路和显示面板
CN111681624A (zh) * 2020-06-19 2020-09-18 武汉华星光电技术有限公司 显示面板及栅极驱动电路驱动方法、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170018245A1 (en) * 2015-07-17 2017-01-19 Samsung Display Co., Ltd. Gate driving circuit and display apparatus having the same
CN104992661A (zh) * 2015-07-29 2015-10-21 京东方科技集团股份有限公司 移位寄存电路及其驱动方法、栅极驱动电路及显示装置
CN106098003A (zh) * 2016-08-08 2016-11-09 武汉华星光电技术有限公司 Goa电路
CN106782389A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 一种阵列基板行驱动电路
CN107749281A (zh) * 2017-10-31 2018-03-02 武汉华星光电技术有限公司 一种栅极驱动电路
CN108962168A (zh) * 2018-07-24 2018-12-07 武汉华星光电技术有限公司 单型goa电路
CN109036304A (zh) * 2018-07-26 2018-12-18 武汉华星光电技术有限公司 一种goa电路、显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI830491B (zh) * 2022-11-09 2024-01-21 友達光電股份有限公司 斜波電壓產生器及其操作方法

Also Published As

Publication number Publication date
US11798511B2 (en) 2023-10-24
CN112289275B (zh) 2022-02-22
CN112289275A (zh) 2021-01-29
US20220358891A1 (en) 2022-11-10

Similar Documents

Publication Publication Date Title
US9875709B2 (en) GOA circuit for LTPS-TFT
US20200273503A1 (en) Shift register unit, gate driving circuit, display device and driving method
US8031160B2 (en) Shift register, shift register array, and flat display apparatus
US9659540B1 (en) GOA circuit of reducing power consumption
CN108766380B (zh) Goa电路
JP5372268B2 (ja) 走査信号線駆動回路、それを備えた表示装置、および走査信号線の駆動方法
WO2019134221A1 (zh) Goa电路
WO2009104307A1 (ja) シフトレジスタ回路および表示装置ならびにシフトレジスタ回路の駆動方法
TWI529682B (zh) A scanning signal line driving circuit, a display device including the same, and a driving method of a scanning signal line
JP2020500333A (ja) Ｉｇｚｏ薄膜トランジスタのｇｏａ回路及び表示装置
US9053677B2 (en) Gate driving circuit and display panel having the same
WO2014092011A1 (ja) 表示装置およびその駆動方法
US10902810B2 (en) Array substrate gate driving unit and apparatus thereof, driving method and display apparatus
WO2019210830A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2017113447A1 (zh) 栅极驱动电路及显示装置
KR20150019098A (ko) 게이트 구동 회로 및 이를 구비한 표시 장치
WO2010067643A1 (ja) シフトレジスタ回路および表示装置ならびにシフトレジスタ回路の駆動方法
WO2020199486A1 (zh) Goa电路结构及驱动方法
WO2021253570A1 (zh) 显示面板及栅极驱动电路驱动方法、显示装置
WO2018193912A1 (ja) 走査信号線駆動回路およびそれを備える表示装置
WO2021159586A1 (zh) 一种goa电路及其显示面板
WO2022095159A1 (zh) Goa 电路及其驱动方法、显示面板
US10269320B1 (en) GOA circuit and embedded touch display panel
US10386663B2 (en) GOA circuit and liquid crystal display device
WO2021103164A1 (zh) 一种 goa 电路及液晶显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20960616

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20960616

Country of ref document: EP

Kind code of ref document: A1