WO2022089586A1 - 半导体器件、三维存储器及半导体器件制备方法 - Google Patents

半导体器件、三维存储器及半导体器件制备方法 Download PDF

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WO2022089586A1
WO2022089586A1 PCT/CN2021/127443 CN2021127443W WO2022089586A1 WO 2022089586 A1 WO2022089586 A1 WO 2022089586A1 CN 2021127443 W CN2021127443 W CN 2021127443W WO 2022089586 A1 WO2022089586 A1 WO 2022089586A1
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contact
substrate
semiconductor device
contacts
gate
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PCT/CN2021/127443
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English (en)
French (fr)
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陈亮
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长江存储科技有限责任公司
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Priority to CN202180007256.3A priority Critical patent/CN116438937A/zh
Publication of WO2022089586A1 publication Critical patent/WO2022089586A1/zh
Priority to US18/090,357 priority patent/US20230134659A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Definitions

  • the present application relates to the technical field of semiconductor memory devices, and in particular, to a semiconductor device, a three-dimensional memory and a method for fabricating a semiconductor device.
  • 3D memory is a flash memory device with three-dimensional stacked memory cells. Compared with planar memory, it is used for higher storage density per unit area.
  • the existing 3D NAND memory cell architecture is usually designed with vertical channel and horizontal control gate layer. Integration can be multiplied on a wafer per unit area.
  • CMOS Complementary Metal Oxide Semiconductor
  • the purpose of the present application is to provide a three-dimensional memory and a preparation method thereof, so as to realize large-density capacitance structures of semiconductor devices and three-dimensional memory devices.
  • the present application provides a semiconductor device, comprising a substrate, a plurality of gates, first contacts corresponding to the plurality of gates, and a plurality of second contacts;
  • a plurality of the gates are spaced on the surface of the substrate, and there is a spacer between every two adjacent gates, and the surface of the substrate is provided with a source located in the spacer pole,
  • Each of the gates includes a connection surface, the connection surface of each of the gates is provided with one of the first contacts, and the orthographic projection of the first contacts on the connection surface is in the shape of a strip, and The length extension direction of the first contact is the same as the gate length direction;
  • a plurality of the second contacts are arranged on the substrate and are connected to the source in the spacer region, the second contacts have the same structure as the first contacts, and the first contacts The two contacts are arranged in parallel with the first contact.
  • the present application also provides a three-dimensional memory, comprising the semiconductor device and a storage array, wherein the semiconductor device and the storage array are electrically connected.
  • the present application also provides a method for preparing a semiconductor device, the method comprising:
  • a plurality of gate electrodes and source electrodes are formed on the substrate, and a spacer is formed between every two of the gate electrodes, and each spacer region is provided with a source electrode; wherein, the gate electrode includes a connection surface,
  • a contact is formed on the connection surface of each of the gates and on the substrate in each of the spacers, the contact is in the shape of an elongated strip on the orthographic projection of the substrate, and the contact
  • the extension direction of the length is the same as the length direction of the gate.
  • FIG. 1 is a schematic top-view structure diagram of a semiconductor device provided by the present application.
  • FIG. 2 is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present application.
  • FIG. 3 is a flow chart of a method for fabricating a semiconductor device provided by the present application.
  • 4-5 are schematic diagrams of various steps of the semiconductor device provided by the present application.
  • Peripheral circuits may be understood as peripheral devices of the memory, ie, may be semiconductor devices, which include any suitable digital, analog and/or mixed-signal peripheral circuits used to facilitate the operation of the memory.
  • peripheral devices may include page buffers, decoders (eg, row decoders and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or active or active in any circuit
  • CMOS complementary metal semiconductor
  • ILD interleukin layer
  • the present application provides a semiconductor device and a three-dimensional memory, including a semiconductor device and a storage array, wherein the semiconductor device and the storage array are electrically connected.
  • the semiconductor device in the embodiment of the present application includes a substrate 10 , a plurality of gates 12 , a first contact 14 corresponding to the plurality of gates 12 , and a plurality of second contacts 16 .
  • a plurality of the gates 12 are spaced on the surface 101 of the substrate 10 , and there is a spacer 102 between every two adjacent gates 12 , and the surface 101 of the substrate 10 is provided with a spacer 102 .
  • the source electrode (not shown) of the spacer region 102 is located.
  • Each of the gates 12 includes a connection surface 121 , and a first contact 14 is disposed on the connection surface 121 of each of the gates 12 , and the first contact 14 is on the positive side of the connection surface 121 .
  • the projection is elongated, and the lengthwise extending direction of the first contact 14 is the same as the lengthwise direction of the gate 12 .
  • a plurality of the second contacts 16 are provided on the substrate 10 and are located in the spacer 102 and connected to the source (not shown), and the second contacts 16 are connected to the first
  • the contacts 14 have the same structure, and the second contacts 16 and the first contacts 14 are arranged in parallel.
  • the semiconductor device is a peripheral circuit, providing electrical connection for the three-dimensional memory, each gate 12 is electrically connected through a first contact 14 , and each source is connected to one of the second contact.
  • An ILD layer (not shown) is formed on the substrate 10, the ILD layer covers the gate electrode 12 and the surface of the substrate 10, and the first contact 14 and the second contact 16 are formed on the surface of the gate electrode 12 and the substrate 10. within the ILD layer.
  • the orthographic projection of each of the first contact 14 and the second contact 16 is a rectangle, that is, the first contact 14 and the second contact 16 are perpendicular to the
  • the gate is in the shape of a rectangular plate when viewed in the length direction, and the thickness of the ILD layer is thinner, which facilitates the formation of the first contact 14 and the second contact 16 in the form of a plate.
  • the first contact 14 and the second contact 16 are in a plate shape instead of a dot matrix, so that the area of the first contact 14 and the second contact 16 is increased, so that the The capacitance provided within the semiconductor device increases.
  • the cross section of the first contact 14 in the width direction of the gate 12 is a trapezoid, and the top edge A of the trapezoid is connected to the connection surface of the gate 12 .
  • the width direction of the gate 12 is understood as the X direction
  • the length direction of the gate 12 is the Y direction
  • a plurality of the gates 12 are arranged at intervals in the X direction
  • a plurality of A contact point 14 is spaced apart in the X direction.
  • the first contact 14 is a rectangular plate, and viewed from the Y direction, the cross section of the first contact 14 is a trapezoid, and the shorter top edge of the trapezoid is connected to the gate 12
  • the contact area between the first contact 14 and the gate 12 in the X direction is guaranteed, that is, the surface contact area between the first contact 14 and the gate 12 is large enough, and the The distance between the first contact 14 and the second contact 16 is reduced, and the distance a between the first contact 14 and the surface edge of the gate 12 is more than 50-70 nanometers, which ensures that the first contact can be accurately connected to the gate
  • the pole surface contacts in turn, can ensure that the distance between the two contacts is reduced.
  • the distance b between the second contact 16 located in the spacer region 102 and the two gate electrodes 12 forming the spacer region is 50-70 nm, which can reduce every two contacts
  • the distance between (the first contact 14 and the second contact 16) can increase the capacitance.
  • the structure of the second contact 16 is the same as the structure of the first contact 14. Viewed from the X direction, the second contact 16 is a rectangular plate body, and when viewed along the Y direction, the second contact 16 is a rectangular plate.
  • the cross-section of the contact 16 is a trapezoid, and the shorter top side of the trapezoid is connected to the source on the substrate 10 , and the end of the second contact 16 connected to the source on the substrate 10 decreases in dimension c in the X direction. small, thereby reducing the gate density, increasing the number of second contacts per unit area, and increasing capacitance.
  • the first contact 14 and the second contact 16 are in the shape of a rectangular plate. Compared with the arrangement of multiple contacts, the surface of the contacts is increased, thereby increasing the capacitance.
  • the semiconductor device further includes a metal layer 18, the metal layer 18 is formed on the surfaces of the plurality of first contacts and the plurality of second contacts away from the substrate, for connecting the first contacts Point 14 and second contact 16 are electrically connected to other devices of the memory.
  • the metal layer 18 includes a first metal layer and a second metal layer that are stacked and separated by an insulating layer, and the first metal layer and the second metal layer are connected by via holes.
  • the method for fabricating a semiconductor device provided by the present application will be described in detail below with reference to the foregoing semiconductor device.
  • the semiconductor device obtained by the method for manufacturing a semiconductor device may also be different from the semiconductor device in the foregoing embodiments.
  • the present application provides a method for preparing a semiconductor device, characterized in that the method includes:
  • a substrate 10 is provided; the substrate 10 is used for the device structure supported thereon.
  • the material of the substrate 10 is single crystal silicon (Si).
  • the material of the substrate 10 may be elemental semiconductors such as germanium (Ge), compound semiconductors such as germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP) , indium phosphide (InP), indium arsenide (InAs) and/or indium antimonide (InSb), alloy semiconductors such as gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs) , gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and/or gallium indium arsen
  • a plurality of gate electrodes 12 and source electrodes are formed on the substrate 10 , and a spacer 102 is formed between each two of the gate electrodes 12 , and each spacer 102 A source electrode is provided; wherein, the gate electrode 12 includes a connection surface 121 .
  • the gate 12 can be made of polysilicon, and the material is silicon nitride (SixNy, such as SiN), amorphous silicon, polysilicon, aluminum oxide, or a combination of the above materials.
  • the gate 12 is formed by coating and etching or masking. Specifically, a gate sacrificial layer is formed first, and the gate sacrificial layer will be replaced by metal to serve as a gate in a subsequent process.
  • the step of forming a plurality of gate electrodes 12 and source electrodes on the substrate 10 further includes forming an ILD layer (not shown) on the substrate 10, and the ILD layer covers the gate electrodes 12 and the source electrodes. the source.
  • a first contact 14 is formed on the connection surface 121 of each of the gate electrodes 12 through a mask and an etching process, and the first contact 14 is on the positive side of the connection surface 121 .
  • the projection is elongated, and the lengthwise extending direction of the first contact 14 is the same as the lengthwise direction of the gate 12 .
  • the orthographic projection of the first contact 14 on the connection surface 121 is located within the orthographic projection of the gate 12 .
  • the first contact 14 may be composed of W, Ru, Co or other suitable conductive materials.
  • the first contact 14 may be formed by forming a via hole on the ILD layer and then filling. The specific method for forming the through hole may be formed in the ILD layer by using a mask plate combined with an etching method, which will not be described in detail here.
  • This embodiment further includes a fourth step of forming a second contact 16 on the substrate 10 in each of the spacers 102 through a mask and etching process, so that the second contact 16 is connected to the source electrode. connection, wherein the second contact 16 and the first contact 14 have the same structure, and the second contact 16 and the first contact 14 are arranged in parallel.
  • the second contact 16 may be composed of W, Ru, Co or other suitable conductive materials.
  • the second contact 16 may be formed by forming a via hole on the ILD layer and then filling. The specific method of forming the through hole can be formed in the ILD layer by using a mask plate combined with an etching method, which will not be repeated here.
  • the cross section of the first contact 14 in the width direction of the gate 12 is a trapezoid, and the top edge of the trapezoid is connected to the gate 12 . and in the width direction of the gate 12, the orthographic projection of each of the first contact 14 and the second contact 16 is a rectangle. In other embodiments, the first contact 14 and the second contact 15 are formed simultaneously.
  • the manufacturing method of the semiconductor device further includes forming a metal layer 18, the metal layer 18 is formed on the surface of the plurality of first contacts 14 and the plurality of second contacts 16 away from the substrate 10 and on the surface of the plurality of first contacts 14 and the plurality of second contacts 16.
  • a drain corresponding to the source is disposed on the ILD layer and the metal layer 18 .
  • the metal layer may be composed of Cu, Al, Ru, Co, W or other suitable conductive materials.
  • the orthographic projection of the connection surface of the first contact on the gate is in the shape of a long strip, and the lengthwise extending direction of the first contact is the same as the lengthwise direction of the gate ;
  • the structure of the second contact is the same as that of the first contact, the independent first contact and the second contact are not represented by a dot matrix, the unit area of the contact is increased, and the capacitance can be increased to realize the semiconductor device and Large-density capacitive structures for three-dimensional memory devices.

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Abstract

本申请提供一种半导体器件、三维存储器及半导体器件制备方法，半导体器件包括衬底，多个栅极、与多个所述栅极对应的第一触点以及数个第二触点；多个所述栅极间隔设于所述衬底的表面上，且每两个相邻的所述栅极之间有间隔区，所述衬底的表面上设有位于所述间隔区的源极，每一所述栅极包括连接面，每一所述栅极的连接面上设有一个所述第一触点，所述第一触点在所述连接面的正投影呈长条状，且所述第一触点的长度延伸方向与所述栅极长度方向相同；数个所述第二触点设于所述衬底上，且位于所述间隔区内与所述源极连接，所述第二触点与所述第一触点结构相同，且所述第二触点与第一触点并列设置。

Description

半导体器件、三维存储器及半导体器件制备方法
相关申请的交叉引用
本申请基于申请号为202011186371.5、申请日为2020年10月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及半导体存储器件技术领域，特别涉及一种半导体器件、三维存储器及半导体器件制备方法。
背景技术
3D存储器是一种存储单元三维堆叠的闪存器件，相比平面型存储器在单位面积上用于更高的存储密度，现有的3D NAND存储单元架构通常为垂直沟道、水平控制栅层设计，在单位面积的晶片上可以成倍地提高集成度。
在X_tacking工艺形成的三维存储器件的中，随着阵列层数的不断提高，CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)芯片尺寸对整个芯片最终的尺寸影响越大，CMOS的小型化的要求也越高，因此越来越需要电容密度更大的电容结构。
发明内容
本申请的目的在于提供一种三维存储器及其制备方法，以实现半导体器件和三维存储器件的大密度的电容结构。
本申请提供一种半导体器件，包括衬底，多个栅极、与多个所述栅极对应的第一触点以及数个第二触点；
多个所述栅极间隔设于所述衬底的表面上，且每两个相邻的所述栅极之间有间隔区，所述衬底的表面上设有位于所述间隔区的源极，
每一所述栅极包括连接面，每一所述栅极的连接面上设有一个所述第一触点，所述第一触点在所述连接面的正投影呈长条状，且所述第一触点的长度延伸方向与所述栅极长度方向相同；
数个所述第二触点设于所述衬底上，且位于所述间隔区内与所述源极连接，所述第二触点与所述第一触点结构相同，且所述第二触点与第一触点并列设置。
本申请还提供一种三维存储器，包括所述的半导体器件和存储阵列，所述半导体器件和所述存储阵列电连接。
本申请还提供一种半导体器件的制备方法，所述方法包括，
提供衬底；
在衬底上形成多个栅极和源极，且使每两个所述栅极之间具有间隔区，每一个间隔区设有一所述源极；其中，所述栅极包括连接面，
在每一所述栅极的连接面上以及每一所述间隔区内的衬底上形成一触点，所述触点在所述衬底的正投影呈长条状，且所述触点的长度延伸方向与所述栅极长度方向相同。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的半导体器件的俯视结构示意图。
图2是本申请实施例提供的半导体器件的截面示意图。
图3是本申请提供的半导体器件的制备方法流程图。
图4-图5是本申请提供的半导体器件的各个步骤示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
现有的三维存储器包括存储阵列及外围电路。存储阵列中形成有在横向衬底上具有垂直方向串行的存储器晶体管，存储器晶体管相对于衬底时沿着垂直方向延伸。外围电路可理解为是存储器的外围器件，即可以成为半导体器件，其包括任何合适的用来促进存储器操作的数字、模拟及/或混合信号的外围电路。举例来说，外围器件可包括页缓冲器、译码器(例如，行译码器以及列译码器)、感测放大器、驱动器、充电泵、电流或电压参考或是任何电路中的主动或被动部件(例如晶体管、二极管、电阻或电容)中的一项或多项。而在X-tacking技术中，通常使用互补式金属半导体(CMOS)技术形成该半导体器件，而X-tacking技术下的半导体器件的ILD(介电质层)层比较薄。
基于X-tacking技术，本申请提供一种半导体器件和三维存储器，包括半导体器件和存储阵列，所述半导体器件和所述存储阵列电连接。请参阅图1和图2，本申请实施例中的半导体器件包括衬底10，多个栅极12、与多个所述栅极12对应的第一触点14以及数个第二触点16。
多个所述栅极12间隔设于所述衬底10的表面101上，且每两个相邻的所述栅极12之间有间隔区102，所述衬底10的表面101上设有位于所述间隔区102的源极(图未示)。
每一所述栅极12包括连接面121，每一所述栅极12的连接面121上设有一个所述第一触点14，所述第一触点14在所述连接面121的正投影呈长条状，且所述第一触点14的长度延伸方向与所述栅极12长度方向相同。
数个所述第二触点16设于所述衬底10上，且位于所述间隔区102内与所述源极(图未示)连接，所述第二触点16与所述第一触点14结构相同，且所述第二触点16与第一触点14并列设置。
如图2具体的，所述半导体器件为外围电路，为所述三维存储器提供电连接，每一个栅极12通过一个第一触点14引出实现电连接，每一个源极连接一个所述第二触点。所述衬底10上形成有ILD层(图未示)，所述ILD层覆盖所述栅极12和所述衬底10的表面，所述第一触点14和第二触点16形成于所述ILD层内。在所述栅极12的宽度方向上，每一所述第一触点14和第二触点16的正投影为矩形，即所述第一触点14和第二触点16从垂直于所述栅极长度方向看是呈矩形板体状，所述ILD层厚度较薄更便于所述第一触点14和第二触点16以板状的形式形成。在同一个单位面积内，所述第一触点14和第二触点16呈板状而非点阵式，以使所述第一触点14和第二触点16的面积增加，使其在半导体器件内提供的电容量增加。
进一步的，如图5，所述第一触点14在所述栅极12宽度方向的横截面为梯形，且该梯形的顶边A处与所述栅极12的连接面连接。具体的，结合参图1，所述栅极12宽度方向理解为X方向，所述栅极12长度方向为Y方向，多个所述栅极12在所述X方向上间隔排列，多个第一触点14在所述X方向上间隔排列。从X方向看，所述第一触点14是呈矩形板体，而沿着Y方向看，该第一触点14截面为梯形，且梯形较短的顶边与所述栅极12的连接面连接，在保证连接性能的前提下，在X方向上保证第一触点14与栅极12的接触面积，即第一触点14与栅极12的表面接触面足够大，而要保证第一触点14和第二触点16之间距离减小，所述第一触点14与栅极 12的表面边缘的距离a为50-70纳米以上，保证第一触点可以准确的与栅极表面接触，又可以保证两个触点之间的距离减小。
进一步的，位于所述间隔区102内的所述第二触点16与形成该间隔区的两个所述栅极12之间的距离b是50-70纳米，可以减小每两个触点(第一触点14和第二触点16)之间的距离，可以增加电容。所述第二触点16的结构与所述第一触点14结构相同，从X方向看，所述第二触点16是呈矩形板体，而沿着Y方向看，所述该第二触点16截面为梯形，且梯形较短的顶边与所述衬底10上的源极连接，第二触点16在所述衬底10上与源极连接的一端在X方向尺寸c减小，进而减小栅极密度，增加单位面积内第二触点的数量，进而增加电容。
本申请中，所述第一触点14和所述第二触点16是呈矩形板体，相较于多个触点设置方式，增加了触点的面，进而增加电容。
进一步的，所述半导体器件还包括金属层18，所述金属层18形成于多个所述第一触点和数个第二触点远离所述衬底的表面上，用于将第一触点14和第二触点16与存储器其它器件电连接。具体的，所述金属层18包括层叠的且通过绝缘层间隔的第一金属层和第二金属层，且所述第一金属层和第二金属层之间通过通孔连接。
下面结合前面的半导体器件对本申请提供的一种半导体器件的制备方法进行详细介绍。在其他实施例中，采用本半导体器件的制备方法获得的半导体器件也可以不同于前述实施例的半导体器件。
本申请提供半导体器件的制备方法，其特征在于，所述方法包括，
请参阅图3，步骤S1，提供衬底10；衬底10用于支撑在其上的器件结构。本实施例中，衬底10的材质为单晶硅(Si)。当然，在其他实施例中，衬底10的材料可以为元素半导体如锗(Ge)、化合物半导体如锗(SiGe)、碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs) 和/或锑化铟(InSb)、合金半导体如磷化镓砷(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)和/或磷化镓铟砷(GaInAsP)或以上各材料的组合。此外，衬底10可以是“绝缘体上半导体”晶圆。
请参阅图4，步骤S2，在衬底10上形成多个栅极12和源极(图未示)，且使每两个所述栅极12之间具有间隔区102，每一个间隔区102设有一所述源极；其中，所述栅极12包括连接面121。所述栅极12可以由多晶硅的材质为氮化硅(SixNy，如SiN)无定型硅、多晶硅、氧化铝或以上各种材料的组合。所述栅极12通过涂布以及蚀刻或者光罩方式形成。具体是先形成栅极牺牲层，栅极牺牲层会在后续工艺中会被金属替换而作为栅极。
进一步的，在衬底10上形成多个栅极12和源极的步骤还包括，在所述衬底10上形成有ILD层(图未示)，所述ILD层覆盖所述栅极12和所述源极。
请参阅图5，步骤S3，通过掩膜和蚀刻工艺，在每一所述栅极12的连接面121上形成第一触点14，所述第一触点14在所述连接面121的正投影呈长条状，且所述第一触点14的长度延伸方向与所述栅极12长度方向相同。而且所述第一触点14在所述连接面121的正投影位于所述栅极12的正投影内。所述第一触点14可以由W、Ru、Co或其他适当导电材料构成。所述第一触点14可通过在ILD层上形成通孔后填充形成。具体形成通孔的方法可以通过掩膜板结合蚀刻方法在ILD层形成，在此不做过多赘述。
本实施例还包括步骤四，通过掩膜和蚀刻工艺，在每一所述间隔区102内的衬底10上形成一第二触点16，使所述第二触点16与所述源极连接，其中，所述第二触点16与所述第一触点14结构相同，且所述第二触点16与第一触点14并列设置。所述第二触点16可以由W、Ru、Co或其他适当导电材料构成。所述第二触点16可通过在ILD层上形成通孔后填充形成。 具体形成通孔的方法可以通过掩膜板结合蚀刻方法在ILD层形成，在此不做过多赘述
需要说明的是，在形成所述第一触点14时，使所述第一触点14在所述栅极12宽度方向的横截面为梯形，且该梯形的顶边与所述栅极12连接；且在所述栅极12的宽度方向上，每一所述第一触点14和第二触点16的正投影为矩形。在其他实施例中，所述第一触点14和第二触点15是同时形成。
所述半导体器件的制备方法还包括形成金属层18，所述金属层18形成于多个所述第一触点14和数个第二触点16远离所述衬底10的表面以及在所述ILD层上，且所述金属层18上设有与所述源极对应的漏极。所述金属层可以由Cu、Al、Ru、Co、W或其他适当导电材料构成。
本申请提供的半导体器件中，所述第一触点在所述栅极上的连接面的正投影呈长条状，且所述第一触点的长度延伸方向与所述栅极长度方向相同；第二触点与第一触点结构相同，独立的所述第一触点和第二触点为而非点阵式体现，触点的单位面积增加，可以增加电容，以实现半导体器件和三维存储器件的大密度的电容结构。
以上所揭露的仅为本申请可选实施例而已，当然不能以此来限定本申请之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本申请权利要求所作的等同变化，仍属于申请所涵盖的范围。

Claims (12)

  1. 一种半导体器件，包括衬底，多个栅极、与多个所述栅极对应的第一触点以及多个第二触点；
    多个所述栅极间隔设于所述衬底的表面上，且每两个相邻的所述栅极之间有间隔区，所述间隔区的衬底中设有源极；
    每一所述栅极包括连接面，每一所述栅极的连接面上设有一个所述第一触点，所述第一触点在所述连接面的正投影呈长条状，且所述第一触点的长度延伸方向与所述栅极长度方向相同；
    多个所述第二触点设于所述间隔区内的所述衬底上，且与所述源极连接，所述第二触点与所述第一触点结构相同，且所述第二触点与第一触点并列设置；
    所述第一触点与所述第二触点远离所述衬底的一侧设有漏极。
  2. 根据权利要求1所述的半导体器件，其中，所述第一触点在所述栅极宽度方向的横截面为梯形，且该梯形的顶边与所述栅极连接。
  3. 根据权利要求2所述的半导体器件，其中，在所述栅极的宽度方向上，每一所述第一触点和第二触点的正投影为矩形。
  4. 根据权利要求2所述的半导体器件，其中，位于所述间隔区内的所述第二触点与形成该间隔区的两个所述栅极之间的距离是50-70纳米。
  5. 根据权利要求1-4任一项所述的半导体器件，其中，所述半导体器件还包括金属层，所述金属层形成于多个所述第一触点和多个第二触点远离所述衬底的表面上。
  6. 根据权利要求1-4任一项所述的半导体器件，其中，所述衬底上形成有介电质层ILD层，所述ILD覆盖所述栅极和所述衬底的表面，所述第一触点和第二触点形成于所述ILD层内。
  7. 一种三维存储器，包括如权利要求1-6任一项所述的半导体器件和 存储阵列，所述半导体器件和所述存储阵列电连接。
  8. 一种半导体器件的制备方法，所述方法包括，
    提供衬底；
    在衬底上形成多个栅极和源极，且使每两个所述栅极之间具有间隔区，每一个间隔区设有一所述源极；其中，所述栅极包括连接面，
    在每一所述栅极的连接面上以及每一所述间隔区内的衬底上形成一触点，所述触点在所述衬底的正投影呈长条状，且所述触点的长度延伸方向与所述栅极长度方向相同；
    于所述触点远离所述衬底的一侧设置漏极。
  9. 根据权利要求8所述的半导体器件制备方法，其中，所述在每一所述栅极的连接面上以及每一所述间隔区内的衬底上形成一触点的步骤包括，
    通过掩膜和蚀刻工艺，在每一所述栅极的连接面上形成第一触点，所述第一触点在所述连接面的正投影呈长条状，且所述第一触点的长度延伸方向与所述栅极长度方向相同。
  10. 根据权利要求9所述的半导体器件制备方法，其中，所述在每一所述栅极的连接面上以及每一所述间隔区内的衬底上形成一触点的步骤包括，通过掩膜和蚀刻工艺，在每一所述间隔区内的衬底上形成一第二触点，使所述第二触点与所述源极连接，其中，所述第二触点与所述第一触点结构相同，且所述第二触点与第一触点并列设置。
  11. 根据权利要求8所述的半导体器件制备方法，其中，所述在每一所述栅极的连接面上以及每一所述间隔区内的衬底上形成一触点的步骤包括，
    在每一所述栅极的连接面上形成第一触点，所述第一触点在所述连接面的正投影呈长条状，且所述第一触点的长度延伸方向与所述栅极长度方 向相同；所述在每一所述栅极的连接面上以及每一所述间隔区内的衬底上形成一触点的步骤包括，在每一所述间隔区内的衬底上形成一第二触点，使所述第二触点与所述源极连接，其中，所述第二触点与所述第一触点结构相同，且所述第二触点与第一触点并列设置。
  12. 根据权利要求10所述的半导体器件制备方法，其中，在衬底上形成多个栅极和源极的步骤还包括，在所述衬底上形成有介电质层ILD层，所述ILD覆盖所述栅极和所述源极，所述第一触点和第二触点形成于所述ILD层内。
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