WO2022088093A1 - 发光二极管基板及其制作方法、显示装置 - Google Patents

发光二极管基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022088093A1
WO2022088093A1 PCT/CN2020/125490 CN2020125490W WO2022088093A1 WO 2022088093 A1 WO2022088093 A1 WO 2022088093A1 CN 2020125490 W CN2020125490 W CN 2020125490W WO 2022088093 A1 WO2022088093 A1 WO 2022088093A1
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Prior art keywords
substrate
light
emitting diode
layer
intermediate carrier
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PCT/CN2020/125490
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English (en)
French (fr)
Inventor
李海旭
张笑
王飞
王明星
李树磊
董学
袁广才
曹占锋
谷新
王珂
曲峰
梁轩
闫俊伟
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002595.8A priority Critical patent/CN114698401A/zh
Priority to PCT/CN2020/125490 priority patent/WO2022088093A1/zh
Priority to US17/427,628 priority patent/US20220352000A1/en
Priority to EP20959255.9A priority patent/EP4174963A4/en
Priority to TW112127532A priority patent/TW202411975A/zh
Priority to TW110136419A priority patent/TWI813030B/zh
Publication of WO2022088093A1 publication Critical patent/WO2022088093A1/zh

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
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    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • Embodiments of the present disclosure relate to a light emitting diode substrate, a method for fabricating the same, and a display device.
  • a light emitting diode is a semiconductor device that emits light through the recombination of electrons and holes, and is usually made of compounds of gallium (Ga), arsenic (As), phosphorus (P), nitrogen (N), and indium (In).
  • Light-emitting diodes can efficiently convert electrical energy into light energy, and can emit monochromatic light of different colors. For example, gallium arsenide diodes can emit red light, gallium phosphide diodes can emit green light, silicon carbide diodes can emit yellow light, and gallium nitride diodes can emit blue light.
  • LED display technology With the continuous development of display technology, light-emitting diode display technology has gradually become one of the research hotspots as a new type of display technology.
  • the light-emitting diode display technology utilizes an array of light-emitting diodes (Light Emitting Diode, LED) for display.
  • LED display technology Compared with other display technologies, LED display technology has the advantages of high luminous intensity, fast response speed, low power consumption, low voltage demand, thin and light equipment, long service life, strong impact resistance, and strong anti-interference ability.
  • micro light-emitting diodes with smaller dimensions can better enable high-resolution products, such as 4K or even 8K resolution smartphones or virtual display screens.
  • OLED organic light emitting diode
  • micro-LEDs the response time of organic light emitting diode (OLED) display panels has been reduced to the microsecond level, it has a very good response time rating.
  • the response time of micro light-emitting diodes (Micro-LEDs) is further reduced to the nanosecond level, which is 1,000 times faster, and therefore more suitable for making virtual display screens.
  • Embodiments of the present disclosure provide a light-emitting diode substrate, a manufacturing method thereof, and a display device.
  • the manufacturing method of the light-emitting diode substrate includes: forming epitaxial layer groups of M light-emitting diode chips on a substrate; transferring the N epitaxial layer groups on the N substrates to a medium carrier substrate; The epitaxial layer groups are densely arranged on the intermediate carrier substrate; and at least some of the light emitting diode chips among the N*M light emitting diode chips corresponding to the N epitaxial layer groups on the intermediate carrier substrate are transferred to the driving substrate.
  • the area of the medium carrier substrate is greater than or equal to the sum of the areas of N substrates, M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 2. Therefore, the method for fabricating the light-emitting diode substrate firstly transfers the N epitaxial layer groups on the N substrates to the medium carrier substrate with a larger size, and these epitaxial layer groups are densely arranged on the medium carrier substrate, and then Then, the light-emitting diode chips on the mid-carrier substrate are transferred to the driving substrate, so that more light-emitting diode chips can be taken at one time, and even the light-emitting diode chips required by the driving substrate can be taken at one time, which can greatly improve the taking efficiency and transfer efficiency. .
  • At least one embodiment of the present disclosure further provides a method for fabricating a light-emitting diode substrate, which includes: forming an epitaxial layer group of M light-emitting diode chips on a substrate; forming N epitaxial layers on the substrate transferring the group to a medium carrier substrate, and the N epitaxial layer groups on the N substrates are densely arranged on the medium carrier substrate; and corresponding the N epitaxial layer groups on the medium carrier substrate At least some of the light-emitting diode chips among the N*M light-emitting diode chips are transferred to the driving substrate, the area of the mid-carrier substrate is greater than or equal to the sum of the areas of the N substrates, and M is greater than or equal to 2 A positive integer, N is a positive integer greater than or equal to 2.
  • the distance between two adjacent epitaxial layer groups is the same as the distance between two adjacent light-emitting diode chips. The distance between them is roughly equal.
  • the shape of the intermediate carrier substrate is substantially the same as the shape of the driving substrate, and the area of the intermediate carrier substrate is approximately the same as that of the driving substrate. equal.
  • the driving substrate includes a base substrate and a plurality of driving circuits located on the base substrate, and each of the driving circuits includes a pad and is configured
  • the manufacturing method further includes: using a bonding process to connect the light-emitting diode chip transferred to the driving substrate with the corresponding driver The pads of the circuit are bound.
  • a bonding process is used to bond the light-emitting diode chip transferred to the driving substrate with the corresponding pad of the driving circuit
  • the method includes: thermally reflowing the driving substrate to bond the light emitting diode chip and the pad together.
  • the driving substrate further includes a plurality of conductive bumps located on a side of the spacer away from the base substrate, and each spacer The orthographic projection on the base substrate overlaps with the orthographic projection of at least one of the conductive bumps on the base substrate, and the manufacturing method further includes: placing the N pieces of the conductive bumps on the intermediate carrier substrate.
  • an organic insulating adhesive is coated on the driving substrate; Binding the light-emitting diode chips on the driving substrate to the corresponding pads of the driving circuit includes: performing thermal reflow on the driving substrate, evaporating the solvent in the organic insulating adhesive, to remove the The light emitting diode chip is bonded with the spacer.
  • transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate includes: on the intermediate carrier substrate forming a first adhesive layer; and transferring the N epitaxial layer groups on the N substrates to a side of the first adhesive layer away from the mid-carrier substrate.
  • forming the first adhesive layer on the intermediate carrier substrate includes: coating a first adhesive material layer on the intermediate carrier substrate; and The first adhesive material layer is patterned to form a plurality of through holes penetrating the first adhesive material layer in the first adhesive material layer.
  • the first adhesive material layer including the plurality of through holes is The adhesive material layer is the first adhesive layer, and the size of the orthographic projection of each of the through holes on the intermediate carrier substrate is smaller than the size of the orthographic projection of the light emitting diode chip on the intermediate carrier substrate.
  • the material of the first adhesive layer includes an ultraviolet light viscosity reducing adhesive or a laser dissociating adhesive.
  • transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate further includes: transferring the N number of the epitaxial layer groups on the N substrates to the intermediate carrier substrate.
  • a plurality of light-shielding structures are formed on the intermediate carrier substrate, and the orthographic projections of each of the light-shielding structures on the intermediate carrier substrate are located in two adjacent light-emitting diode chips in the intermediate carrier substrate. between orthographic projections on the carrier substrate.
  • the fabricating method further includes: forming the epitaxial layer on the substrate. forming M electrode structures on a side of the group away from the substrate; and dividing the epitaxial layer group and the M electrode structures to form M light emitting diode chips.
  • dividing the epitaxial layer group and the M number of the electrode structures to form the M number of the light-emitting diode chips includes: using an etching process to separate the The epitaxial layer group and the M number of the electrode structures are divided to form the M number of the light emitting diode chips.
  • transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate includes: forming M all the epitaxial layer groups on the intermediate carrier substrate. transferring the substrate of the light-emitting diode chips to a transfer substrate; peeling the substrate from the transfer substrate; and transferring the N*M light-emitting diode chips on the N transfer substrates to the transfer substrate On the intermediate carrier substrate, the area of the transfer substrate is approximately equal to the area of the substrate.
  • transferring the substrate on which the M light-emitting diode chips are formed onto the transfer substrate includes: coating the transfer substrate on the transfer substrate a second adhesive layer; and transferring the substrate on which the M light-emitting diode chips are formed to a side of the second adhesive layer away from the transfer substrate.
  • the material of the second adhesive layer includes an ultraviolet viscosity reducing adhesive or a laser dissociating adhesive, and the N*M adhesives on the N transfer substrates are combined. After each of the light-emitting diode chips is transferred to the intermediate carrier substrate, light is irradiated to the transfer substrate to reduce the viscosity of the second adhesive layer, so as to remove the transfer substrate.
  • the mid-carrier substrate includes a plurality of first support structures, and each of the first support structures has a direction perpendicular to the mid-carrier substrate.
  • the size is larger than the size of the light-emitting diode chips in a direction perpendicular to the mid-carrier substrate, and transferring the N*M light-emitting diode chips on the N transfer substrates to the mid-carrier substrate includes: The N number of the transfer substrates are aligned with the intermediate carrier substrate in sequence, so that a plurality of the first support structures are located between the two adjacent light emitting diode chips on the transfer substrate.
  • each of the first support structures is a columnar structure
  • the shape of the orthographic projection of each of the first support structures on the intermediate carrier substrate includes a rectangle. , one of T-shaped and round.
  • each of the first support structures is a columnar structure, and the orthographic projections of the first support structures on the intermediate carrier substrate are connected to each other to form grid.
  • the method for fabricating a light-emitting diode substrate includes: aligning the intermediate carrier substrate with the driving substrate, so that the plurality of first support structures are located between the intermediate carrier substrate and the driving substrate; a first mask plate is aligned with the intermediate carrier substrate, the first mask plate includes a plurality of openings, and the plurality of openings correspond to a plurality of the light-emitting diode chips to be transferred; and the first mask plate passes through the first mask The membrane plate irradiates light to the intermediate carrier substrate, so as to transfer a plurality of the light emitting diode chips to be transferred onto the driving substrate.
  • the first mask plate includes a light absorbing material, and the light absorption rate of the light absorbing material is greater than 60%.
  • the first mask includes: a first transparent substrate; and a first light absorption pattern layer, which is located on the first transparent substrate and includes For the plurality of openings, the first light absorbing pattern layer is made of the light absorbing material, and the light absorption rate of the light absorbing material is greater than 60%.
  • the first mask further includes: a first magnetic attraction structure located between the first transparent substrate and the first light absorption pattern layer and the orthographic projection of the first magnetic attraction structure on the first transparent substrate and the orthographic projection of the plurality of openings on the first transparent substrate are arranged at intervals.
  • the driving substrate includes a plurality of first receiving structures
  • aligning the intermediate carrier substrate with the driving substrate includes: aligning the intermediate carrier substrate with the driving substrate.
  • the plurality of first support structures on the substrate are inserted into the plurality of first receiving structures on the driving substrate, the plurality of first support structures and the plurality of first receiving structures are arranged in a one-to-one correspondence, and each of the The dimension of the first receiving structure perpendicular to the driving substrate is smaller than the dimension of the light emitting diode chip perpendicular to the driving substrate.
  • forming the epitaxial layer group of M light-emitting diode chips on the substrate includes: forming a semiconductor of a first conductivity type on the substrate forming a light emitting layer on a side of the first conductive type semiconductor layer away from the substrate; and forming a second conductive type semiconductor layer on a side of the light emitting layer away from the first conductive type semiconductor layer.
  • forming the M number of the electrode structures on the side of the epitaxial layer group away from the substrate includes: patterning the epitaxial layer group to expose the Part of the first conductive type semiconductor layer to form M exposed parts; forming M first electrodes on the side of the M exposed parts away from the substrate; on the second conductive type semiconductor layer away from the substrate M second electrodes are formed on one side of the M second electrodes; a passivation layer is formed on the side of the M first electrodes and the M second electrodes away from the substrate; the passivation layer is patterned to form on the passivation layer a first via hole corresponding to the first electrode and a second via hole corresponding to the second electrode in the passivation layer; a first electrode pad and a second via hole are formed on the side of the passivation layer away from the substrate Two electrode pads, the first electrode pad is connected to the first electrode through the first via hole, the second electrode pad is connected to the
  • forming the epitaxial layer group of M light-emitting diode chips on the substrate further includes: forming the light-emitting layer and the second conductive layer on the substrate.
  • An electron blocking layer is formed between the type semiconductor layers.
  • the fabricating method before forming the first conductive type semiconductor layer on the substrate, the fabricating method further includes: performing a high temperature treatment on the substrate , and cleaning the surface of the substrate; and forming a buffer layer on the substrate.
  • the first conductive type semiconductor layer is an n-type semiconductor layer
  • the second conductive type semiconductor layer is a p-type semiconductor layer
  • the first conductive type semiconductor layer is n-type gallium nitride
  • the second conductive type semiconductor layer is p-type gallium nitride
  • the The buffer layer is aluminum nitride.
  • the method for fabricating a light-emitting diode substrate includes: providing a selection substrate, the selection substrate includes a plurality of selection structures; aligning the selection substrate with the intermediate carrier substrate, a plurality of the selection structures and a plurality of to-be-transferred structures contact with the light-emitting diode chip; align the second mask plate with the intermediate carrier substrate, the second mask plate includes a plurality of openings, and the plurality of openings correspond to the plurality of the selection structures; the second mask plate irradiates light to the intermediate carrier substrate, so as to transfer a plurality of the light emitting diode chips to be transferred to a plurality of the selection structures on the selection substrate; aligning the driving substrate; bonding a plurality of the light
  • the second mask includes a light absorbing material, and the light absorption rate of the light absorbing material is greater than 60%.
  • the second mask includes: a second transparent substrate; and a second light absorption pattern layer, which is located on the second transparent substrate and includes The plurality of openings and the second light absorption pattern layer are made of the light absorption material, and the light absorption rate of the light absorption material is greater than 60%.
  • the second mask further includes: a second magnetic attraction structure located between the second transparent substrate and the second light absorption pattern layer and the orthographic projection of the second magnetic attraction structure on the second transparent substrate and the orthographic projection of the plurality of openings on the second transparent substrate are arranged at intervals.
  • each of the selection structures includes a support portion and a pyrolysis portion located on the support portion away from the mid-carrier substrate.
  • the selection substrate and the intermediate carrier substrate are aligned, and a plurality of the selection structures are in contact with a plurality of the light-emitting diode chips to be transferred
  • the method includes: aligning the selection substrate with the intermediate carrier substrate in a vacuum environment; applying pressure to the selection substrate to make the pyrolysis part in the selection structure adhere to the corresponding light emitting diode chip.
  • the method for fabricating a light-emitting diode substrate provided by an embodiment of the present disclosure, light is irradiated to the mid-carrier substrate through the second mask, so as to transfer a plurality of the light-emitting diode chips to be transferred to the
  • the multiple selection structures on the selection substrate include: after irradiating light to the intermediate carrier substrate through the second mask, passing an inert gas between the selection substrate and the intermediate carrier substrate .
  • removing a plurality of the selected structures includes: heating in a vacuum environment to melt the pyrolysis parts, so as to remove the plurality of selected structures Structural removal.
  • the material of each of the selected structures includes UV adhesive or laser dissociative adhesive
  • removing a plurality of the selected structures includes: adding to the selected structures The substrate irradiates light to remove a plurality of the selected structures.
  • each of the selected structures includes an elastic material.
  • the shape of the cross-section of each of the selection structures taken perpendicular to a plane of the selection substrate includes a trapezoid.
  • the driving substrate includes a plurality of second support structures, and the size of each of the second support structures in a direction perpendicular to the driving substrate is larger than A dimension of the light emitting diode chip in a direction perpendicular to the driving substrate.
  • Transferring the diode chips to the driving substrate includes: aligning the intermediate carrier substrate with the driving substrate, and inserting a plurality of the second support structures into two adjacent light emitting diode chips on the intermediate carrier substrate between; aligning a third mask plate with the intermediate carrier substrate, the third mask plate including a plurality of openings corresponding to a plurality of the light-emitting diode chips to be transferred; The third mask plate irradiates light to the intermediate carrier substrate, so as to transfer a plurality of the light emitting diode chips to be transferred onto the driving substrate.
  • transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate includes: transferring the N substrates The N epitaxial layer groups on the bottom are sequentially transferred to the intermediate carrier substrate; M electrode structures are formed on the side of the N epitaxial layer groups away from the intermediate carrier substrate; The N epitaxial layer groups are divided to form M light emitting diode chips together with the M electrode structures.
  • the N epitaxial layer groups on the intermediate carrier substrate are divided to form M all the electrode structure groups together with the M electrode structure groups.
  • the light-emitting diode chip includes: using an etching process to divide the N epitaxial layer groups on the mid-carrier substrate to form M light-emitting diode chips together with the M electrode structure groups.
  • forming the epitaxial layer group of M light-emitting diode chips on the substrate includes: forming a semiconductor of a first conductivity type on the substrate forming a light-emitting layer on a side of the first conductive type semiconductor layer away from the substrate; and forming a second conductive layer on a side of the light-emitting layer away from the first conductive type semiconductor layer and away from the substrate type of semiconductor layer.
  • the fabricating method before forming the first conductive type semiconductor layer on the substrate, the fabricating method further includes: performing a high temperature treatment on the substrate , and cleaning the surface of the substrate; and forming a buffer layer on the substrate.
  • the first conductive type semiconductor layer is an n-type semiconductor layer
  • the second conductive type semiconductor layer is a p-type semiconductor layer
  • the first conductive type semiconductor layer is n-type gallium nitride
  • the second conductive type semiconductor layer is p-type gallium nitride
  • the The buffer layer is aluminum nitride.
  • each of the electrode structures includes a first electrode and J second electrodes, which are formed on a side of the epitaxial layer group away from the substrate.
  • the M number of the electrode structures include: patterning the epitaxial group layer to expose part of the first conductive type semiconductor layer to form M exposed portions, and dividing the second conductive type semiconductor layer into M*Jth semiconductor layers Two conductive type semiconductor blocks; M*J second electrodes are formed on the side of the M*J second conductive type semiconductor blocks away from the intermediate carrier substrate; M*J second electrodes are formed on the side away from the intermediate carrier substrate A passivation layer is formed on one side; the passivation layer is patterned to form M first via holes corresponding to the M exposed portions and M corresponding to the M*J second electrodes in the passivation layer *J second via holes; M first electrodes are formed on the side of the M exposed parts away from the substrate through the M first via holes; and the passivation layer is away from the mid-carrier substrate A first electrode pad and a second electrode pad are formed on one side of the electrode, the first electrode pad is connected to the first electrode through the first via hole, and the second electrode pad is connected to the first electrode through the second via hole.
  • forming the epitaxial layer group of M light-emitting diode chips on the substrate further includes: forming the light-emitting layer and the second conductive layer on the substrate.
  • An electron blocking layer is formed between the type semiconductor layers.
  • forming M pieces of the epitaxial layer group of the light-emitting diode chips on a substrate includes: forming M pieces of the epitaxial layer group on the circular substrate the epitaxial layer group of the light-emitting diode chip; and cutting the circular substrate into a square or hexagonal substrate along the edge of the epitaxial layer group, where the epitaxial layer group is located
  • the shape of the orthographic projection on the substrate is a square or a hexagon.
  • transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate includes: transferring N square or six
  • the N epitaxial layer groups on the polygonal substrate are densely arranged on the intermediate carrier substrate.
  • forming the M epitaxial layer groups of the light-emitting diode chips on a substrate includes: cutting the circular substrate into squares or hexagonal said substrates; splicing together N square or hexagonal said substrates to form a combination of N said substrates; forming M* on the combination of N said substrates The N epitaxial layers of the light-emitting diode chip.
  • transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate includes: placing the N substrates on the N substrates.
  • the epitaxial layers of the M*N light-emitting diode chips formed on the bottom combination are transferred to the mid-carrier substrate.
  • each of the spacers includes at least two sub-spacers, and each of the sub-spacers includes a groove, and the groove is configured to receive a corresponding electrode pads of the light-emitting diode chip.
  • At least one embodiment of the present disclosure further provides a light-emitting diode substrate, which is fabricated by using any one of the fabrication methods described above.
  • the driving substrate includes a plurality of receiving structures, and the size of each of the first receiving structures perpendicular to the driving substrate is smaller than that of the light-emitting diode chip perpendicular to the driving substrate. size on the drive substrate.
  • the light emitting diode substrate further includes a plurality of support structures located between the adjacent light emitting diode chips, and each of the support structures is perpendicular to the driving substrate.
  • the size is larger than the size of the light emitting diode chip in a direction perpendicular to the driving substrate.
  • the driving substrate includes a base substrate and a plurality of driving circuits located on the base substrate, each of the driving circuits includes a pad, and is configured to drive and
  • the light-emitting diode chips electrically connected to the spacers emit light each spacer includes at least two sub spacers, each of the sub spacers includes a groove, and the groove is configured to receive the corresponding light-emitting diode Electrode pads of the chip.
  • At least one embodiment of the present disclosure further provides a display device including the light-emitting diode substrate described in any one of the above.
  • FIG. 1 is a schematic diagram of a method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure
  • 2-4 are schematic diagrams of steps of a method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure
  • 5A-5C are schematic diagrams of steps of a binding process according to an embodiment of the present disclosure.
  • 6A and 6B are schematic diagrams of steps of a method for manufacturing a first adhesive layer according to an embodiment of the present disclosure
  • 6C is a schematic diagram of transferring a light-emitting diode chip on a mid-carrier substrate to a driving substrate according to an embodiment of the present disclosure
  • FIGS. 7-14 are schematic diagrams of steps of another method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure.
  • 15 is a schematic diagram of a mid-load substrate according to an embodiment of the disclosure.
  • FIG. 16 is a schematic diagram of a first mask according to an embodiment of the disclosure.
  • FIG. 17 is a schematic diagram of a spacer on a drive substrate according to an embodiment of the present disclosure.
  • 18A-18C are schematic plan views of a first support structure according to an embodiment of the present disclosure.
  • 18D is a schematic plan view of another first support structure provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of aligning a middle carrier substrate and a driving substrate according to an embodiment of the present disclosure
  • 20A-20D are schematic diagrams of steps of a method for fabricating a first support structure according to an embodiment of the present disclosure
  • 21A-21D are schematic diagrams of steps of another method for fabricating a first support structure according to an embodiment of the present disclosure.
  • 22-34 are schematic diagrams of steps of a method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure
  • 35 is a schematic diagram of a selection structure provided by an embodiment of the present disclosure.
  • 36A-36C are schematic diagrams of steps of a method for fabricating a selection structure according to an embodiment of the present disclosure
  • 37A-37D are schematic diagrams of steps of another method for fabricating a selection structure provided by an embodiment of the present disclosure.
  • 38-43 are schematic diagrams of steps of another method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure.
  • 45-50 are schematic diagrams of steps of another method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure.
  • 51A-51C are schematic diagrams of a method for transferring N epitaxial layer groups on N substrates to a medium carrier substrate according to an embodiment of the present disclosure
  • 52A-52C are schematic diagrams of another method for transferring N epitaxial layer groups on N substrates to a medium carrier substrate according to an embodiment of the present disclosure
  • FIG. 53 is a schematic diagram of a light-emitting diode substrate according to an embodiment of the disclosure.
  • FIG. 54 is a schematic diagram of another light-emitting diode substrate provided by an embodiment of the disclosure.
  • 55 is a schematic diagram of another light-emitting diode substrate provided by an embodiment of the disclosure.
  • FIG. 56 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • a common manufacturing method of a light emitting diode (LED) substrate includes: firstly fabricating a light emitting diode chip on a substrate; and then transferring the light emitting diode chip on the substrate to a driving substrate by a mass transfer technology.
  • a mass transfer technology since the size of the substrate is small and the size of the driving substrate is large, it is necessary to sequentially transfer the light emitting diode chips on a plurality of substrates to the driving substrate, resulting in low transfer efficiency.
  • Embodiments of the present disclosure provide a light emitting diode substrate and a manufacturing method thereof.
  • the manufacturing method of the light-emitting diode substrate includes: forming epitaxial layer groups of M light-emitting diode chips on a substrate; transferring the N epitaxial layer groups on the N substrates to a medium carrier substrate; The epitaxial layer groups are densely arranged on the intermediate carrier substrate; and at least some of the light emitting diode chips among the N*M light emitting diode chips corresponding to the N epitaxial layer groups on the intermediate carrier substrate are transferred to the driving substrate.
  • the area of the medium carrier substrate is greater than or equal to the sum of the areas of N substrates, M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 2. Therefore, the method for fabricating the light-emitting diode substrate firstly transfers the N epitaxial layer groups on the N substrates to the medium carrier substrate with a larger size, and these epitaxial layer groups are densely arranged on the medium carrier substrate, and then Then, the light-emitting diode chips on the mid-carrier substrate are transferred to the driving substrate, so that more light-emitting diode chips can be taken at one time, and even the light-emitting diode chips required by the driving substrate can be taken at one time, which can greatly improve the taking efficiency and transfer efficiency. .
  • FIG. 1 is a schematic diagram of a method for fabricating a light-emitting diode substrate according to an embodiment of the disclosure.
  • 2-4 are schematic diagrams of steps of a method for fabricating a light-emitting diode substrate according to an embodiment of the disclosure.
  • the manufacturing method of the light-emitting diode substrate includes the following steps S101-S103.
  • Step S101 forming M epitaxial layer groups of light-emitting diode chips on the substrate, where M is a positive integer greater than or equal to 2.
  • FIG. 2 shows a substrate formed by a manufacturing method provided by an embodiment of the present disclosure and an epitaxial group layer on the substrate; as shown in FIG. 2 , an epitaxial layer group 120 is formed on the substrate 110 .
  • the above-mentioned epitaxial layer group may include sequentially grown epitaxial layers such as a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer, and these epitaxial layers may constitute the above-mentioned epitaxial layer group 120 of the M light-emitting diode chips.
  • M may be a positive integer greater than 1000, or a positive integer greater than 10000.
  • Step S102 Transfer the N epitaxial layer groups on the N substrates to the intermediate carrier substrate, where the N epitaxial layer groups on the N substrates are densely arranged on the intermediate carrier substrate, and N is a positive integer greater than or equal to 2.
  • FIG. 3A shows a schematic plan view of an intermediate carrier substrate and an epitaxial layer group on the intermediate carrier substrate formed by a manufacturing method provided by an embodiment of the present disclosure
  • a schematic cross-sectional view of the intermediate carrier substrate and the epitaxial layer group on the intermediate carrier substrate as shown in FIGS. 3A and 3B , the 6 epitaxial layer groups 120 on the 6 substrates are transferred to the intermediate carrier 210, and the 6 epitaxial layers The groups 120 are densely arranged on the intermediate carrier substrate 210 .
  • FIG. 3 only shows 6 substrates, but the specific value of N in the embodiment of the present disclosure includes but is not limited to this.
  • the above-mentioned “dense arrangement” means that the distance between two adjacent epitaxial layer groups is substantially equal to the distance between two adjacent light emitting diode chips formed after the epitaxial layer group is divided.
  • the above-mentioned “transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate” includes the case of transferring the N epitaxial layer groups on the N substrates that have not been divided to the intermediate carrier substrate. It includes the case of transferring the divided N epitaxial layer groups on the N substrates (the divided N epitaxial layer groups may be N*M light emitting diode chips) to the intermediate carrier substrate.
  • Step S103 Transfer at least some of the light-emitting diode chips among the N*M light-emitting diode chips corresponding to the N epitaxial layer groups on the intermediate carrier substrate to the driving substrate, and the area of the intermediate carrier substrate is greater than or equal to the sum of the areas of the N substrates .
  • the light emitting diode chips 180 among the N*M light emitting diode chips 180 corresponding to the N epitaxial layer groups 120 on the intermediate carrier substrate 210 are transferred to the driving substrate 510 .
  • the epitaxial layer groups on the N substrates can be divided into different numbers of light-emitting diode chips, that is, different
  • M is used here only to explain and illustrate the present disclosure more clearly.
  • the specific value of the above N can be 3; the epitaxial layer group on the first substrate can be divided into M1 light-emitting diode chips, the epitaxial layer group on the second substrate can be divided into M2 light-emitting diode chips, the first The epitaxial layer group on the three substrates can be divided into M3 light-emitting diode chips.
  • the above N*M may be M1+M2+M3.
  • the method for fabricating the light emitting diode substrate firstly transfers the N epitaxial layer groups on the N substrates to a medium carrier substrate with a larger size, and transfers these epitaxial layer groups to a medium carrier substrate with a larger size. Densely arranged on the intermediate carrier substrate; then, at least part of the light emitting diode chips on the intermediate carrier substrate are transferred to the driving substrate. Since the N epitaxial layer groups on the N substrates are densely arranged on the intermediate carrier substrate, at least some of the light emitting diode chips among the N*M light emitting diode chips corresponding to the N epitaxial layer groups on the intermediate carrier substrate are transferred.
  • the light-emitting diode chips on the intermediate carrier substrate are evenly distributed, so that more light-emitting diode chips (greater than the number of light-emitting diode chips that can be taken by one substrate) can be used at one time, even at one time.
  • the LED chips of the same color required by the driving substrate can be selectively used, that is, the LED chips of the same color on the driving substrate can be completed by only one transfer process. Therefore, the manufacturing method of the light-emitting diode substrate can greatly improve the taking efficiency and the transfer efficiency.
  • the light emitting diode substrate provided by the embodiments of the present disclosure can be used as a display substrate for direct display, and also as a backlight plate for providing a backlight source.
  • the display substrate provided by the embodiment of the present disclosure is used as a backlight plate, the above-mentioned substrate may not be peeled off, thereby saving process steps and reducing costs.
  • the light-emitting diode substrate is used as a backlight
  • the light-emitting diode chips in the light-emitting diode substrate may be light-emitting diode chips that emit light of the same color.
  • the distance D1 between two adjacent epitaxial layer groups 120 is substantially equal to the distance D2 between two adjacent light emitting diode chips 180 .
  • the N epitaxial layer groups on the intermediate carrier substrate can be arranged in an array.
  • the outline of one epitaxial layer group 120 can be roughly rectangular, and the N epitaxial layer groups 120 on the mid-carrier substrate can be arranged in an array to form a larger rectangle.
  • the shape of the intermediate carrier substrate 210 is substantially the same as the shape of the driving substrate 510 , and the area of the intermediate carrier substrate 210 and the driving substrate 510 are substantially equal.
  • the manufacturing method of the light-emitting diode substrate can transfer the light-emitting diode chips of the same color required by the driving substrate from the carrier substrate to the driving substrate at one time, thereby greatly improving the efficiency of taking and transferring.
  • the first color emitting diode chip can be placed first.
  • the mid-carrier substrate 210 and the driving substrate 510 are aligned, and then a plurality of first-color LED chips (eg, red light-emitting diode chips) on the mid-carrier substrate 210 can be transferred to the driving substrate 510 corresponding to a plurality of first colors at one time on a plurality of driving circuits of the light-emitting diode chips; then, align the mid-carrier substrate 210 carrying the second-color light-emitting diode chips (eg, green light-emitting diode chips) with the driving substrate 510, and then the mid-carrier substrate 210 can be mounted at one time
  • the plurality of second-color LED chips on the driving substrate 510 are transferred to a plurality of driving circuits corresponding to the plurality of second-color LED chips; finally, the third-color LED chips (for example, blue LED chips ) of the middle carrier substrate 210 and the driving substrate 510 are aligned, and then a plurality of third-color light emitting diode chips
  • the manufacturing method of the light-emitting diode substrate can transfer light-emitting diode chips of one color to the driving substrate through one transfer process, and all the light-emitting diode chips can be transferred to the driving substrate through three transfer processes in total, so that the Greatly improve access efficiency and transfer efficiency.
  • the drive substrate 510 includes a base substrate 511 and a plurality of drive circuits 514 on the base substrate 511, each drive circuit 514 includes a pad 5142; each drive circuit 514 is configured to drive The light emitting diode chip 180 electrically connected to the pad 5142 emits light.
  • the manufacturing method of the light-emitting diode substrate further includes: using a bonding process to bond the light-emitting diode chips 180 transferred onto the driving substrate 510 to the corresponding pads 5142 of the driving circuit 514 .
  • the driving substrate can drive the light emitting diode chip to emit light or display.
  • the number of the driving circuits 514 on the driving substrate 510 is approximately the same as the number of the light-emitting diode chips 180 on the intermediate carrier substrate 210 ;
  • the positions of the light-emitting diode chips 180 are arranged in a one-to-one correspondence.
  • any number of light emitting diode chips that need to be transferred on the intermediate substrate can be transferred to the driving substrate at one time.
  • the above-mentioned transferring the N epitaxial layer groups on the N substrates to the intermediate carrier substrate includes: forming the first adhesive layer 220 on the intermediate carrier substrate 210 ; and transferring the N substrates
  • the N epitaxial layer groups 120 on the 110 are transferred to the side of the first adhesive layer 220 away from the intermediate carrier substrate 210 . Therefore, the light emitting diode substrate can simply dissociate the first adhesive layer 220 or reduce the viscosity of the first adhesive layer 220 to transfer the light emitting diode chips 180 to be transferred to the driving substrate 510, thereby improving the transfer efficiency.
  • the material of the first adhesive layer 220 includes UV adhesive or laser dissociative adhesive; when the first adhesive layer 220 is an UV adhesive, it can be reduced by irradiating ultraviolet light to a part of the mid-load substrate 210 The viscosity of the corresponding area of the first adhesive layer 220 causes the light-emitting diode chips 180 in this area to fall off and transfer to the driving substrate; when the first adhesive layer 220 is a laser release adhesive, it can pass the part of the intermediate carrier substrate 210 The area corresponding to the first adhesive layer 220 is dissociated by irradiating the area with laser light, so that the light emitting diode chip 180 in this area is peeled off and transferred to the driving substrate.
  • UV adhesive or laser dissociative adhesive when the first adhesive layer 220 is an UV adhesive, it can be reduced by irradiating ultraviolet light to a part of the mid-load substrate 210
  • the viscosity of the corresponding area of the first adhesive layer 220 causes the light-emitting diode chips 180 in
  • the intermediate carrier substrate when transferring at least some of the light-emitting diode chips among the N*M light-emitting diode chips corresponding to the N epitaxial layer groups on the intermediate carrier substrate to the driving substrate, the intermediate carrier substrate can be placed on the driving substrate according to the direction of gravity.
  • the intermediate carrier substrate and the driving substrate are arranged in sequence along the direction of gravity, so that the light-emitting diode chips that need to be transferred on the intermediate carrier substrate can be transferred to the driving substrate by using gravity with the above-mentioned UV adhesive or laser dissociating adhesive. .
  • the first adhesive layer includes but is not limited to the above-mentioned ultraviolet light viscosity reducing adhesive or laser dissociation adhesive, and the first adhesive layer can also be a pyrolytic adhesive;
  • the region corresponding to the first adhesive layer is dissociated by heating, so that the light emitting diode chip in this region is peeled off and transferred to the driving substrate.
  • the size of the aforementioned substrate 110 is greater than or equal to 2 inches. That is to say, the above-mentioned substrate is a single crystalline substrate or wafer, rather than a large-sized light-emitting diode chip having a plurality of sub-light-emitting structures.
  • the aforementioned substrate may be a sapphire substrate.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned substrates, and the above-mentioned substrates may also be other suitable substrates such as silicon carbide substrates.
  • the driving substrate 510 further includes a plurality of conductive bumps 518 located on the side of the spacer 5142 away from the base substrate 511 , and the orthographic projection of each spacer 5142 on the base substrate 511 is related to at least one conductive bump The orthographic projections of 518 on the base substrate 511 are overlapped, and the manufacturing method of the light-emitting diode substrate further includes: at least part of the N*M light-emitting diode chips 180 corresponding to the N epitaxial layer groups 120 on the intermediate carrier substrate 210 emit light.
  • an organic insulating adhesive material 560 is coated on the driving substrate 510; the light emitting diode chip 180 transferred to the driving substrate 510 and the corresponding spacer 5142 of the driving circuit 514 are bonded by a bonding process
  • the bonding includes: as shown in FIGS. 5B-5C , thermally reflowing the driving substrate 510 and evaporating the solvent in the organic insulating adhesive 560 to bond the LED chip 180 and the spacer 5142 together.
  • the plurality of conductive bumps 518 shown in FIGS. 5A-5C covers the entire driving substrate 510, embodiments of the present disclosure include, but are not limited to, the conductive bumps 518 may also be provided only on the pads 5142 above. In addition, the plurality of conductive bumps are insulated from each other.
  • the material of the conductive bumps can be metal, alloy or other conductive materials.
  • the material of the conductive bump can be any one of aluminum, silver, molybdenum, copper, and gold, or an alloy composed of at least two of them.
  • the embodiments of the present disclosure include, but are not limited to, the conductive bumps, and other conductive materials may also be used.
  • the size of the orthographic projection of the conductive bump on the driving substrate is smaller than the size of the orthographic projection of the pad on the driving substrate.
  • the base substrate may be a rigid substrate or a flexible substrate, which is not limited in this embodiment of the present disclosure.
  • the material of the base substrate may be glass, quartz or plastic.
  • the shape of the cross-section of the conductive protrusions perpendicular to the plane of the driving substrate includes: arcuate, single-pointed cone, trapezoid, boss-shaped, or multi-pointed cone.
  • the above-mentioned conductive bumps can be fabricated by a nanoimprint process.
  • the nano-imprint manufacturing method of the conductive bumps may include: forming a conductive layer (for example, forming a metal layer by a deposition process); coating an imprint glue material on the conductive layer; imprinting the above-mentioned embossing using a stencil having a recessed structure Imprinting adhesive material; curing imprinting adhesive material by ultraviolet light irradiation; demolding; using dry etching process to replicate the structure on the template formed by imprinting adhesive material into the conductive layer.
  • the conductive bumps provided by the embodiments of the present disclosure may also be fabricated by other methods, such as exposure etching, wet etching, electrochemical deposition, and the like.
  • a conductive anti-oxidation layer can be covered after the conductive bumps are prepared, but the anti-oxidation layer between the conductive bumps and the conductive bumps needs to be removed to ensure electrical conductivity.
  • the protrusions are insulated from each other.
  • FIGS. 6A-6B are schematic diagrams of steps of a method for fabricating a first adhesive layer according to an embodiment of the present disclosure.
  • forming the first adhesive layer 220 on the intermediate carrier substrate 210 includes: coating the first adhesive material layer 221 on the intermediate carrier substrate 210 ; and patterning the first adhesive material layer 211 to A plurality of through holes 225 penetrating through the first adhesive material layer 221 are formed in the first adhesive material layer 221 .
  • the first adhesive material layer 221 including the plurality of through holes 225 is the first adhesive layer 220 , and the size of the orthographic projection of each of the through holes 225 on the intermediate carrier substrate 210 is smaller than that of the orthographic projection of the light emitting diode chips 180 on the intermediate carrier substrate 210 . size.
  • a plurality of through holes 225 are arranged in a matrix on the intermediate carrier substrate 210 .
  • each through hole 225 may be a rectangle or a circle.
  • the embodiments of the present disclosure include but are not limited thereto, and the shape of each through hole may also adopt other shapes.
  • FIG. 6C is a schematic diagram of transferring a light-emitting diode chip on a mid-carrier substrate to a driving substrate according to an embodiment of the present disclosure.
  • the first adhesive layer 220 adopts the structure shown in FIG. 6B
  • the plurality of through holes 225 in the first adhesive layer 220 can effectively prevent Light or heat affects non-target areas, improving accuracy and improving product yield.
  • FIGS. 7-14 are schematic diagrams of steps of another method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure.
  • the method for fabricating the light-emitting diode substrate further includes: when the epitaxial layer group 120 is far from the substrate M electrode structures 130 are formed on one side of 110 ; and the epitaxial layer group 120 and the M electrode structures 130 are divided to form M light emitting diode chips 180 . That is, in this example, M electrode structures are formed on the substrate, and the epitaxial layer group and the M electrode structures are also divided on the substrate to form M light emitting diode chips.
  • forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the substrate 110 includes: forming a first conductive type semiconductor layer 121 on the substrate 110 ; forming a first conductive type semiconductor layer 121 on the substrate 110 ; A light emitting layer 122 is formed on a side of the layer 121 away from the substrate 110 ; and a second conductive type semiconductor layer 123 is formed on a side of the light emitting layer 122 away from the first conductive type semiconductor layer 121 .
  • the first conductive type semiconductor layer 121 may be an n-type semiconductor layer
  • the second conductive type semiconductor layer 123 may be a p-type semiconductor layer
  • the embodiments of the present disclosure include, but are not limited to, the first conductive type semiconductor layer 121 may be a p-type semiconductor layer, and the second conductive type semiconductor layer 123 may be an n-type semiconductor layer.
  • the material of the first conductive type semiconductor layer 121 and the second conductive type semiconductor layer 123 may be selected from a gallium nitride material.
  • the first conductive type semiconductor layer 121 may be an n-type gallium nitride layer
  • the second conductive type semiconductor layer 123 may be a p-type gallium nitride layer.
  • the embodiments of the present disclosure include, but are not limited to, the materials of the first conductive type semiconductor layer 121 and the second conductive type semiconductor layer 123 can also be selected from other suitable semiconductor materials.
  • the above-mentioned gallium nitride may be used for the first conductive type semiconductor layer and the second conductive type semiconductor layer.
  • the first conductive type semiconductor layer and the second conductive type semiconductor layer may adopt gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs) or aluminum gallium indium phosphide ( AlGaInP).
  • GaP gallium phosphide
  • AlGaAs aluminum gallium arsenide
  • AlGaInP aluminum gallium indium phosphide
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned first conductivity type semiconductor layer and second conductivity type semiconductor layer may also be fabricated by using other suitable materials.
  • the substrate can be a sapphire substrate.
  • the sapphire substrate may further include a patterned sapphire (Patterned Sapphire Substrate, PSS) layer.
  • the patterned sapphire layer can effectively reduce the dislocation density of the first conductive type semiconductor layer (ie, the epitaxial layer), thereby reducing non-radiative recombination, reducing reverse leakage current, and improving the life of the light-emitting diode chip.
  • the light emitted by the light-emitting layer can be scattered multiple times in the patterned sapphire layer, which changes the exit angle of the total reflection light, thereby improving the light extraction efficiency.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer. It should be noted that other substrates, such as silicon carbide substrates, can also be used as the substrate.
  • the above-mentioned patterned sapphire layer can be fabricated by a dry etching process.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer can also be fabricated by other suitable methods.
  • forming the epitaxial layer group 120 of the M light-emitting diode chips 180 on the substrate 110 further includes: forming an electron blocking layer 124 between the light-emitting layer 122 and the second conductive type semiconductor layer 123 .
  • the electron blocking layer 124 can block electrons from entering the second conductive type semiconductor layer 123 to restrict the flow of carriers, thereby improving luminous efficiency and luminous intensity.
  • the electron blocking layer 124 may be p-type aluminum gallium nitride (p-AlGaN).
  • p-AlGaN p-type aluminum gallium nitride
  • the embodiments of the present disclosure include, but are not limited to, the electron blocking layer 124 may also be made of other suitable materials.
  • the manufacturing method before forming the first conductive type semiconductor layer 121 on the substrate 110 , the manufacturing method further includes: performing a high temperature treatment on the substrate 110 and cleaning the surface of the substrate 110 ; and A buffer layer 140 is formed on the substrate 110 .
  • the first conductive type semiconductor layer 121 is then formed on the side of the buffer layer 140 away from the substrate 110 .
  • the buffer layer is aluminum nitride.
  • the embodiments of the present disclosure include, but are not limited to, any material that can improve the degree of lattice matching for the buffer layer.
  • forming M electrode structures on a side of the epitaxial layer set away from the substrate includes: patterning the epitaxial set layer 120 to expose a portion of the first conductive type semiconductor layer 121 to form M electrode structures Exposed parts 1212; M first electrodes 150 are formed on the side of the M exposed parts 1212 away from the substrate 110; M second electrodes 160 are formed on the side of the second conductive type semiconductor layer 123 away from the substrate 110; A passivation layer 170 is formed on one side of the first electrodes 150 and the M second electrodes 160 away from the substrate 110 ; the passivation layer 170 is patterned to form first via holes corresponding to the first electrodes 150 in the passivation layer 170 H1 and a second via hole H2 corresponding to the second electrode 160; a first electrode pad 154 and a second electrode pad 164 are formed on the side of the passivation layer 170 away from the substrate 110, and the first electrode pad 154 passes through the first via hole H1 is connected to the first electrode 150
  • the second conductive type semiconductor layer 123 and the exposed part can be formed 1212
  • a first conductive layer is formed on the side away from the substrate 110, and then the first conductive layer is patterned to form the above-mentioned first electrode 150 and second electrode 160; the first electrode 150 is arranged in contact with the exposed portion 1212, and the second The electrode 160 is disposed in contact with the second conductive type semiconductor layer 123, and the first electrode 150 and the second electrode 160 are insulated from each other.
  • the passivation layer 170 is patterned to form the first via hole H1 corresponding to the first electrode 150 and the second via hole H1 corresponding to the second electrode 160 in the passivation layer 170 .
  • a second conductive layer may be formed on the side of the passivation layer 170 away from the substrate 110, and then the second conductive layer may be patterned to form the first electrode pad 154 and the second electrode pad 164 described above.
  • dividing the epitaxial layer group 120 and the M electrode structures 130 to form the M light-emitting diode chips 180 includes: using an etching process to divide the epitaxial layer group 120 and the M electrode structures 130 to form the M light-emitting diode chips 180 .
  • the embodiments of the present disclosure include but are not limited to this, and other processes may also be used for segmentation.
  • the first alignment marks 710 may be formed on the substrate 110 .
  • the embodiments of the present disclosure do not limit the manufacturing method of the first alignment mark.
  • transferring the N epitaxial layer sets 120 on the N substrates 110 onto the mid-carrier substrate 210 includes: transferring the substrate 110 formed with the M light-emitting diode chips 180 onto the transfer substrate 310; peel off the substrate 110 from the transfer substrate 310; and transfer the N*M light emitting diode chips 180 on the N transfer substrates 310 to the intermediate carrier substrate 210, the area of the transfer substrate 310 is the same as that of the substrate 110 are roughly equal in area.
  • the manufacturing method of the light-emitting diode substrate firstly transfers the light-emitting diode chips on the substrate to a transfer substrate with approximately the same area, and then transfers the N*M light-emitting diode chips on the N transfer substrates to the medium on the carrier substrate, so that the N epitaxial layer groups on the N substrates are transferred to the medium carrier substrate.
  • the electrode structure of the light emitting diode chip on the intermediate carrier substrate is located on the side of the light emitting diode chip away from the intermediate carrier substrate; therefore, the light emitting diode chip on the intermediate carrier substrate can be easily and directly mounted on the intermediate carrier substrate It is transferred to the driving substrate, and the electrode structure of the light emitting diode chip can also be conveniently bound with the pads on the driving substrate.
  • transferring the substrate 110 formed with the M light-emitting diode chips 180 onto the transfer substrate 310 includes: coating the second adhesive layer 320 on the transfer substrate 310 ; The substrate 110 of each light-emitting diode chip 180 is transferred to the side of the second adhesive layer 320 away from the transfer substrate 310 .
  • the manufacturing method of the LED substrate can adhere the M LED chips 180 on the transfer substrate 310 through the second adhesive layer 320. At this time, the electrode structures 130 of the LED chips 180 are located on the LED chip 180 close to the second adhesive layer. 320 side.
  • the second adhesive layer 320 is used to adhere the M light-emitting diode chips 180 on the transfer substrate 310, the transfer can be performed conveniently in the subsequent transfer steps, thereby improving the transfer efficiency and reducing the cost.
  • the substrate 110 and the transfer substrate 310 are first aligned ; Then the substrate 110 moves to the transfer substrate 310 and contacts with the second adhesive layer 320 , at this time, the second adhesive layer 320 can adhere the light-emitting diode chips 180 on the substrate 110 .
  • the first alignment marks 710 formed on the substrate 110 are also transferred to the transfer substrate 310 .
  • the material of the second adhesive layer 320 includes UV adhesive or laser dissociation adhesive.
  • the viscosity of the second adhesive layer 320 can be reduced by irradiating the transfer substrate 310 with ultraviolet light, so that the light emitting diode chips 180 on the transfer substrate 310 are peeled off and transferred. onto the driving substrate 510; when the second adhesive layer 320 is a laser dissociation adhesive, the second adhesive layer 320 can be dissociated by irradiating the transfer substrate 310 with laser light, so that the light emitting diode chips 180 on the transfer substrate 310 can fall off, and transferred to the drive substrate 510 .
  • the materials of the second adhesive layer include, but are not limited to, the above-mentioned ultraviolet light viscosity reducing adhesive and laser dissociating adhesive, and the second adhesive layer may also be a pyrolytic adhesive.
  • peeling the substrate 110 from the transfer substrate 310 may include thinning the substrate 110 from the side of the substrate 110 remote from the transfer substrate 310 using a thinning process, and then The thinned substrate 110 is peeled off from the transfer substrate 310 using a laser lift off (LLO) process.
  • LLO laser lift off
  • a laser light source 900 may be used to irradiate laser light from a side of the substrate 110 away from the transfer substrate 310 , so that the buffer layer 140 is decomposed, thereby peeling off the substrate 110 .
  • the laser light source 900 can be a surface light source or a line light source; when the laser light source 900 is a line light source, the exposure can be completed by moving the laser light source 900 for scanning.
  • the medium carrier substrate 210 includes a plurality of first support structures 240 , and the size of each first support structure 240 in a direction perpendicular to the medium carrier substrate 210 is larger than that of the light emitting diode chips 180 in a direction perpendicular to the direction perpendicular to the medium carrier substrate 210 .
  • transferring the N*M light emitting diode chips 180 on the N transfer substrates 310 to the intermediate carrier substrate 210 includes: sequentially aligning the N transfer substrates 310 with the intermediate carrier substrate 210, So that the plurality of first support structures 240 are located between two adjacent light emitting diode chips 180 on the transfer substrate 310 .
  • the first support structure 240 can not only support the interval between the intermediate carrier substrate 210 and the transfer substrate 310 arranged oppositely, and make the interval between the intermediate carrier substrate 210 and the transfer substrate 310 uniform, but also buffering effect.
  • each of the first support structures 240 in a direction perpendicular to the mid-load substrate 210 ranges from 3 to 10 microns.
  • the embodiments of the present disclosure include but are not limited to this.
  • a transfer device 800 eg, a transfer head may be used to move the transfer substrate 310 above the intermediate carrier substrate 210 for alignment with the intermediate carrier substrate 210 .
  • the transfer substrate 310 may move toward the intermediate carrier substrate 210 and contact the first adhesive layer 220 on the intermediate carrier substrate 210 ;
  • the first adhesive layer 220 can adhere the LED chips 180 on the transfer substrate 310; then, the transfer substrate 310 is irradiated with ultraviolet light or laser to reduce the viscosity of the second adhesive layer 320, or the transfer substrate 310 is heated to reduce the viscosity
  • the adhesiveness of the second adhesive layer 320 enables the light emitting diode chips 180 on the transfer substrate 310 to be transferred to the intermediate carrier substrate 210 , and the transfer substrate 310 is peeled off.
  • the material of the mid-load substrate may be a glass substrate, so that the cost can be reduced.
  • the plane shape of the mid-load substrate can be a rectangle, such as a 300mm*300mm square, a 500mm*500mm square, a 450mm*550mm rectangle (Gen 2.5), or a 2200mm*2500mm rectangle (Gen 8.5).
  • the planar shape and size of the mid-carrier substrate provided by the embodiments of the present disclosure include but are not limited to this.
  • the manufacturing method of the light-emitting diode substrate can use an alignment machine, a high-precision alignment device, and a photosensitive device (CCD) to realize alignment of the transfer substrate and the intermediate carrier substrate; in addition, the light-emitting diode substrate has
  • a cleaning device can be used to clean the adhesive material of the second adhesive layer remaining on the intermediate carrier substrate, so as to avoid the adhesive material from affecting subsequent processes.
  • the intermediate carrier substrate 210 may further include a second alignment mark 720; at this time, the above-mentioned photosensitive device (CCD) can be based on the first alignment mark on the transfer substrate and the first alignment mark on the intermediate carrier substrate. Second, the position of the alignment mark is identified, recorded, calculated, and fed back to the high-precision alignment unit to ensure alignment and accuracy.
  • CCD photosensitive device
  • the above-mentioned alignment machine may have the function of moving in three axial directions, so as to facilitate the alignment; in addition, the above-mentioned alignment machine may also include a vacuum adsorption function, so as to better align the intermediate substrate. Adsorption and immobilization.
  • the above-mentioned alignment machine may further include a realignment and alignment function to realize the alignment of the initial position of the mid-load substrate; in addition, the above-mentioned alignment machine may also have a lifting and lowering structure to realize mid-loading The automatic loading and unloading function of the substrate.
  • At least some of the light-emitting diode chips 180 among the N*M light-emitting diode chips 180 corresponding to the N epitaxial layer groups 120 on the mid-carrier substrate 210 are transferred to the driving substrate 510 This includes: as shown in FIG. 12 , aligning the intermediate carrier substrate 210 and the driving substrate 510 , so that the plurality of first support structures 240 are located between the intermediate carrier substrate 210 and the driving substrate 510 ; as shown in FIG.
  • the mask plate 610 is aligned with the mid-carrier substrate 210 , the first mask plate 610 includes a plurality of openings 615 , and the plurality of openings 615 correspond to the plurality of light-emitting diode chips 180 to be transferred;
  • the substrate 210 is irradiated with light to transfer the plurality of light emitting diode chips 180 to be transferred onto the driving substrate 510 .
  • the intermediate carrier substrate 210 is separated from the driving substrate 510 .
  • the N*M light-emitting diode chips corresponding to the N epitaxial layer groups refer to N*M light-emitting diode chips that can be formed by the N epitaxial layer groups.
  • the first mask plate 610 includes a light absorbing material, and the light absorption rate of the light absorbing material is greater than 60%. Therefore, the first mask plate can effectively avoid the reflection of light, so as to prevent the reflected light from entering the non-target area of the mid-carrier substrate again.
  • the medium carrier substrate 210 is coated with the first adhesive layer 220 ; when the medium carrier substrate 210 is irradiated with light through the first mask plate 610 , the light (such as ultraviolet light or laser) passes through the first mask plate 610 .
  • the opening 615 of the membrane plate 610 is irradiated to the corresponding area on the intermediate carrier substrate 210; at this time, the viscosity of the first adhesive layer 220 corresponding to this area is weakened, or the first adhesive layer 220 corresponding to this area is dissociated, so that the The transferred light emitting diode chips 180 fall off from the carrier substrate 210 and land on the driving substrate 510 .
  • the material of the first adhesive layer 220 includes UV adhesive or laser dissociative adhesive; when the first adhesive layer 220 is an UV adhesive, it can be reduced by irradiating ultraviolet light to a part of the mid-load substrate 210 The viscosity of the corresponding area of the first adhesive layer 220 causes the light-emitting diode chips 180 in this area to fall off and transfer to the driving substrate; when the first adhesive layer 220 is the first laser release adhesive, it can A part of the area of 220 is irradiated with laser to dissociate the corresponding area of the first adhesive layer 220, so that the light emitting diode chip 180 in this area is peeled off and transferred to the driving substrate.
  • UV adhesive or laser dissociative adhesive when the first adhesive layer 220 is an UV adhesive, it can be reduced by irradiating ultraviolet light to a part of the mid-load substrate 210
  • the viscosity of the corresponding area of the first adhesive layer 220 causes the light-emitting diode chips 180 in this area to fall off
  • the first adhesive layer includes but is not limited to the above-mentioned ultraviolet light viscosity reducing adhesive or laser dissociation adhesive, and the first adhesive layer can also be a pyrolytic adhesive;
  • the region corresponding to the first adhesive layer is dissociated by heating, so that the light emitting diode chip in this region is peeled off and transferred to the driving substrate.
  • the first adhesive layer 220 may adopt the structure shown in FIG. 6B , that is, include a plurality of through holes 225 arranged in an array. Therefore, since the first adhesive layer includes a plurality of through holes, that is, the first adhesive layer is patterned, the first adhesive layer corresponding to each light-emitting diode chip is relatively independent. When light is irradiated or heated to a specific area of the mid-carrier substrate 210, the first adhesive layer outside the specific area (ie, the non-target area) will not be affected, so that the light-emitting diode chips that should not be transferred can be prevented from being transferred. Product yield can be improved.
  • FIG. 15 is a schematic diagram of a mid-load substrate according to an embodiment of the disclosure.
  • transferring the N epitaxial layer groups 120 on the N substrates 110 to the intermediate carrier substrate 210 further includes: forming a first adhesive layer on the intermediate carrier substrate 210 Before 220 , a plurality of light-shielding structures 260 are formed on the mid-carrier substrate 210 , and the orthographic projections of each light-shielding structure 260 on the mid-carrier substrate 210 are located between the orthographic projections of two adjacent LED chips 180 on the mid-carrier substrate 210 .
  • the light shielding structure 260 can shield the stray light passing through the mid-carrier substrate and prevent the stray light from being irradiated to the area shielded by the first mask, so that the LED chips can be transferred with high precision and the product yield can be improved.
  • the size of the light shielding structure 260 is smaller than the size of the interval between adjacent light emitting diode chips 180 .
  • the light-shielding structure may coexist with the first support structure, and the light-shielding structure may be located on a side of the first support structure close to the mid-carrier substrate.
  • the embodiments of the present disclosure include, but are not limited to, the first support structure may be made of a light-shielding material, so as to function as a light-shielding structure.
  • the light-shielding structure can be fabricated by a photolithography process; for example, a whole layer of light-shielding layer can be fabricated on a mid-carrier substrate, and then a patterned light-shielding structure can be realized by a photolithography process, which is not described herein again in this embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a first mask according to an embodiment of the disclosure.
  • the first mask 610 includes a first transparent substrate 611 and a first light-absorbing pattern layer 612; the first light-absorbing pattern layer 612 is located on the first transparent substrate 611 and includes a plurality of openings 615;
  • the pattern layer 612 includes a light absorbing material, and the light absorption rate of the light absorbing material is greater than 60%.
  • the first mask 610 further includes: a first magnetic attraction structure 613 located between the first transparent substrate 611 and the first light absorption pattern layer 612 , and the first magnetic attraction structure 613 is located in the first transparent substrate 612 .
  • the orthographic projection on the substrate 611 is spaced apart from the orthographic projection of the plurality of openings 615 on the first transparent substrate 611 . Therefore, the first magnetic attraction structure 613 can be adsorbed and fixed, so that the flatness of the first mask plate during the exposure process can be improved, thereby improving the exposure accuracy.
  • the above-mentioned first magnetic attraction structure can be made of materials such as nickel, iron-nickel alloy, etc., so that it has certain magnetic properties and can be attracted by the electromagnet.
  • planar shape of the above-mentioned first magnetic attraction structure may be a grid structure.
  • the first mask 610 further includes: a first protective layer 614 located on the side of the first light absorbing pattern layer 612 away from the first transparent substrate 611 .
  • the first protective layer 614 can be a transparent protective layer so as not to affect the transmission of light.
  • the embodiments of the present disclosure include, but are not limited to, the first protective layer may also be opaque; in this case, the first protective layer may be peeled off when the first mask is used.
  • the above-mentioned first transparent substrate can be made of quartz or silica glass with high hardness and thickness, so that the deformation amount of the mask plate due to gravity can be reduced.
  • the driver substrate 510 includes a plurality of driver circuits 514 , each driver circuit 514 includes a pad 5142 ; each driver circuit 514 is configured to drive the LED chips 180 electrically connected to the pad 5142 . to glow.
  • the manufacturing method of the light-emitting diode substrate further includes: using a bonding process to bond the light-emitting diode chip 180 transferred to the driving substrate 510 with the corresponding pad 5142 of the driving circuit 514; The first electrode pads 154 and the second electrode pads 164 are respectively bound to the corresponding pads 5142 of the driving circuit 514 .
  • the driving substrate can drive the light emitting diode chip to emit light or display.
  • the number of the driving circuits 514 on the driving substrate 510 is approximately the same as the number of the LED chips 180 on the intermediate carrier substrate 210 ;
  • the positions of the light-emitting diode chips 180 are arranged in a one-to-one correspondence. Thus, after the intermediate substrate and the driving substrate are aligned, any number of light emitting diode chips that need to be transferred on the intermediate substrate can be transferred to the driving substrate at one time.
  • FIG. 17 is a schematic diagram of a spacer on a drive substrate according to an embodiment of the disclosure. As shown in FIG. 17 , each pad 5142 includes at least two sub-pads 5140 , and each sub-pad 5140 includes a groove 5140A configured to receive the corresponding electrode pad 154 or 164 of the LED chip 180 .
  • each of the first support structures 240 is a columnar structure.
  • the shape of the orthographic projection of each of the first support structures 240 on the mid-load substrate 210 includes at least one of a rectangle, a T-shape, and a circle.
  • FIGS. 18A-18C are schematic plan views of a first support structure according to an embodiment of the present disclosure.
  • the shape of the orthographic projection of each first support structure 240 on the intermediate carrier substrate 210 includes a rectangle; as shown in FIG. 18B , the shape of the orthographic projection of each first support structure 240 on the intermediate carrier substrate 210 includes T-shaped; as shown in FIG. 18C , the shape of the orthographic projection of each first support structure 240 on the intermediate carrier substrate 210 includes a circle.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned situations, and the shape of the orthographic projection of each first support structure on the intermediate carrier substrate may also be other shapes.
  • FIG. 18D is a schematic plan view of another first support structure provided by an embodiment of the present disclosure. As shown in FIG. 18D , each of the first support structures 240 is a columnar structure, and the orthographic projections of the first support structures 240 on the intermediate carrier substrate 210 are connected to each other to form a grid.
  • FIG. 19 is a schematic diagram of alignment of a middle carrier substrate and a driving substrate according to an embodiment of the disclosure.
  • the driving substrate 510 includes a plurality of first receiving structures 550
  • aligning the intermediate carrier substrate 210 with the driving substrate 510 includes: inserting the plurality of first supporting structures 240 on the intermediate carrier substrate 210 into the driving substrate 510
  • the plurality of first receiving structures 550, the plurality of first supporting structures 240 and the plurality of first receiving structures 550 are arranged in a one-to-one correspondence, and the size of each first receiving structure 240 perpendicular to the driving substrate 510 is smaller than that of the light-emitting diode chip 180 Perpendicular to the dimension on the drive substrate 510 . Therefore, the alignment accuracy between the intermediate carrier substrate and the driving substrate can be improved through the plurality of first supporting structures and the plurality of first receiving structures.
  • 20A-20D are schematic diagrams of steps of a method for fabricating a first support structure according to an embodiment of the present disclosure.
  • a second alignment mark 720 is formed on the intermediate carrier substrate 210 ;
  • a support material layer 245 is formed on the intermediate carrier substrate 210 , and the supporting material layer 245 is perpendicular to the intermediate carrier substrate 210 .
  • the dimension in the direction of the light emitting diode chip 180 is larger than the dimension of the light emitting diode chip 180 in the direction perpendicular to the medium carrier substrate 210; as shown in FIG.
  • the support material layer 245 is patterned to form a plurality of first supports
  • the period and size of the objects 240 can be related to the spacing between the LED chips 180 on the transfer substrate 310 and the size of the LED chips 180, and the size of each first support 240 is smaller than the spacing between the LED chips 180;
  • the above-mentioned first adhesive layer 220 is formed between the plurality of first supports 240 .
  • 21A-21D are schematic diagrams of steps of another method for fabricating a first support structure according to an embodiment of the present disclosure.
  • a second alignment mark 720 is formed on the intermediate carrier substrate 210 ;
  • the above-mentioned first adhesive layer 220 is formed on the intermediate carrier substrate 210 ;
  • the first A support material layer 245 is formed on the side of the adhesive layer 220 away from the intermediate carrier substrate 210 .
  • the size of the support material layer 245 in the direction perpendicular to the intermediate carrier substrate 210 is larger than that of the light emitting diode chip 180 in the direction perpendicular to the intermediate carrier substrate 210 . Size; as shown in FIG.
  • the support material layer 245 is patterned to form a plurality of first supporters 240 , and the period and size of the plurality of first supporters 240 may be based on the spacing between the light emitting diode chips 180 on the transfer substrate 310 In relation to the size of the light emitting diode chips 180 , the size of each of the first supporters 240 is smaller than the distance between the light emitting diode chips 180 .
  • first support structure can also be fabricated on the transfer substrate through the above-mentioned process, and its function is the same as that on the intermediate carrier substrate, and then when the light-emitting diode chips on the transfer substrate are transferred to the intermediate carrier substrate, The first support structure is also transferred to the mid-carrier substrate synchronously.
  • the above-mentioned supporting material layer may be an organic material layer such as an optical adhesive layer or a resin.
  • 22-34 are schematic diagrams of steps of a method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure.
  • the method for fabricating the light-emitting diode substrate further includes: when the epitaxial layer group 120 is far from the substrate M electrode structures 130 are formed on one side of 110 ; and the epitaxial layer group 120 and the M electrode structures 130 are divided to form M light emitting diode chips 180 . That is, in this example, M electrode structures are formed on the substrate, and the epitaxial layer group and the M electrode structures are also divided on the substrate to form M light emitting diode chips.
  • forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the substrate 110 includes: forming the first conductive type semiconductor layer 121 on the substrate 110 ; forming the first conductive type semiconductor layer 121 on the substrate 110 ; A light emitting layer 122 is formed on the side of the layer 121 away from the substrate 110 ;
  • the first conductive type semiconductor layer 121 may be an n-type semiconductor layer
  • the second conductive type semiconductor layer 123 may be a p-type semiconductor layer
  • the embodiments of the present disclosure include, but are not limited to, the first conductive type semiconductor layer 121 may be a p-type semiconductor layer, and the second conductive type semiconductor layer 123 may be an n-type semiconductor layer.
  • the material of the first conductive type semiconductor layer 121 and the second conductive type semiconductor layer 123 may be selected from a gallium nitride material.
  • the first conductive type semiconductor layer 121 may be an n-type gallium nitride layer
  • the second conductive type semiconductor layer 123 may be a p-type gallium nitride layer.
  • the first conductive type semiconductor layer and the second conductive type semiconductor layer may adopt gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs) or aluminum gallium indium phosphide ( AlGaInP).
  • GaP gallium phosphide
  • AlGaAs aluminum gallium arsenide
  • AlGaInP aluminum gallium indium phosphide
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned first conductivity type semiconductor layer and second conductivity type semiconductor layer may also be fabricated from other suitable materials.
  • the substrate can be a sapphire substrate.
  • the sapphire substrate may further include a patterned sapphire (Patterned Sapphire Substrate, PSS) layer.
  • the patterned sapphire layer can effectively reduce the dislocation density of the first conductive type semiconductor layer (ie, the epitaxial layer), thereby reducing non-radiative recombination, reducing reverse leakage current, and improving the life of the light-emitting diode chip.
  • the light emitted by the light-emitting layer can be scattered multiple times in the patterned sapphire layer, which changes the exit angle of the total reflection light, thereby improving the light extraction efficiency.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer. It should be noted that other substrates, such as silicon carbide substrates, can also be used as the substrate.
  • the above-mentioned patterned sapphire layer can be fabricated by a dry etching process.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer can also be fabricated by other suitable methods.
  • forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the substrate 110 further includes: forming an electron blocking layer 124 between the light-emitting layer 122 and the second conductive type semiconductor layer 123 .
  • the electron blocking layer 124 can block electrons from entering the second conductive type semiconductor layer 123 to restrict the flow of carriers, thereby improving luminous efficiency and luminous intensity.
  • the electron blocking layer 124 may be p-type aluminum gallium nitride (p-AlGaN).
  • p-AlGaN p-type aluminum gallium nitride
  • the embodiments of the present disclosure include, but are not limited to, the electron blocking layer 124 may also be made of other suitable materials.
  • the manufacturing method before forming the first conductive type semiconductor layer 121 on the substrate 110 , the manufacturing method further includes: performing a high temperature treatment on the substrate 110 and cleaning the surface of the substrate 110 ; and A buffer layer 140 is formed on the substrate 110 . Then, the first conductive type semiconductor layer 121 may be formed on the side of the buffer layer 140 away from the substrate 110 .
  • the degree of lattice matching can be improved and the subsequent growth of the epitaxial layer group is facilitated.
  • the buffer layer is aluminum nitride.
  • the embodiments of the present disclosure include, but are not limited to, any material that can improve the degree of lattice matching for the buffer layer.
  • forming the M number of the electrode structures on the side of the epitaxial layer set away from the substrate includes: patterning the epitaxial set layer 120 to expose a portion of the first conductive type semiconductor layer 121 to form M exposed parts 1212; M first electrodes 150 are formed on the side of the M exposed parts 1212 away from the substrate 110; M second electrodes 160 are formed on the side of the second conductive type semiconductor layer 123 away from the substrate 110; A passivation layer 170 is formed on one side of the M first electrodes 150 and the M second electrodes 160 away from the substrate 110; A via hole H1 and a second via hole H2 corresponding to the second electrode 160; a first electrode pad 154 and a second electrode pad 164 are formed on the side of the passivation layer 170 away from the substrate 110, and the first electrode pad 154 passes through the first electrode pad 154.
  • the via hole H1 is connected to the first electrode 150, and the second electrode pad 164 is connected to the second electrode 160 through the second via hole H2.
  • Each conductive structure 130 includes a first electrode 150 , a first electrode pad 154 , a second electrode 160 and a second electrode pad 164 .
  • the second conductive type semiconductor layer 123 and the exposed part can be formed 1212
  • a first conductive layer is formed on the side away from the substrate 110, and then the first conductive layer is patterned to form the above-mentioned first electrode 150 and second electrode 160; the first electrode 150 is arranged in contact with the exposed portion 1212, and the second The electrode 160 is disposed in contact with the second conductive type semiconductor layer 123, and the first electrode 150 and the second electrode 160 are insulated from each other.
  • the passivation layer 170 is patterned to form the first via hole H1 corresponding to the first electrode 150 and the second via hole H1 corresponding to the second electrode 160 in the passivation layer 170 .
  • a second conductive layer may be formed on the side of the passivation layer 170 away from the substrate 110, and then the second conductive layer may be patterned to form the first electrode pad 154 and the second electrode pad 164 described above.
  • dividing the epitaxial layer group 120 and the M electrode structures 130 to form the M light-emitting diode chips 180 includes: using an etching process to divide the epitaxial layer group 120 and the M electrode structures 130 to form the M light-emitting diode chips 180 .
  • the embodiments of the present disclosure include but are not limited to this, and other processes may also be used for segmentation.
  • the first alignment marks 710 may be formed on the substrate 110 .
  • the embodiments of the present disclosure do not limit the manufacturing method of the first alignment mark.
  • the method for fabricating the light-emitting diode substrate includes: transferring the N epitaxial layer groups 120 on the N substrates 110 to the medium carrier substrate 210 , and the N substrates 110 The N epitaxial layer groups 120 are densely arranged on the medium carrier substrate 210 .
  • a first adhesive layer 220 is formed on the intermediate carrier substrate 210; then a transfer device 800 (eg, a transfer head) can be used to move the substrate 110 and the light emitting diode chips 180 on the substrate 110 to the intermediate carrier above the substrate 210 for alignment with the middle carrier substrate 210 .
  • the light emitting diode chip 180 is located between the substrate 110 and the intermediate carrier substrate 210 , and the electrode structure 130 of the light emitting diode chip 180 is located on the side of the light emitting diode chip 180 close to the intermediate carrier substrate 210 .
  • the substrate 110 is moved toward the intermediate carrier substrate 210 , so that the light-emitting diode chips 180 are in contact with the first adhesive layer 220 on the intermediate carrier substrate 210 ; at this time, the first adhesive layer 220 can connect the light-emitting diodes Chip 180 is attached.
  • the substrate 110 is irradiated with laser light from the side of the substrate 110 away from the intermediate carrier substrate 210 , so that the buffer layer 140 on the substrate 110 is decomposed, so that the light emitting diode chips 180 on the substrate 110 are transferred to the substrate 110 .
  • the substrate 110 can be peeled off on the intermediate carrier substrate 210 .
  • the material of the mid-load substrate may be a glass substrate, so that the cost can be reduced.
  • the plane shape of the mid-load substrate can be a rectangle, such as a 300mm*300mm square, a 500mm*500mm square, a 450mm*550mm rectangle (Gen 2.5), or a 2200mm*2500mm rectangle (Gen 8.5).
  • the planar shape and size of the mid-carrier substrate provided by the embodiments of the present disclosure include but are not limited to this.
  • the manufacturing method of the light-emitting diode substrate can use an alignment machine, a high-precision alignment device, and a photosensitive device (CCD) to realize alignment of the transfer substrate and the intermediate carrier substrate; in addition, the light-emitting diode substrate has
  • a cleaning device can be used to clean the adhesive material of the second adhesive layer remaining on the intermediate carrier substrate, so as to avoid the adhesive material from affecting subsequent processes.
  • the intermediate carrier substrate 210 may further include a second alignment mark 720; at this time, the above-mentioned photosensitive device (CCD) can be based on the first alignment mark on the transfer substrate and the first alignment mark on the intermediate carrier substrate. Second, the position of the alignment mark is identified, recorded, calculated, and fed back to the high-precision alignment unit to ensure alignment and accuracy.
  • CCD photosensitive device
  • the above-mentioned alignment machine may have the function of moving in three axial directions, so as to facilitate the alignment; in addition, the above-mentioned alignment machine may also include a vacuum adsorption function, so as to better align the intermediate substrate. Adsorption and immobilization.
  • the above-mentioned alignment machine may further include a realignment and alignment function to realize the alignment of the initial position of the mid-load substrate; in addition, the above-mentioned alignment machine may also have a lifting and lowering structure to realize mid-loading The automatic loading and unloading function of the substrate.
  • At least some of the light-emitting diode chips 180 among the N*M light-emitting diode chips 180 corresponding to the N epitaxial layer groups 120 on the mid-carrier substrate 210 are transferred to the driving substrate 510 Including: as shown in FIG. 27, a selection substrate 410 is provided, and the selection substrate 410 includes a plurality of selection structures 420; as shown in FIG. The transferred LED chips 180 are in contact; as shown in FIG. 29 , align the second mask 620 with the mid-carrier substrate 210 , the second mask 620 includes a plurality of openings 625 , and the plurality of openings 625 correspond to a plurality of selected structures 420 ; as shown in FIGS.
  • the manufacturing method of the light emitting diode substrate can transfer the light emitting diode chips on the intermediate carrier substrate to the driving substrate by selecting the substrate and the selecting structure on the selecting substrate.
  • the second mask plate 620 is made of a light absorbing material, and the light absorption rate of the light absorbing material is greater than 60%. Therefore, the second mask plate can effectively avoid the reflection of light, so as to prevent the reflected light from entering the non-target area of the selected substrate again.
  • FIG. 34 is a schematic diagram of a second mask according to an embodiment of the disclosure.
  • the second mask 620 includes: a second transparent substrate 621 and a second light absorption pattern layer 622; the second light absorption pattern layer 622 is located on the second transparent substrate 621 and includes a plurality of openings 625, the second light absorption pattern layer 622
  • the light absorption pattern layer 622 is made of a light absorption material, and the light absorption rate of the light absorption material is greater than 60%.
  • the second mask 620 further includes: a second magnetic attraction structure 623 located between the second transparent substrate 621 and the second light absorption pattern layer 622, and the second magnetic attraction structure 623 is located in the second transparent substrate 622.
  • the orthographic projection on the substrate 621 is spaced apart from the orthographic projection of the plurality of openings 625 on the second transparent substrate 621 . Therefore, the second magnetic attraction structure 623 can be adsorbed and fixed, so that the flatness of the second mask plate during the exposure process can be improved, thereby improving the exposure accuracy.
  • the above-mentioned second magnetic attraction structure can be made of materials such as nickel, iron-nickel alloy, etc., so that it has certain magnetic properties and can be attracted by the electromagnet.
  • planar shape of the above-mentioned second magnetic attraction structure may be a grid structure.
  • the second mask 620 further includes: a second protective layer 624 located on the side of the first light absorbing pattern layer 622 away from the first transparent substrate 621 .
  • the second protective layer 624 can be a transparent protective layer so as not to affect the transmission of light.
  • the embodiments of the present disclosure include, but are not limited to, the second protective layer may also be opaque; in this case, the second protective layer may be peeled off when the second mask is used.
  • the above-mentioned second transparent substrate can be made of quartz or silica glass with high hardness and thickness, so that the deformation amount of the mask plate due to gravity can be reduced.
  • the selection substrate 410 further includes a third alignment mark 730 .
  • the third alignment mark 70 can be used to align the selection substrate 410 with the intermediate carrier substrate 210 , and make a plurality of The selection structure 420 is in contact with the plurality of LED chips 180 to be transferred. When the selection structure 420 is in contact with the LED chip 180 , the selection structure 420 can adhere the LED chip 180 .
  • FIG. 35 is a schematic diagram of a selection structure provided by an embodiment of the present disclosure. As shown in FIG. 35 , each extraction structure 420 includes a support portion 422 and a pyrolysis portion 425 located on the support portion 425 away from the extraction substrate 410 .
  • the selection substrate 410 is aligned with the mid-carrier substrate 210 , and the contact between the selection structures 420 and the LED chips 180 to be transferred includes: The selection substrate 410 is aligned with the intermediate carrier substrate 210 in a vacuum environment; pressure is applied to the selection substrate 410 to make the pyrolysis portion 425 in the selection structure 420 adhere to the corresponding LED chip 180 .
  • irradiating light to the mid-carrier substrate 210 through the second mask plate 620 to transfer the plurality of light emitting diode chips 180 to be transferred onto the plurality of selection structures 420 on the selection substrate 410 includes: passing through the second After the mask plate 620 irradiates light to the intermediate carrier substrate 210 , an inert gas is introduced between the selection substrate 410 and the intermediate carrier substrate 210 .
  • removing the plurality of extraction structures 420 includes heating in a vacuum environment to melt the pyrolysis portion 425 to remove the plurality of extraction structures 420 .
  • each selection structure 420 includes UV adhesive or laser dissociation glue
  • removing the multiple selection structures 420 includes: irradiating light to the selection substrate to remove the multiple selection structures.
  • each selection structure 420 away from the selection substrate 410 is approximately equal to the area of the orthographic projection of the LED chips 180 on the selection substrate 410 , so that the LED chips 180 can be better selected.
  • each selected structure includes an elastic material to provide some cushioning and improve product yield.
  • the shape of the cross-section of each extraction structure taken perpendicular to a plane of the extraction substrate includes a trapezoid.
  • the embodiments of the present disclosure include, but are not limited to, the shape of the cross-section of each selection structure taken by a plane perpendicular to the selection substrate, and may also be other shapes.
  • 36A-36C are schematic diagrams of steps of a method for fabricating a selection structure according to an embodiment of the present disclosure.
  • a third alignment mark 730 is formed on the selection substrate 410 ;
  • a first selection adhesive material layer 425 is formed on the selection substrate 410 , and the thickness of the first selection adhesive material layer 425 is greater than that of the light-emitting
  • the thickness of the diode chip 180 that is, the size of the first selection glue material layer 425 in the direction perpendicular to the selection substrate 410 is greater than the size of the light emitting diode chip 180 in the direction perpendicular to the selection substrate 410; as shown in FIG. 36C, for the first selection
  • the adhesive material layer 425 is patterned to form the aforementioned selection structure 420 .
  • FIG. 37A-37D are schematic diagrams of steps of another method for fabricating a selection structure according to an embodiment of the present disclosure.
  • a third alignment mark 730 is formed on the selected substrate 410; as shown in FIG. 37B, a selected material layer 430 is formed on the selected substrate 410; as shown in FIG. 37C, the selected material layer 430 is patterned to A plurality of raised structures 435 are formed; as shown in FIG. 37D , a second selection adhesive material layer 427 is formed on the side of the plurality of raised structures 435 away from the selection substrate 410 .
  • the second selection glue material layer 427 can form a selection structure 420 .
  • the above-mentioned first selected glue material layer 425 and second selected glue material layer 427 may be made of ultraviolet light viscosity reducing material or laser dissociation material.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned first selected glue material layer 425 and second selected glue material layer 427 may also be pyrolytic materials.
  • the above-mentioned selected material layer 430 may be an organic material such as optical glue or resin.
  • 38-43 are schematic diagrams of steps of another method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure.
  • the method for fabricating the light-emitting diode substrate further includes: when the epitaxial layer group 120 is far from the substrate M electrode structures 130 are formed on one side of 110 ; and the epitaxial layer group 120 and the M electrode structures 130 are divided to form M light emitting diode chips 180 . That is, in this example, M electrode structures are formed on the substrate, and the epitaxial layer group and the M electrode structures are also divided on the substrate to form M light emitting diode chips.
  • forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the substrate 110 includes: forming the first conductive type semiconductor layer 121 on the substrate 110 ; forming the first conductive type semiconductor layer 121 on the substrate 110 ; A light emitting layer 122 is formed on a side of the layer 121 away from the substrate 110 ; and a second conductive type semiconductor layer 123 is formed on a side of the light emitting layer 122 away from the first conductive type semiconductor layer 121 .
  • the first conductive type semiconductor layer 121 may be an n-type semiconductor layer
  • the second conductive type semiconductor layer 123 may be a p-type semiconductor layer
  • the embodiments of the present disclosure include, but are not limited to, the first conductive type semiconductor layer 121 may be a p-type semiconductor layer, and the second conductive type semiconductor layer 123 may be an n-type semiconductor layer.
  • the material of the first conductive type semiconductor layer 121 and the second conductive type semiconductor layer 123 may be selected from a gallium nitride material.
  • the first conductive type semiconductor layer 121 may be an n-type gallium nitride layer
  • the second conductive type semiconductor layer 123 may be a p-type gallium nitride layer.
  • the embodiments of the present disclosure include, but are not limited to, the materials of the first conductive type semiconductor layer 121 and the second conductive type semiconductor layer 123 can also be selected from other suitable semiconductor materials.
  • the substrate can be a sapphire substrate.
  • the sapphire substrate may further include a patterned sapphire (Patterned Sapphire Substrate, PSS) layer.
  • the patterned sapphire layer can effectively reduce the dislocation density of the first conductive type semiconductor layer (ie, the epitaxial layer), thereby reducing non-radiative recombination, reducing reverse leakage current, and improving the life of the light-emitting diode chip.
  • the light emitted by the light-emitting layer can be scattered multiple times in the patterned sapphire layer, which changes the exit angle of the total reflection light, thereby improving the light extraction efficiency.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer in the light-emitting diode chip. It should be noted that other substrates, such as silicon carbide substrates, can also be used as the substrate.
  • the above-mentioned patterned sapphire layer can be fabricated by a dry etching process.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer can also be fabricated by other suitable methods.
  • forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the substrate 110 further includes: forming an electron blocking layer 124 between the light-emitting layer 122 and the second conductive type semiconductor layer 123 .
  • the electron blocking layer 124 can block electrons from entering the second conductive type semiconductor layer 123 to restrict the flow of carriers, thereby improving luminous efficiency and luminous intensity.
  • the electron blocking layer 124 may be p-type aluminum gallium nitride (p-AlGaN).
  • p-AlGaN p-type aluminum gallium nitride
  • the embodiments of the present disclosure include, but are not limited to, the electron blocking layer 124 may also be made of other suitable materials.
  • the manufacturing method before forming the first conductive type semiconductor layer 121 on the substrate 110, includes: performing a high temperature treatment on the substrate 110, and cleaning the surface of the substrate 110; A buffer layer 140 is formed on the bottom 110 . Then, the first conductive type semiconductor layer 121 may be formed on the side of the buffer layer 140 away from the substrate 110 .
  • the degree of lattice matching can be improved and the subsequent growth of the epitaxial layer group is facilitated.
  • the buffer layer is aluminum nitride.
  • the embodiments of the present disclosure include, but are not limited to, any material that can improve the degree of lattice matching for the buffer layer.
  • forming the M number of the electrode structures on the side of the epitaxial layer set away from the substrate includes: patterning the epitaxial set layer 120 to expose a portion of the first conductive type semiconductor layer 121 to form M exposed parts 1212; M first electrodes 150 are formed on the side of the M exposed parts 1212 away from the substrate 110; M second electrodes 160 are formed on the side of the second conductive type semiconductor layer 123 away from the substrate 110; A passivation layer 170 is formed on one side of the M first electrodes 150 and the M second electrodes 160 away from the substrate 110; A via hole H1 and a second via hole H2 corresponding to the second electrode 160; a first electrode pad 154 and a second electrode pad 164 are formed on the side of the passivation layer 170 away from the substrate 110, and the first electrode pad 154 passes through the first electrode pad 154.
  • the via hole H1 is connected to the first electrode 150, and the second electrode pad 164 is connected to the second electrode 160 through the second via hole H2.
  • Each conductive structure 130 includes a first electrode 150 , a first electrode pad 154 , a second electrode 160 and a second electrode pad 164 .
  • the second conductive type semiconductor layer 123 and the exposed part can be formed 1212
  • a first conductive layer is formed on the side away from the substrate 110, and then the first conductive layer is patterned to form the above-mentioned first electrode 150 and second electrode 160; the first electrode 150 is arranged in contact with the exposed portion 1212, and the second The electrode 160 is disposed in contact with the second conductive type semiconductor layer 123, and the first electrode 150 and the second electrode 160 are insulated from each other.
  • the passivation layer 170 is patterned to form the first via hole H1 corresponding to the first electrode 150 and the second via hole H1 corresponding to the second electrode 160 in the passivation layer 170 .
  • a second conductive layer may be formed on the side of the passivation layer 170 away from the substrate 110, and then the second conductive layer may be patterned to form the first electrode pad 154 and the second electrode pad 164 described above.
  • dividing the epitaxial layer group 120 and the M electrode structures 130 to form the M light-emitting diode chips 180 includes: using an etching process to divide the epitaxial layer group 120 and the M electrode structures 130 to form the M light-emitting diode chips 180 .
  • the embodiments of the present disclosure include but are not limited to this, and other processes may also be used for segmentation.
  • the first alignment marks 710 may be formed on the substrate 110 .
  • the embodiments of the present disclosure do not limit the manufacturing method of the first alignment mark.
  • the N epitaxial layer groups 120 on the N substrates 110 are transferred to the intermediate carrier substrate 210 through the transfer substrate 310 , and the specific transfer process can be referred to in FIGS. 9 to 11 . Relevant descriptions are not repeated here.
  • the driving substrate 510 includes a plurality of second supporting structures 540 , and the size of each second supporting structure 540 in a direction perpendicular to the driving substrate 510 is larger than that of the light emitting diode chips 180 in a direction perpendicular to the driving substrate 510 on the dimension in the direction.
  • the second support structure 540 can not only support the space between the intermediate carrier substrate 210 and the driving substrate 510 that are opposite to each other, and make the space between the intermediate carrier substrate 210 and the driving substrate 510 uniform, but also play a role of buffering .
  • At least some of the light-emitting diode chips 180 among the N*M light-emitting diode chips 180 corresponding to the N epitaxial layer groups 120 on the mid-carrier substrate 210 are transferred to the driving substrate 510 It includes: as shown in FIG. 41 , aligning the intermediate carrier substrate 210 with the driving substrate 510 , and inserting a plurality of second support structures 540 between two adjacent LED chips 180 on the intermediate carrier substrate 210 ; as shown in FIG.
  • the third mask plate 630 aligns the third mask plate 630 with the middle carrier substrate 210, the third mask plate 630 includes a plurality of openings 635, and the plurality of openings 635 correspond to a plurality of light-emitting diode chips 180 to be transferred; as shown in FIG.
  • the third mask 630 irradiates light to the intermediate carrier substrate 210 to transfer the plurality of LED chips 180 to be transferred onto the driving substrate 510 ; as shown in FIG. 43 , the intermediate carrier substrate 210 is removed from the driving substrate 510 , and bind the light emitting diode chip 180 transferred to the driving substrate 510 with the driving substrate 510 .
  • the third mask plate 630 is made of a light absorbing material, and the light absorption rate of the light absorbing material is greater than 60%. Therefore, the third mask plate can effectively avoid the reflection of light, so as to prevent the reflected light from entering the non-target area of the selected substrate again.
  • FIG. 44 is a schematic diagram of a third mask according to an embodiment of the disclosure.
  • the third mask 630 includes: a third transparent substrate 631 and a third light absorption pattern layer 632; the third light absorption pattern layer 632 is located on the third transparent substrate 631 and includes a plurality of openings 635, and the third light absorption pattern layer 632 is located on the third transparent substrate 631.
  • the light absorption pattern layer 632 is made of a light absorption material, and the light absorption rate of the light absorption material is greater than 60%.
  • the third mask 630 further includes: a third magnetic attraction structure 633 located between the third transparent substrate 631 and the third light absorption pattern layer 632, and the third magnetic attraction structure 633 is located in the third transparent substrate 632.
  • the orthographic projection on the substrate 631 is spaced apart from the orthographic projection of the plurality of openings 635 on the third transparent substrate 631 . Therefore, the third magnetic attraction structure 633 can be adsorbed and fixed, so that the flatness of the third mask plate during the exposure process can be improved, thereby improving the exposure accuracy.
  • the above-mentioned third magnetic attraction structure can be made of materials such as nickel, iron-nickel alloy, etc., so that it has certain magnetic properties and can be attracted by the electromagnet.
  • planar shape of the above-mentioned third magnetic attraction structure may be a grid structure.
  • the third mask 630 further includes: a third protective layer 634 located on the side of the third light absorbing pattern layer 632 away from the third transparent substrate 631 .
  • the third protective layer 634 can be a transparent protective layer so as not to affect the transmission of light.
  • the embodiments of the present disclosure include, but are not limited to, the third protective layer may also be opaque; in this case, the third protective layer may be peeled off when the third mask is used.
  • the above-mentioned third transparent substrate can be made of quartz or silica glass with high hardness and high thickness, so that the deformation amount of the mask plate due to gravity can be reduced.
  • the first mask plate, the second mask plate, and the third mask plate may be the same mask plate.
  • the embodiments of the present disclosure include but are not limited to this.
  • each of the second support structures 540 in a direction perpendicular to the driving substrate 510 may range from 3 to 10 microns.
  • the embodiments of the present disclosure include but are not limited to this.
  • the fabrication method of the second support structure 540 reference may be made to the fabrication method of the first support structure, and details are not described herein again.
  • 45-50 are schematic diagrams of steps of another method for fabricating a light-emitting diode substrate according to an embodiment of the present disclosure.
  • forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the substrate 110 includes: forming the second conductive type semiconductor layer 123 on the substrate 110 ; forming the second conductive type semiconductor layer 123 on the substrate 110 ; A light emitting layer 122 is formed on a side of the layer 123 away from the substrate 110 ; and a first conductive type semiconductor layer 121 is formed on a side of the light emitting layer 122 away from the second conductive type semiconductor layer 123 . It should be noted that the order of each epitaxial layer in the epitaxial layer group shown in FIG. 45 is opposite to the order of each epitaxial layer in the epitaxial layer group shown in FIG. 7 .
  • the embodiments of the present disclosure include, but are not limited to, the order of each epitaxial layer in the epitaxial layer group shown in FIG. 45 may also be the same as the order of each epitaxial layer in the epitaxial layer group shown in FIG. 7 .
  • the first conductive type semiconductor layer 121 may be an n-type semiconductor layer
  • the second conductive type semiconductor layer 123 may be a p-type semiconductor layer
  • the embodiments of the present disclosure include, but are not limited to, the first conductive type semiconductor layer 121 may be a p-type semiconductor layer, and the second conductive type semiconductor layer 123 may be an n-type semiconductor layer.
  • the material of the first conductive type semiconductor layer 121 and the second conductive type semiconductor layer 123 may be selected from a gallium nitride material.
  • the first conductive type semiconductor layer 121 may be an n-type gallium nitride layer
  • the second conductive type semiconductor layer 123 may be a p-type gallium nitride layer.
  • the embodiments of the present disclosure include, but are not limited to, the materials of the first conductive type semiconductor layer 121 and the second conductive type semiconductor layer 123 can also be selected from other suitable semiconductor materials.
  • the substrate can be a sapphire substrate.
  • the substrate can be a sapphire substrate.
  • the sapphire substrate may further include a patterned sapphire (Patterned Sapphire Substrate, PSS) layer.
  • the patterned sapphire layer can effectively reduce the dislocation density of the first conductive type semiconductor layer (ie, the epitaxial layer), thereby reducing non-radiative recombination, reducing reverse leakage current, and improving the life of the light-emitting diode chip.
  • the light emitted by the light-emitting layer can be scattered multiple times in the patterned sapphire layer, which changes the exit angle of the total reflection light, thereby improving the light extraction efficiency.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer. It should be noted that other substrates, such as silicon carbide substrates, can also be used as the substrate.
  • the above-mentioned patterned sapphire layer can be fabricated by a dry etching process.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned patterned sapphire layer can also be fabricated by other suitable methods.
  • forming the epitaxial layer group 120 of the M light emitting diode chips 180 on the substrate 110 further includes: forming an electron blocking layer 124 between the light emitting layer 122 and the second conductive type semiconductor layer 123 .
  • the electron blocking layer 124 can block electrons from entering the second conductive type semiconductor layer 123 to restrict the flow of carriers, thereby improving luminous efficiency and luminous intensity.
  • the electron blocking layer 124 may be p-type aluminum gallium nitride (p-AlGaN).
  • p-AlGaN p-type aluminum gallium nitride
  • the embodiments of the present disclosure include, but are not limited to, the electron blocking layer 124 may also be made of other suitable materials.
  • the manufacturing method before forming the first conductive type semiconductor layer 121 on the substrate 110 , includes: performing a high temperature treatment on the substrate 110 and cleaning the surface of the substrate 110 ; and forming a buffer layer on the substrate 110 140. Then, the first conductive type semiconductor layer 121 is formed on the side of the buffer layer 140 away from the substrate 110 .
  • the degree of lattice matching can be improved and the subsequent growth of the epitaxial layer group is facilitated.
  • the buffer layer is aluminum nitride.
  • the embodiments of the present disclosure include, but are not limited to, any material that can improve the degree of lattice matching for the buffer layer.
  • transferring the N epitaxial layer groups 120 on the N substrates 110 to the intermediate carrier substrate 210 includes: as shown in FIG. 46 - As shown in FIG. 49, the N epitaxial layer groups 120 on the N substrates 110 are sequentially transferred to the intermediate carrier substrate 210, and the epitaxial layer groups 120 are not divided at this time; as shown in FIG. 50, in the N epitaxial layers M electrode structures 130 are formed on the side of the layer group 120 away from the intermediate carrier substrate 210 ; the N epitaxial layer groups 120 on the intermediate carrier substrate 210 are divided to form M light emitting diode chips 180 together with the M electrode structures 130 .
  • the substrate 110 can be brought close to the intermediate carrier substrate 210 first, and the part outside the epitaxial layer group 120 can be thinned, so as to prevent the substrate 100 from colliding or damaging the substrate 100 that has been transferred to the intermediate carrier substrate 210 .
  • Epitaxial layer set 120 In the process of carrying the substrate 210 , the substrate 110 can be brought close to the intermediate carrier substrate 210 first, and the part outside the epitaxial layer group 120 can be thinned, so as to prevent the substrate 100 from colliding or damaging the substrate 100 that has been transferred to the intermediate carrier substrate 210 .
  • Epitaxial layer set 120 Epitaxial layer set 120 .
  • dividing the N epitaxial layer groups on the mid-carrier substrate to form M light-emitting diode chips together with the M electrode structure groups includes: using an etching process to divide the N epitaxial layer groups on the mid-carrier substrate to form M light-emitting diode chips together with the M electrode structure groups. Together with the M electrode structure groups, M light-emitting diode chips are formed.
  • the embodiments of the present disclosure include but are not limited thereto, and other suitable methods such as laser cutting may also be used to divide the N epitaxial layer groups on the mid-carrier substrate to form M light-emitting diode chips together with the M electrode structure groups.
  • each electrode structure 130 includes a first electrode 150 and J second electrodes 160
  • forming M electrode structures 130 on the side of the epitaxial layer group 120 away from the substrate 110 includes: a pattern The epitaxial group layer 120 is formed to expose part of the first conductive type semiconductor layer 121 to form M exposed portions 1212, and the second conductive type semiconductor layer 123 is divided into M*J second conductive type semiconductor blocks 1230; M*J second electrodes 160 are formed on the side of the second conductive type semiconductor blocks 1230 away from the intermediate carrier substrate 210; passivation layers 170 are formed on the side of the M*J second electrodes 160 away from the intermediate carrier substrate 210; Passivating the passivation layer 170 to form M first via holes H1 corresponding to the M exposed portions 1212 and M*J second via holes H2 corresponding to the M*J second electrodes 160 in the passivation layer 170; M first electrodes 150 are formed on the side of the M exposed parts 1212 away from the substrate 110 through the M first
  • each electrode structure 130 includes a first electrode 150 and j second electrodes 160, a first electrode, a second electrode, a first conductive type semiconductor layer, a first electrode
  • the two-conductivity-type semiconductor block and the light-emitting layer can form an LED light-emitting structure.
  • a single light emitting diode chip may include j (j is a positive integer greater than or equal to 2) second conductive type semiconductor blocks and j second electrodes, and thus a single light emitting diode chip may be formed with at least two light emitting diodes that can emit light independently structure.
  • the size of the single light emitting structure can be reduced. That is to say, the LED chips with smaller size can be fabricated with the existing process precision. Therefore, the light emitting diode chip can reduce the manufacturing difficulty and cost of a small-sized LED light emitting structure, and can also achieve higher pixel density.
  • the small size of a single light-emitting structure due to the small size of a single light-emitting structure, its efficiency is also high when driven by a small current, so that the light-emitting efficiency can be improved.
  • the intermediate carrier substrate 210 and the light emitting diode chips 180 on the intermediate carrier substrate 210 may be transferred to the driving substrate 510, the specific process can refer to the related descriptions in FIG. 12-FIG. 14, and details are not repeated here.
  • Forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the substrate 110 includes: as shown in FIG. 51A , forming the epitaxial layer group 120 of M light-emitting diode chips 180 on the circular substrate 110 , The shape of the orthographic projection on the substrate 110 is a square; as shown in FIG. 51B , the circular substrate 110 is cut into a square substrate 110 along the edge of the epitaxial layer group 120 ; as shown in FIG.
  • the N Transferring the N epitaxial layer groups 120 on the substrates 110 to the intermediate carrier substrate 210 includes: densely arranging the N epitaxial layer groups 120 on the N square substrates 110 on the intermediate carrier substrate 210 .
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned circular substrates can also be cut into hexagonal substrates according to the crystalline properties of the substrates.
  • the substrate is a sapphire substrate
  • sapphire is a hexagonal crystal
  • the sapphire substrate since the epitaxial layer is epitaxially grown along the crystal axis, there are two crystal planes in the dissociation plane parallel to the crystal axis direction, and the two crystal planes are perpendicular to each other.
  • the sapphire is dissociated parallel to the reference edge or perpendicular to the reference edge, so that the circular sapphire substrate can be cut into a square sapphire substrate, and can also be dissociated into a hexagonal sapphire substrate according to the crystal plane distribution.
  • the epitaxial layer group 120 for forming M light-emitting diode chips 180 on the substrate 110 includes: as shown in FIG. 52A , cutting the circular substrate 110 into square substrates 110 ; as shown in FIG. 52B , cutting N square substrates 110 The substrates 110 are spliced together to form a combination of N substrates 110 ; as shown in FIG. 52C , epitaxial layers 120 of M*N light-emitting diode chips 180 are formed on the combination of N substrates 110 .
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned circular substrates can also be cut into hexagonal substrates according to the crystalline properties of the substrates.
  • transferring the sets of N epitaxial layers on the N substrates to the mid-carrier substrate includes: transferring epitaxial layers of M*N light-emitting diode chips formed on the combination of the N substrates to the mid-carrier substrate superior.
  • FIG. 53 is a schematic diagram of a light emitting diode substrate according to an embodiment of the disclosure.
  • the light-emitting diode substrate can be fabricated by any of the aforementioned fabrication methods.
  • the above-mentioned manufacturing method of a light-emitting diode substrate is performed by first transferring the N epitaxial layer groups on the N substrates to a larger-sized intermediate carrier substrate, and densely arranging these epitaxial layer groups on the intermediate carrier substrate; then, Then, at least part of the selected light emitting diode chips on the intermediate carrier substrate are transferred to the driving substrate.
  • the N epitaxial layer groups on the N substrates are densely arranged on the intermediate carrier substrate, at least some of the light emitting diode chips among the N*M light emitting diode chips corresponding to the N epitaxial layer groups on the intermediate carrier substrate are transferred.
  • the light-emitting diode chips on the intermediate carrier substrate are evenly distributed, so that more light-emitting diode chips (greater than the number of light-emitting diode chips that can be taken by one substrate) can be used at one time, even at one time.
  • the LED chips of the same color required by the driving substrate can be selectively used, that is, the LED chips of the same color on the driving substrate can be completed by only one transfer process. Therefore, the manufacturing method of the light-emitting diode substrate can greatly improve the taking efficiency and the transfer efficiency. Therefore, the light emitting diode substrate has higher fabrication efficiency and lower cost.
  • the driving substrate 510 includes a plurality of receiving structures 560 , and the size of each receiving structure 560 perpendicular to the driving substrate 510 is smaller than that of the LED chip 180 perpendicular to the driving substrate 510 . size on . Therefore, the above-mentioned receiving structure can improve the alignment accuracy between the intermediate carrier substrate and the driving substrate, thereby improving the product yield.
  • FIG. 54 is a schematic diagram of another light emitting diode substrate according to an embodiment of the disclosure.
  • the light emitting diode substrate 10 includes a driving substrate 510 and a plurality of light emitting diode chips 180 on the driving substrate 510 .
  • the light emitting diode substrate 10 further includes a plurality of support structures 540 located between adjacent light emitting diode chips 180. The size of each support structure 540 in a direction perpendicular to the driving substrate 510 is larger than that of the light emitting diode chips 180 in a direction perpendicular to the driving substrate 510. Dimensions in the direction of the substrate 510 .
  • the support structure can not only support the interval between the oppositely disposed intermediate carrier substrate and the driving substrate 510 during the manufacturing process, and make the interval between the intermediate carrier substrate and the driving substrate 510 uniform, but also serve as a buffer. , which can improve product yield.
  • FIG. 55 is a schematic diagram of another light emitting diode substrate according to an embodiment of the disclosure.
  • the drive substrate 510 includes a base substrate 511 and a plurality of drive circuits 514 located on the base substrate 511 , each drive circuit 514 includes a pad 5142 ; each drive circuit 514 is configured to drive and electrically connect to the pad 5142 The light-emitting diode chips 180 that are connected sexually emit light.
  • Each pad 5142 includes at least two sub-pads 5140 , and each sub-pad 5140 includes a groove 5140A configured to receive the corresponding electrode pad 154 or 164 of the LED chip 180 .
  • the driving substrate can drive the light emitting diode chip to emit light or display.
  • grooves can also improve the accuracy of bonding, which can improve product yield.
  • the number of the driving circuits 514 on the driving substrate 510 is approximately the same as the number of the light-emitting diode chips 180 on the intermediate carrier substrate 210 ;
  • the positions of the light-emitting diode chips 180 are arranged in a one-to-one correspondence. In this way, after the intermediate substrate and the driving substrate are aligned, any number of light emitting diode chips that need to be transferred on the intermediate substrate can be transferred to the driving substrate at one time.
  • FIG. 56 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the display device 20 includes the above-mentioned light-emitting diode substrate 10 .
  • the above-mentioned light-emitting diode substrate 10 includes light-emitting diode chips that emit light of multiple colors (for example, red, green, and blue)
  • the light-emitting diode substrate 10 may be a display substrate of the display device 20, Direct color display.
  • the light-emitting diode substrate 10 when the above-mentioned light-emitting diode substrate 10 only includes light-emitting diode chips emitting one color (eg, white or blue), the light-emitting diode substrate 10 can be a backlight source of the display device 20 .
  • the light-emitting diode substrate 10 can be a backlight source of the display device 20 .
  • the display device may be an electronic product with a display function, such as a TV, a computer, a notebook computer, a smart phone, a navigator, a tablet computer, an electronic picture frame, and the like.
  • a display function such as a TV, a computer, a notebook computer, a smart phone, a navigator, a tablet computer, an electronic picture frame, and the like.
  • FIG. 16 is a schematic diagram of a mask according to an embodiment of the disclosure.
  • the mask 610 includes a transparent substrate 611 and a light-absorbing pattern layer 612; the light-absorbing pattern layer 612 is located on the transparent substrate 611 and includes a plurality of openings 615; the light-absorbing pattern layer 612 is made of a light-absorbing material, and the light-absorbing material The absorption rate is greater than 60%.
  • the chrome pattern used in the common mask has a reflectivity of 65% (about 65%) due to the high energy of the laser. 35% absorption rate), which will cause the laser to be reflected; and the reflected laser will be reflected and projected to the non-target area again, which will cause the non-target area to be exposed, resulting in false dissociation.
  • the mask provided by the embodiment of the present disclosure since the light-absorbing pattern layer is made of a light-absorbing material, the light absorption rate of the light-absorbing material is greater than 60%. Therefore, the mask can reduce or even eliminate the reflection of the mask. This avoids false dissociation from exposure of non-target regions.
  • the mask plate 610 further includes: a magnetic attraction structure 613 located between the transparent substrate 611 and the light absorption pattern layer 612 , the orthographic projection of the magnetic attraction structure 613 on the transparent substrate 611 and the plurality of openings 615
  • the orthographic projections on the transparent substrate 611 are arranged at intervals. Therefore, the magnetic attraction structure 613 can be adsorbed and fixed, so that the flatness of the mask plate during the exposure process can be improved, thereby improving the exposure accuracy.
  • the mask 610 further includes: a protective layer 614 located on the side of the light absorbing pattern layer 612 away from the transparent substrate 611 .
  • the protective layer 614 can be a transparent protective layer so as not to affect the transmission of light.
  • the embodiments of the present disclosure include, but are not limited to, the protective layer may also be opaque; in this case, the protective layer may be peeled off when the mask is used.
  • the light absorbing material can be obtained by oxidizing a metal pattern.
  • the transparent substrate of the mask includes light-transmitting materials such as quartz, glass, and sapphire.
  • the transparent substrate of the mask can be made of quartz or silica glass with high hardness and thickness, so that the deformation of the mask due to gravity can be reduced.

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Abstract

一种发光二极管基板及其制作方法和显示装置。该发光二极管基板的制作方法包括：在衬底上形成M个发光二极管芯片的外延层组；将N个衬底上的N个外延层组转移到中载基板上，N个衬底上的N个外延层组密集排列在中载基板上；以及将中载基板上的N个外延层组对应的N*M个发光二极管芯片中至少部分发光二极管芯片转移到驱动基板上。中载基板的面积大于等于N个衬底的面积之和，M为大于等于2的正整数，N为大于等于2的正整数。由此，该发光二极管基板的制作方法可大大提高取用效率和转移效率。

Description

发光二极管基板及其制作方法、显示装置 技术领域
本公开的实施例涉及一种发光二极管基板及其制作方法和显示装置。
背景技术
发光二极管是一种通过电子与空穴复合来发光的半导体器件，其通常可采用镓(Ga)与砷(As)、磷(P)、氮(N)、铟(In)的化合物制成。发光二极管可高效地将电能转化为光能，并且可以发出不同颜色的单色光。例如，砷化镓二极管可发红光，磷化镓二极管可发绿光，碳化硅二极管可发黄光，氮化镓二极管可发蓝光。
随着显示技术的不断发展，发光二极管显示技术作为一种新型的显示技术逐渐成为研究的热点之一。发光二极管显示技术利用发光二极管(Light Emitting Diode，LED)组成的阵列来进行显示。相对于其他显示技术，发光二极管显示技术具有发光强度高、响应速度快、功耗低、电压需求低、设备轻薄、使用寿命长、耐冲击、抗干扰能力强等优点。
另一方面，具有较小尺寸的微型发光二极管(Micro-LED)可更好地实现高分辨率的产品，例如4K甚至8K分辨率的智能手机或虚拟显示屏幕等。对于虚拟显示屏幕来说，虽然有机发光二极管(OLED)显示面板的响应时间已经降低到了微秒级别，拥有非常不错的响应时间等级。然而，微型发光二极管(Micro-LED)的响应时间又进一步降低到了纳秒级别，更快了1000倍，因此更适合制作虚拟显示屏幕。
发明内容
本公开实施例提供一种发光二极管基板及其制作方法和显示装置。该发光二极管基板的制作方法包括：在衬底上形成M个发光二极管芯片的外延层组；将N个衬底上的N个外延层组转移到中载基板上，N个衬底上的N个外延层组密集排列在中载基板上；以及将中载基板上的N个外延层组对应的N*M个发光二极管芯片中至少部分发光二极管芯片转移到驱动基板上。中载基板的面积大于等于N个衬底的面积之和，M为大于等于2的正整数，N为大于等于2的正整数。由此，该发光二极管基板的制作方法通过先将N个衬底上的N个 外延层组转移到尺寸更大的中载基板上，并且这些外延层组密集排布在中载基板上，然后再从中载基板上的发光二极管芯片转移到驱动基板上，从而可一次取用更多的发光二极管芯片，甚至一次性取用驱动基板需要的发光二极管芯片，进而可大大提高取用效率和转移效率。
本公开至少一个实施例还提供一种发光二极管基板的制作方法，其包括：在衬底上形成M个发光二极管芯片的外延层组；将N个所述衬底上的N个所述外延层组转移到中载基板上，N个所述衬底上的N个所述外延层组密集排列在所述中载基板上；以及将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到驱动基板上，所述中载基板的面积大于等于N个所述衬底的面积之和，M为大于等于2的正整数，N为大于等于2的正整数。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述中载基板上，相邻两个所述外延层组之间的距离与相邻的两个所述发光二极管芯片之间的距离大致相等。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述中载基板的形状与所述驱动基板的形状大致相同，所述中载基板的面积与所述驱动基板的面积大致相等。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述驱动基板包括衬底基板和位于衬底基板上的多个驱动电路，各所述驱动电路包括垫片，并被配置为驱动与所述垫片电性相连的所述发光二极管芯片进行发光，所述制作方法还包括：采用绑定工艺将转移到所述驱动基板上的所述发光二极管芯片与对应的所述驱动电路的所述垫片绑定。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，采用绑定工艺将转移到所述驱动基板上的所述发光二极管芯片与对应的所述驱动电路的所述垫片绑定包括：对所述驱动基板进行热回流，以将所述发光二极管芯片与所述垫片键合在一起。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述驱动基板还包括多个导电凸起，位于所述垫片远离所述衬底基板的一侧，各所述垫片在所述衬底基板上的正投影与至少一个所述导电凸起在所述衬底基板上的正投影交叠，所述制作方法还包括：将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到所述 驱动基板上之前，在所述驱动基板上涂覆有机绝缘胶材；采用绑定工艺将转移到所述驱动基板上的所述发光二极管芯片与对应的所述驱动电路的所述垫片绑定包括：对所述驱动基板进行热回流，蒸发所述有机绝缘胶材中的溶剂，以将所述发光二极管芯片与所述垫片键合在一起。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将N个所述衬底上的N个所述外延层组转移到所述中载基板包括：在所述中载基板上形成第一胶层；以及将N个所述衬底上的N个所述外延层组转移到所述第一胶层远离所述中载基板的一侧。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述中载基板上形成所述第一胶层包括：在所述中载基板上涂覆第一胶材层；以及图案化所述第一胶材层，以在所述第一胶材层中形成贯穿所述第一胶材层的多个通孔，此时，包括所述多个通孔的所述第一胶材层为所述第一胶层，各所述通孔在所述中载基板上的正投影的尺寸小于所述发光二极管芯片在所述中载基板上的正投影的尺寸。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一胶层的材料包括紫外光减粘胶或激光解离胶。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将N个所述衬底上的N个所述外延层组转移到所述中载基板还包括：在所述中载基板上形成第一胶层之前，在所述中载基板上形成多个遮光结构，各所述遮光结构在所述中载基板上的正投影位于相邻两个所述发光二极管芯片在所述中载基板上的正投影之间。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述衬底上形成M个所述发光二极管芯片的外延层组之后，所述制作方法还包括：在所述外延层组远离所述衬底的一侧形成M个电极结构；以及将所述外延层组和M个所述电极结构分割以形成M个所述发光二极管芯片。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将所述外延层组和M个所述电极结构分割以形成M个所述发光二极管芯片包括：采用刻蚀工艺将所述外延层组和M个所述电极结构分割以形成M个所述发光二极管芯片。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将N个所述衬底上的N个所述外延层组转移到所述中载基板上包括：将形成有M个所 述发光二极管芯片的所述衬底转移到转移基板上；将所述衬底从所述转移基板上剥离；以及将N个所述转移基板上的N*M个所述发光二极管芯片转移到所述中载基板上，所述转移基板的面积与所述衬底的面积大致相等。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将形成有M个所述发光二极管芯片的所述衬底转移到所述转移基板上包括：在所述转移基板上涂覆第二胶层；以及将形成有M个所述发光二极管芯片的所述衬底转移到所述第二胶层远离所述转移基板的一侧。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第二胶层的材料包括紫外减粘胶或激光解离胶，在将N个所述转移基板上的N*M个所述发光二极管芯片转移到所述中载基板上之后，向所述转移基板照射光线以降低所述第二胶层的粘性，以将所述转移基板移除。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述中载基板包括多个第一支撑结构，各所述第一支撑结构在垂直于所述中载基板的方向上的尺寸大于所述发光二极管芯片在垂直于所述中载基板上的方向上的尺寸，将N个所述转移基板上的N*M个所述发光二极管芯片转移到所述中载基板上包括：依次将N个所述转移基板与所述中载基板对位，以使得多个所述第一支撑结构位于所述转移基板上相邻的两个所述发光二极管芯片之间。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述第一支撑结构为柱状结构，各所述第一支撑结构在所述中载基板上的正投影的形状包括矩形、T字形和圆形中的一种。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述第一支撑结构为柱状结构，各所述第一支撑结构在所述中载基板上的正投影相互连接以形成网格。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到所述驱动基板上包括：将所述中载基板与所述驱动基板对位，以使多个所述第一支撑结构位于所述中载基板和所述驱动基板之间；将第一掩膜板与所述中载基板对位，所述第一掩膜板包括多个开口，所述多个开口对应多个待转移的所述发光二极管芯片；以及通过所述第一掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述驱动基板上。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一掩膜板包括吸光材料，所述吸光材料的光吸收率大于60％。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一掩膜板包括：第一透明基板；以及第一吸光图案层，位于所述第一透明基板上，且包括所述多个开口，所述第一吸光图案层采用所述吸光材料制作，所述吸光材料的光吸收率大于60％。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一掩膜板还包括：第一磁吸结构，位于所述第一透明基板和所述第一吸光图案层之间，所述第一磁吸结构在所述第一透明基板上的正投影与所述多个开口在所述第一透明基板上的正投影间隔设置。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述驱动基板包括多个第一接收结构，将所述中载基板与所述驱动基板对位包括：将所述中载基板上的多个所述第一支撑结构插入所述驱动基板上的多个第一接收结构，多个所述第一支撑结构和多个所述第一接收结构一一对应设置，各所述第一接收结构在垂直于所述驱动基板上的尺寸小于所述发光二极管芯片在垂直于所述驱动基板上的尺寸。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述衬底上形成M个发光二极管芯片的所述外延层组包括：在所述衬底上形成第一导电类型半导体层；在所述第一导电类型半导体层远离所述衬底的一侧形成发光层；以及在所述发光层远离所述第一导电类型半导体层的一侧形成第二导电类型半导体层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述外延层组远离所述衬底的一侧形成M个所述电极结构包括：图案化所述外延组层以暴露部分所述第一导电类型半导体层以形成M个暴露部；在M个所述暴露部远离衬底的一侧形成M个第一电极；在所述第二导电类型半导体层远离所述衬底的一侧形成M个第二电极；在M个所述第一电极和M个所述第二电极远离所述衬底的一侧形成钝化层；图案化所述钝化层以形成在钝化层中与所述第一电极对应的第一过孔和与所述第二电极对应的第二过孔；在所述钝化层远离所述衬底的一侧形成第一电极垫和第二电极垫，所述第一电极垫通过所述第一过孔与所述第一电极相连，所述第二电极垫通过所述第二过孔与所述第二电极相连，各所述导电结构包括一个第一电极、一个第一电极垫、一个第二电极 和一个第二电极垫。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述衬底上形成M个发光二极管芯片的所述外延层组还包括：在所述发光层和所述第二导电类型半导体层之间形成电子阻挡层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述衬底上形成所述第一导电类型半导体层之前，所述制作方法还包括：对所述衬底进行高温处理，并清理所述衬底的表面；以及在所述衬底上形成缓冲层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一导电类型半导体层为n型半导体层，所述第二导电类型半导体层为p型半导体层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一导电类型半导体层为n型氮化镓，所述第二导电类型半导体层为p型氮化镓，所述缓冲层为氮化铝。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到所述驱动基板上包括：提供选取基板，所述选取基板包括多个选取结构；将所述选取基板与所述中载基板对位，多个所述选取结构与多个待转移的所述发光二极管芯片接触；将第二掩膜板与所述中载基板对位，所述第二掩膜板包括多个开口，所述多个开口对应多个所述选取结构；通过所述第二掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述选取基板上的多个所述选取结构上；将所述选取基板和所述驱动基板对位；将所述选取基板上的多个所述选取结构上的多个待转移的所述发光二极管芯片与所述驱动基板键合；以及将多个所述选取结构去除。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第二掩膜板包括吸光材料，所述吸光材料的光吸收率大于60％。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第二掩膜板包括：第二透明基板；以及第二吸光图案层，位于所述第二透明基板上，且包括所述多个开口，所述第二吸光图案层采用所述吸光材料制作，所述吸光材料的光吸收率大于60％。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第二掩膜板还包括：第二磁吸结构，位于所述第二透明基板和所述第二吸光图案层 之间，所述第二磁吸结构在所述第二透明基板上的正投影与所述多个开口在所述第二透明基板上的正投影间隔设置。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述选取结构包括支撑部和位于支撑部远离所述中载基板上的热解部。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将所述选取基板与所述中载基板对位，多个所述选取结构与多个待转移的所述发光二极管芯片接触包括：在真空环境下将所述选取基板与所述中载基板对位；向所述选取基板施加压力以使得所述选取结构中的热解部与对应的所述发光二极管芯片粘附。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，通过所述第二掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述选取基板上的多个所述选取结构上包括：在通过所述第二掩膜板向所述中载基板照射光线之后，向所述选取基板和所述中载基板之间通入惰性气体。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将多个所述选取结构去除包括：在真空环境下进行加热以使得所述热解部熔解，以将多个所述选取结构去除。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述选取结构的材料包括紫外减粘胶或激光解离胶，将多个所述选取结构去除包括：向所述选取基板照射光线，以将多个所述选取结构去除。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述选取结构包括弹性材料。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述选取结构被垂直于所述选取基板的一平面所截取的横截面的形状包括梯形。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述驱动基板包括多个第二支撑结构，各所述第二支撑结构在垂直于所述驱动基板的方向上的尺寸大于所述发光二极管芯片在垂直于所述驱动基板上的方向上的尺寸。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到所述驱动基板上包括：将所述中载基板与所述驱动 基板对位，多个所述第二支撑结构插入所述中载基板上相邻的两个所述发光二极管芯片之间；将第三掩膜板与所述中载基板对位，所述第三掩膜板包括多个开口，所述多个开口对应多个待转移的所述发光二极管芯片；以及通过所述第三掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述驱动基板上。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将N个所述衬底上的N个所述外延层组转移到所述中载基板上包括：将N个所述衬底上的N个所述外延层组依次转移到所述中载基板上；在N个所述外延层组远离所述中载基板的一侧形成M个电极结构；将所述中载基板上的N个所述外延层组分割以与所述M个所述电极结构共同形成M个所述发光二极管芯片。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将所述中载基板上的N个所述外延层组分割以与所述M个所述电极结构组共同形成M个所述发光二极管芯片包括：采用刻蚀工艺将所述中载基板上的N个所述外延层组分割以与所述M个所述电极结构组共同形成M个所述发光二极管芯片。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述衬底上形成M个发光二极管芯片的所述外延层组包括：在所述衬底上形成第一导电类型半导体层；在所述第一导电类型半导体层远离所述衬底的一侧形成发光层；以及在所述发光层远离所述第一导电类型半导体层远离所述衬底的一侧形成第二导电类型半导体层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述衬底上形成所述第一导电类型半导体层之前，所述制作方法还包括：对所述衬底进行高温处理，并清理所述衬底的表面；以及在所述衬底上形成缓冲层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一导电类型半导体层为n型半导体层，所述第二导电类型半导体层为p型半导体层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，所述第一导电类型半导体层为n型氮化镓，所述第二导电类型半导体层为p型氮化镓，所述缓冲层为氮化铝。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述电极结构包括一个第一电极和J个第二电极，在所述外延层组远离所述衬底的一侧形成M个所述电极结构包括：图案化所述外延组层以暴露部分所述第一导 电类型半导体层以形成M个暴露部，并将所述第二导电类型半导体层分割为M*J个第二导电类型半导体块；在M*J个第二导电类型半导体块远离中载基板的一侧形成M*J个第二电极；在M*J个所述第二电极远离所述中载基板的一侧形成钝化层；图案化所述钝化层以形成在钝化层中与M个所述暴露部对应的M个第一过孔、与M*J个所述第二电极对应的M*J个第二过孔；通过M个所述第一过孔在M个所述暴露部远离衬底的一侧形成M个第一电极；以及在所述钝化层远离所述中载基板的一侧形成第一电极垫和第二电极垫，所述第一电极垫通过所述第一过孔与所述第一电极相连，所述第二电极垫通过所述第二过孔与所述第二电极相连，J为大于等于2的正整数。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在所述衬底上形成M个发光二极管芯片的所述外延层组还包括：在所述发光层和所述第二导电类型半导体层之间形成电子阻挡层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在衬底上形成M个所述发光二极管芯片的所述外延层组包括：在圆形的所述衬底上形成M个所述发光二极管芯片的所述外延层组；以及沿着所述外延层组的边缘将圆形的所述衬底切割为方形或六边形的所述衬底，所述外延层组在所述衬底上的正投影的形状为方形或六边形。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将N个所述衬底上的N个所述外延层组转移到所述中载基板上包括：将N个方形或六边形的所述衬底上的N个所述外延层组密集排布在所述中载基板上。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，在衬底上形成M个所述发光二极管芯片的所述外延层组包括：将圆形的所述衬底切割为方形或六边形的所述衬底；将N个方形或六边形的所述衬底拼接在一起，以形成N个所述衬底的组合；在N个所述衬底的组合上形成M*N个所述发光二极管芯片的所述外延层。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，将N个所述衬底上的N个所述外延层组转移到所述中载基板上包括：在N个所述衬底的组合上形成的M*N个所述发光二极管芯片的所述外延层转移到所述中载基板上。
例如，在本公开一实施例提供的发光二极管基板的制作方法中，各所述垫片包括至少两个子垫片，各所述子垫片包括凹槽，所述凹槽被配置为接纳对应 的所述发光二极管芯片的电极垫。
本公开至少一个实施例还提供一种发光二极管基板，其采用上述任一项的制作方法制作。
在本公开一实施例提供的发光二极管基板中，所述驱动基板包括多个接收结构，各所述第一接收结构在垂直于所述驱动基板上的尺寸小于所述发光二极管芯片在垂直于所述驱动基板上的尺寸。
在本公开一实施例提供的发光二极管基板中，该发光二极管基板还包括多个支撑结构，位于相邻的所述发光二极管芯片之间，各所述支撑结构在垂直于驱动基板的方向上的尺寸大于所述发光二极管芯片在垂直于驱动基板的方向上的尺寸。
在本公开一实施例提供的发光二极管基板中，所述驱动基板包括衬底基板和位于衬底基板上的多个驱动电路，各所述驱动电路包括垫片，并被配置为驱动与所述垫片电性相连的所述发光二极管芯片进行发光，各所述垫片包括至少两个子垫片，各所述子垫片包括凹槽，所述凹槽被配置为接纳对应的所述发光二极管芯片的电极垫。
本公开至少一个实施例还提供一种显示装置，包括上述任一项所述的发光二极管基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种发光二极管基板的制作方法的示意图；
图2-图4为本公开一实施例提供的一种发光二极管基板的制作方法的步骤示意图；
图5A-图5C为本公开一实施例提供的一种绑定工艺的步骤示意图；
图6A和图6B为本公开一实施例提供的一种第一胶层的制作方法的步骤示意图；
图6C为本公开一实施例提供的一种将中载基板上的发光二极管芯片转移到驱动基板上的示意图；
图7-图14为本公开一实施例提供的另一种发光二极管基板的制作方法的 步骤示意图；
图15为本公开一实施例提供的一种中载基板的示意图；
图16为本公开一实施例提供的一种第一掩膜板的示意图；
图17为本公开一实施例提供的一种驱动基板上垫片的示意图；
图18A-图18C为本公开一实施例提供的一种第一支撑结构的平面示意图；
图18D为本公开一实施例提供的另一种第一支撑结构的平面示意图；
图19为本公开一实施例提供的一种中载基板和驱动基板进行对位的示意图；
图20A-图20D为本公开一实施例提供的一种第一支撑结构的制作方法的步骤示意图；
图21A-图21D为本公开一实施例提供的另一种第一支撑结构的制作方法的步骤示意图；
图22-图34为本公开一实施例提供的一种发光二极管基板的制作方法的步骤示意图；
图35为本公开一实施例提供的一种选取结构的示意图；
图36A-图36C为本公开一实施例提供的一种选取结构的制作方法的步骤示意图；
图37A-图37D为本公开一实施例提供的另一种选取结构的制作方法的步骤示意图；
图38-图43为本公开一实施例提供的另一种发光二极管基板的制作方法的步骤示意图；
图44为本公开一实施例提供的一种第三掩膜板的示意图；
图45-图50为本公开一实施例提供的另一种发光二极管基板的制作方法的步骤示意图；
图51A-图51C为本公开一实施例提供的一种将N个衬底上的N个外延层组转移到中载基板上的方法的示意图；
图52A-图52C为本公开一实施例提供的另一种将N个衬底上的N个外延层组转移到中载基板上的方法的示意图；
图53为本公开一实施例提供的一种发光二极管基板的示意图；
图54为本公开一实施例提供的另一种发光二极管基板的示意图；
图55为本公开一实施例提供的另一种发光二极管基板的示意图；以及
图56为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常的发光二极管(LED)基板的制作方法包括：先在衬底上制作发光二极管芯片；然后通过巨量转移技术将衬底上的发光二极管芯片转移到驱动基板上。然而，由于衬底的尺寸较小而驱动基板的尺寸较大，因此需要将多个衬底上的发光二极管芯片依次转移到驱动基板上，从而导致转移的效率较低。
本公开实施例提供一种发光二极管基板及其制作方法。该发光二极管基板的制作方法包括：在衬底上形成M个发光二极管芯片的外延层组；将N个衬底上的N个外延层组转移到中载基板上，N个衬底上的N个外延层组密集排列在中载基板上；以及将中载基板上的N个外延层组对应的N*M个发光二极管芯片中至少部分发光二极管芯片转移到驱动基板上。中载基板的面积大于等于N个衬底的面积之和，M为大于等于2的正整数，N为大于等于2的正整数。由此，该发光二极管基板的制作方法通过先将N个衬底上的N个外延层组转移到尺寸更大的中载基板上，并且这些外延层组密集排布在中载基板上，然后再从中载基板上的发光二极管芯片转移到驱动基板上，从而可一次取用更多的发光二极管芯片，甚至一次性取用驱动基板需要的发光二极管芯片，进而可大大提高取用效率和转移效率。
下面，结合附图对本公开实施例提供的发光二极管基板及其制作方法进行 详细的说明。
本公开一实施例提供一种发光二极管基板的制作方法。图1为本公开一实施例提供的一种发光二极管基板的制作方法的示意图。图2-图4为本公开一实施例提供的一种发光二极管基板的制作方法的步骤示意图。
如图1所示，该发光二极管基板的制作方法包括以下步骤S101-S103。
步骤S101：在衬底上形成M个发光二极管芯片的外延层组，M为大于等于2的正整数。
例如，图2示出了本公开一实施例提供的制作方法形成的衬底和衬底上的外延组层；如图2所示，在衬底110上形成外延层组120。例如，上述的外延层组可包括依次生长的第一导电类型半导体层、发光层和第二导电类型半导体层等外延层，这些外延层可构成上述的M个发光二极管芯片的外延层组120。需要说明的是，M可为大于1000的正整数，或者大于10000的正整数。
步骤S102：将N个衬底上的N个外延层组转移到中载基板上，N个衬底上的N个外延层组密集排列在中载基板上，N为大于等于2的正整数。
例如，图3A示出了本公开一实施例提供的制作方法形成的中载基板和中载基板上的外延层组的平面示意图；图3B示出了本公开一实施例提供的制作方法形成的中载基板和中载基板上的外延层组的剖面示意图；如图3A和图3B所示，将6个衬底上的6个外延层组120转移到中载件210上，6个外延层组120密集排列在中载基板210上。当然，为了清楚地进行说明，图3仅示出了6个衬底，但是本公开实施例中的N的具体数值包括但不限于此。
需要说明的是，上述的“密集排布”是指相邻的两个外延层组之间的距离与外延层组分割之后形成的两个相邻的发光二极管芯片之间的距离大致相等。另外，上述的“将N个衬底上的N个外延层组转移到中载基板上”包括将N个衬底上的没有经过分割的N个外延层组转移到中载基板的情况，也包括将N个衬底上的经过分割的N个外延层组(经过分割的N个外延层组可为N*M个发光二极管芯片)转移到中载基板的情况。
步骤S103：将中载基板上的N个外延层组对应的N*M个发光二极管芯片中至少部分发光二极管芯片转移到驱动基板上，中载基板的面积大于等于N个衬底的面积之和。
例如，如图4所示，将中载基板210上的N个外延层组120对应的N*M个发光二极管芯片180中至少部分发光二极管芯片180转移到驱动基板510上。
需要说明的是，当将N个衬底上的N个外延层组转移到中载基板上时，不同的衬底上的外延层组可分割为不同数量的发光二极管芯片，也就是说，不同的衬底上M的具体数值可以不同，这里均采用M仅仅是为了更清楚地对本公开进行解释和说明。例如，上述N的具体数值可为3；第一个衬底上的外延层组可分割为M1个发光二极管芯片，第二个衬底上的外延层组可分割为M2个发光二极管芯片，第三个衬底上的外延层组可分割为M3个发光二极管芯片。此时，上述的N*M可为M1+M2+M3。
在本公开实施例提供的发光二极管基板中，该发光二极管基板的制作方法通过先将N个衬底上的N个外延层组转移到尺寸更大的中载基板上，并且将这些外延层组密集排布在中载基板上；然后，再将中载基板上的发光二极管芯片中选取至少部分转移到驱动基板上。由于N个衬底上的N个外延层组密集排布在中载基板上，因此在将中载基板上的N个外延层组对应的N*M个发光二极管芯片中至少部分发光二极管芯片转移到驱动基板上的过程中，中载基板上的发光二极管芯片是均匀分布的，从而可一次取用更多的发光二极管芯片(大于一个衬底能取用的发光二极管芯片的数量)，甚至一次性取用驱动基板需要的同一颜色的发光二极管芯片，也就是说，驱动基板上同一颜色的发光二极管芯片可仅通过一次转移工艺就可完成。由此，该发光二极管基板的制作方法可大大提高取用效率和转移效率。
在一些示例中，本公开实施例提供发光二极管基板可作为直接进行显示的显示基板，也可作为提供背光源的背光板。当本公开实施例提供的显示基板作为背光板时，上述的衬底可以不用剥离，从而可节省工艺步骤，降低成本。另外，当该发光二极管基板作为背光板时，该发光二极管基板中的发光二极管芯片可为发出同一颜色的光的发光二极管芯片。
在一些示例中，如图3B所示，在中载基板210上，相邻两个外延层组120之间的距离D1与相邻的两个发光二极管芯片180之间的距离D2大致相等。当上述的N值较大时(例如大于等于4)，中载基板上的N个外延层组可阵列排布。
例如，如图3A所示，一个外延层组120的轮廓的形状可大致为矩形，中载基板上的N个外延层组120可阵列排布以组成一个更大的矩形。
在一些示例中，如图4所示，中载基板210的形状与驱动基板510的形状大致相同，中载基板210的面积与驱动基板510的面积大致相等。此时，该发 光二极管基板的制作方法可将驱动基板需要的同种颜色的发光二极管芯片一次性从中载基板转移到驱动基板上，从而可极大地提高取用效率和转移效率。
例如，如图4所示，当中载基板210的形状与驱动基板510的形状大致相同，中载基板210的面积与驱动基板510的面积大致相等时，可先将承载第一颜色发光二极管芯片的中载基板210和驱动基板510对准，然后可一次性将中载基板210上的多个第一颜色发光二极管芯片(例如，红色发光二极管芯片)转移到驱动基板510上对应多个第一颜色发光二极管芯片的多个驱动电路上；然后，将将承载第二颜色发光二极管芯片(例如，绿色发光二极管芯片)的中载基板210和驱动基板510对准，然后可一次性将中载基板210上的多个第二颜色发光二极管芯片转移到驱动基板510上对应多个第二颜色发光二极管芯片的多个驱动电路上；最后，将承载第三颜色发光二极管芯片(例如，蓝色发光二极管芯片)的中载基板210和驱动基板510对准，然后可一次性将中载基板210上的多个第三颜色发光二极管芯片(例如，蓝色发光二极管芯片)转移到驱动基板510上对应多个第三颜色发光二极管芯片的多个驱动电路上。由此，该发光二极管基板的制作方法通过一次转移工艺可将一种颜色的发光二极管芯片转移到驱动基板上，总共通过三次转移工艺就可将所有的发光二极管芯片转移到驱动基板上，从而可大大提高取用效率和转移效率。
在一些示例中，如图4所示，驱动基板510包括衬底基板511和位于衬底基板511上的多个驱动电路514，各驱动电路514包括垫片5142；各驱动电路514被配置为驱动与垫片5142电性相连的发光二极管芯片180进行发光。此时，该发光二极管基板的制作方法还包括：采用绑定工艺将转移到驱动基板510上的发光二极管芯片180与对应的驱动电路514的垫片5142绑定。由此，驱动基板可驱动发光二极管芯片进行发光或显示。
在一些示例中，如图4所示，驱动基板510上驱动电路514的数量与中载基板210上发光二极管芯片180的数量大致相同；驱动基板510上驱动电路514的位置与中载基板210上发光二极管芯片180的位置一一对应设置。由此，当中载基板和驱动基板对准之后，可将中载基板上需要转移的任意数量的发光二极管芯片一次性转移到驱动基板上。
在一些示例中，上述的将N个衬底上的N个外延层组转移到中载基板(即步骤S102)包括：在中载基板210上形成第一胶层220；以及将N个衬底110上的N个外延层组120转移到第一胶层220远离中载基板210的一侧。由此， 该发光二极管基板可通过简单地将第一胶层220解离或者降低第一胶层220的粘性，就可将需要转移的发光二极管芯片180转移到驱动基板510上，从而也可提高转移效率。
例如，第一胶层220的材料包括紫外光减粘胶或激光解离胶；当第一胶层220为紫外光减粘胶时，可通过向中载基板210的部分区域照射紫外光来降低第一胶层220对应区域的粘性，从而使得该区域的发光二极管芯片180脱落，并转移到驱动基板上；当第一胶层220为激光解离胶时，可通过向中载基板210的部分区域照射激光来第一胶层220对应区域解离，从而使得该区域的发光二极管芯片180脱落，并转移到驱动基板上。
例如，将中载基板上的N个外延层组对应的N*M个发光二极管芯片中至少部分发光二极管芯片转移到驱动基板上时，可按照重力的方向，将中载基板设置在驱动基板的上方，即中载基板和驱动基板沿着重力的方向依次设置，从而可利用重力配合上述的紫外光减粘胶或激光解离胶将中载基板上需要转移的发光二极管芯片转移到驱动基板上。
需要说明的是，第一胶层包括但不限于上述的紫外光减粘胶或激光解离胶，第一胶层也可为热解胶；此时，可通过向中载基板的部分区域进行加热来第一胶层对应区域解离，从而使得该区域的发光二极管芯片脱落，并转移到驱动基板上。
在一些示例中，上述的衬底110的尺寸大于等于2英寸。也就是说，上述衬底为单独的一个结晶衬底或者晶圆，而并非一个尺寸较大，且具有多个子发光结构的发光二极管芯片。
例如，上述的衬底可为蓝宝石衬底。当然，本公开实施例包括但不限于此，上述的衬底也可为碳化硅衬底等其他合适的衬底。
图5A-图5C为本公开一实施例提供的一种绑定工艺的步骤示意图。如图5A所示，驱动基板510还包括多个导电凸起518，位于垫片5142远离衬底基板511的一侧，各垫片5142在衬底基板511上的正投影与至少一个导电凸起518在衬底基板511上的正投影交叠，该发光二极管基板的制作方法还包括：将中载基板210上的N个外延层组120对应的N*M个发光二极管芯片180中至少部分发光二极管芯片180转移到驱动基板510上之前，在驱动基板510上涂覆有机绝缘胶材560；采用绑定工艺将转移到驱动基板510上的发光二极管芯片180与对应的驱动电路514的垫片5142绑定包括：如图5B-图5C所示， 对驱动基板510进行热回流，蒸发有机绝缘胶材560中的溶剂，以将发光二极管芯片180与垫片5142键合在一起。
需要说明的是，虽然图5A-图5C示出的多个导电凸起518布满了整个驱动基板510，但是本公开实施例包括但不限于此，导电凸起518也可仅设置在垫片5142上方。另外，多个导电凸起相互绝缘。
例如，导电凸起的材料可为金属、合金或其他导电材料。例如，导电凸起的材料可为铝、银、钼、铜、金中任一种金属或者它们中至少两者组成的合金。当然，本公开实施例包括但不限于此，该导电凸起还可采用其他导电材料。例如，导电凸起在驱动基板上的正投影的尺寸小于垫片在驱动基板上的正投影的尺寸。
例如，衬底基板可为刚性基板或者柔性基板，本公开实施例在此不作限制。另外，衬底基板的材料可为玻璃、石英或者塑料。
例如，导电凸起被垂直于驱动基板的平面所截出的横截面的形状包括：拱形、单尖锥形、梯形、凸台形、或者多尖锥形等。
在一些示例中，上述的导电凸起可采用纳米压印工艺制作。例如，该导电凸起的纳米压印制作方法可包括：形成导电层(例如采用沉积工艺形成金属层)；在导电层上涂布压印胶材；采用具有凹陷结构的模版压印上述的压印胶材；采用紫外光照射固化压印胶材；脱模；采用干刻工艺使压印胶材形成的模版上的结构复制到导电层中。当然，本公开实施例提供的导电凸起也可采用其他方法制作，例如，曝光刻蚀，湿法刻蚀，电化学沉积等。
需要说明的是，为避免导电层的氧化等问题，可以在导电凸起制备完成之后覆盖可导电的防氧化层，但需要去除导电凸起与导电凸起之间的防氧化层，以保证导电凸起相互绝缘。
图6A和图6B为本公开一实施例提供的一种第一胶层的制作方法的步骤示意图。如图6A-图6B所示，在中载基板210上形成第一胶层220包括：在中载基板210上涂覆第一胶材层221；以及图案化第一胶材层211以在所述第一胶材层221中形成贯穿所述第一胶材层221的多个通孔225。包括多个通孔225的第一胶材层221为第一胶层220，各通孔225在中载基板210上的正投影的尺寸小于发光二极管芯片180在中载基板210上的正投影的尺寸。
例如，如图6B所示，多个通孔225在中载基板210上呈矩阵设置。
例如，如图6B所示，各通孔225的形状可为矩形或圆形。当然，本公开 实施例包括但不限于此，各通孔的形状也可采用其他形状。
图6C为本公开一实施例提供的一种将中载基板上的发光二极管芯片转移到驱动基板上的示意图。如图6C所示，当第一胶层220采用如图6B所示的结构时，当对中载基板210进行曝光或者加热时，第一胶层220中的多个通孔225可有效地防止光线或者热量影响非目标区域，从而可提高精准度，并提高产品良率。
图7-图14为本公开一实施例提供的另一种发光二极管基板的制作方法的步骤示意图。
在一些示例中，如图7和图8所示，在衬底110上形成M个发光二极管芯片的外延层组120之后，该发光二极管基板的制作方法还包括：在外延层组120远离衬底110的一侧形成M个电极结构130；以及将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180。也就是说，在该示例中，M个电极结构是在衬底上形成的，并且外延层组和M个电极结构也是在衬底上进行分割以形成M个发光二极管芯片。
在一些示例中，如图7所示，在衬底110上形成M个发光二极管芯片180的外延层组120包括：在衬底110上形成第一导电类型半导体层121；在第一导电类型半导体层121远离衬底110的一侧形成发光层122；以及在发光层122远离第一导电类型半导体层121的一侧形成第二导电类型半导体层123。
例如，第一导电类型半导体层121可为n型半导体层，第二导电类型半导体层123为p型半导体层。当然，本公开实施例包括但不限于此，第一导电类型半导体层121可为p型半导体层，第二导电类型半导体层123为n型半导体层。
例如，第一导电类型半导体层121和第二导电类型半导体层123的材料可选择氮化镓材料。例如，第一导电类型半导体层121可为n型氮化镓层，第二导电类型半导体层123可为p型氮化镓层。当然，本公开实施例包括但不限于此，第一导电类型半导体层121和第二导电类型半导体层123的材料也可选择其他合适的半导体材料。
例如，当上述的发光二极管芯片用于发蓝光或绿光时，第一导电类型半导体层和第二导电类型半导体层可采用上述的氮化镓(GaN)。另外，当该发光二极管芯片用于发红光时，第一导电类型半导体层和第二导电类型半导体层可采用磷化镓(GaP)、砷化铝镓(AlGaAs)或磷化铝镓铟(AlGaInP)。当然， 本公开实施例包括但不限于此，上述的第一导电类型半导体层和第二导电类型半导体层也可采用其他合适的材料制作。
例如，衬底可采用蓝宝石衬底。又例如，该蓝宝石衬底还可包括图形化蓝宝石(Patterned Sapphire Substrate，PSS)层。一方面，图形化蓝宝石层可以有效减少第一导电类型半导体层(即外延层)的位错密度，从而减小非辐射复合，减小反向漏电流，提高该发光二极管芯片的寿命。另一方面，发光层发出的光可在图形化蓝宝石层进行多次散射，改变了全反射光的出射角，从而提高了光的提取效率。当然，本公开实施例包括但不限于此，该发光二极管芯片也可不设置上述的图形化蓝宝石层。需要说明的是，衬底也可采用其他衬底，例如碳化硅衬底。
例如，上述的图形化蓝宝石层可采用干刻工艺制作。当然，本公开实施例包括但不限于此，上述的图形化蓝宝石层也可采用其他合适的方法制作。
在一些示例中，如图7所示，在衬底110上形成M个发光二极管芯片180的外延层组120还包括：在发光层122和第二导电类型半导体层123之间形成电子阻挡层124。电子阻挡层124可阻挡电子进入第二导电类型半导体层123之中，以限制载流子流过，从而可提高发光效率和发光强度。
例如，电子阻挡层124可为p型氮化镓铝(p-AlGaN)。当然，本公开实施例包括但不限于此，电子阻挡层124还可为其他合适的材料。
在一些示例中，如图7所示，在衬底110上形成第一导电类型半导体层121之前，该制作方法还包括：对衬底110进行高温处理，并清理衬底110的表面；以及在衬底110上形成缓冲层140。然后在在缓冲层140远离衬底110的一侧形成第一导电类型半导体层121。通过对衬底进行高温处理和清理，并在衬底上形成缓冲层，可提高晶格匹配程度，便于后续外延层组的生长。
例如，当第一导电类型半导体层为n型氮化镓，第二导电类型半导体层为p型氮化镓时，缓冲层为氮化铝。当然，本公开实施例包括但不限于此，缓冲层可选择任意可以提高晶格匹配程度的材料。
在一些示例中，如图8所示，在外延层组远离所述衬底的一侧形成M个电极结构包括：图案化外延组层120以暴露部分第一导电类型半导体层121以形成M个暴露部1212；在M个暴露部1212远离衬底110的一侧形成M个第一电极150；在第二导电类型半导体层123远离衬底110的一侧形成M个第二电极160；在M个第一电极150和M个第二电极160远离衬底110的一侧形 成钝化层170；图案化钝化层170以形成在钝化层170中与第一电极150对应的第一过孔H1和与第二电极160对应的第二过孔H2；在钝化层170远离衬底110的一侧形成第一电极垫154和第二电极垫164，第一电极垫154通过第一过孔H1与第一电极150相连，第二电极垫164通过第二过孔H2与第二电极160相连。各导电结构130包括一个第一电极150、一个第一电极垫154、一个第二电极160和一个第二电极垫164。
例如，在该发光二极管基板的制作方法中，在图案化外延组层120以暴露部分第一导电类型半导体层121以形成M个暴露部1212之后，可在第二导电类型半导体层123和暴露部1212远离衬底110的一侧形成第一导电层，然后对第一导电层进行图案化以形成上述的第一电极150和第二电极160；第一电极150与暴露部1212接触设置，第二电极160与第二导电类型半导体层123接触设置，第一电极150和第二电极160相互绝缘。
例如，在该发光二极管基板的制作方法中，在图案化钝化层170以形成在钝化层170中与第一电极150对应的第一过孔H1和与第二电极160对应的第二过孔H2之后，可在钝化层170远离衬底110的一侧形成第二导电层，然后对第二导电层进行图案化以形成上述的第一电极垫154和第二电极垫164。
例如，将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180包括：采用刻蚀工艺将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180。当然，本公开实施例包括但不限于此，也可采用其他工艺进行分割。
例如，如图8所示，在衬底110上形成外延层组120的同时，可在衬底110上形成第一对位标记710。本公开实施例对于第一对位标记的制作方法不作限定。
在一些示例中，如图9-11所示，将N个衬底110上的N个外延层组120转移到中载基板210上包括：将形成有M个发光二极管芯片180的衬底110转移到转移基板310上；将衬底110从转移基板310上剥离；以及将N个转移基板310上的N*M个发光二极管芯片180转移到中载基板210上，转移基板310的面积与衬底110的面积大致相等。也就是说，该发光二极管基板的制作方法先将衬底上的发光二极管芯片转移到一个面积大致相等的转移基板上，然后再将N个转移基板上的N*M个发光二极管芯片转移到中载基板上，从而实现将N个衬底上的N个外延层组转移到中载基板上。另外，由于经过两次转 移，在中载基板上的发光二极管芯片的电极结构位于发光二极管芯片远离中载基板的一侧；因此，中载基板上的发光二极管芯片可方便直接地从中载基板上转移到驱动基板上，并且发光二极管芯片的电极结构也可方便地与驱动基板上的垫片绑定。
在一些示例中，如图9所示，将形成有M个发光二极管芯片180的衬底110转移到转移基板310上包括：在转移基板310上涂覆第二胶层320；以及将形成有M个发光二极管芯片180的衬底110转移到第二胶层320远离转移基板310的一侧。该发光二极管基板的制作方法可通过第二胶层320将M个发光二极管芯片180粘附在转移基板310上，此时发光二极管芯片180的电极结构130位于该发光二极管芯片180靠近第二胶层320的一侧。另外，由于是采用第二胶层320将M个发光二极管芯片180粘附在转移基板310上，在后续的转移步骤中可方便地进行转移，从而可提高转移效率并降低成本。
在一些示例中，如图9和图10所示，在将形成有M个发光二极管芯片180的衬底110转移到转移基板310上的过程中，先将衬底110与转移基板310进行对位；然后衬底110向转移基板310移动，并与第二胶层320接触，此时，第二胶层320可将衬底110上的发光二极管芯片180粘附。
例如，如图10所示，在将形成有M个发光二极管芯片180的衬底110转移到转移基板310上之后，衬底110上形成的第一对位标记710也被转移到转移基板310上。
在一些示例中，第二胶层320的材料包括紫外减粘胶或激光解离胶，在将N个转移基板310上的N*M个发光二极管芯片180转移到中载基板210上之后，可向转移基板310照射光线以降低第二胶层320的粘性，以将转移基板310移除。由此，该发光二极管基板的制作方法可方便地将发光二极管芯片180进行转移，并将转移基板310移除。
例如，当第二胶层320为紫外光减粘胶时，可通过向转移基板310照射紫外光来降低第二胶层320的粘性，从而使得转移基板310上的发光二极管芯片180脱落，并转移到驱动基板510上；当第二胶层320为激光解离胶时，可通过向转移基板310照射激光来第二胶层320解离，从而使得转移基板310上的发光二极管芯片180脱落，并转移到驱动基板510上。
需要说明的是，本公开实施例提供的第二胶层的材料包括也不限于上述的紫外光减粘胶和激光解离胶，第二胶层也可为热解胶。
在一些示例中，如图9和图10所示，将衬底110从转移基板310上剥离可包括：采用减薄工艺从衬底110远离转移基板310的一侧将衬底110减薄，然后采用激光剥离(LLO)工艺将减薄后的衬底110从转移基板310上剥离。
例如，如图9所示，可采用激光光源900从衬底110远离转移基板310的一侧照射激光，使得缓冲层140分解，从而将衬底110剥离。需要说明的是，激光光源900可采用面光源，也可采用线光源；当该激光光源900采用线光源时，可通过移动激光光源900进行扫描，来完成曝光。
在一些示例中，如图11所示，中载基板210包括多个第一支撑结构240，各第一支撑结构240在垂直于中载基板210的方向上的尺寸大于发光二极管芯片180在垂直于中载基板210的方向上的尺寸，将N个转移基板310上的N*M个发光二极管芯片180转移到中载基板210上包括：依次将N个转移基板310与中载基板210对位，以使得多个第一支撑结构240位于转移基板310上相邻的两个发光二极管芯片180之间。此时，第一支撑结构240不仅可以起到支撑相对设置的中载基板210和转移基板310之间的间隔，并使得中载基板210和转移基板310之间的间隔均一，另外还可起到缓冲的作用。
例如，各第一支撑结构240在垂直于中载基板210的方向上的尺寸范围为3-10微米。当然，本公开实施例包括但不限于此。
例如，如图11所示，可采用转移装置800(例如，转移头)将转移基板310移动到中载基板210上方，以与中载基板210进行对位。
在一些示例中，如图11所示，在转移基板310与中载基板210对位之后，转移基板310可向中载基板210移动，并与中载基板210上的第一胶层220接触；第一胶层220可将转移基板310上的发光二极管芯片180粘附；然后，通过向转移基板310照射紫外光或激光以降低第二胶层320的粘性，或者向转移基板310进行加热以降低第二胶层320的粘性，从而使得转移基板310上的发光二极管芯片180可转移到中载基板210上，并且将转移基板310剥离。
例如，中载基板的材料可为玻璃基板，从而可降低成本。
例如，中载基板的平面形状可为矩形，例如300mm*300mm的正方形、500mm*500mm的正方形、450mm*550mm的长方形(2.5代线)、或者2200mm*2500mm的长方形(8.5代线)。当然，本公开实施例提供的中载基板的平面形状和尺寸包括但不限于此。
在一些示例中，该发光二极管基板的制作方法可采用对位机台、高精度对 位装置、感光装置(CCD)来实现将转移基板和中载基板进行对位；另外，该发光二极管基板的制作方法可采用清洗装置对残留在中载基板上的第二胶层的胶材进行清洗，避免胶材影响后续的工艺。
例如，如图11所示，中载基板210还可包括第二对位标记720；此时，上述的感光装置(CCD)可根据转移基板上的第一对位标记和中载基板上的第二对位标记的位置进行识别、记录、计算、并反馈给高精度对位单元，以保证对位实现和精度。
例如，上述的对位机台可具有在三个轴向进行移动的功能，从而便于进行对位；另外，上述的对位机台还可包括真空吸附功能，从而更好地将中载基板进行吸附和固定。
例如，上述的对位机台还可包括归正对位功能，以实现对中载基板的初始位置归正；另外，上述的对位机台还可具备顶升和下降结构，以实现中载基板的自动化上下料功能。
在一些示例中，如图12-图14所示，将中载基板210上的N个外延层组120对应的N*M个发光二极管芯片180中至少部分发光二极管芯片180转移到驱动基板510上包括：如图12所示，将中载基板210与驱动基板510对位，以使多个第一支撑结构240位于中载基板210和驱动基板510之间；如图13所示，将第一掩膜板610与中载基板210对位，第一掩膜板610包括多个开口615，多个开口615对应多个待转移的发光二极管芯片180；以及通过第一掩膜板610向中载基板210照射光线，以将多个待转移的发光二极管芯片180转移到驱动基板510上。如图14所示，将中载基板210与驱动基板510分离。需要说明的是，N个外延层组对应的N*M个发光二极管芯片是指N个外延层组可以形成的N*M个发光二极管芯片。
例如，第一掩膜板610包括吸光材料，吸光材料的光吸收率大于60％。由此，第一掩膜板可有效地避免对光线造成反射，从而避免反射后的光线再次进入中载基板的非目标区域。
例如，如图13所示，中载基板210涂覆有第一胶层220；当通过第一掩膜板610向中载基板210照射光线时，光线(例如紫外光或者激光)通过第一掩膜板610的开口615照射到中载基板210上对应的区域；此时，该区域对应的第一胶层220的粘性减弱，或者，该区域对应的第一胶层220解离，从而使得待转移的发光二极管芯片180从中载基板210上脱落并落在驱动基板510上。
例如，第一胶层220的材料包括紫外光减粘胶或激光解离胶；当第一胶层220为紫外光减粘胶时，可通过向中载基板210的部分区域照射紫外光来降低第一胶层220对应区域的粘性，从而使得该区域的发光二极管芯片180脱落，并转移到驱动基板上；当第一胶层220为第一激光解离胶时，可通过向中载基板210的部分区域照射激光来第一胶层220对应区域解离，从而使得该区域的发光二极管芯片180脱落，并转移到驱动基板上。
需要说明的是，第一胶层包括但不限于上述的紫外光减粘胶或激光解离胶，第一胶层也可为热解胶；此时，可通过向中载基板的部分区域进行加热来第一胶层对应区域解离，从而使得该区域的发光二极管芯片脱落，并转移到驱动基板上。
在一些示例中，第一胶层220可采用如图6B所示的结构，即包括阵列设置的多个通孔225。由此，由于第一胶层包括多个通孔，即第一胶层是图案化的，所以每个发光二极管芯片对应的第一胶层是相对独立的。在向中载基板210的特定区域照射光线或者加热时，该特定区域之外(即非目标区域)的第一胶层不会受到影响，从而可防止不该转移的发光二极管芯片被转移，从而可提高产品良率。
图15为本公开一实施例提供的一种中载基板的示意图。如图15所示，在该发光二极管基板的制作方法中，将N个衬底110上的N个外延层组120转移到中载基板210还包括：在中载基板210上形成第一胶层220之前，在中载基板210上形成多个遮光结构260，各遮光结构260在中载基板210上的正投影位于相邻两个发光二极管芯片180在中载基板210上的正投影之间。由此，遮光结构260可遮挡经过中载基板的杂散光，防止杂散光照射到第一掩膜板遮挡的区域，从而可高精度地转移发光二极管芯片，并且可提高产品良率。
例如，遮光结构260的尺寸小于相邻的发光二极管芯片180之间的间隔的尺寸。
在一些示例中，遮光结构可与第一支撑结构同时存在，遮光结构可位于第一支撑结构靠近中载基板的一侧。当然，本公开实施例包括但不限于此，第一支撑结构可采用遮光材料制作，从而起到遮光结构的作用。
例如，遮光结构可采用光刻工艺制作；例如，可先在中载基板上制作整层遮光层，再通过光刻工艺实现图案化的遮光结构，本公开实施例在此不再赘述。
图16为本公开一实施例提供的一种第一掩膜板的示意图。如图16所示， 第一掩膜板610包括第一透明基板611和第一吸光图案层612；第一吸光图案层612位于第一透明基板611上，且包括多个开口615；第一吸光图案层612包括吸光材料，吸光材料的光吸收率大于60％。
例如，如图16所示，第一掩膜板610还包括：第一磁吸结构613，位于第一透明基板611和第一吸光图案层612之间，第一磁吸结构613在第一透明基板611上的正投影与多个开口615在第一透明基板611上的正投影间隔设置。由此，第一磁吸结构613可被吸附固定，从而可提高第一掩膜板在曝光过程中的平坦性，从而提高曝光精准度。
例如，上述的第一磁吸结构可采用镍、铁镍合金等材料制作，从而具有一定磁性，可被电磁铁吸附。
例如，上述的第一磁吸结构的平面形状可为网格结构。
例如，如图16所示，第一掩膜板610还包括：第一保护层614，位于第一吸光图案层612远离第一透明基板611的一侧。第一保护层614可为透明保护层，从而不影响光线的透过。当然，本公开实施例包括但不限于此，第一保护层也可为不透明的；此时，第一保护层可在第一掩膜板使用时剥离。
例如，上述的第一透明基板可采用高硬度和高厚度的石英或氧化硅玻璃进行制作，从而可减小掩膜板因重力导致的变形量。
在一些示例中，如图14所示，驱动基板510包括多个驱动电路514，各驱动电路514包括垫片5142；各驱动电路514被配置为驱动与垫片5142电性相连的发光二极管芯片180进行发光。此时，该发光二极管基板的制作方法还包括：采用绑定工艺将转移到驱动基板510上的发光二极管芯片180与对应的驱动电路514的垫片5142绑定；例如，将发光二极管芯片180的第一电极垫154和第二电极垫164分别与对应的驱动电路514的垫片5142绑定。由此，驱动基板可驱动发光二极管芯片进行发光或显示。
在一些示例中，如图14所示，驱动基板510上驱动电路514的数量与中载基板210上发光二极管芯片180的数量大致相同；驱动基板510上驱动电路514的位置与中载基板210上发光二极管芯片180的位置一一对应设置。由此，当中载基板和驱动基板对准之后，可将中载基板上需要转移的任意数量的发光二极管芯片一次性转移到驱动基板上。
图17为本公开一实施例提供的一种驱动基板上垫片的示意图。如图17所示，各垫片5142包括至少两个子垫片5140，各子垫片5140包括凹槽5140A， 凹槽5140A被配置为接纳对应的发光二极管芯片180的电极垫154或164。
在一些示例中，如图12-图14所示，各第一支撑结构240为柱状结构。
在一些示例中，各第一支撑结构240在中载基板210上的正投影的形状包括矩形、T字形和圆形中的至少一种。
图18A-图18C为本公开一实施例提供的一种第一支撑结构的平面示意图。如图18A所示，各第一支撑结构240在中载基板210上的正投影的形状包括矩形；如图18B所示，各第一支撑结构240在中载基板210上的正投影的形状包括T字形；如图18C所示，各第一支撑结构240在中载基板210上的正投影的形状包括圆形。当然，本公开实施例包括但不限于上述的几种情况，各第一支撑结构在中载基板上的正投影的形状还可为其他形状。
图18D为本公开一实施例提供的另一种第一支撑结构的平面示意图。如图18D所示，各第一支撑结构240为柱状结构，第一支撑结构240在中载基板210上的正投影相互连接以形成网格。
图19为本公开一实施例提供的一种中载基板和驱动基板进行对位的示意图。如图19所示，驱动基板510包括多个第一接收结构550，将中载基板210与驱动基板510对位包括：将中载基板210上的多个第一支撑结构240插入驱动基板510上的多个第一接收结构550，多个第一支撑结构240和多个第一接收结构550一一对应设置，各第一接收结构240在垂直于驱动基板510上的尺寸小于发光二极管芯片180在垂直于驱动基板510上的尺寸。由此，通过多个第一支撑结构和多个第一接收结构可提高中载基板和驱动基板之间的对位精度。
图20A-图20D为本公开一实施例提供的一种第一支撑结构的制作方法的步骤示意图。如图20A所示，在中载基板210上形成第二对位标记720；如图20B所示，在中载基板210上形成支撑材料层245，支撑材料层245的在垂直于中载基板210的方向上的尺寸大于发光二极管芯片180在垂直于中载基板210的方向上的尺寸；如图20C所示，图案化支撑材料层245以形成多个第一支撑物240，多个第一支撑物240的周期和大小可根据转移基板310上的发光二极管芯片180之间的间距和发光二极管芯片180的大小相关，各第一支撑物240的大小小于发光二极管芯片180之间的间距；如图20D所示，在多个第一支撑物240之间形成上述的第一胶层220。
图21A-图21D为本公开一实施例提供的另一种第一支撑结构的制作方法 的步骤示意图。如图21A所示，在中载基板210上形成第二对位标记720；如图21B所示，在中载基板210上形成上述的第一胶层220；如图21C所示，在第一胶层220远离中载基板210的一侧形成支撑材料层245，支撑材料层245的在垂直于中载基板210的方向上的尺寸大于发光二极管芯片180在垂直于中载基板210的方向上的尺寸；如图21D所示，图案化支撑材料层245以形成多个第一支撑物240，多个第一支撑物240的周期和大小可根据转移基板310上的发光二极管芯片180之间的间距和发光二极管芯片180的大小相关，各第一支撑物240的大小小于发光二极管芯片180之间的间距。
需要说明的是，上述的第一支撑结构也可以通过上述工艺制作在转移基板上，其作用与制作在中载基板上相同，然后在将转移基板上发光二极管芯片转移到中载基板上时，将第一支撑结构也同步转移到了中载基板上。
例如，上述的支撑材料层可为光学胶层或者树脂等有机材料层。
图22-图34为本公开一实施例提供的一种发光二极管基板的制作方法的步骤示意图。
在一些示例中，如图22和图23所示，在衬底110上形成M个发光二极管芯片的外延层组120之后，该发光二极管基板的制作方法还包括：在外延层组120远离衬底110的一侧形成M个电极结构130；以及将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180。也就是说，在该示例中，M个电极结构是在衬底上形成的，并且外延层组和M个电极结构也是在衬底上进行分割以形成M个发光二极管芯片。
在一些示例中，如图22所示，在衬底110上形成M个发光二极管芯片180的外延层组120包括：在衬底110上形成第一导电类型半导体层121；在第一导电类型半导体层121远离衬底110的一侧形成发光层122；以及在发光层122远离第一导电类型半导体层121远离衬底110的一侧形成第二导电类型半导体层123。
例如，第一导电类型半导体层121可为n型半导体层，第二导电类型半导体层123为p型半导体层。当然，本公开实施例包括但不限于此，第一导电类型半导体层121可为p型半导体层，第二导电类型半导体层123为n型半导体层。
例如，第一导电类型半导体层121和第二导电类型半导体层123的材料可选择氮化镓材料。例如，第一导电类型半导体层121可为n型氮化镓层，第二 导电类型半导体层123可为p型氮化镓层。另外，当该发光二极管芯片用于发红光时，第一导电类型半导体层和第二导电类型半导体层可采用磷化镓(GaP)、砷化铝镓(AlGaAs)或磷化铝镓铟(AlGaInP)。当然，本公开实施例包括但不限于此，上述的第一导电类型半导体层和第二导电类型半导体层也可采用其他合适的材料制作。
例如，衬底可采用蓝宝石衬底。又例如，该蓝宝石衬底还可包括图形化蓝宝石(Patterned Sapphire Substrate，PSS)层。一方面，图形化蓝宝石层可以有效减少第一导电类型半导体层(即外延层)的位错密度，从而减小非辐射复合，减小反向漏电流，提高该发光二极管芯片的寿命。另一方面，发光层发出的光可在图形化蓝宝石层进行多次散射，改变了全反射光的出射角，从而提高了光的提取效率。当然，本公开实施例包括但不限于此，该发光二极管芯片也可不设置上述的图形化蓝宝石层。需要说明的是，衬底也可采用其他衬底，例如碳化硅衬底。
例如，上述的图形化蓝宝石层可采用干刻工艺制作。当然，本公开实施例包括但不限于此，上述的图形化蓝宝石层也可采用其他合适的方法制作。
在一些示例中，如图22所示，在衬底110上形成M个发光二极管芯片180的外延层组120还包括：在发光层122和第二导电类型半导体层123之间形成电子阻挡层124。电子阻挡层124可阻挡电子进入第二导电类型半导体层123之中，以限制载流子流过，从而可提高发光效率和发光强度。
例如，电子阻挡层124可为p型氮化镓铝(p-AlGaN)。当然，本公开实施例包括但不限于此，电子阻挡层124还可为其他合适的材料。
在一些示例中，如图22所示，在衬底110上形成第一导电类型半导体层121之前，该制作方法还包括：对衬底110进行高温处理，并清理衬底110的表面；以及在衬底110上形成缓冲层140。然后，可在缓冲层140远离衬底110的一侧形成第一导电类型半导体层121。通过对衬底进行高温处理和清理，并在衬底上形成缓冲层，可提高晶格匹配程度，便于后续外延层组的生长。
例如，当第一导电类型半导体层为n型氮化镓，第二导电类型半导体层为p型氮化镓时，缓冲层为氮化铝。当然，本公开实施例包括但不限于此，缓冲层可选择任意可以提高晶格匹配程度的材料。
在一些示例中，如图23所示，在外延层组远离所述衬底的一侧形成M个所述电极结构包括：图案化外延组层120以暴露部分第一导电类型半导体层 121以形成M个暴露部1212；在M个暴露部1212远离衬底110的一侧形成M个第一电极150；在第二导电类型半导体层123远离衬底110的一侧形成M个第二电极160；在M个第一电极150和M个第二电极160远离衬底110的一侧形成钝化层170；图案化钝化层170以形成在钝化层170中与第一电极150对应的第一过孔H1和与第二电极160对应的第二过孔H2；在钝化层170远离衬底110的一侧形成第一电极垫154和第二电极垫164，第一电极垫154通过第一过孔H1与第一电极150相连，第二电极垫164通过第二过孔H2与第二电极160相连。各导电结构130包括一个第一电极150、一个第一电极垫154、一个第二电极160和一个第二电极垫164。
例如，在该发光二极管基板的制作方法中，在图案化外延组层120以暴露部分第一导电类型半导体层121以形成M个暴露部1212之后，可在第二导电类型半导体层123和暴露部1212远离衬底110的一侧形成第一导电层，然后对第一导电层进行图案化以形成上述的第一电极150和第二电极160；第一电极150与暴露部1212接触设置，第二电极160与第二导电类型半导体层123接触设置，第一电极150和第二电极160相互绝缘。
例如，在该发光二极管基板的制作方法中，在图案化钝化层170以形成在钝化层170中与第一电极150对应的第一过孔H1和与第二电极160对应的第二过孔H2之后，可在钝化层170远离衬底110的一侧形成第二导电层，然后对第二导电层进行图案化以形成上述的第一电极垫154和第二电极垫164。
例如，将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180包括：采用刻蚀工艺将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180。当然，本公开实施例包括但不限于此，也可采用其他工艺进行分割。
例如，如图23所示，在衬底110上形成外延层组120的同时，可在衬底110上形成第一对位标记710。本公开实施例对于第一对位标记的制作方法不作限定。
在一些示例中，如图24-图26所示，该发光二极管基板的制作方法包括：将N个衬底110上的N个外延层组120转移到中载基板210上，N个衬底110上的N个外延层组120密集排列在中载基板210上。
例如，如图24所示，在中载基板210形成第一胶层220；然后可采用转移装置800(例如，转移头)将衬底110和衬底110上的发光二极管芯片180移 动到中载基板210上方，以与中载基板210进行对位。此时，发光二极管芯片180位于衬底110和中载基板210之间，并且发光二极管芯片180的电极结构130位于发光二极管芯片180靠近中载基板210的一侧。
例如，如图25所示，将衬底110向中载基板210移动，使得发光二极管芯片180与中载基板210上的第一胶层220接触；此时，第一胶层220可将发光二极管芯片180粘附。
例如，如图26所示，从衬底110远离中载基板210的一侧对衬底110照射激光，使得衬底110上的缓冲层140分解，从而使得衬底110上发光二极管芯片180转移到中载基板210上，并可将衬底110剥离。
例如，中载基板的材料可为玻璃基板，从而可降低成本。
例如，中载基板的平面形状可为矩形，例如300mm*300mm的正方形、500mm*500mm的正方形、450mm*550mm的长方形(2.5代线)、或者2200mm*2500mm的长方形(8.5代线)。当然，本公开实施例提供的中载基板的平面形状和尺寸包括但不限于此。
在一些示例中，该发光二极管基板的制作方法可采用对位机台、高精度对位装置、感光装置(CCD)来实现将转移基板和中载基板进行对位；另外，该发光二极管基板的制作方法可采用清洗装置对残留在中载基板上的第二胶层的胶材进行清洗，避免胶材影响后续的工艺。
例如，如图26所示，中载基板210还可包括第二对位标记720；此时，上述的感光装置(CCD)可根据转移基板上的第一对位标记和中载基板上的第二对位标记的位置进行识别、记录、计算、并反馈给高精度对位单元，以保证对位实现和精度。
例如，上述的对位机台可具有在三个轴向进行移动的功能，从而便于进行对位；另外，上述的对位机台还可包括真空吸附功能，从而更好地将中载基板进行吸附和固定。
例如，上述的对位机台还可包括归正对位功能，以实现对中载基板的初始位置归正；另外，上述的对位机台还可具备顶升和下降结构，以实现中载基板的自动化上下料功能。
在一些示例中，如图27-图33所示，将中载基板210上的N个外延层组120对应的N*M个发光二极管芯片180中至少部分发光二极管芯片180转移到驱动基板510上包括：如图27所示，提供选取基板410，选取基板410包括 多个选取结构420；如图28所示，将选取基板410与中载基板210对位，多个选取结构420与多个待转移的发光二极管芯片180接触；如图29所示，将第二掩膜板620与中载基板210对位，第二掩膜板620包括多个开口625，多个开口625对应多个选取结构420；如图29-图30所示，通过第二掩膜板620向中载基板210照射光线，以将多个待转移的发光二极管芯片180转移到选取基板410上的多个选取结构420上；如图31所示，将选取基板410和驱动基板510对位；如图32所示，将选取基板410上的多个选取结构420上的多个待转移的发光二极管芯片180与驱动基板510键合；如图33所示，将多个选取结构420去除。由此，该发光二极管基板的制作方法可通过选取基板和选取基板上的选取结构将中载基板上的发光二极管芯片转移到驱动基板上。
例如，第二掩膜板620采用吸光材料制作，吸光材料的光吸收率大于60％。由此，第二掩膜板可有效地避免对光线造成反射，从而避免反射后的光线再次进入选取基板的非目标区域。
图34为本公开一实施例提供的一种第二掩膜板的示意图。如图34所示，第二掩膜板620包括：第二透明基板621和第二吸光图案层622；第二吸光图案层622位于第二透明基板621上，且包括多个开口625，第二吸光图案层622采用吸光材料制作，吸光材料的光吸收率大于60％。
例如，如图34所示，第二掩膜板620还包括：第二磁吸结构623，位于第二透明基板621和第二吸光图案层622之间，第二磁吸结构623在第二透明基板621上的正投影与多个开口625在第二透明基板621上的正投影间隔设置。由此，第二磁吸结构623可被吸附固定，从而可提高第二掩膜板在曝光过程中的平坦性，从而提高曝光精准度。
例如，上述的第二磁吸结构可采用镍、铁镍合金等材料制作，从而具有一定磁性，可被电磁铁吸附。
例如，上述的第二磁吸结构的平面形状可为网格结构。
例如，如图34所示，第二掩膜板620还包括：第二保护层624，位于第一吸光图案层622远离第一透明基板621的一侧。第二保护层624可为透明保护层，从而不影响光线的透过。当然，本公开实施例包括但不限于此，第二保护层也可为不透明的；此时，第二保护层可在第二掩膜板使用时剥离。
例如，上述的第二透明基板可采用高硬度和高厚度的石英或氧化硅玻璃进行制作，从而可减小掩膜板因重力导致的变形量。
在一些示例中，如图27所示，选取基板410还包括第三对位标记730，此时，可利用第三对位标记70将选取基板410与中载基板210对位，并使得多个选取结构420与多个待转移的发光二极管芯片180接触。当选取结构420与发光二极管芯片180接触时，选取结构420可将发光二极管芯片180粘附。
图35为本公开一实施例提供的一种选取结构的示意图。如图35所示，各选取结构420包括支撑部422和位于支撑部425远离选取基板410上的热解部425。
在一些示例中，当选取结构420采用如图35所示的结构时，将选取基板410与中载基板210对位，多个选取结构420与多个待转移的发光二极管芯片180接触包括：在真空环境下将选取基板410与中载基板210对位；向选取基板410施加压力以使得选取结构420中的热解部425与对应的发光二极管芯片180粘附。
在一些示例中，通过第二掩膜板620向中载基板210照射光线，以将多个待转移的发光二极管芯片180转移到选取基板410上的多个选取结构420上包括：在通过第二掩膜板620向中载基板210照射光线之后，向选取基板410和中载基板210之间通入惰性气体。
在一些示例中，将多个选取结构420去除包括：在真空环境下进行加热以使得热解部425熔解，以将多个选取结构420去除。
在一些示例中，各选取结构420的材料包括紫外减粘胶或激光解离胶，将多个选取结构420去除包括：向选取基板照射光线，以将多个选取结构去除。
在一些示例中，各选取结构420远离选取基板410的表面与发光二极管芯片180在选取基板410上的正投影的面积大致相等，从而可更好地将发光二极管芯片180选取。
在一些示例中，各选取结构包括弹性材料，从而可提供一定的缓冲，提高产品良率。
在一些示例中，各选取结构被垂直于选取基板的一平面所截取的横截面的形状包括梯形。当然，本公开实施例包括但不限于此，各选取结构被垂直于选取基板的一平面所截取的横截面的形状也可为其他形状。
图36A-图36C为本公开一实施例提供的一种选取结构的制作方法的步骤示意图。如图36A所示，在选取基板410上制作第三对位标记730；如图36B所示，在选取基板410上形成第一选取胶材层425，第一选取胶材层425的厚 度大于发光二极管芯片180的厚度，即第一选取胶材层425在垂直于选取基板410的方向上的尺寸大于发光二极管芯片180在垂直于选取基板410的方向上的尺寸；如图36C，对第一选取胶材层425进行图案化，以形成上述的选取结构420。
图37A-图37D为本公开一实施例提供的另一种选取结构的制作方法的步骤示意图。如图37A所示，在选取基板410上制作第三对位标记730；如图37B所示，在选取基板410上形成选取材料层430；如图37C所示，将选取材料层430图案化以形成多个凸起结构435；如图37D所示，在多个凸起结构435远离选取基板410的一侧形成第二选取胶材层427，此时各凸起结构435和凸起结构435上的第二选取胶材层427可组成一个选取结构420。
例如，上述的第一选取胶材层425和第二选取胶材层427的材料可为紫外光减粘材料或者激光解离材料。当然，本公开实施例包括但不限于此，上述的第一选取胶材层425和第二选取胶材层427的材料也可为热解材料。
例如，上述的选取材料层430可为光学胶或者树脂等有机材料。
图38-图43为本公开一实施例提供的另一种发光二极管基板的制作方法的步骤示意图。
在一些示例中，如图38和图39所示，在衬底110上形成M个发光二极管芯片的外延层组120之后，该发光二极管基板的制作方法还包括：在外延层组120远离衬底110的一侧形成M个电极结构130；以及将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180。也就是说，在该示例中，M个电极结构是在衬底上形成的，并且外延层组和M个电极结构也是在衬底上进行分割以形成M个发光二极管芯片。
在一些示例中，如图38所示，在衬底110上形成M个发光二极管芯片180的外延层组120包括：在衬底110上形成第一导电类型半导体层121；在第一导电类型半导体层121远离衬底110的一侧形成发光层122；以及在发光层122远离第一导电类型半导体层121的一侧形成第二导电类型半导体层123。
例如，第一导电类型半导体层121可为n型半导体层，第二导电类型半导体层123为p型半导体层。当然，本公开实施例包括但不限于此，第一导电类型半导体层121可为p型半导体层，第二导电类型半导体层123为n型半导体层。
例如，第一导电类型半导体层121和第二导电类型半导体层123的材料可 选择氮化镓材料。例如，第一导电类型半导体层121可为n型氮化镓层，第二导电类型半导体层123可为p型氮化镓层。当然，本公开实施例包括但不限于此，第一导电类型半导体层121和第二导电类型半导体层123的材料也可选择其他合适的半导体材料。
例如，衬底可采用蓝宝石衬底。又例如，该蓝宝石衬底还可包括图形化蓝宝石(Patterned Sapphire Substrate，PSS)层。一方面，图形化蓝宝石层可以有效减少第一导电类型半导体层(即外延层)的位错密度，从而减小非辐射复合，减小反向漏电流，提高该发光二极管芯片的寿命。另一方面，发光层发出的光可在图形化蓝宝石层进行多次散射，改变了全反射光的出射角，从而提高了光的提取效率。当然，本公开实施例包括但不限于此，该发光二极管芯片也可不设置上述的图形化蓝宝石层。需要说明的是，衬底也可采用其他衬底，例如碳化硅衬底。
例如，上述的图形化蓝宝石层可采用干刻工艺制作。当然，本公开实施例包括但不限于此，上述的图形化蓝宝石层也可采用其他合适的方法制作。
在一些示例中，如图38所示，在衬底110上形成M个发光二极管芯片180的外延层组120还包括：在发光层122和第二导电类型半导体层123之间形成电子阻挡层124。电子阻挡层124可阻挡电子进入第二导电类型半导体层123之中，以限制载流子流过，从而可提高发光效率和发光强度。
例如，电子阻挡层124可为p型氮化镓铝(p-AlGaN)。当然，本公开实施例包括但不限于此，电子阻挡层124还可为其他合适的材料。
在一些示例中，如图38所示，在衬底110上形成第一导电类型半导体层121之前，该制作方法包括：对衬底110进行高温处理，并清理衬底110的表面；以及在衬底110上形成缓冲层140。然后，可在缓冲层140远离衬底110的一侧形成第一导电类型半导体层121。通过对衬底进行高温处理和清理，并在衬底上形成缓冲层，可提高晶格匹配程度，便于后续外延层组的生长。
例如，当第一导电类型半导体层为n型氮化镓，第二导电类型半导体层为p型氮化镓时，缓冲层为氮化铝。当然，本公开实施例包括但不限于此，缓冲层可选择任意可以提高晶格匹配程度的材料。
在一些示例中，如图39所示，在外延层组远离所述衬底的一侧形成M个所述电极结构包括：图案化外延组层120以暴露部分第一导电类型半导体层121以形成M个暴露部1212；在M个暴露部1212远离衬底110的一侧形成M 个第一电极150；在第二导电类型半导体层123远离衬底110的一侧形成M个第二电极160；在M个第一电极150和M个第二电极160远离衬底110的一侧形成钝化层170；图案化钝化层170以形成在钝化层170中与第一电极150对应的第一过孔H1和与第二电极160对应的第二过孔H2；在钝化层170远离衬底110的一侧形成第一电极垫154和第二电极垫164，第一电极垫154通过第一过孔H1与第一电极150相连，第二电极垫164通过第二过孔H2与第二电极160相连。各导电结构130包括一个第一电极150、一个第一电极垫154、一个第二电极160和一个第二电极垫164。
例如，在该发光二极管基板的制作方法中，在图案化外延组层120以暴露部分第一导电类型半导体层121以形成M个暴露部1212之后，可在第二导电类型半导体层123和暴露部1212远离衬底110的一侧形成第一导电层，然后对第一导电层进行图案化以形成上述的第一电极150和第二电极160；第一电极150与暴露部1212接触设置，第二电极160与第二导电类型半导体层123接触设置，第一电极150和第二电极160相互绝缘。
例如，在该发光二极管基板的制作方法中，在图案化钝化层170以形成在钝化层170中与第一电极150对应的第一过孔H1和与第二电极160对应的第二过孔H2之后，可在钝化层170远离衬底110的一侧形成第二导电层，然后对第二导电层进行图案化以形成上述的第一电极垫154和第二电极垫164。
例如，将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180包括：采用刻蚀工艺将外延层组120和M个电极结构130分割以形成M个发光二极管芯片180。当然，本公开实施例包括但不限于此，也可采用其他工艺进行分割。
例如，如图39所示，在衬底110上形成外延层组120的同时，可在衬底110上形成第一对位标记710。本公开实施例对于第一对位标记的制作方法不作限定。
在一些示例中，如图40所示，通过转移基板310将N个衬底110上的N个外延层组120转移到中载基板210上，其具体的转移过程可参见图9-图11的相关描述，在此不再赘述。
在一些示例中，如图40所示，驱动基板510包括多个第二支撑结构540，各第二支撑结构540在垂直于驱动基板510的方向上的尺寸大于发光二极管芯片180在垂直于驱动基板510上的方向上的尺寸。第二支撑结构540不仅可以 起到支撑相对设置的中载基板210和驱动基板510之间的间隔，并使得中载基板210和驱动基板510之间的间隔均一，另外还可起到缓冲的作用。
在一些示例中，如图41-图43所示，将中载基板210上的N个外延层组120对应的N*M个发光二极管芯片180中至少部分发光二极管芯片180转移到驱动基板510上包括：如图41所示，将中载基板210与驱动基板510对位，多个第二支撑结构540插入中载基板210上相邻的两个发光二极管芯片180之间；如图42所示，将第三掩膜板630与中载基板210对位，第三掩膜板630包括多个开口635，多个开口635对应多个待转移的发光二极管芯片180；如图42所示，通过第三掩膜板630向中载基板210照射光线，以将多个待转移的发光二极管芯片180转移到驱动基板510上；如图43所示，将中载基板210从驱动基板510上移开，并将转移到驱动基板510上的发光二极管芯片180与驱动基板510绑定。
例如，第三掩膜板630采用吸光材料制作，吸光材料的光吸收率大于60％。由此，第三掩膜板可有效地避免对光线造成反射，从而避免反射后的光线再次进入选取基板的非目标区域。
图44为本公开一实施例提供的一种第三掩膜板的示意图。如图44所示，第三掩膜板630包括：第三透明基板631和第三吸光图案层632；第三吸光图案层632位于第三透明基板631上，且包括多个开口635，第三吸光图案层632采用吸光材料制作，吸光材料的光吸收率大于60％。
例如，如图44所示，第三掩膜板630还包括：第三磁吸结构633，位于第三透明基板631和第三吸光图案层632之间，第三磁吸结构633在第三透明基板631上的正投影与多个开口635在第三透明基板631上的正投影间隔设置。由此，第三磁吸结构633可被吸附固定，从而可提高第三掩膜板在曝光过程中的平坦性，从而提高曝光精准度。
例如，上述的第三磁吸结构可采用镍、铁镍合金等材料制作，从而具有一定磁性，可被电磁铁吸附。
例如，上述的第三磁吸结构的平面形状可为网格结构。
例如，如图44所示，第三掩膜板630还包括：第三保护层634，位于第三吸光图案层632远离第三透明基板631的一侧。第三保护层634可为透明保护层，从而不影响光线的透过。当然，本公开实施例包括但不限于此，第三保护层也可为不透明的；此时，第三保护层可在第三掩膜板使用时剥离。
例如，上述的第三透明基板可采用高硬度和高厚度的石英或氧化硅玻璃进行制作，从而可减小掩膜板因重力导致的变形量。
需要说明的是，在本公开实施例中，第一掩膜板、第二掩膜板和第三掩膜板可为同一掩膜板。当然，本公开实施例包括但不限于此。
例如，各第二支撑结构540在垂直于驱动基板510的方向上的尺寸范围可为3-10微米。当然，本公开实施例包括但不限于此。另外，第二支撑结构540的制作方法可参见第一支撑结构的制作方法，在此不再赘述。
图45-图50为本公开一实施例提供的另一种发光二极管基板的制作方法的步骤示意图。
在一些示例中，如图45所示，在衬底110上形成M个发光二极管芯片180的外延层组120包括：在衬底110上形成第二导电类型半导体层123；在第二导电类型半导体层123远离衬底110的一侧形成发光层122；以及在发光层122远离第二导电类型半导体层123的一侧形成第一导电类型半导体层121。需要说明的是，图45所示的外延层组中各个外延层的顺序与图7所示的外延层组中各个外延层的顺序相反。当然，本公开实施例包括但不限于此，图45所示的外延层组中各个外延层的顺序也可与图7所示的外延层组中各个外延层的顺序相同。
例如，第一导电类型半导体层121可为n型半导体层，第二导电类型半导体层123为p型半导体层。当然，本公开实施例包括但不限于此，第一导电类型半导体层121可为p型半导体层，第二导电类型半导体层123为n型半导体层。
例如，第一导电类型半导体层121和第二导电类型半导体层123的材料可选择氮化镓材料。例如，第一导电类型半导体层121可为n型氮化镓层，第二导电类型半导体层123可为p型氮化镓层。当然，本公开实施例包括但不限于此，第一导电类型半导体层121和第二导电类型半导体层123的材料也可选择其他合适的半导体材料。
例如，衬底可采用蓝宝石衬底。例如，衬底可采用蓝宝石衬底。又例如，该蓝宝石衬底还可包括图形化蓝宝石(Patterned Sapphire Substrate，PSS)层。一方面，图形化蓝宝石层可以有效减少第一导电类型半导体层(即外延层)的位错密度，从而减小非辐射复合，减小反向漏电流，提高该发光二极管芯片的寿命。另一方面，发光层发出的光可在图形化蓝宝石层进行多次散射，改变了 全反射光的出射角，从而提高了光的提取效率。当然，本公开实施例包括但不限于此，该发光二极管芯片也可不设置上述的图形化蓝宝石层。需要说明的是，衬底也可采用其他衬底，例如碳化硅衬底。
例如，上述的图形化蓝宝石层可采用干刻工艺制作。当然，本公开实施例包括但不限于此，上述的图形化蓝宝石层也可采用其他合适的方法制作。
在一些示例中，在衬底110上形成M个发光二极管芯片180的外延层组120还包括：在发光层122和第二导电类型半导体层123之间形成电子阻挡层124。电子阻挡层124可阻挡电子进入第二导电类型半导体层123之中，以限制载流子流过，从而可提高发光效率和发光强度。
例如，电子阻挡层124可为p型氮化镓铝(p-AlGaN)。当然，本公开实施例包括但不限于此，电子阻挡层124还可为其他合适的材料。
在一些示例中，在衬底110上形成第一导电类型半导体层121之前，该制作方法包括：对衬底110进行高温处理，并清理衬底110的表面；以及在衬底110上形成缓冲层140。然后，在缓冲层140远离衬底110的一侧形成第一导电类型半导体层121。通过对衬底进行高温处理和清理，并在衬底上形成缓冲层，可提高晶格匹配程度，便于后续外延层组的生长。
例如，当第一导电类型半导体层为n型氮化镓，第二导电类型半导体层为p型氮化镓时，缓冲层为氮化铝。当然，本公开实施例包括但不限于此，缓冲层可选择任意可以提高晶格匹配程度的材料。
在一些示例中，如图46-图50所示，在该发光二极管基板的制作方法中，将N个衬底110上的N个外延层组120转移到中载基板210上包括：如图46-图49所示，将N个衬底110上的N个外延层组120依次转移到中载基板210上，此时外延层组120并未被分割；如图50所示，在N个外延层组120远离中载基板210的一侧形成M个电极结构130；将中载基板210上的N个外延层组120分割以与M个电极结构130共同形成M个发光二极管芯片180。
在一些示例中，如图48所示，在将第一个衬底110上的外延层组120转移到中载基板210之后，在将第二个衬底110上的外延层组120转移到中载基板210的过程中，可先将衬底110靠近中载基板210，并且位于外延层组120之外的部分进行减薄，从而避免衬底100碰撞或损坏已经转移到中载基板210上的外延层组120。
在一些示例中，将中载基板上的N个外延层组分割以与M个电极结构组 共同形成M个发光二极管芯片包括：采用刻蚀工艺将中载基板上的N个外延层组分割以与M个电极结构组共同形成M个发光二极管芯片。当然，本公开实施例包括但不限于此，也可采用激光切割等其他合适的方法将中载基板上的N个外延层组分割以与M个电极结构组共同形成M个发光二极管芯片。
在一些示例中，如图50所示，各电极结构130包括一个第一电极150和J个第二电极160，在外延层组120远离衬底110的一侧形成M个电极结构130包括：图案化外延组层120以暴露部分第一导电类型半导体层121以形成M个暴露部1212，并将第二导电类型半导体层123分割为M*J个第二导电类型半导体块1230；在M*J个第二导电类型半导体块1230远离中载基板210的一侧形成M*J个第二电极160；在M*J个第二电极160远离中载基板210的一侧形成钝化层170；图案化钝化层170以形成在钝化层170中与M个暴露部1212对应的M个第一过孔H1、与M*J个第二电极160对应的M*J个第二过孔H2；通过M个第一过孔H1在M个暴露部1212远离衬底110的一侧形成M个第一电极150；以及在钝化层170远离中载基板210的一侧形成第一电极垫154和第二电极垫164，第一电极垫154通过第一过孔H1与第一电极150相连，第二电极垫164通过第二过孔H2与第二电极160相连，J为大于等于2的正整数。
在该发光二极管芯片基板的制作方法中，当各电极结构130包括一个第一电极150和j个第二电极160时，一个第一电极、一个第二电极、第一导电类型半导体层、一个第二导电类型半导体块和发光层可形成一个LED发光结构。由此，单个发光二极管芯片可包括j(j大于等于2的正整数)个第二导电类型半导体块和j个第二电极，因此单个发光二极管芯片可形成有至少两个可单独进行发光的发光结构。一方面，形成的单个发光二极管芯片的整体尺寸保持不变的情况下，通过在发光二极管芯片内形成多个发光结构，可降低单个发光结构的尺寸。也就是说，可以采用现有的工艺精度制作尺寸更小的发光二极管芯片。由此，该发光二极管芯片可降低小尺寸的LED发光结构的制作难度并降低成本，并且还可实现较高的像素密度。另一方面，由于单个发光结构的尺寸较小，其在小电流的驱动下效率也较高，从而可提高发光效率。
需要说明的是，在形成如图50所示的中载基板210和中载基板210上的发光二极管芯片180之后，可将中载基板210上的发光二极管芯片180中的至少一部分转移到驱动基板510上，具体过程可参见如图12-图14的相关描述， 在此不再赘述。
图51A-图51C为本公开一实施例提供的一种将N个衬底上的N个外延层组转移到中载基板上的方法的示意图。在衬底110上形成M个发光二极管芯片180的外延层组120包括：如图51A所示，在圆形的衬底110上形成M个发光二极管芯片180的外延层组120，外延层组120在衬底110上的正投影的形状为方形；如图51B所示，沿着外延层组120的边缘将圆形的衬底110切割为方形的衬底110；如图51C所示，将N个衬底110上的N个外延层组120转移到中载基板210上包括：将N个方形的衬底110上的N个外延层组120密集排布在中载基板210上。当然，本公开实施例包括但不限于此，根据衬底的结晶特性，上述的圆形衬底也可切割为六边形的衬底。
例如，当衬底为蓝宝石衬底时，由于蓝宝石为六方晶体，晶体中存在解离面的概念，解离面是指矿物晶体在外力作用下严格沿着一定结晶方向破裂，并且能裂出光滑平面的性质的平面。对于蓝宝石衬底来说，由于外延层是沿晶轴向外延生长的，因此在平行于晶轴方向的解离面有两个晶面，且两个晶面是相互垂直的，因此可以采用沿平行于参考边或者垂直于参考边对蓝宝石进行解离，从而可以将圆形的蓝宝石衬底切割成方形的蓝宝石衬底，根据晶面分布也可以解离成六边形的蓝宝石衬底。图52A-图52C为本公开一实施例提供的另一种将N个衬底上的N个外延层组转移到中载基板上的方法的示意图。在衬底110上形成M个发光二极管芯片180的外延层组120包括：如图52A所示，将圆形的衬底110切割为方形的衬底110；如图52B所示，将N个方形的衬底110拼接在一起，以形成N个衬底110的组合；如图52C所示，在N个衬底110的组合上形成M*N个发光二极管芯片180的外延层120。类似地，本公开实施例包括但不限于此，根据衬底的结晶特性，上述的圆形衬底也可切割为六边形的衬底。
在一些示例中，将N个衬底上的N个外延层组转移到中载基板上包括：在N个衬底的组合上形成的M*N个发光二极管芯片的外延层转移到中载基板上。
本公开一实施例还提供一种发光二极管基板。图53为本公开一实施例提供的一种发光二极管基板的示意图。该发光二极管基板可采用上述的任一的制作方法制作。上述的发光二极管基板的制作方法通过先将N个衬底上的N个外延层组转移到尺寸更大的中载基板上，并且将这些外延层组密集排布在中载 基板上；然后，再将中载基板上的发光二极管芯片中选取至少部分转移到驱动基板上。由于N个衬底上的N个外延层组密集排布在中载基板上，因此在将中载基板上的N个外延层组对应的N*M个发光二极管芯片中至少部分发光二极管芯片转移到驱动基板上的过程中，中载基板上的发光二极管芯片是均匀分布的，从而可一次取用更多的发光二极管芯片(大于一个衬底能取用的发光二极管芯片的数量)，甚至一次性取用驱动基板需要的同一颜色的发光二极管芯片，也就是说，驱动基板上同一颜色的发光二极管芯片可仅通过一次转移工艺就可完成。由此，该发光二极管基板的制作方法可大大提高取用效率和转移效率。由此，该发光二极管基板具有较高的制作效率和较低的成本。
例如，如图53所示，在该发光二极管基板10中，驱动基板510包括多个接收结构560，各接收结构560在垂直于驱动基板510上的尺寸小于发光二极管芯片180在垂直于驱动基板510上的尺寸。由此，可通过上述的接收结构可提高中载基板和驱动基板之间的对位精度，从而可提高产品良率。
图54为本公开一实施例提供的另一种发光二极管基板的示意图。如图54所示，该发光二极管基板10包括驱动基板510和驱动基板510上的多个发光二极管芯片180。另外，该发光二极管基板10还包括多个支撑结构540，位于相邻的发光二极管芯片180之间，各支撑结构540在垂直于驱动基板510的方向上的尺寸大于发光二极管芯片180在垂直于驱动基板510的方向上的尺寸。由此，支撑结构不仅可在制作过程中以起到支撑相对设置的中载基板和驱动基板510之间的间隔，并使得中载基板和驱动基板之间的间隔均一，另外还可起到缓冲的作用，从而可提高产品良率。
图55为本公开一实施例提供的另一种发光二极管基板的示意图。如图55所示，驱动基板510包括衬底基板511和位于衬底基板511上的多个驱动电路514，各驱动电路514包括垫片5142；各驱动电路514被配置为驱动与垫片5142电性相连的发光二极管芯片180进行发光。各垫片5142包括至少两个子垫片5140，各子垫片5140包括凹槽5140A，凹槽5140A被配置为接纳对应的发光二极管芯片180的电极垫154或164。由此，驱动基板可驱动发光二极管芯片进行发光或显示。另外，凹槽也可提高绑定的精度，从而可提高产品良率。
在一些示例中，如图55所示，驱动基板510上驱动电路514的数量与中载基板210上发光二极管芯片180的数量大致相同；驱动基板510上驱动电路514的位置与中载基板210上发光二极管芯片180的位置一一对应设置。由此， 当中载基板和驱动基板对准之后，可将中载基板上需要转移的任意数量的发光二极管芯片一次性转移到驱动基板上。
本公开一实施例还提供一种显示装置。图56为本公开一实施例提供的一种显示装置的示意图。如图56所示，该显示装置20包括上述的发光二极管基板10。需要说明的是，当上述的发光二极管基板10上包括发多种颜色(例如，红色、绿色和蓝色)的光的发光二极管芯片时，该发光二极管基板10可为显示装置20的显示基板，直接进行彩色显示。当上述的发光二极管基板10上仅包括发一种颜色(例如白色或者蓝色)的发光二极管芯片时，该发光二极管基板10可为显示装置20的背光源。
例如，该显示装置可为电视、电脑、笔记本电脑、智能手机、导航仪、平板电脑、电子画框等具有显示功能的电子产品。
本公开一实施例还提供一种掩膜板。图16为本公开一实施例提供的一种掩膜板的示意图。如图16所示，掩膜板610包括透明基板611和吸光图案层612；吸光图案层612位于透明基板611上，且包括多个开口615；吸光图案层612采用吸光材料制作，吸光材料的光吸收率大于60％。
在上述发光二极管基板的制作方法中，当采用激光通过通常的掩膜板进行照射时，由于激光的能量较高，而普通的掩膜板所采用的铬图案有有65％的反射率(约35％的吸收率)，从而会导致激光被反射；而反射后的激光经过反射和投射之后会再次射向非目标区域，从而导致非目标区域被曝光，导致错误的解离。然而，在采用本公开实施例提供的掩膜板时，由于吸光图案层采用吸光材料制作，吸光材料的光吸收率大于60％，因此，该掩膜板可减少甚至消除掩膜板的反射，从而避免非目标区域被曝光而导致错误的解离。
例如，如图16所示，掩膜板610还包括：磁吸结构613，位于透明基板611和吸光图案层612之间，磁吸结构613在透明基板611上的正投影与多个开口615在透明基板611上的正投影间隔设置。由此，磁吸结构613可被吸附固定，从而可提高掩膜板在曝光过程中的平坦性，从而提高曝光精准度。
例如，如图16所示，掩膜板610还包括：保护层614，位于吸光图案层612远离透明基板611的一侧。保护层614可为透明保护层，从而不影响光线的透过。当然，本公开实施例包括但不限于此，保护层也可为不透明的；此时，保护层可在掩膜板使用时剥离。
例如，该吸光材料可采用对金属图案进行氧化而得到。
例如，该掩膜板的透明基板包括石英、玻璃、蓝宝石等透光材料。例如，该掩膜板的透明基板可采用高硬度和高厚度的石英或氧化硅玻璃进行制作，从而可减小掩膜板因重力导致的变形量。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (60)

  1. 一种发光二极管基板的制作方法，包括：
    在衬底上形成M个发光二极管芯片的外延层组；
    将N个所述衬底上的N个所述外延层组转移到中载基板上，N个所述衬底上的N个所述外延层组密集排列在所述中载基板上；以及
    将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到驱动基板上，
    其中，所述中载基板的面积大于等于N个所述衬底的面积之和，M为大于等于2的正整数，N为大于等于2的正整数。
  2. 根据权利要求1所述的发光二极管基板的制作方法，其中，在所述中载基板上，相邻两个所述外延层组之间的距离与相邻的两个所述发光二极管芯片之间的距离大致相等。
  3. 根据权利要求1所述的发光二极管基板的制作方法，其中，所述中载基板的形状与所述驱动基板的形状大致相同，所述中载基板的面积与所述驱动基板的面积大致相等。
  4. 根据权利要求1所述的发光二极管基板的制作方法，其中，所述驱动基板包括衬底基板和位于衬底基板上的多个驱动电路，各所述驱动电路包括垫片，并被配置为驱动与所述垫片电性相连的所述发光二极管芯片进行发光，所述制作方法还包括：
    采用绑定工艺将转移到所述驱动基板上的所述发光二极管芯片与对应的所述驱动电路的所述垫片绑定。
  5. 根据权利要求4所述的发光二极管基板的制作方法，其中，采用绑定工艺将转移到所述驱动基板上的所述发光二极管芯片与对应的所述驱动电路的所述垫片绑定包括：
    对所述驱动基板进行热回流，以将所述发光二极管芯片与所述垫片键合在一起。
  6. 根据权利要求4所述的发光二极管基板的制作方法，其中，所述驱动基板还包括多个导电凸起，位于所述垫片远离所述衬底基板的一侧，各所述垫片在所述衬底基板上的正投影与至少一个所述导电凸起在所述衬底基板上的正投影交叠，所述制作方法还包括：
    将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到所述驱动基板上之前，在所述驱动基板上涂覆有机绝缘胶材；
    采用绑定工艺将转移到所述驱动基板上的所述发光二极管芯片与对应的所述驱动电路的所述垫片绑定包括：
    对所述驱动基板进行热回流，蒸发所述有机绝缘胶材中的溶剂，以将所述发光二极管芯片与所述垫片键合在一起。
  7. 根据权利要求1所述的发光二极管基板的制作方法，其中，将N个所述衬底上的N个所述外延层组转移到所述中载基板包括：
    在所述中载基板上形成第一胶层；以及
    将N个所述衬底上的N个所述外延层组转移到所述第一胶层远离所述中载基板的一侧。
  8. 根据权利要求7所述的发光二极管基板的制作方法，其中，在所述中载基板上形成所述第一胶层包括：
    在所述中载基板上涂覆第一胶材层；以及
    图案化所述第一胶材层，以在所述第一胶材层中形成贯穿所述第一胶材层的多个通孔，
    其中，包括所述多个通孔的所述第一胶材层为所述第一胶层，各所述通孔在所述中载基板上的正投影的尺寸小于所述发光二极管芯片在所述中载基板上的正投影的尺寸。
  9. 根据权利要求7所述的发光二极管基板的制作方法，其中，所述第一胶层的材料包括紫外光减粘胶或激光解离胶。
  10. 根据权利要求7所述的发光二极管基板的制作方法，其中，将N个所述衬底上的N个所述外延层组转移到所述中载基板还包括：
    在所述中载基板上形成第一胶层之前，在所述中载基板上形成多个遮光结构，各所述遮光结构在所述中载基板上的正投影位于相邻两个所述发光二极管芯片在所述中载基板上的正投影之间。
  11. 根据权利要求1-10中任一项所述的发光二极管基板的制作方法，其中，在所述衬底上形成M个所述发光二极管芯片的外延层组之后，所述制作方法还包括：
    在所述外延层组远离所述衬底的一侧形成M个电极结构；以及
    将所述外延层组和M个所述电极结构分割以形成M个所述发光二极管芯片。
  12. 根据权利要求11所述的发光二极管基板的制作方法，其中，将所述外延层组和M个所述电极结构分割以形成M个所述发光二极管芯片包括：
    采用刻蚀工艺将所述外延层组和M个所述电极结构分割以形成M个所述发光二极管芯片。
  13. 根据权利要求11所述的发光二极管基板的制作方法，其中，将N个所述衬底上的N个所述外延层组转移到所述中载基板上包括：
    将形成有M个所述发光二极管芯片的所述衬底转移到转移基板上；
    将所述衬底从所述转移基板上剥离；以及
    将N个所述转移基板上的N*M个所述发光二极管芯片转移到所述中载基板上，
    其中，所述转移基板的面积与所述衬底的面积大致相等。
  14. 根据权利要求13所述的发光二极管基板的制作方法，其中，将形成有M个所述发光二极管芯片的所述衬底转移到所述转移基板上包括：
    在所述转移基板上涂覆第二胶层；以及
    将形成有M个所述发光二极管芯片的所述衬底转移到所述第二胶层远离所述转移基板的一侧。
  15. 根据权利要求14所述的发光二极管基板的制作方法，其中，所述第二胶层的材料包括紫外减粘胶或激光解离胶，在将N个所述转移基板上的N*M个所述发光二极管芯片转移到所述中载基板上之后，向所述转移基板照射光线以降低所述第二胶层的粘性，以将所述转移基板移除。
  16. 根据权利要求13-15中任一项所述的发光二极管基板的制作方法，其中，所述中载基板包括多个第一支撑结构，各所述第一支撑结构在垂直于所述中载基板的方向上的尺寸大于所述发光二极管芯片在垂直于所述中载基板上的方向上的尺寸，将N个所述转移基板上的N*M个所述发光二极管芯片转移到所述中载基板上包括：
    依次将N个所述转移基板与所述中载基板对位，以使得多个所述第一支撑结构位于所述转移基板上相邻的两个所述发光二极管芯片之间。
  17. 根据权利要求16所述的发光二极管基板的制作方法，其中，各所述第一支撑结构为柱状结构，各所述第一支撑结构在所述中载基板上的正投影的 形状包括矩形、T字形和圆形中的一种。
  18. 根据权利要求16所述的发光二极管基板的制作方法，其中，各所述第一支撑结构为柱状结构，各所述第一支撑结构在所述中载基板上的正投影相互连接以形成网格。
  19. 根据权利要求16所述的发光二极管基板的制作方法，其中，将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到所述驱动基板上包括：
    将所述中载基板与所述驱动基板对位，以使多个所述第一支撑结构位于所述中载基板和所述驱动基板之间；
    将第一掩膜板与所述中载基板对位，所述第一掩膜板包括多个开口，所述多个开口对应多个待转移的所述发光二极管芯片；以及
    通过所述第一掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述驱动基板上。
  20. 根据权利要求19所述的发光二极管基板的制作方法，其中，所述第一掩膜板包括吸光材料，所述吸光材料的光吸收率大于60％。
  21. 根据权利要求19所述的发光二极管基板的制作方法，其中，所述第一掩膜板包括：
    第一透明基板；以及
    第一吸光图案层，位于所述第一透明基板上，且包括所述多个开口，
    其中，所述第一吸光图案层采用所述吸光材料制作，所述吸光材料的光吸收率大于60％。
  22. 根据权利要求21所述的发光二极管基板的制作方法，其中，所述第一掩膜板还包括：
    第一磁吸结构，位于所述第一透明基板和所述第一吸光图案层之间，
    其中，所述第一磁吸结构在所述第一透明基板上的正投影与所述多个开口在所述第一透明基板上的正投影间隔设置。
  23. 根据权利要求19所述的发光二极管基板的制作方法，其中，所述驱动基板包括多个第一接收结构，将所述中载基板与所述驱动基板对位包括：将所述中载基板上的多个所述第一支撑结构插入所述驱动基板上的多个第一接收结构，多个所述第一支撑结构和多个所述第一接收结构一一对应设置，各所述第一接收结构在垂直于所述驱动基板上的尺寸小于所述发光二极管芯片在 垂直于所述驱动基板上的尺寸。
  24. 根据权利要求11-23中任一项所述的发光二极管基板的制作方法，其中，在所述衬底上形成M个发光二极管芯片的所述外延层组包括：
    在所述衬底上形成第一导电类型半导体层；
    在所述第一导电类型半导体层远离所述衬底的一侧形成发光层；以及
    在所述发光层远离所述第一导电类型半导体层的一侧形成第二导电类型半导体层。
  25. 根据权利要求24所述的发光二极管基板的制作方法，其中，在所述外延层组远离所述衬底的一侧形成M个所述电极结构包括：
    图案化所述外延组层以暴露部分所述第一导电类型半导体层以形成M个暴露部；
    在M个所述暴露部远离衬底的一侧形成M个第一电极；
    在所述第二导电类型半导体层远离所述衬底的一侧形成M个第二电极；
    在M个所述第一电极和M个所述第二电极远离所述衬底的一侧形成钝化层；
    图案化所述钝化层以在钝化层中形成与所述第一电极对应的第一过孔和与所述第二电极对应的第二过孔；
    在所述钝化层远离所述衬底的一侧形成第一电极垫和第二电极垫，所述第一电极垫通过所述第一过孔与所述第一电极相连，所述第二电极垫通过所述第二过孔与所述第二电极相连，
    其中，各所述导电结构包括一个第一电极、一个第一电极垫、一个第二电极和一个第二电极垫。
  26. 根据权利要求25所述的发光二极管基板的制作方法，其中，在所述衬底上形成M个发光二极管芯片的所述外延层组还包括：
    在所述发光层和所述第二导电类型半导体层之间形成电子阻挡层。
  27. 根据权利要求25所述的发光二极管基板的制作方法，其中，在所述衬底上形成所述第一导电类型半导体层前，所述制作方法还包括：
    对所述衬底进行高温处理，并清理所述衬底的表面；以及
    在所述衬底上形成缓冲层。
  28. 根据权利要求25所述的发光二极管基板的制作方法，其中，所述第一导电类型半导体层为n型半导体层，所述第二导电类型半导体层为p型半导 体层。
  29. 根据权利要求27所述的发光二极管基板的制作方法，其中，所述第一导电类型半导体层为n型氮化镓，所述第二导电类型半导体层为p型氮化镓，所述缓冲层为氮化铝。
  30. 根据权利要求11所述的发光二极管基板的制作方法，其中，将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部分所述发光二极管芯片转移到所述驱动基板上包括：
    提供选取基板，所述选取基板包括多个选取结构；
    将所述选取基板与所述中载基板对位，多个所述选取结构与多个待转移的所述发光二极管芯片接触；
    将第二掩膜板与所述中载基板对位，所述第二掩膜板包括多个开口，所述多个开口对应多个所述选取结构；
    通过所述第二掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述选取基板上的多个所述选取结构上；
    将所述选取基板和所述驱动基板对位；
    将所述选取基板上的多个所述选取结构上的多个待转移的所述发光二极管芯片与所述驱动基板键合；以及
    将多个所述选取结构去除。
  31. 根据权利要求30所述的发光二极管基板的制作方法，其中，所述第二掩膜板包括吸光材料，所述吸光材料的光吸收率大于60％。
  32. 根据权利要求31所述的发光二极管基板的制作方法，其中，所述第二掩膜板包括：
    第二透明基板；以及
    第二吸光图案层，位于所述第二透明基板上，且包括所述多个开口，
    其中，所述第二吸光图案层采用所述吸光材料制作，所述吸光材料的光吸收率大于60％。
  33. 根据权利要求32所述的发光二极管基板的制作方法，其中，所述第二掩膜板还包括：
    第二磁吸结构，位于所述第二透明基板和所述第二吸光图案层之间，
    其中，所述第二磁吸结构在所述第二透明基板上的正投影与所述多个开口在所述第二透明基板上的正投影间隔设置。
  34. 根据权利要求30所述的发光二极管基板的制作方法，其中，各所述选取结构包括支撑部和位于支撑部远离所述中载基板上的热解部。
  35. 根据权利要求34所述的发光二极管基板的制作方法，其中，将所述选取基板与所述中载基板对位，多个所述选取结构与多个待转移的所述发光二极管芯片接触包括：
    在真空环境下将所述选取基板与所述中载基板对位；
    向所述选取基板施加压力以使得所述选取结构中的热解部与对应的所述发光二极管芯片粘附。
  36. 根据权利要求35所述的发光二极管基板的制作方法，其中，通过所述第二掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述选取基板上的多个所述选取结构上包括：
    在通过所述第二掩膜板向所述中载基板照射光线之后，向所述选取基板和所述中载基板之间通入惰性气体。
  37. 根据权利要求34所述的发光二极管基板的制作方法，其中，将多个所述选取结构去除包括：
    在真空环境下进行加热以使得所述热解部熔解，以将多个所述选取结构去除。
  38. 根据权利要求30所述的发光二极管基板的制作方法，其中，各所述选取结构的材料包括紫外减粘胶或激光解离胶，将多个所述选取结构去除包括：
    向所述选取基板照射光线，以将多个所述选取结构去除。
  39. 根据权利要求30所述的发光二极管基板的制作方法，其中，各所述选取结构包括弹性材料。
  40. 根据权利要求30所述的发光二极管基板的制作方法，其中，各所述选取结构被垂直于所述选取基板的一平面所截取的横截面的形状包括梯形。
  41. 根据权利要求13-15中任一项所述的发光二极管基板的制作方法，其中，所述驱动基板包括多个第二支撑结构，各所述第二支撑结构在垂直于所述驱动基板的方向上的尺寸大于所述发光二极管芯片在垂直于所述驱动基板上的方向上的尺寸。
  42. 根据权利要求41所述的发光二极管基板的制作方法，其中，将所述中载基板上的N个所述外延层组对应的N*M个所述发光二极管芯片中至少部 分所述发光二极管芯片转移到所述驱动基板上包括：
    将所述中载基板与所述驱动基板对位，多个所述第二支撑结构插入所述中载基板上相邻的两个所述发光二极管芯片之间；
    将第三掩膜板与所述中载基板对位，所述第三掩膜板包括多个开口，所述多个开口对应多个待转移的所述发光二极管芯片；以及
    通过所述第三掩膜板向所述中载基板照射光线，以将多个待转移的所述发光二极管芯片转移到所述驱动基板上。
  43. 根据权利要求1-10中任一项所述的发光二极管基板的制作方法，其中，将N个所述衬底上的N个所述外延层组转移到所述中载基板上包括：
    将N个所述衬底上的N个所述外延层组依次转移到所述中载基板上；
    在N个所述外延层组远离所述中载基板的一侧形成M个电极结构；
    将所述中载基板上的N个所述外延层组分割以与所述M个所述电极结构共同形成M个所述发光二极管芯片。
  44. 根据权利要求43所述的发光二极管基板的制作方法，其中，将所述中载基板上的N个所述外延层组分割以与所述M个所述电极结构组共同形成M个所述发光二极管芯片包括：
    采用刻蚀工艺将所述中载基板上的N个所述外延层组分割以与所述M个所述电极结构组共同形成M个所述发光二极管芯片。
  45. 根据权利要求44所述的发光二极管基板的制作方法，其中，在所述衬底上形成M个发光二极管芯片的所述外延层组包括：
    在所述衬底上形成第一导电类型半导体层；
    在所述第一导电类型半导体层远离所述衬底的一侧形成发光层；以及
    在所述发光层远离所述第一导电类型半导体层的一侧形成第二导电类型半导体层。
  46. 根据权利要求45所述的发光二极管基板的制作方法，其中，在所述衬底上形成所述第一导电类型半导体层前，所述制作方法还包括：
    对所述衬底进行高温处理，并清理所述衬底的表面；以及
    在所述衬底上形成缓冲层。
  47. 根据权利要求45所述的发光二极管基板的制作方法，其中，所述第一导电类型半导体层为n型半导体层，所述第二导电类型半导体层为p型半导体层。
  48. 根据权利要求46所述的发光二极管基板的制作方法，其中，所述第一导电类型半导体层为n型氮化镓，所述第二导电类型半导体层为p型氮化镓，所述缓冲层为氮化铝。
  49. 根据权利要求45所述的发光二极管基板的制作方法，其中，各所述电极结构包括一个第一电极和J个第二电极，在所述外延层组远离所述衬底的一侧形成M个所述电极结构包括：
    图案化所述外延组层以暴露部分所述第一导电类型半导体层以形成M个暴露部，并将所述第二导电类型半导体层分割为M*J个第二导电类型半导体块；
    在M*J个第二导电类型半导体块远离中载基板的一侧形成M*J个第二电极；
    在M*J个所述第二电极远离所述中载基板的一侧形成钝化层；
    图案化所述钝化层以形成在钝化层中与M个所述暴露部对应的M个第一过孔、与M*J个所述第二电极对应的M*J个第二过孔；
    通过M个所述第一过孔在M个所述暴露部远离衬底的一侧形成M个第一电极；以及
    在所述钝化层远离所述中载基板的一侧形成第一电极垫和第二电极垫，所述第一电极垫通过所述第一过孔与所述第一电极相连，所述第二电极垫通过所述第二过孔与所述第二电极相连，
    其中，J为大于等于2的正整数。
  50. 根据权利要求46所述的发光二极管基板的制作方法，其中，在所述衬底上形成M个发光二极管芯片的所述外延层组还包括：
    在所述发光层和所述第二导电类型半导体层之间形成电子阻挡层。
  51. 根据权利要求1-10中任一项所述的发光二极管基板的制作方法，其中，在衬底上形成M个所述发光二极管芯片的所述外延层组包括：
    在圆形的所述衬底上形成M个所述发光二极管芯片的所述外延层组；以及
    沿着所述外延层组的边缘将圆形的所述衬底切割为方形或六边形的所述衬底，
    其中，所述外延层组在所述衬底上的正投影的形状为方形。
  52. 根据权利要求51所述的发光二极管基板的制作方法，其中，将N个 所述衬底上的N个所述外延层组转移到所述中载基板上包括：
    将N个方形或六边形的所述衬底上的N个所述外延层组密集排布在所述中载基板上。
  53. 根据权利要求1-10中任一项所述的发光二极管基板的制作方法，其中，在衬底上形成M个所述发光二极管芯片的所述外延层组包括：
    将圆形的所述衬底切割为方形或六边形的所述衬底；
    将N个方形或六边形的所述衬底拼接在一起，以形成N个所述衬底的组合；
    在N个所述衬底的组合上形成M*N个所述发光二极管芯片的所述外延层。
  54. 根据权利要求53所述的发光二极管基板的制作方法，其中，将N个所述衬底上的N个所述外延层组转移到所述中载基板上包括：
    在N个所述衬底的组合上形成的M*N个所述发光二极管芯片的所述外延层转移到所述中载基板上。
  55. 根据权利要求4所述的发光二极管基板的制作方法，其中，各所述垫片包括至少两个子垫片，各所述子垫片包括凹槽，所述凹槽被配置为接纳对应的所述发光二极管芯片的电极垫。
  56. 一种发光二极管基板，采用根据权利要求1-3中任一项所述制作方法制作。
  57. 根据权利要求56所述的发光二极管基板，其中，所述驱动基板包括多个接收结构，各所述第一接收结构在垂直于所述驱动基板上的尺寸小于所述发光二极管芯片在垂直于所述驱动基板上的尺寸。
  58. 根据权利要求56所述的发光二极管基板，还包括：
    多个支撑结构，位于相邻的所述发光二极管芯片之间，各所述支撑结构在垂直于驱动基板的方向上的尺寸大于所述发光二极管芯片在垂直于驱动基板的方向上的尺寸。
  59. 根据权利要求56所述的发光二极管基板，其中，所述驱动基板包括衬底基板和位于衬底基板上的多个驱动电路，各所述驱动电路包括垫片，并被配置为驱动与所述垫片电性相连的所述发光二极管芯片进行发光，各所述垫片包括至少两个子垫片，各所述子垫片包括凹槽，所述凹槽被配置为接纳对应的所述发光二极管芯片的电极垫。
  60. 一种显示装置，包括根据权利要求56-59中任一项所述的发光二极管基板。
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