WO2022088055A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2022088055A1
WO2022088055A1 PCT/CN2020/125328 CN2020125328W WO2022088055A1 WO 2022088055 A1 WO2022088055 A1 WO 2022088055A1 CN 2020125328 W CN2020125328 W CN 2020125328W WO 2022088055 A1 WO2022088055 A1 WO 2022088055A1
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Prior art keywords
diamond
substrate
trench
trenches
groove
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PCT/CN2020/125328
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English (en)
French (fr)
Inventor
胡彬
段焕涛
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20959217.9A priority Critical patent/EP4213184A4/en
Priority to JP2023526332A priority patent/JP2023547925A/ja
Priority to PCT/CN2020/125328 priority patent/WO2022088055A1/zh
Priority to CN202080102849.3A priority patent/CN115812254A/zh
Publication of WO2022088055A1 publication Critical patent/WO2022088055A1/zh
Priority to US18/310,071 priority patent/US20230268243A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732—Diamonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method thereof.
  • the heat dissipation performance of the substrate is an important factor affecting the performance of the device.
  • the high power performance of the semiconductor device cannot be effectively exerted due to the limitation of the heat dissipation of the substrate.
  • the high-electron-mobility transistor (HEMT) based on gallium nitride (GaN) is in the fifth generation of mobile communication technology (the 5th generation mobile network, 5G) field of power amplifier (power amplifier, PA) chip has been more and more applications, as the third generation wide bandgap semiconductor material, gallium nitride has high two-dimensional electron gas concentration and The breakdown voltage and high electron saturation velocity provide favorable conditions for the nitride device structure as a high-power device.
  • These new application scenarios have a great impact on the power and frequency of GaN-based HEMT devices. , efficiency and reliability also put forward higher requirements.
  • GaN-based HEMT devices heat dissipation has become a key bottleneck for GaN-based HEMT devices. This is because silicon-based and sapphire and other materials are currently used as substrates. These materials have poor thermal conductivity. When gallium nitride devices are output as high-power devices, a large amount of heat will be generated. Emitted out, limiting the performance of GaN-enabled devices.
  • a first aspect of the present application provides a semiconductor device and a method for manufacturing the same, which improves the heat dissipation performance of the semiconductor device and facilitates the effective exertion of the high-power performance of the semiconductor device.
  • a semiconductor device including a substrate, an epitaxial layer and an electrode sequentially located on the substrate, wherein the substrate has a diamond structure extending through the substrate in a longitudinal direction, and the diamond structure is divided in the longitudinal direction.
  • the second diamond portion may be located below the first diamond portion, and the lateral dimensions of the first diamond portion and the second diamond portion may be different, specifically, may be completely different or not identical.
  • the diamond structure running through the substrate can form a longitudinal heat conduction channel, so that the heat generated during the operation of the device can be efficiently conducted to the periphery of the device, improving the heat dissipation performance of the semiconductor device, which is beneficial to the high performance of the semiconductor device. Effective power performance.
  • the lateral dimensions of the first diamond portion and the second diamond portion are different, which can be achieved by two etching processes, reducing the aspect ratio of the etching, which is beneficial to control the structures of the first diamond portion and the second diamond portion, and at the same time can Taking into account the heat dissipation performance and the lattice matching between the epitaxial layers is beneficial to obtain a higher-quality epitaxial layer and to obtain a high-performance semiconductor device.
  • the first diamond structure and the second diamond structure are multiple, and the multiple first diamond portions and the multiple second diamond portions are in one-to-one correspondence, and are circular frustums at least one of a structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure, and a prismatic structure.
  • the first diamond portion and the second diamond portion can be in one-to-one correspondence, so that a first diamond structure and a second diamond structure can form a longitudinal heat conduction channel, so that a plurality of heat conduction channels can be used to reach the periphery of the device Heat dissipation to achieve high heat dissipation efficiency.
  • the first diamond part and the second diamond part can have various shapes, and can be designed for different epitaxial layers, so as to take into account the heat dissipation performance and lattice matching, and improve the epitaxial quality.
  • the number of the second diamond parts is less than the number of the first diamond parts, there are a plurality of the first diamond parts connected to the same second diamond part, the first diamond parts
  • the part is at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure.
  • the number of the second diamond parts below may be less than the number of the first diamond parts, so that one second diamond part can be connected with a plurality of first diamond parts, so that the lateral dimension of the second diamond part can be Greater than the first diamond portion, the surface of the substrate far from the epitaxial layer is exposed to more diamond, while the surface of the substrate close to the epitaxial layer is less exposed, ensuring the heat dissipation performance of the device and taking into account the epitaxial quality.
  • the second diamond portion is one and is longitudinally connected to all or part of the first diamond portion.
  • the second diamond portion there is one second diamond portion, so that the second diamond portion can have a larger lateral dimension, thereby further improving the heat dissipation performance of the device without affecting the quality of the epitaxial layer.
  • the second diamond portions extend in a predetermined direction parallel to the surface of the substrate, and at least one of the second diamond portions is associated with the substrate surface.
  • a plurality of said first diamond portions are longitudinally connected.
  • the lateral dimension of the first diamond portion is in the range of 1-10 um
  • the longitudinal dimension of the first diamond portion is in the range of 1-10 um
  • the distance between the different first diamond portions is in the range of is 1-10um
  • the thickness of the substrate is in the range of 50-100um.
  • the first diamond portion may occupy a small portion of the thickness of the substrate, and each first diamond portion has a reasonable distance, so as to ensure the quality of the epitaxial layer and the heat dissipation performance of the device.
  • the material of the substrate is one or more of silicon, silicon carbide, aluminum nitride, and sapphire.
  • the substrate may be one or more of a silicon substrate, a silicon carbide substrate, an aluminum nitride substrate, and a sapphire substrate. Even if the heat dissipation performance of the substrate is not good enough, when diamond is used to form heat dissipation After the channel is formed, the heat dissipation performance of the device can be ensured, and the manufacturing process of these substrates is simple, which is easy for large-scale production.
  • the diamond structure is single crystal diamond or polycrystalline diamond.
  • the diamond structure may be single crystal diamond or polycrystalline diamond, which can be determined according to the actual situation, as long as good heat dissipation can be achieved.
  • the epitaxial layer includes a buffer layer and a barrier layer
  • the buffer layer is a gallium nitride layer
  • the material of the barrier layer is one of AlGaN, InAlN, AlN and ScAlN or variety.
  • the epitaxial layer may include a buffer layer and a barrier layer
  • the buffer layer may be a gallium nitride layer
  • the semiconductor structure may be a gallium nitride device
  • a two-dimensional layer may be formed between the barrier layer and the gallium nitride layer. electron gas, thereby providing better device performance.
  • the thickness of the gallium nitride layer is in the range of 0.1-2um, and the thickness of the barrier layer is in the range of 5-20nm.
  • the thicknesses of the gallium nitride layer and the barrier layer can be within a reasonable range to ensure the performance of the device.
  • the electrode includes a source electrode, a drain electrode and a gate electrode, and the material of the electrode is at least one of Au, Ti, Al, Ni, and Ta.
  • the electrodes may include a source electrode, a drain electrode and a gate electrode, and the electrode materials may be various, which ensures the integrity and superior performance of the device.
  • a second aspect of the embodiments of the present application provides a method for forming a semiconductor device, including:
  • the second surface of the substrate is etched to obtain a second trench, the second trench is communicated with the first trench, and the lateral dimensions are different; the first surface and the second surface are two opposing surfaces;
  • the second trench is filled with diamond material.
  • the diamond material on the first surface of the substrate can be formed first, then the device structure on the substrate can be formed, and then the diamond structure on the second surface can be formed.
  • the combined steps are matched, so the device with high performance and high heat dissipation in the embodiments of the present application can be obtained under the premise of as few steps as possible.
  • both the first trenches and the second trenches are multiple, the multiple first trenches and the multiple second trenches are in one-to-one correspondence, and the The shape of the diamond material in the first groove and the second groove is at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure.
  • the number of the second trenches is less than the number of the first trenches, there are multiple first trenches connected to the same second trench, the first trenches
  • the shape of the groove is one of a circular truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure.
  • the second trench is one, and the bottom of the second trench exposes all or part of the diamond material in the first trench.
  • the second trenches are a plurality of trenches extending in a predetermined direction parallel to the surface of the substrate, and at least one of the second trenches has a bottom that exposes a plurality of all trenches. diamond material in the first groove.
  • the method before the second trench is obtained by etching the second surface of the substrate, the method further includes:
  • the substrate is thinned from the second surface of the substrate.
  • a third aspect of the embodiments of the present application provides a method for forming a semiconductor device, including:
  • a first trench is obtained by etching from the first surface of the substrate, the first trench is filled with diamond material; and a second trench is obtained by etching from the second surface of the substrate, in The second groove is filled with diamond material; the first groove and the second groove communicate with each other and have different lateral dimensions; the first surface and the second surface are two opposite surfaces;
  • An epitaxial layer and an electrode are sequentially formed on the first surface of the substrate.
  • the diamond material on the first surface of the substrate can be formed first, then the diamond structure on the second surface can be formed, and then the device structure on the substrate can be formed, so that a complete substrate can be obtained first, and then the device structure can be formed, and
  • the device structure can be formed on the first surface or on the second surface, which can better meet different requirements.
  • both the first trenches and the second trenches are multiple, the multiple first trenches and the multiple second trenches are in one-to-one correspondence, and the The shape of the diamond material in the first groove and the second groove is at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure.
  • the number of the second trenches is less than the number of the first trenches, there are multiple first trenches connected to the same second trench, the first trenches
  • the groove is at least one of a circular truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure.
  • the second trench is one, and if the second trench is formed after the first trench, the bottom of the second trench exposes all or part of the first trench
  • the diamond material in the grooves if the second grooves are formed before the first grooves, the bottoms of the plurality of the first grooves expose the diamond material in the second grooves.
  • the second trenches are a plurality of trenches extending in a predetermined direction parallel to the surface of the substrate, if the second trenches are located in the first trenches After forming, at least one of the second groove bottoms exposes the diamond material in the plurality of first grooves, and if the second grooves are formed before the first grooves, there are a plurality of the first grooves. The bottoms of a trench all expose diamond material in the same second trench.
  • the method before the second trench is obtained by etching the second surface of the substrate, the method further includes:
  • the substrate is thinned from the second surface of the substrate.
  • a power amplifier chip is provided, including the semiconductor device provided in the first aspect of the embodiments of the present application.
  • the embodiments of the present application have the following advantages:
  • Embodiments of the present application provide a semiconductor device and a method for fabricating the same.
  • the semiconductor device may include a substrate, an epitaxial layer and an electrode on the substrate, wherein the substrate has a diamond structure extending through the substrate in a longitudinal direction, and the diamond structure is in the longitudinal direction.
  • the substrate has a diamond structure extending through the substrate in a longitudinal direction, and the diamond structure is in the longitudinal direction.
  • the substrate has a diamond structure extending through the substrate in a longitudinal direction, and the diamond structure is in the longitudinal direction.
  • the lateral dimensions of the first diamond portion and the second diamond portion are different, which can be achieved by two etching processes, reducing the aspect ratio of the etching, which is beneficial to control the structures of the first diamond portion and the second diamond portion, and at the same time can Taking into account the heat dissipation performance and the lattice matching between the epitaxial layers is beneficial to obtain a higher-quality epitaxial layer and to obtain a high-performance semiconductor device.
  • the manufacturing process of the semiconductor device is simple, the difficulty is small, and the substrate is easy to be produced on a large scale.
  • FIG. 1 is a schematic diagram of a base station according to an embodiment of the present application.
  • FIG. 2A is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • FIG. 2B is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.
  • 5-12 are schematic diagrams of device structures in a method for manufacturing a semiconductor device provided by embodiments of the present application.
  • FIG. 13 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present application.
  • the embodiments of the present application provide a semiconductor device and a manufacturing method thereof, which can improve the heat dissipation performance of the semiconductor device and facilitate the effective exertion of the high power performance of the semiconductor device.
  • the heat dissipation performance of the substrate is an important factor affecting the performance of the device.
  • the high power performance of the semiconductor device cannot be effectively exerted due to the limitation of the heat dissipation of the substrate.
  • gallium nitride has the advantages of high two-dimensional electron gas concentration and breakdown voltage, as well as high electron saturation velocity. These advantages are the structure of nitride devices. Provides favorable conditions as a high-power device.
  • the high power performance of semiconductor devices cannot be effectively exerted. This is because silicon-based and sapphire and other materials are currently used as substrates. These materials have poor thermal conductivity.
  • a semiconductor device is output as a high-power device, a large amount of heat will be generated.
  • the substrate material with low thermal conductivity cannot dissipate a large amount of heat in time. , limiting the performance of semiconductor functional devices.
  • the thermal conductivity of the sapphire material is 30-40W/mk
  • the thermal conductivity of the silicon substrate material is 130-150W/mk
  • the single crystal structure type is 4H silicon carbide (silicon carbide, SiC) substrate (referred to as
  • the thermal conductivity range of 4H-SiC substrates can be 280-370W/mk
  • the thermal conductivity of silicon carbide is several times that of traditional silicon or sapphire substrates. Even this cannot meet the heat dissipation of gallium nitride high-power electronic devices. , thus limiting the high-power performance of GaN high-power devices to a certain extent.
  • an active antenna unit (active antenna unit, AAU) of the base station may include a digital to analog converter (digital to analog converter, DAC), a radio frequency Unit (radio frequency, RF), power amplifier (PA) and antenna and other components, the main digital information in AAU is converted into analog signal by digital-to-analog converter, modulated into high-frequency signal by radio frequency unit, and finally amplified by power amplifier to a sufficient level After power, it is transmitted by the antenna unit.
  • DAC digital to analog converter
  • RF radio frequency Unit
  • PA power amplifier
  • the PA In the overall power consumption of the base station, the PA is one of the main power consumption units, and for the 5G base station, the power consumption of the PA in the AAU has a high energy consumption in the form of heat, so the PA needs to have better heat dissipation , in order to ensure the safety of the RF PA chip. If the high heat cannot be conducted out of the device in time, it will have a fatal impact on the PA, and the reliability of the PA will be reduced, and may even fail. For example, if the RF output power of the antenna is 100W, if the power consumption efficiency of the PA is 50%, the power consumption of the PA needs to be 200W, and 100W of energy needs to be consumed as heat. If the power consumption efficiency of the PA is 30%, Then the power consumption of the PA needs to be 333W, and the energy of 233W needs to be consumed in the form of heat, which puts forward very high requirements for the heat dissipation of the device.
  • the way to solve the problem of heat dissipation of high-power devices is to find a material with good thermal conductivity as its substrate, so that the epitaxial layer material can be directly grown on the material, or the two can be effectively bonded to achieve good heat dissipation.
  • the semiconductor device may include a substrate, an epitaxial layer and an electrode located on the substrate, wherein the substrate has a diamond structure extending through the substrate in a longitudinal direction.
  • the diamond structure comprises the first diamond part and the second diamond part below the first diamond part, the lateral dimensions of the first diamond part and the second diamond part are different, due to the good thermal conductivity of the diamond structure, the diamond structure running through the substrate can be formed
  • the longitudinal heat conduction channel can efficiently conduct the heat generated during the operation of the device to the periphery of the device, improve the heat dissipation performance of the semiconductor device, and facilitate the effective performance of the high power performance of the semiconductor device.
  • the lateral dimensions of the first diamond portion and the second diamond portion are different, which can be achieved by two etching processes, reducing the aspect ratio of the etching, which is beneficial to control the structures of the first diamond portion and the second diamond portion, and at the same time can Taking into account the heat dissipation performance and the lattice matching between the epitaxial layers is beneficial to obtain a higher-quality epitaxial layer and to obtain a high-performance semiconductor device.
  • the manufacturing process of the semiconductor device is simple, the difficulty is small, and the substrate is easy to be produced on a large scale.
  • the semiconductor device may include a substrate 100 , an epitaxial layer 200 , and electrodes 401 / 402 / 403 from bottom to top.
  • the substrate 100 is a component that provides support for the device, and has a certain thermal conductivity, which can dissipate the heat generated when the device operates to the outside of the device.
  • the substrate 100 may be a semi-insulating semiconductor material.
  • the material of the substrate 100 may be one or more of silicon, silicon carbide, aluminum nitride, and sapphire.
  • the material of the substrate 100 is silicon carbide.
  • it may be single crystal 4H-SiC, and the thermal conductivity of single crystal 4H-SiC substrate material is generally 280-370 W/mk, which limits the high power performance of semiconductor devices.
  • the substrate 100 may have a diamond structure 110 extending through the substrate in a longitudinal direction, and the diamond structure 110 is a single crystal diamond or a polycrystalline diamond. Since diamond has good thermal conductivity (500-2000 W/mk), the diamond structure 110 extending longitudinally through the substrate 100 can form a longitudinal heat dissipation channel, thus greatly improving the heat dissipation efficiency of the device.
  • the diamond structure 110 may be longitudinally divided into a first diamond portion 112 and a second diamond portion 113, wherein the second diamond portion 113 is located below the first diamond portion 112, the lateral dimension of the first diamond portion 112 and the second diamond portion 113 different, for example, the lateral dimension of the first diamond portion 112 is larger than the lateral dimension of the second diamond portion 113, or the lateral dimension of the first diamond portion 112 is smaller than the lateral dimension of the second diamond portion 113, or the first diamond portion 112 and the second diamond portion 113.
  • Portions 113 have different structures and thus have different dimensional characteristics.
  • the lateral direction refers to the direction along the substrate surface
  • the longitudinal direction refers to the direction perpendicular to the substrate surface, which is also the direction in which the substrate 100 and the epitaxial layer 200 are stacked.
  • the lateral direction can be It is the horizontal direction in the figure and the vertical direction of the paper
  • the longitudinal direction can be the vertical direction in the figure.
  • the first diamond portion 112 may have the same lateral dimension at different heights or may have different lateral dimensions
  • the second diamond portion 113 may have the same lateral dimension at different heights or may have different lateral dimensions.
  • the first diamond portion 112 and the second diamond portion 113 are connected in the longitudinal direction, and the contact positions may have the same lateral dimension, or may have different lateral dimensions.
  • the different lateral dimensions of the first diamond portion 112 and the second diamond portion 113 may be completely different or not completely the same. Different heights have the same lateral dimension, the second diamond portion 113 has the same lateral dimension at different heights, and the lateral dimensions of the first diamond portion 112 and the second diamond portion 113 are different, then the two are completely different; second, One of the first diamond portion 112 and the second diamond portion 113 has the same lateral dimension at different heights, and the other has different lateral dimensions at different heights, then the lateral dimensions of the first diamond portion 112 and the second diamond portion 113 The dimensions are completely different, or not exactly the same; third, the first diamond portion 112 has different lateral dimensions at different heights, the second diamond portion 113 has different lateral dimensions at different heights, the first diamond portion 112 and the second diamond portion 112 have different lateral dimensions at different heights.
  • the lateral dimensions of the diamond portion 113 are completely different or not exactly the same, for example, the two can have different shapes so that the lateral dimensions of the two are not exactly the same or completely different, or they can have the same shape so that the lateral dimensions of the two are not exactly the same. or completely different.
  • the thickness of the substrate 100 may be in the range of 50 -100um
  • the longitudinal dimensions of the first diamond portion 112 and the second diamond portion 113 may be determined according to the shapes of the first diamond portion 112 and the second diamond portion 113 .
  • first diamond portions 112 and second diamond portions 113 there may be multiple first diamond portions 112 and second diamond portions 113, and multiple first diamond portions 112 and multiple second diamond portions 113 are in one-to-one correspondence, that is, one first diamond portion 112 may In connection with a second diamond portion 113, a diamond structure 110 through the substrate 100 is formed.
  • the shape of the first diamond portion 112 and the second diamond portion 113 may be at least one of a circular truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure, that is, the first diamond portion 112 and the second diamond portion.
  • the shape of 113 can be the same or different.
  • the first diamond portion 112 When the first diamond portion 112 is a truncated truncated structure, a prismatic structure or a bowl-shaped structure, the first diamond portion 112 can have different lateral dimensions at different heights. One end is located in the direction of the surface of the substrate 10.
  • the second diamond portion 113 When the second diamond portion 113 is a truncated truncated structure, a prismatic structure or a bowl-shaped structure, the second diamond portion 113 may have different lateral dimensions at different heights. Usually, the end with the larger lateral dimension is located at the surface of the substrate 10. The surface orientation of the substrate 10 .
  • the angle between the sidewall of the first diamond portion 112 and the surface of the substrate is 10-80°, specifically, 30-60° °
  • the angle between the side wall of the bowl-shaped structure and the surface of the substrate 100 can be defined as the angle between the connection line between the bottom center point and the upper edge of the bowl-shaped structure and the surface of the substrate
  • the second diamond portion 113 has similar properties.
  • the first diamond portion 112 may be a truncated cone structure, and the second diamond portion 113 may be a cylindrical structure.
  • the first diamond portion 112 and the second diamond portion 113 may be cylindrical structures with different diameters (refer to FIG. 2B ) As shown, the diameter of the first diamond portion 112 may be larger than the diameter of the second diamond portion 113) or other structures.
  • the longitudinal dimension of the first diamond portion 112 may be 1-10um
  • the lateral dimension of the first diamond portion 112 may be in the range of 1-10um
  • the spacing between the first diamond portions 112 may be in the range of 1-10um
  • the lateral dimension of the second diamond portion 113 may be in the range of 1-10um.
  • the size range is 5-20um, and when the first diamond portion 112 has different lateral dimensions at different heights, the above dimensions represent the size of the first diamond portion 112 at the substrate surface, and the second diamond portion 113 has different heights at different heights.
  • the above dimensions represent the dimensions of the second diamond portion 113 at the substrate surface when the lateral dimension is .
  • the size of the first diamond portion 112 is its diameter, and when the first diamond portion 112 is polygonal at the substrate surface, the size of the first diamond portion 112 is Dimensioned as its side length, the second diamond portion 113 has similar properties.
  • the first diamond portions 112 and the second diamond portions 113 may not be in one-to-one correspondence, and the number of the second diamond portions 113 may be less than the number of the first diamond portions 112, so that there are multiple first diamond portions 112 and
  • the shape of the first diamond portion 112 may be at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure, and the shape of each first diamond portion 112 Can be consistent or inconsistent. Referring to FIG.
  • the second diamond portion 113 may be an integral structure, and the second diamond portion 113 may be longitudinally connected with each of the first diamond portions 112, or may be longitudinally connected with only a portion of the first diamond portions 112, or , the second diamond portion 113 may be multiple, and the second diamond portion 113 extends in a preset direction parallel to the surface of the substrate, and at least one second diamond portion 113 is longitudinally connected with the plurality of first diamond portions 112, thereby forming Bottom-up penetrating structure.
  • an epitaxial layer 200 may be formed, and in the GaN-based HEMT device, the epitaxial layer 200 may include a buffer layer and a barrier layer, and the buffer layer and the barrier layer may form a heterostructure, thereby generating two-dimensional electrons gas, the formed semiconductor device can use the two-dimensional electron gas generated by the heterostructure to work.
  • the semiconductor device in the embodiment of this application can also be other energy devices or lasers, and the epitaxial layer is the epitaxial layer in other devices. , we will not give examples here.
  • the buffer layer can be a gallium nitride layer
  • the material of the barrier layer can be at least one of AlGaN, InAlN, AlN and ScAlN
  • the thickness of the buffer layer can be in the range of 0.1-2um
  • the thickness of the barrier layer can be in the range of 5-20nm . Since the substrate 100 is a silicon carbide substrate, and part of the diamond structure is exposed on the surface of the substrate, the lattice matching degree between the gallium nitride layer and the substrate 100 is high, so the gallium nitride layer has better epitaxial quality, Conducive to the formation of high-performance devices.
  • the gallium nitride layer may include a low temperature gallium nitride layer and a high temperature gallium nitride layer, wherein the low temperature gallium nitride layer serves as a buffer layer between the high temperature gallium nitride layer and the substrate to improve the epitaxial quality of the high temperature gallium nitride layer.
  • Electrodes 401/402/403 may be formed on the epitaxial layer 200, the electrodes may include a source electrode 401, a drain electrode 403 and a gate electrode 402, the gate electrode 402 may be located between the source electrode 401 and the drain electrode 403, and the electrodes 401/402/
  • the material of 403 can be a metal material, for example, it can be at least one of Au, Ti, Al, Ni, and Ta.
  • the material of the electrode can be Au, Ti/Al/Ni/Au stack or Ta/Al/Ta stacks.
  • Embodiments of the present application provide a semiconductor device.
  • the semiconductor device may include a substrate, an epitaxial layer and an electrode on the substrate, wherein the substrate has a diamond structure longitudinally extending through the substrate, and the diamond structure includes a first diamond portion and an electrode.
  • the second diamond portion below the first diamond portion, the lateral dimensions of the first diamond portion and the second diamond portion are different, due to the good thermal conductivity of the diamond structure, the diamond structure running through the substrate can form a longitudinal heat conduction channel, so that the device can be connected.
  • the heat generated in the working process is efficiently conducted to the periphery of the device, which improves the heat dissipation performance of the semiconductor device and is beneficial to the effective exertion of the high-power performance of the semiconductor device.
  • the lateral dimensions of the first diamond portion and the second diamond portion are different, which can be achieved by two etching processes, reducing the aspect ratio of the etching, which is beneficial to control the structures of the first diamond portion and the second diamond portion, and at the same time can Taking into account the heat dissipation performance and the lattice matching between the epitaxial layers is beneficial to obtain a higher-quality epitaxial layer and to obtain a high-performance semiconductor device.
  • the manufacturing process of the semiconductor device is simple, the difficulty is small, and the substrate is easy to be produced on a large scale.
  • the embodiment of the present application also provides a method for manufacturing a semiconductor device.
  • the embodiment of the present application provides a method for manufacturing a semiconductor device that provides the substrate 100 .
  • 5-12 are schematic diagrams of the structure of the device in the device manufacturing process.
  • the first diamond portion 112 in the diamond structure can be formed in the substrate 100 first, and then the device structure on it is formed, and then Forming the second diamond portion 113 in the diamond structure in the substrate 100, specifically, the method may include:
  • a substrate 100 is provided, as shown in FIG. 5 .
  • the substrate 100 is a component that provides support for the device, and has a certain thermal conductivity, which can dissipate the heat generated when the device operates to the outside of the device.
  • the substrate 100 may be a semi-insulating semiconductor material.
  • the material of the substrate 100 may be one or more of silicon, silicon carbide, aluminum nitride, and sapphire.
  • the material of the substrate 100 is silicon carbide.
  • it may be single crystal 4H-SiC, and the thermal conductivity of single crystal 4H-SiC substrate material is generally 280-370 W/mk, which limits the high power performance of semiconductor devices.
  • the first trench 101 may be obtained by etching the first surface of the substrate 100 , as shown in FIG. 6 , and the first trench 101 is filled with diamond material, and the first trench 101 is filled with diamond material.
  • the diamond material can be used as the first diamond portion 112 in the previous embodiment, as shown in FIG. 8 .
  • the etching of the substrate 100 may use dry anisotropic etching, such as plasma etching.
  • the lateral dimension of the first trenches 101 obtained by etching is 1-10um, the etching depth is 1-10um, the spacing between different first trenches 101 is in the range of 1-10um, and the first trenches 101 can form periodicity array arrangement.
  • the shape of the first trench 101 can be controlled by controlling the etching parameters of the substrate 100, and the shape of the first trench 101 can be at least one of a frustum structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure , wherein the larger ends of the circular truncated structure, the prismatic structure and the bowl-shaped structure face the surface of the substrate.
  • the damage to the sidewall of the first trench 101 by the etching gas can be reduced by slowing down the etching rate. , so as to form the structure of the first trench 101 with a large upper and a smaller lower.
  • diamond material may be filled in the first trench 101, and the diamond material is single crystal diamond or polycrystalline diamond.
  • diamond material can be grown on the substrate 100 formed with the first groove 101, and after a period of growth, a high-quality polycrystalline diamond layer 111 can be formed on the substrate with a thickness of 1-50um, Refer to Figure 7.
  • part of the diamond layer 111 is removed by grinding and polishing to expose the surface of the substrate 100, so that the diamond material is only formed in the first groove 101, and the size of the diamond material is the same or similar to that of the first groove 101, referring to FIG. 8 shown.
  • the way of growing the diamond material can be microwave plasma chemical vapor deposition (MPCVD), the temperature range of material growth can be 800-1200°C, and the pressure range can be 1-15KPa.
  • MPCVD method has the advantages of stable plasma discharge and less pollution, and can grow high-quality diamond materials.
  • An epitaxial layer 200 may be formed on the first surface of the substrate 100.
  • the epitaxial layer 200 may include a buffer layer and a barrier layer, and the buffer layer and the barrier layer A heterostructure can be formed to generate a two-dimensional electron gas, and the formed semiconductor device can work with the two-dimensional electron gas generated by the heterostructure.
  • the buffer layer can be a gallium nitride layer
  • the material of the barrier layer can be at least one of AlGaN, InAlN, AlN and ScAlN
  • the thickness of the buffer layer can be in the range of 0.1-2um
  • the thickness of the barrier layer can be in the range of 5-20nm .
  • a buffer layer may be formed on the first surface of the substrate 100, and then a barrier layer may be formed on the buffer layer.
  • the formation method of the gallium nitride layer can be metal organic chemical vapor deposition (MOCVD). Due to the serious lattice mismatch between the diamond material and gallium nitride, gallium nitride grows faster on silicon carbide. The growth on diamond is slow or even impossible, so that the lateral growth of gallium nitride on silicon carbide is strengthened, dislocations merge, and a higher quality gallium nitride layer is obtained.
  • MOCVD metal organic chemical vapor deposition
  • the gallium nitride layer may include a low temperature gallium nitride layer and a high temperature gallium nitride layer, wherein the low temperature gallium nitride layer serves as a buffer layer between the high temperature gallium nitride layer and the substrate to improve the epitaxial quality of the high temperature gallium nitride layer.
  • the formation method of the barrier layer may also be the method of MOCVD.
  • Electrodes 401/402/403 may be formed on the epitaxial layer 200, the electrodes 401/402/403 may include a source electrode 401, a drain electrode 403 and a gate electrode 402, and the gate electrode 402 may be located between the source electrode 401 and the drain electrode 403, refer to As shown in FIG. 10 , the material of the electrodes 401/402/403 may be metal materials, for example, at least one of Au, Ti, Al, Ni, and Ta. As a possible implementation, the electrodes 401/402/403 The material can be Au, Ti/Al/Ni/Au stack or Ta/Al/Ta stack.
  • the second surface of the substrate 100 is etched to obtain a second trench 102.
  • the second trench 102 is connected to the first trench 101 and has different lateral dimensions.
  • the second trench 102 is filled with diamond material, as shown in FIG. 11. Figure 12, Figure 2A, Figure 2B, and Figure 3.
  • a dielectric layer may also be formed to cover the electrodes 401/402/403 to form protection for the electrodes (not shown in the figure).
  • the second surface of the substrate 100 may be etched to obtain the second trench 102 , the first surface and the second surface are two opposite surfaces, as shown in FIG. 11 and FIG. 12 , and in the second trench 102 Filled with diamond material, the diamond material in the second groove 102 can be used as the second diamond portion 113 in the previous embodiment, the first groove 101 and the second groove 102 are connected, then the diamond material in the first groove 101 Contact with the diamond material in the second trench 102 constitutes a through-substrate diamond structure 110 as shown with reference to FIGS.
  • the substrate 100 Before etching the second surface of the substrate 100, the substrate 100 may also be thinned from the second surface of the substrate 100, so that the thickness of the substrate 100 is in the range of 50-100um, the first diamond portion 112 The sum of the longitudinal dimensions of the second diamond portion 113 is the same as the thickness of the substrate 100 .
  • chip bonding can be performed. At this time, the chip will be turned over to make the substrate face up to realize bonding.
  • the above etching of the second surface of the substrate is compatible with the actual operation steps. , higher performance devices can be obtained without adding too many steps.
  • first trenches 101 and second trenches 102 there may be multiple first trenches 101 and second trenches 102 , the first trenches 101 and the second trenches 102 may be in one-to-one correspondence, and one first trench 101 may correspond to one second trench 102 connected to form a through hole through the substrate, as shown in FIG. 11 .
  • the shapes of the first grooves 101 and the second grooves 102 may be at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure, and the first grooves 101 and the second grooves 102 The shapes can be the same or different.
  • the first diamond portion 112 is a truncated frustum structure, a prismatic frustum structure or a bowl-shaped structure
  • the end with the larger lateral dimension is located in the direction of the substrate surface.
  • usually the larger end of the lateral dimension is located in the direction of the surface of the substrate.
  • the angle between the sidewall of the first trench 101 and the surface of the substrate is 10-80°, specifically, 30-60° °
  • the angle between the side wall of the bowl-shaped structure and the surface of the substrate can be defined as the angle between the connection line between the bottom center point and the upper edge of the bowl-shaped structure and the surface of the substrate
  • the second diamond portion 113 have similar characteristics.
  • the lateral dimension of the second trench 102 is in the range of 5-20um, and the longitudinal dimension can be 40-99um.
  • the above dimensions indicate that the first trench 101 is on the surface of the substrate
  • the second trench 102 has different lateral dimensions at different heights
  • the above dimensions represent the size of the opening of the second trench 102 at the substrate surface.
  • the size of the first trench 101 is its diameter
  • the size of the first trench 101 is Dimensioned as its side length, the second trench 102 has similar properties.
  • the first trenches 101 and the second trenches 102 may not be in one-to-one correspondence, and the number of the second trenches 102 may be less than the number of the first trenches 101, so that there are multiple first trenches 101 and
  • the shape of the first groove 101 may be at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure, as shown in FIG. 12 . Referring to FIG.
  • the second groove 102 may be an integral structure, and the second groove 102 may be longitudinally connected with each of the first grooves 101 , or may be longitudinally connected with only a part of the first diamond portion 112 , that is, The bottom of the second trench 102 may expose all or part of the diamond material in the first trench 101 .
  • the number of second trenches 102 may also be multiple, and the second trenches 102 extend in a predetermined direction parallel to the surface of the substrate. At least one second trench 102 is longitudinally connected with the multiple first trenches 101 , thereby forming The bottom-up through structure, that is, at least one second trench 102 exists at the bottom to expose the diamond material in the plurality of first trenches 101 .
  • a large-area etching can be performed on the second surface of the substrate, and most of the material on the second surface of the substrate can be removed to obtain a cavity structure as the second trench 102, and the cavity structure exposes the first trench
  • the diamond material in the groove 101 so that after the second groove 102 is filled with the diamond material, the diamond material in the first groove 101 and the diamond material in the second groove 102 are in contact, forming a diamond structure through the substrate, forming a longitudinal The thermal conduction path, the first diamond portion 112 of the diamond structure is in contact with the epitaxial layer on the substrate, and the second diamond portion 113 of the diamond structure is exposed outside the substrate, which can conduct heat generated inside the device to the outside of the device.
  • a heat sink may also be arranged under the substrate, and the second diamond portion 113 of the diamond structure may be in contact with the heat sink, so as to rapidly conduct heat to the heat sink, thereby realizing rapid heat dissipation of the device.
  • the second trench 102 is a large-area cavity structure, the exposed area of the diamond structure outside the substrate is larger, and the contact area with the heat sink is also larger, which further improves the heat dissipation efficiency.
  • the substrate 100 may have a first trench 101 that is not communicated with the second trench 102 , may be used as a third trench, or may have a second trench 102 that is not communicated with the first trench 101 .
  • the diamond material in the third groove and the fourth groove can still dissipate heat outward, for example, through lateral heat conduction to conduct heat to other diamond materials, or downward heat dissipation to directly diffuse heat out of the device, or through the lining
  • the bottom 100 diffuses out of the device, or out of the device through the substrate 100 and other diamond material.
  • a first trench can be obtained by etching a first surface of a substrate, and a diamond material is filled in the first trench, and a first trench can be obtained on the first surface of the substrate.
  • the epitaxial layer and the electrode are formed in sequence, and then the second surface of the substrate can be etched to obtain a second trench, the second trench is connected with the first trench, and the lateral dimensions of the two are different, and the second trench is filled with diamond material, such that the diamond material in the first groove is in contact with the diamond material in the second groove to form a diamond structure that penetrates the substrate. Due to the good thermal conductivity of the diamond structure, the diamond structure that penetrates the substrate can form a longitudinal thermal conductivity.
  • the heat generated during the operation of the device can be efficiently conducted to the periphery of the device, the heat dissipation performance of the semiconductor device can be improved, and the high power performance of the semiconductor device can be effectively exerted.
  • the lateral dimensions of the first diamond portion and the second diamond portion are different, which can be achieved by two etching processes, reducing the aspect ratio of the etching, which is beneficial to control the structures of the first diamond portion and the second diamond portion, so as to take into account
  • the heat dissipation performance and the lattice matching between the epitaxial layers are beneficial to obtain a higher quality epitaxial layer and to obtain a high-performance semiconductor device.
  • the manufacturing process of the semiconductor device is simple, the difficulty is small, and the substrate is easy to be produced on a large scale.
  • the embodiment of the present application also provides a method for manufacturing a semiconductor device.
  • a flowchart of another method for manufacturing a semiconductor device provided by the embodiment of the present application is shown in FIG. 13 .
  • the first diamond portion 112 and the second diamond portion 113 in the diamond structure can be formed in the substrate 100 first, and then the device structure thereon is formed.
  • the method can include:
  • the substrate 100 is provided.
  • the substrate 100 is a component that provides support for the device, and has a certain thermal conductivity, which can dissipate the heat generated when the device operates to the outside of the device.
  • the substrate 100 may be a semi-insulating semiconductor material.
  • the material of the substrate 100 may be one or more of silicon, silicon carbide, aluminum nitride, and sapphire.
  • the material of the substrate 100 is silicon carbide.
  • it may be single crystal 4H-SiC, and the thermal conductivity of single crystal 4H-SiC substrate material is generally 280-370 W/mk, which limits the high power performance of semiconductor devices.
  • the first groove 101 may be obtained by etching the first surface of the substrate 100, and the diamond material is filled in the first groove 101, and the diamond material filled in the first groove 101 can be used as the aforementioned The first diamond portion 112 in the embodiment.
  • the etching of the substrate 100 may use dry anisotropic etching, such as plasma etching.
  • the lateral dimension of the first trenches 101 obtained by etching is 1-10um, the etching depth is 1-10um, the spacing between different first trenches 101 is in the range of 1-10um, and the first trenches 101 can form periodicity array arrangement.
  • the shape of the first trench 101 can be controlled by controlling the etching parameters of the substrate 100, and the shape of the first trench 101 can be at least one of a frustum structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure , wherein the larger ends of the circular truncated structure, the prismatic structure and the bowl-shaped structure face the surface of the substrate.
  • the damage to the sidewall of the first trench 101 by the etching gas can be reduced by slowing down the etching rate. , so as to form the structure of the first trench 101 with a large upper and a smaller lower.
  • diamond material may be filled in the first trench 101, and the diamond material is single crystal diamond or polycrystalline diamond.
  • diamond material can be grown on the substrate 100 formed with the first grooves 101 , and after a period of growth, a high-quality polycrystalline diamond layer 111 with a thickness of 1-50um can be formed on the substrate 100 .
  • part of the diamond layer 111 is removed by grinding and polishing to expose the surface of the substrate 100 , so that the diamond material is only formed in the first groove 101 , and the size of the diamond material is the same or similar to that of the first groove 101 .
  • the way of growing the diamond material can be MPCVD, the temperature range of the material growth can be 800-1200°C, and the pressure range can be 1-15KPa.
  • the MPCVD method has the advantages of stable plasma discharge and less pollution, and can grow high-quality diamond materials.
  • the second surface of the substrate 100 may also be etched to obtain the second trench 102, and the second trench 102 is filled with diamond material, and the first surface and the second surface are two opposite
  • the diamond material in the second groove 102 can be used as the second diamond portion 113 in the previous embodiment, and the first groove 101 and the second groove 102 communicate with each other, then the diamond material in the first groove 101 and the second
  • the diamond material in the trenches 102 contacts the diamond structures that make up the through-substrate 100 . Since the lateral dimensions of the first trench 101 and the second trench 102 are different, the lateral dimensions of the first diamond portion 112 and the second diamond portion 113 of the formed diamond structure are different.
  • the diamond structure extending longitudinally through the substrate 100 can form a longitudinal heat dissipation channel, which can greatly improve the heat dissipation efficiency of the device.
  • the substrate 100 Before etching the second surface of the substrate 100, the substrate 100 may also be thinned from the second surface of the substrate 100, so that the thickness of the substrate 100 is in the range of 50-100um, the first diamond portion 112 The sum of the longitudinal dimensions of the second diamond portion 113 is the same as the thickness of the substrate 100 .
  • the etching sequence of the first trench 101 and the second trench 102 can be arbitrary. If the first trench 101 is etched before the second trench 102, the etching is performed in the second trench 102. The diamond material needs to be filled in the first trench 101 before, and the diamond material in the first trench 101 is exposed at the bottom of the second trench 102. If the second trench 102 is etched before the first trench 101, the Before the trench 101 is etched, the second trench 102 needs to be filled with diamond material, and the diamond material in the second trench 102 is exposed at the bottom of the first trench 101 .
  • first trenches 101 and the second trenches 102 may be in one-to-one correspondence, and a first trench 101 may be communicated with a second trench 102 to form a through hole passing through the substrate 100 .
  • the shapes of the first grooves 101 and the second grooves 102 may be at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure, and the first grooves 101 and the second grooves 102 The shapes can be the same or different.
  • first diamond portion 112 is a truncated frustum structure, a prismatic frustum structure or a bowl-shaped structure
  • the end with the larger lateral dimension is located in the direction of the surface of the substrate 100
  • the second diamond portion 113 is a frustum, frustum or bowl-shaped structure.
  • the end with the larger lateral dimension is located in the direction of the surface of the substrate 100 .
  • the angle between the sidewall of the first trench 101 and the surface of the substrate is 10-80°, specifically, 30-60° °
  • the angle between the side wall of the bowl-shaped structure and the surface of the substrate can be defined as the angle between the connection line between the bottom center point and the upper edge of the bowl-shaped structure and the surface of the substrate
  • the second diamond portion 113 have similar characteristics.
  • the lateral dimension of the second trench 102 is in the range of 5-20um, and the longitudinal dimension can be 40-99um.
  • the above dimensions indicate that the first trench 101 is on the surface of the substrate
  • the second trench 102 has different lateral dimensions at different heights
  • the above dimensions represent the size of the opening of the second trench 102 at the substrate surface.
  • the size of the first trench 101 is its diameter
  • the size of the first trench 101 is Dimensioned as its side length, the second trench 102 has similar properties.
  • the first trenches 101 and the second trenches 102 may not be in one-to-one correspondence, and the number of the second trenches 102 may be less than the number of the first trenches 101, so that there are multiple first trenches 101 and
  • the shape of the first groove 101 may be at least one of a truncated truncated structure, a prismatic structure, a bowl-shaped structure, a cylindrical structure and a prismatic structure.
  • the second grooves 102 may be an integral structure, and the second grooves 102 may be longitudinally connected with each of the first grooves 101 , or may be longitudinally connected with only a part of the first grooves 101 . Specifically, if the second trench 102 is formed after the first trench 101 , the bottom of the second trench 102 may expose all or part of the diamond material in the first trench 101 . Before the trenches 101 are formed, the bottoms of the plurality of first trenches 101 all expose the diamond material in the second trenches 102 .
  • the number of second trenches 102 may also be multiple, and the second trenches 102 extend in a predetermined direction parallel to the surface of the substrate. At least one second trench 102 is longitudinally connected with the multiple first trenches 101 , thereby forming Bottom-up penetrating structure. Specifically, if the second trenches 102 are formed before the first trenches 101 , at least one second trench 102 exists at the bottom to expose the diamond material in the plurality of first trenches 101 . After the trenches 101 are formed, the bottoms of the plurality of first trenches 101 all expose the diamond material in the same second trench 102 .
  • a large-area etching can be performed on the second surface of the substrate 100, and most of the material on the second surface of the substrate 100 can be removed to obtain a cavity structure as the second trench 102, the first trench 101 and the The second trenches 102 are connected, so that after the diamond material is filled in the first trench 101 and the second trench 102 , the diamond material in the first trench 101 and the diamond material in the second trench 102 are in contact to form a through-substrate 100
  • the diamond structure forms a longitudinal thermal conduction path, the first diamond portion 112 of the diamond structure is in contact with the epitaxial layer on the substrate 100, and the second diamond portion 113 of the diamond structure is exposed outside the substrate 100, which can convert the heat generated inside the device.
  • a heat sink may also be disposed under the substrate 100, and the second diamond portion 113 of the diamond structure may be in contact with the heat sink, so as to rapidly conduct heat to the heat sink, thereby realizing rapid heat dissipation of the device.
  • the second trench 102 is a large-area cavity structure, the exposed area of the diamond structure outside the substrate 100 is larger, and the contact area with the heat sink is also larger, which further improves the heat dissipation efficiency.
  • the substrate 100 may have a first trench 101 that is not communicated with the second trench 102 , may be used as a third trench, or may have a second trench 102 that is not communicated with the first trench 101 .
  • the diamond material in the third groove and the fourth groove can still dissipate heat outward, for example, through lateral heat conduction to conduct heat to other diamond materials, or downward heat dissipation to directly diffuse heat out of the device, or through the lining
  • the bottom 100 diffuses out of the device, or out of the device through the substrate 100 and other diamond material.
  • An epitaxial layer 200 may be formed on the substrate 100, and when the semiconductor device is a GaN-based HEMT device, the epitaxial layer 200 may include a buffer layer and a barrier layer, and the buffer layer and the barrier layer may form a heterostructure, thereby generating a two-dimensional Electron gas, the formed semiconductor device can work with the two-dimensional electron gas generated by this heterostructure.
  • the buffer layer can be a gallium nitride layer
  • the material of the barrier layer can be at least one of AlGaN, InAlN, AlN and ScAlN
  • the thickness of the buffer layer can be in the range of 0.1-2um
  • the thickness of the barrier layer can be in the range of 5-20nm .
  • a buffer layer may be formed on the first surface of the substrate 100, and then a barrier layer may be formed on the buffer layer.
  • the formation method of gallium nitride layer can be MOCVD. Due to the serious lattice mismatch between diamond material and gallium nitride, gallium nitride grows faster on silicon carbide, and grows slowly or even cannot grow on diamond, which makes carbide Lateral growth of gallium nitride on silicon is enhanced and dislocations merge, resulting in a higher quality gallium nitride layer.
  • the gallium nitride layer may include a low temperature gallium nitride layer and a high temperature gallium nitride layer, wherein the low temperature gallium nitride layer serves as a buffer layer between the high temperature gallium nitride layer and the substrate 100 to improve the epitaxial quality of the high temperature gallium nitride layer.
  • the formation method of the barrier layer may also be the method of MOCVD.
  • Electrodes 401/402/403 may be formed on the epitaxial layer 200, the electrodes 401/402/403 may include a source electrode 401, a drain electrode 403 and a gate electrode 402, the gate electrode 402 may be located between the source electrode 401 and the drain electrode 403, and the electrode
  • the material of 401/402/403 can be a metal material, for example, it can be at least one of Au, Ti, Al, Ni, and Ta.
  • the material of the electrodes 401/402/403 can be Au, Ti/Al/Ni/Au stack or Ta/Al/Ta stack.
  • a dielectric layer may also be formed to cover the electrodes to protect the electrodes 401/402/403.
  • a first trench can be obtained by etching a first surface of a substrate, and diamond material is filled in the first trench, and a second surface of the substrate is etched.
  • the second trench is obtained by etching, the second trench is connected with the first trench, and the lateral dimensions of the two are different, the second trench is filled with diamond material, and then an epitaxial layer can be formed on the first surface of the substrate in sequence and electrode, so that the diamond material in the first groove is in contact with the diamond material in the second groove to form a diamond structure that runs through the substrate. Due to the good thermal conductivity of the diamond structure, the diamond structure that runs through the substrate can form a longitudinal thermal conductivity.
  • the heat generated during the operation of the device can be efficiently conducted to the periphery of the device, the heat dissipation performance of the semiconductor device can be improved, and the high power performance of the semiconductor device can be effectively exerted.
  • the lateral dimensions of the first diamond portion and the second diamond portion are different, which can be achieved by two etching processes, reducing the aspect ratio of the etching, which is beneficial to control the structure of the first diamond portion and the second diamond portion, so as to take into account
  • the heat dissipation performance and the lattice matching between the epitaxial layers are beneficial to obtain a higher quality epitaxial layer and to obtain a high-performance semiconductor device.
  • the manufacturing process of the semiconductor device is simple, the difficulty is small, and the substrate is easy to be produced on a large scale.

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Abstract

本申请实施例公开了一种半导体器件及其制造方法，半导体器件可以包括衬底，以及位于衬底上的外延层和电极，其中衬底中具有纵向贯穿衬底的金刚石结构，金刚石结构在纵向上可以分为第一金刚石部分和第一金刚石部分下方的第二金刚石部分，第一金刚石部分和第二金刚石部分的横向尺寸不同，由于金刚石结构的导热性能好，贯穿衬底的金刚石结构可以构成纵向的导热通道，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。此外，第一金刚石部分和第二金刚石部分的横向尺寸不同，则利于控制第一金刚石部分和第二金刚石部分的结构，同时可以兼顾散热性能和外延层之间的晶格匹配，利于得到更高质量的外延层，利于得到高性能的半导体器件。

Description

一种半导体器件及其制造方法 技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
在半导体器件中，基底的散热性能是影响器件性能的重要因素，在一些场景下由于基底散热的限制，半导体器件的高功率性能并不能有效发挥出来。
举例来说，随着高频、高功率的发展趋势，基于氮化镓(gallium nitride，GaN)的高电子迁移率晶体管(high-electron-mobility transistor，HEMT)在第五代移动通信技术(the 5th generation mobile network，5G)领域的功率放大器(power amplifier，PA)芯片上得到越来越多的应用，氮化镓作为第三代宽禁带半导体材料，具有较高的二维电子气浓度和击穿电压，同时还具有较高的电子饱和速度等优点，这些优点为氮化物器件结构作为大功率器件提供了有利的条件，这些新的应用场景对基于氮化镓的HEMT器件的功率、频率、效率和可靠性也提出了更高的要求。但是散热成为了基于氮化镓的HEMT器件的一个关键瓶颈。这是因为目前基底多使用硅基和蓝宝石等材料，这些材料的导热性能较差，氮化镓器件作为大功率器件输出时会产生大量的热，低热导率的基底材料不能及时将大量的热散发出去，限制了氮化镓功能器件的性能。
发明内容
有鉴于此，本申请的第一方面提供了一种半导体器件及其制造方法，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。
本申请实施例的第一方面，提供了一种半导体器件，包括衬底，依次位于衬底上的外延层以及电极，其中衬底中具有纵向贯穿衬底的金刚石结构，金刚石结构在纵向上分为第一金刚石部分和第二金刚石部分，第二金刚石部分可以位于第一金刚石部分的下方，第一金刚石部分和第二金刚石部分的横向尺寸可以不同，具体的，可以完全不同或不完全相同。由于金刚石结构的导热性能好，贯穿衬底的金刚石结构可以构成纵向的导热通道，从而可以将器件工作过程中产生的热量高效地传导至器件外围，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。此外，第一金刚石部分和第二金刚石部分的横向尺寸不同，则可以通过两次刻蚀工艺实现，降低刻蚀的深宽比，利于控制第一金刚石部分和第二金刚石部分的结构，同时可以兼顾散热性能和外延层之间的晶格匹配，利于得到更高质量的外延层，利于得到高性能的半导体器件。
在一些可能的实施方式中，所述第一金刚石结构和所述第二金刚石结构均为多个，多个所述第一金刚石部分和多个所述第二金刚石部分一一对应，且为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
本申请实施例中，第一金刚石部分和第二金刚石部分可以一一对应，这样一个第一金刚石结构和一个第二金刚石结构可以形成一个纵向的导热通道，从而可以利用多个导热通道向器件外围散热，实现较高的散热效率。第一金刚石部分和第二金刚石部分可以有多种 形状，针对不同的外延层可以有针对性的设计，从而兼顾散热性能和晶格匹配，提高外延质量。
在一些可能的实施方式中，所述第二金刚石部分的数量少于所述第一金刚石部分的数量，存在多个所述第一金刚石部分与同一个第二金刚石部分连接，所述第一金刚石部分为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
本申请实施例中，在下方的第二金刚石部分的数量可以少于第一金刚石部分的数量，这样一个第二金刚石部分可以和多个第一金刚石部分连接，从而第二金刚石部分的横向尺寸可以大于第一金刚石部分，使衬底远离外延层的表面的金刚石暴露较多，而靠近外延层的表面的金刚石暴露较少，保证器件散热性能的同时兼顾外延质量。
在一些可能的实施方式中，所述第二金刚石部分为一个，且与全部或部分所述第一金刚石部分纵向连接。
本申请实施例中，第二金刚石部分为一个，这样第二金刚石部分可以具有较大的横向尺寸，从而在不影响外延层质量的同时进一步提高器件的散热性能。
在一些可能的实施方式中，所述第二金刚石部分为多个，所述第二金刚石部分在平行于所述衬底表面的预设方向上延伸，且至少存在一个所述第二金刚石部分与多个所述第一金刚石部分纵向连接。
本申请实施例中，第二金刚石部分也可以为多个，多个第二金刚石部分可以沿同一方向延伸，这样第二金刚石部分可以具有较大的横向尺寸，从而在不影响外延层质量的同时进一步提高器件的散热性能。
在一些可能的实施方式中，所述第一金刚石部分的横向尺寸范围为1-10um，所述第一金刚石部分的纵向尺寸范围为1-10um，不同所述第一金刚石部分之间的间距范围为1-10um，所述衬底的厚度范围为50-100um。
本申请实施例中，第一金刚石部分可以占衬底厚度的小部分，各个第一金刚石部分之间具有合理的间距，从而在保证外延层质量的同时保证器件的散热性能。
在一些可能的实施方式中，所述衬底的材料为硅、碳化硅、氮化铝、蓝宝石中的一种或多种。
本申请实施例中，衬底可以为硅衬底、碳化硅衬底、氮化铝衬底、蓝宝石衬底中的一种或多种，即使衬底的散热性能不够好，在利用金刚石形成散热通道后，可以保证器件的散热性能，且这些衬底的制造工艺简单，易于规模化生产。
在一些可能的实施方式中，所述金刚石结构为单晶金刚石或多晶金刚石。
本申请实施例中，金刚石结构可以为单晶金刚石也可以为多晶金刚石，可以根据实际情况确定，能够实现良好的散热即可。
在一些可能的实施方式中，所述外延层包括缓冲层和势垒层，所述缓冲层为氮化镓层，所述势垒层的材料为AlGaN、InAlN、AlN和ScAlN中的一种或多种。
本申请实施例中，外延层可以包括缓冲层和势垒层，缓冲层可以为氮化镓层，则半导体结构可以为氮化镓器件，势垒层和氮化镓层之间可以形成二维电子气，从而提供较好的器件性能。
在一些可能的实施方式中，所述氮化镓层的厚度范围为0.1-2um，所述势垒层的厚度范围为5-20nm。
本申请实施例中，氮化镓层和势垒层的厚度可以在合理的范围，保证器件的性能。
在一些可能的实施方式中，所述电极包括源极、漏极和栅极，所述电极的材料为Au、Ti、Al、Ni、Ta中的至少一种。
本申请实施例中，电极可以包括源极、漏极和栅极，电极材料可以为多种，保证了器件的完整性和优越的性能。
本申请实施例的第二方面，提供了一种半导体器件的形成方法，包括：
提供衬底；
对所述衬底的第一表面进行刻蚀得到第一沟槽；
在所述第一沟槽中填充金刚石材料；
在所述衬底的第一表面上依次形成外延层和电极；
对所述衬底的第二表面进行刻蚀得到第二沟槽，所述第二沟槽和所述第一沟槽连通，且横向尺寸不同；所述第一表面和所述第二表面为两个相对的表面；
在所述第二沟槽中填充金刚石材料。
本申请实施例中，可以先形成衬底第一表面的金刚石材料，再形成衬底上的器件结构，再形成第二表面的金刚石结构，这样与现有技术中形成器件结构后翻转器件进行键合的步骤匹配，因此可以在尽量少步骤的前提下得到本申请实施例中的高性能高散热的器件。
在一些可能的实施方式中，所述第一沟槽和所述第二沟槽均为多个，多个所述第一沟槽和多个所述第二沟槽一一对应，且所述第一沟槽和所述第二沟槽中的金刚石材料的形状为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
在一些可能的实施方式中，所述第二沟槽的数量少于所述第一沟槽的数量，存在多个所述第一沟槽与同一个第二沟槽连接，所述第一沟槽的形状为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的一种。
在一些可能的实施方式中，所述第二沟槽为一个，且所述第二沟槽底部暴露全部或部分所述第一沟槽中的金刚石材料。
在一些可能的实施方式中，所述第二沟槽为多个在平行于所述衬底表面的预设方向上延伸的沟槽，且至少存在一个所述第二沟槽底部暴露多个所述第一沟槽中的金刚石材料。
在一些可能的实施方式中，所述对所述衬底的第二表面进行刻蚀得到第二沟槽之前，还包括：
从所述衬底的第二表面对所述衬底进行减薄。
本申请实施例的第三方面，提供了一种半导体器件的形成方法，包括：
提供衬底；
从所述衬底的第一表面进行刻蚀得到第一沟槽，在所述第一沟槽中填充金刚石材料；以及从所述衬底的第二表面进行刻蚀得到第二沟槽，在所述第二沟槽中填充金刚石材料； 所述第一沟槽和所述第二沟槽连通，且横向尺寸不同；所述第一表面和所述第二表面为两个相对的表面；
在所述衬底的第一表面依次形成外延层和电极。
本申请实施例中，可以先形成衬底第一表面的金刚石材料，再形成第二表面的金刚石结构，再形成衬底上的器件结构，这样能够先得到完整的衬底再形成器件结构，且器件结构可以形成于第一表面，也可以形成于第二表面，更加能够满足不同的需求。
在一些可能的实施方式中，所述第一沟槽和所述第二沟槽均为多个，多个所述第一沟槽和多个所述第二沟槽一一对应，且所述第一沟槽和所述第二沟槽中的金刚石材料的形状为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
在一些可能的实施方式中，所述第二沟槽的数量少于所述第一沟槽的数量，存在多个所述第一沟槽与同一个第二沟槽连接，所述第一沟槽为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
在一些可能的实施方式中，所述第二沟槽为一个，则若所述第二沟槽在所述第一沟槽之后形成，所述第二沟槽底部暴露全部或部分所述第一沟槽中的金刚石材料，若所述第二沟槽在所述第一沟槽之前形成，多个所述第一沟槽的底部暴露所述第二沟槽中的金刚石材料。
在一些可能的实施方式中，所述第二沟槽为多个在平行于所述衬底表面的预设方向上延伸的沟槽，则若所述第二沟槽在所述第一沟槽之后形成，至少存在一个所述第二沟槽底部暴露多个所述第一沟槽中的金刚石材料，若所述第二沟槽在所述第一沟槽之前形成，存在多个所述第一沟槽底部均暴露同一所述第二沟槽中的金刚石材料。
在一些可能的实施方式中，所述对所述衬底的第二表面进行刻蚀得到第二沟槽之前，还包括：
从所述衬底的第二表面对所述衬底进行减薄。
本申请实施例第四方面，提供了一种功率放大器芯片，包括如本申请实施例第一方面提供的所述的半导体器件。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例提供一种半导体器件及其制造方法，半导体器件可以包括衬底，以及位于衬底上的外延层和电极，其中衬底中具有纵向贯穿衬底的金刚石结构，金刚石结构在纵向上可以分为第一金刚石部分和第一金刚石部分下方的第二金刚石部分，第一金刚石部分和第二金刚石部分的横向尺寸不同，由于金刚石结构的导热性能好，贯穿衬底的金刚石结构可以构成纵向的导热通道，从而可以将器件工作过程中产生的热量高效地传导至器件外围，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。此外，第一金刚石部分和第二金刚石部分的横向尺寸不同，则可以通过两次刻蚀工艺实现，降低刻蚀的深宽比，利于控制第一金刚石部分和第二金刚石部分的结构，同时可以兼顾散热性能和外延层之间的晶格匹配，利于得到更高质量的外延层，利于得到高性能的半导体器件。同 时，半导体器件的制造工艺简单，难度小，衬底易于规模化生产。
附图说明
为了清楚地理解本申请的具体实施方式，下面将描述本申请具体实施方式时用到的附图做一简要说明。显而易见地，这些附图仅是本申请的部分实施例。
图1为本申请实施例提供的一种基站的示意图；
图2A为本申请实施例提供的一种半导体器件的结构示意图；
图2B为本申请实施例提供的另一种半导体器件的结构示意图；
图3为本申请实施例提供的又一种半导体器件的结构示意图；
图4为本申请实施例提供的一种半导体器件的制造方法的流程图；
图5-图12为本申请实施例提供的一种半导体器件的制造方法中器件结构示意图；
图13为本申请实施例提供的另一种半导体器件的制造方法的流程图。
具体实施方式
本申请实施例提供了一种半导体器件及其制造方法，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
在半导体器件中，衬底的散热性能是影响器件性能的重要因素，在一些场景下由于基底散热的限制，半导体器件的高功率性能并不能有效发挥出来。
举例来说，氮化镓作为第三代宽禁带半导体材料，具有较高的二维电子气浓度和击穿电压，同时还具有较高的电子饱和速度等优点，这些优点为氮化物器件结构作为大功率器件提供了有利的条件。但是由于基底散热的限制，半导体器件的高功率性能并不能有效发挥出来。这是因为目前基底多使用硅基和蓝宝石等材料，这些材料的导热性能较差，半导体器件作为大功率器件输出时会产生大量的热，低热导率的基底材料不能及时将大量的热散发出去，限制了半导体功能器件的性能。通常，蓝宝石材料的热导率为30-40W/mk，硅衬底材料的热导率在130-150W/mk，单晶的结构类型为4H的碳化硅(silicon carbide，SiC)衬底(记为4H-SiC衬底)的热导率范围可以在280-370W/mk，碳化硅的导热是传统的硅或者蓝宝石衬底的好几倍，即使这样也不能满足氮化镓大功率电子器件的散热，因此在一 定程度上限制了氮化镓大功率器件的高功率性能。
随着高频、高功率的发展趋势，基于氮化镓的HEMT在5G领域的PA芯片上得到越来越多的应用，下面对PA的应用场景进行介绍。参考图1所示，为本申请实施例提供的一种基站的示意图，其中，基站的有源天线单元(active antenna unit，AAU)可以包括数模转换器(digital to analog converter，DAC)、射频单元(radio frequency，RF)、功率放大器(PA)和天线等部件，AAU中的主要数字信息经过数模转换器转为模拟信号，通过射频单元调制成高频信号，最后通过功率放大器放大至足够功率后，由天线单元发射出去。在基站的整体功耗中，PA作为其中一个较主要的功耗单元，且对于5G基站，AAU中PA的功耗中有很高的能量以热的方式消耗，所以需要PA有更好的散热，以保障射频PA芯片的安全，如果很高的热量不能及时传导出器件，会对PA有致命的影响，PA可靠性会降低，甚至可能失效。举例来说，天线射频输出功率为100W，如果PA的功耗效率为50％，则PA的功耗需要200W，有100W的能量需要以热的方式消耗，如果PA的功耗效率为30％，则PA的功耗需要333W，有233W的能量需要以热的方式消耗，这对器件的散热提出了非常高的要求。
解决大功率器件散热问题的途径是寻找一种热导率良好的材料作为其基底，使外延层材料直接生长在该材料上，或者将二者有效键合，达到良好散热的目的。研究发现，金刚石具有良好的热导率(500～2000W/mk)，采用金刚石作为半导体大功率器件的基底能有效解决其散热问题。举例来说，采用金刚石作为HEMT器件衬底，目前已经实现了器件在10GHz下输出功率达10W/mm以上的良好性能。
然而，将金刚石作为器件衬底还存在一系列的挑战，例如，若将外延层材料直接生长在金刚石衬底上，存在外延生长难度大的问题，影响外延层材料的成膜，导致器件的电学性能差，且金刚石衬底一般较小，很难实现大尺寸工业化批量量产。若在半导体器件背面键合金刚石衬底，需要进入低热导率的界面键合材料，降低了器件整体的散热性能，从而导致器件的性能优势无法充分发挥。
基于以上技术问题，本申请实施例提供了一种半导体器件及其制造方法，半导体器件可以包括衬底，以及位于衬底上的外延层和电极，其中衬底中具有纵向贯穿衬底的金刚石结构，金刚石结构包括第一金刚石部分和第一金刚石部分下方的第二金刚石部分，第一金刚石部分和第二金刚石部分的横向尺寸不同，由于金刚石结构的导热性能好，贯穿衬底的金刚石结构可以构成纵向的导热通道，从而可以将器件工作过程中产生的热量高效地传导至器件外围，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。此外，第一金刚石部分和第二金刚石部分的横向尺寸不同，则可以通过两次刻蚀工艺实现，降低刻蚀的深宽比，利于控制第一金刚石部分和第二金刚石部分的结构，同时可以兼顾散热性能和外延层之间的晶格匹配，利于得到更高质量的外延层，利于得到高性能的半导体器件。同时，半导体器件的制造工艺简单，难度小，衬底易于规模化生产。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
参考图2A、图2B和图3所示，为本申请实施例提供的半导体器件的结构示意图，半导体器件由下至上可以包括衬底100、外延层200、电极401/402/403。
本申请实施例中，衬底100是为器件提供支撑的部件，且具有一定的导热性能，能够将器件工作时产生的热量扩散到器件之外。衬底100可以为半绝缘半导体材料，具体的，衬底100的材料可以为硅、碳化硅、氮化铝、蓝宝石中的一种或多种，以下将以衬底100的材料为碳化硅为例进行说明，具体可以为单晶的4H-SiC，单晶的4H-SiC衬底材料的热导率一般在280-370W/mk，这种热导率限制了半导体器件的高功率性能。
本申请实施例中，衬底100中可以具有纵向贯穿衬底的金刚石结构110，金刚石结构110为单晶金刚石或多晶金刚石。由于金刚石具有良好的热导率(500～2000W/mk)，纵向贯穿衬底100的金刚石结构110可以形成纵向的散热通道，因此能够大大提升器件的散热效率。
金刚石结构110可以在纵向上分为第一金刚石部分112和第二金刚石部分113，其中第二金刚石部分113位于第一金刚石部分112的下方，第一金刚石部分112和第二金刚石部分113的横向尺寸不同，例如第一金刚石部分112的横向尺寸大于第二金刚石部分113的横向尺寸，或者第一金刚石部分112的横向尺寸小于第二金刚石部分113的横向尺寸，或者第一金刚石部分112和第二金刚石部分113具有不同的结构从而具有不同的尺寸特性。其中，横向指的是沿着衬底表面的方向，纵向指的是垂直衬底表面的方向，也是衬底100和外延层200堆叠的方向，在图2A、图2B和图3中，横向可以是图中的水平方向以及垂直纸面方向，纵向可以是图中的竖直方向。第一金刚石部分112在不同高度处可以具有相同的横向尺寸，也可以具有不同的横向尺寸，第二金刚石部分113在不同高度处可以具有相同的横向尺寸，也可以具有不同的横向尺寸。第一金刚石部分112和第二金刚石部分113在纵向上连接，接触的位置可以具有相同的横向尺寸，也可以具有不同的横向尺寸。
本申请实施例中，第一金刚石部分112和第二金刚石部分113的横向尺寸不同可以具体为完全不同或不完全相同，具体的，可以分为多种情况：第一、第一金刚石部分112在不同高度处具有相同的横向尺寸，第二金刚石部分113在不同高度处具有相同的横向尺寸，且第一金刚石部分112和第二金刚石部分113的横向尺寸不同，则二者完全不同；第二、第一金刚石部分112和第二金刚石部分113中的一个在不同高度处具有相同的横向尺寸，另一个在不同高度处具有不同的横向尺寸，则第一金刚石部分112和第二金刚石部分113的横向尺寸完全不同，或不完全相同；第三、第一金刚石部分112在不同高度处具有不同的横向尺寸，第二金刚石部分113在不同高度处具有不同的横向尺寸，第一金刚石部分112和第二金刚石部分113的横向尺寸完全不同或不完全相同，例如二者具有可以不同的形状使二者的横向尺寸不完全相同或完全不同，也可以具有相同的形状而使二者的横向尺寸不完全相同或完全不同。
由于金刚石结构110纵向贯穿衬底100，则第一金刚石部分112和第二金刚石部分113的纵向尺寸之和与衬底100的厚度相同，本申请实施例中，衬底100的厚度范围可以为50-100um，第一金刚石部分112和第二金刚石部分113的纵向尺寸可以根据第一金刚石部分112和第二金刚石部分113的形状确定。
具体的，第一金刚石部分112和第二金刚石部分113可以为多个，且多个第一金刚石部分112和多个第二金刚石部分113一一对应，也就是说，一个第一金刚石部分112可以和一个第二金刚石部分113连接，构成贯穿衬底100的金刚石结构110。其中，第一金刚石部分112和第二金刚石部分113的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种，即第一金刚石部分112和第二金刚石部分113的形状可以相同，也可以不同，在第一金刚石部分112为圆台结构、棱台结构或碗形结构时，第一金刚石部分112不同高度处可以具有不同的横向尺寸，通常横向尺寸较大的一端位于衬底10表面方向，在第二金刚石部分113为圆台结构、棱台结构或碗形结构时，第二金刚石部分113不同高度处可以具有不同的横向尺寸，通常横向尺寸较大的一端位于衬底10的表面方向。在第一金刚石部分112为圆台结构、棱台结构或碗形结构时，第一金刚石部分112的侧壁与衬底表面之间的夹角为10-80°，具体的，可以为30-60°，碗形结构的侧壁与衬底100表面之间的夹角可以定义为碗形结构的底部中心点与上边缘之间的连线与衬底表面之间的夹角，第二金刚石部分113具有类似的特性。
参考图2A所示，第一金刚石部分112可以为圆台结构，第二金刚石部分113可以为圆柱结构，当然，第一金刚石部分112和第二金刚石部分113可以为直径不同的圆柱结构(参考图2B所示，第一金刚石部分112的尺径可以大于第二金刚石部分113的直径)或其他结构。第一金刚石部分112的纵向尺寸可以为1-10um，第一金刚石部分112的横向尺寸范围为1-10um，第一金刚石部分112之间的间距范围为1-10um，第二金刚石部分113的横向尺寸范围为5-20um，在第一金刚石部分112不同高度处具有不同的横向尺寸时，以上尺寸表示第一金刚石部分112在衬底表面处的尺寸，在第二金刚石部分113不同高度处具有不同的横向尺寸时，以上尺寸表示第二金刚石部分113在衬底表面处的尺寸。其中，第一金刚石部分112在衬底表面处呈现为圆形时，第一金刚石部分112的尺寸为其直径，第一金刚石部分112在衬底表面处呈现为多边形时，第一金刚石部分112的尺寸为其边长，第二金刚石部分113具有类似的特性。
具体的，第一金刚石部分112和第二金刚石部分113也可以不一一对应，其中第二金刚石部分113的数量可以少于第一金刚石部分112的数量，这样存在多个第一金刚石部分112与同一个第二金刚石部分113连接的情况，第一金刚石部分112的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种，各个第一金刚石部分112的形状可以一致，也可以不一致。参考图3所示，第二金刚石部分113可以为一个整体结构，该第二金刚石部分113可以与各个第一金刚石部分112均纵向连接，或者仅与其中一部分的第一金刚石部分112纵向连接，或者，第二金刚石部分113可以为多个，且第二金刚石部分113在平行衬底表面的预设方向上延伸，至少存在一个第二金刚石部分113与多个第一金刚石部分112纵向连接，从而构成由下至上的贯穿结构。
在衬底100上，可以形成有外延层200，在基于GaN的HEMT器件中，外延层200可以包括缓冲层和势垒层，缓冲层和势垒层可以形成异质结构，从而产生二维电子气，形成的半导体器件可以利用该异质结构产生的二维电子气工作，当然，本申请实施例中的半导体器件也可以为其他能源器件或激光器，则该外延层为其他器件中的外延层，在此不进行 一一举例。缓冲层可以为氮化镓层，势垒层的材料可以为AlGaN、InAlN、AlN和ScAlN的至少一种，缓冲层的厚度范围可以为0.1-2um，势垒层的厚度范围可以为5-20nm。由于衬底100为碳化硅衬底，且衬底表面暴露出部分金刚石结构，氮化镓层和衬底100之间的晶格匹配度较高，因此氮化镓层具有较好的外延质量，利于形成高性能的器件。氮化镓层可以包括低温氮化镓层和高温氮化镓层，其中低温氮化镓层作为高温氮化镓层和衬底之间的缓冲层，提高高温氮化镓层的外延质量。
在外延层200上可以形成有电极401/402/403，电极可以包括源极401、漏极403和栅极402，栅极402可以位于源极401和漏极403之间，电极401/402/403的材料可以为金属材料，例如可以为Au、Ti、Al、Ni、Ta中的至少一种，作为一种可能的实现方式，电极的材料可以为Au、Ti/Al/Ni/Au叠层或Ta/Al/Ta叠层。
本申请实施例提供了一种半导体器件，半导体器件可以包括衬底，以及位于衬底上的外延层和电极，其中衬底中具有纵向贯穿衬底的金刚石结构，金刚石结构包括第一金刚石部分和第一金刚石部分下方的第二金刚石部分，第一金刚石部分和第二金刚石部分的横向尺寸不同，由于金刚石结构的导热性能好，贯穿衬底的金刚石结构可以构成纵向的导热通道，从而可以将器件工作过程中产生的热量高效地传导至器件外围，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。此外，第一金刚石部分和第二金刚石部分的横向尺寸不同，则可以通过两次刻蚀工艺实现，降低刻蚀的深宽比，利于控制第一金刚石部分和第二金刚石部分的结构，同时可以兼顾散热性能和外延层之间的晶格匹配，利于得到更高质量的外延层，利于得到高性能的半导体器件。同时，半导体器件的制造工艺简单，难度小，衬底易于规模化生产。
基于以上实施例提供的一种半导体器件，本申请实施例还提供了一种半导体器件的制造方法，参考图4所示，为本申请实施例提供衬底100的一种半导体器件的制造方法的流程图，图5-图12为在器件制造过程中器件的结构示意图，该方法中，可以先在衬底100中形成金刚石结构中的第一金刚石部分112，而后形成其上的器件结构，再在衬底100中形成金刚石结构中的第二金刚石部分113，具体的，该方法可以包括：
S101，提供衬底100，参考图5所示。
本申请实施例中，衬底100是为器件提供支撑的部件，且具有一定的导热性能，能够将器件工作时产生的热量扩散到器件之外。衬底100可以为半绝缘半导体材料，具体的，衬底100的材料可以为硅、碳化硅、氮化铝、蓝宝石中的一种或多种，以下将以衬底100的材料为碳化硅为例进行说明，具体可以为单晶的4H-SiC，单晶的4H-SiC衬底材料的热导率一般在280-370W/mk，这种热导率限制了半导体器件的高功率性能。
S102，对衬底100的第一表面进行刻蚀得到第一沟槽101，并在第一沟槽101中填充金刚石材料，参考图6-图8所示。
本申请实施例中，可以对衬底100的第一表面进行刻蚀得到第一沟槽101，参考图6所示，并在第一沟槽101中填充金刚石材料，第一沟槽101中填充的金刚石材料可以作为前述实施例中的第一金刚石部分112，参考图8所示。对衬底100的刻蚀可以采用干法各向 异性刻蚀，例如等离子体刻蚀。刻蚀得到的第一沟槽101的横向尺寸为1-10um，刻蚀深度为1-10um，不同第一沟槽101之间的间距范围为1-10um，第一沟槽101可以形成周期性的阵列排布。
通过控制对衬底100的刻蚀参数可以控制第一沟槽101的形状，第一沟槽101的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种，其中圆台结构、棱台结构和碗形结构的尺寸较大的一端朝向衬底表面，在刻蚀过程中，可以通过减缓刻蚀速率来减少刻蚀气体对第一沟槽101侧壁的损伤，从而形成第一沟槽101的上大下小的结构。
在刻蚀形成第一沟槽101后，可以在第一沟槽101中填充金刚石材料，金刚石材料为单晶金刚石或多晶金刚石。具体的，可以在形成有第一沟槽101的衬底100上生长金刚石材料，经过一段时间的生长，在衬底上可以生成一层高品质的多晶金刚石层111，厚度为1-50um，参考图7所示。而后通过研磨和抛光去除部分金刚石层111，露出衬底100表面，这样金刚石材料仅形成于第一沟槽101中，且金刚石材料的尺寸与第一沟槽101的尺寸一致或近似，参考图8所示。生长金刚石材料的方式可以是微波等离子化学气相沉积(microwave plasma chemical vapor eeposition，MPCVD)，材料生长的温度范围可以为800-1200℃，压力范围可以是1-15KPa。MPCVD方法具有等离子体放电稳定和受到污染小等优点，可以生长得到高品质金刚石材料。
S103，在衬底100的第一表面上依次形成外延层200和电极401/402/403，参考图9-图10。
在衬底100的第一表面上可以形成外延层200，参考图9所示，在半导体器件为基于GaN的HEMT器件时，外延层200可以包括缓冲层和势垒层，缓冲层和势垒层可以形成异质结构，从而产生二维电子气，形成的半导体器件可以利用该异质结构产生的二维电子气工作。缓冲层可以为氮化镓层，势垒层的材料可以为AlGaN、InAlN、AlN和ScAlN的至少一种，缓冲层的厚度范围可以为0.1-2um，势垒层的厚度范围可以为5-20nm。
具体的，可以在衬底100的第一表面上形成缓冲层，而后在缓冲层上形成势垒层。氮化镓层的形成方式可以为有机金属化学气相沉积(Metal organic chemical vapor deposition，MOCVD)，由于金刚石材料和氮化镓的晶格失配严重，因此氮化镓在碳化硅上生长较快，在金刚石上生长较慢甚至无法生长，从而使得碳化硅上的氮化镓横向生长加强，位错合并，从而得到质量较高的氮化镓层。其中，在第一沟槽中形成的金刚石材料为圆台结构、棱台结构或碗形结构时，更加利于衬底上的氮化镓的生长，得到更高质量的氮化镓层。氮化镓层可以包括低温氮化镓层和高温氮化镓层，其中低温氮化镓层作为高温氮化镓层和衬底之间的缓冲层，提高高温氮化镓层的外延质量。势垒层的形成方式也可以为MOCVD的方式。
在外延层200上可以形成电极401/402/403，电极401/402/403可以包括源极401、漏极403和栅极402，栅极402可以位于源极401和漏极403之间，参考图10所示，电极401/402/403的材料可以为金属材料，例如可以为Au、Ti、Al、Ni、Ta中的至少一种，作为一种可能的实现方式，电极401/402/403的材料可以为Au、Ti/Al/Ni/Au叠层或Ta/Al/Ta叠层。
S104，对衬底100的第二表面进行刻蚀得到第二沟槽102，第二沟槽102和第一沟槽101连通且横向尺寸不同，在第二沟槽102中填充金刚石材料，参考图11、图12、图2A、图2B和图3。
在形成电极401/402/403后，还可以形成介质层覆盖电极401/402/403以构成对电极的保护(图未示出)。而后可以对衬底100的第二表面进行刻蚀得到第二沟槽102，第一表面和第二表面为两个相对的表面，参考图11和图12所示，并在第二沟槽102中填充金刚石材料，第二沟槽102中的金刚石材料可以作为前述实施例中的第二金刚石部分113，第一沟槽101和第二沟槽102连通，则第一沟槽101中的金刚石材料和第二沟槽中102的金刚石材料接触构成贯穿衬底的金刚石结构110，参考图2A、图2B和图3所示。由于第一沟槽101和第二沟槽102的横向尺寸不同，则形成的金刚石结构的第一金刚石部分112和第二金刚石部分113的横向尺寸不同。由于金刚石具有良好的热导率，纵向贯穿衬底的金刚石结构可以形成纵向的散热通道，能够大大提升器件的散热效率。在对衬底100进行第二表面的刻蚀之前，还可以从衬底100的第二表面对衬底100进行减薄，从而使衬底100的厚度范围为50-100um，第一金刚石部分112和第二金刚石部分113的纵向尺寸之和与衬底100的厚度相同。
实际操作中，在形成器件后，可以进行芯片的键合，此时会翻转芯片使其衬底朝上实现键合，则以上的对衬底的第二表面的刻蚀与实际操作的步骤兼容，可以在不增加过多的步骤的情况下得到更高性能的器件。
具体的，第一沟槽101和第二沟槽102可以均为多个，第一沟槽101和第二沟槽102可以一一对应，一个第一沟槽101可以和一个第二沟槽102连通，构成贯穿衬底的通孔，参考图11所示。其中，第一沟槽101和第二沟槽102的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种，第一沟槽101和第二沟槽102的形状可以相同，也可以不同。在第一金刚石部分112为圆台结构、棱台结构或碗形结构时，通常横向尺寸较大的一端位于衬底表面方向，在第二金刚石部分113为圆台结构、棱台结构或碗形结构时，通常横向尺寸较大的一端位于衬底的表面方向。在第一沟槽101为圆台结构、棱台结构或碗形结构时，第一沟槽101的侧壁与衬底表面之间的夹角为10-80°，具体的，可以为30-60°，碗形结构的侧壁与衬底表面之间的夹角可以定义为碗形结构的底部中心点与上边缘之间的连线与衬底表面之间的夹角，第二金刚石部分113具有类似的特性。
第二沟槽102的横向尺寸范围为5-20um，纵向尺寸可以为40-99um，在第一沟槽101不同高度处具有不同的横向尺寸时，以上尺寸表示第一沟槽101在衬底表面处开口的尺寸，在第二沟槽102不同高度处具有不同的横向尺寸时，以上尺寸表示第二沟槽102在衬底表面处开口的尺寸。其中，第一沟槽101在衬底表面处呈现为圆形时，第一沟槽101的尺寸为其直径，第一沟槽101在衬底表面处呈现为多边形时，第一沟槽101的尺寸为其边长，第二沟槽102具有类似的特性。
具体的，第一沟槽101和第二沟槽102也可以不一一对应，其中第二沟槽102的数量可以少于第一沟槽101的数量，这样存在多个第一沟槽101与同一个第二沟槽102连接的情况，第一沟槽101的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构 中的至少一种，参考图12所示。参考图12所示，第二沟槽102可以为一个整体结构，该第二沟槽102可以与各个第一沟槽101均纵向连接，或者仅与其中一部分的第一金刚石部分112纵向连接，即第二沟槽102底部可以暴露全部或部分第一沟槽101中的金刚石材料。第二沟槽102也可以为多个，且第二沟槽102在平行衬底表面的预设方向上延伸，至少存在一个第二沟槽102与多个第一沟槽101纵向连接，从而构成由下至上的贯穿结构，即至少存在一个第二沟槽102底部暴露多个第一沟槽101中的金刚石材料。
该场景下，可以对衬底的第二表面进行大面积的刻蚀，去除衬底的第二表面的大部分的材料得到空腔结构作为第二沟槽102，该空腔结构暴露第一沟槽101中的金刚石材料，这样在第二沟槽102中填充金刚石材料后，第一沟槽101中金刚石材料和第二沟槽102中金刚石材料接触，构成贯穿衬底的金刚石结构，形成纵向的导热路径，金刚石结构的第一金刚石部分112与衬底上的外延层接触，金刚石结构的第二金刚石部分113暴露在衬底之外，可以将器件内部产生的热量传导至器件之外。衬底下方还可以设置热沉，则金刚石结构的第二金刚石部分113可以和热沉接触，将热量快速传导至热沉，实现器件的快速散热。在第二沟槽102为大面积的空腔结构时，金刚石结构暴露在衬底外的面积较大，与热沉的接触面积也较大，进一步提升散热效率。
需要说明的是，衬底100中可以存在不与第二沟槽102连通的第一沟槽101，可以作为第三沟槽，也可以存在不与第一沟槽101连通的第二沟槽102，可以作为第四沟槽，第三沟槽和第四沟槽并未贯穿衬底100，其中的金刚石材料仅形成于衬底100中的部分深度内，此时并未形成上下贯穿的散热通道，但是第三沟槽和第四沟槽中的金刚石材料依然可以向外散热，例如通过横向导热使热量传导至其他金刚石材料中，或者向下散热使热量直接扩散至器件之外，或者通过衬底100扩散至器件之外，或通过衬底100和其他金刚石材料扩散至器件之外。
本申请实施例提供的一种半导体器件的制造方法，在衬底的第一表面可以进行刻蚀得到第一沟槽，并在第一沟槽中填充金刚石材料，在衬底的第一表面可以依次形成外延层和电极，而后可以对衬底的第二表面进行刻蚀得到第二沟槽，第二沟槽和第一沟槽连通，且二者横向尺寸不同，在第二沟槽中填充金刚石材料，这样第一沟槽中的金刚石材料和第二沟槽中的金刚石材料接触，构成贯穿衬底的金刚石结构，由于金刚石结构的导热性能好，贯穿衬底的金刚石结构可以构成纵向的导热通道，从而可以将器件工作过程中产生的热量高效地传导至器件外围，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。此外，第一金刚石部分和第二金刚石部分的横向尺寸不同，则可以通过两次刻蚀工艺实现，降低刻蚀的深宽比，利于控制第一金刚石部分和第二金刚石部分的结构，从而兼顾散热性能和外延层之间的晶格匹配，利于得到更高质量的外延层，利于得到高性能的半导体器件。同时，半导体器件的制造工艺简单，难度小，衬底易于规模化生产。
基于以上实施例提供的一种半导体器件，本申请实施例还提供了一种半导体器件的制造方法，参考图13所示，为本申请实施例提供的另一种半导体器件的制造方法的流程图，该方法中，可以先在衬底100中形成金刚石结构中的第一金刚石部分112和第二金刚石部 分113，而后形成其上的器件结构，具体的，该方法可以包括：
S201，提供衬底100。
本申请实施例中，衬底100是为器件提供支撑的部件，且具有一定的导热性能，能够将器件工作时产生的热量扩散到器件之外。衬底100可以为半绝缘半导体材料，具体的，衬底100的材料可以为硅、碳化硅、氮化铝、蓝宝石中的一种或多种，以下将以衬底100的材料为碳化硅为例进行说明，具体可以为单晶的4H-SiC，单晶的4H-SiC衬底材料的热导率一般在280-370W/mk，这种热导率限制了半导体器件的高功率性能。
S202，对衬底100的第一表面进行刻蚀得到第一沟槽101，并在第一沟槽101中填充金刚石材料；以及对衬底100的第二表面进行刻蚀得到第二沟槽102，第二沟槽102和第一沟槽101连通且横向尺寸不同，在第二沟槽102中填充金刚石材料。
本申请实施例中，可以对衬底100的第一表面进行刻蚀得到第一沟槽101，并在第一沟槽101中填充金刚石材料，第一沟槽101中填充的金刚石材料可以作为前述实施例中的第一金刚石部分112。对衬底100的刻蚀可以采用干法各向异性刻蚀，例如等离子体刻蚀。刻蚀得到的第一沟槽101的横向尺寸为1-10um，刻蚀深度为1-10um，不同第一沟槽101之间的间距范围为1-10um，第一沟槽101可以形成周期性的阵列排布。
通过控制对衬底100的刻蚀参数可以控制第一沟槽101的形状，第一沟槽101的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种，其中圆台结构、棱台结构和碗形结构的尺寸较大的一端朝向衬底表面，在刻蚀过程中，可以通过减缓刻蚀速率来减少刻蚀气体对第一沟槽101侧壁的损伤，从而形成第一沟槽101的上大下小的结构。
在刻蚀形成第一沟槽101后，可以在第一沟槽101中填充金刚石材料，金刚石材料为单晶金刚石或多晶金刚石。具体的，可以在形成有第一沟槽101的衬底100上生长金刚石材料，经过一段时间的生长，在衬底100上可以生成一层高品质的多晶金刚石层111，厚度为1-50um。而后通过研磨和抛光去除部分金刚石层111，露出衬底100表面，这样金刚石材料仅形成于第一沟槽101中，且金刚石材料的尺寸与第一沟槽101的尺寸一致或近似。生长金刚石材料的方式可以是MPCVD，材料生长的温度范围可以为800-1200℃，压力范围可以是1-15KPa。MPCVD方法具有等离子体放电稳定和受到污染小等优点，可以生长得到高品质金刚石材料。
本申请实施例中，还可以对衬底100的第二表面进行刻蚀得到第二沟槽102，并在第二沟槽102中填充金刚石材料，第一表面和第二表面为两个相对的表面，第二沟槽102中的金刚石材料可以作为前述实施例中的第二金刚石部分113，第一沟槽101和第二沟槽102连通，则第一沟槽101中的金刚石材料和第二沟槽102中的金刚石材料接触构成贯穿衬底100的金刚石结构。由于第一沟槽101和第二沟槽102的横向尺寸不同，则形成的金刚石结构的第一金刚石部分112和第二金刚石部分113的横向尺寸不同。由于金刚石具有良好的热导率，纵向贯穿衬底100的金刚石结构可以形成纵向的散热通道，能够大大提升器件的散热效率。在对衬底100进行第二表面的刻蚀之前，还可以从衬底100的第二表面对衬底100进行减薄，从而使衬底100的厚度范围为50-100um，第一金刚石部分112和第二金 刚石部分113的纵向尺寸之和与衬底100的厚度相同。
需要说明的是，第一沟槽101和第二沟槽102的刻蚀顺序可以是任意的，若第一沟槽101在第二沟槽102之前刻蚀，则在第二沟槽102刻蚀之前需要在第一沟槽101中填充金刚石材料，第二沟槽102底部暴露第一沟槽101中的金刚石材料，若第二沟槽102在第一沟槽101之前刻蚀，则在第一沟槽101刻蚀之前需要在第二沟槽102中填充金刚石材料，第一沟槽101底部暴露第二沟槽102中的金刚石材料。
具体的，第一沟槽101和第二沟槽102可以一一对应，一个第一沟槽101可以和一个第二沟槽102连通，构成贯穿衬底100的通孔。其中，第一沟槽101和第二沟槽102的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种，第一沟槽101和第二沟槽102的形状可以相同，也可以不同。在第一金刚石部分112为圆台结构、棱台结构或碗形结构时，通常横向尺寸较大的一端位于衬底100表面方向，在第二金刚石部分113为圆台结构、棱台结构或碗形结构时，通常横向尺寸较大的一端位于衬底100的表面方向。在第一沟槽101为圆台结构、棱台结构或碗形结构时，第一沟槽101的侧壁与衬底表面之间的夹角为10-80°，具体的，可以为30-60°，碗形结构的侧壁与衬底表面之间的夹角可以定义为碗形结构的底部中心点与上边缘之间的连线与衬底表面之间的夹角，第二金刚石部分113具有类似的特性。
第二沟槽102的横向尺寸范围为5-20um，纵向尺寸可以为40-99um，在第一沟槽101不同高度处具有不同的横向尺寸时，以上尺寸表示第一沟槽101在衬底表面处开口的尺寸，在第二沟槽102不同高度处具有不同的横向尺寸时，以上尺寸表示第二沟槽102在衬底表面处开口的尺寸。其中，第一沟槽101在衬底表面处呈现为圆形时，第一沟槽101的尺寸为其直径，第一沟槽101在衬底表面处呈现为多边形时，第一沟槽101的尺寸为其边长，第二沟槽102具有类似的特性。
具体的，第一沟槽101和第二沟槽102也可以不一一对应，其中第二沟槽102的数量可以少于第一沟槽101的数量，这样存在多个第一沟槽101与同一个第二沟槽102连接的情况，第一沟槽101的形状可以为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
第二沟槽102可以为一个整体结构，该第二沟槽102可以与各个第一沟槽101均纵向连接，或者仅与其中一部分的第一沟槽101纵向连接。具体的，若第二沟槽102在第一沟槽101之后形成，则第二沟槽102底部可以暴露全部或部分的第一沟槽101中的金刚石材料，若第二沟槽102在第一沟槽101之前形成，则多个第一沟槽101的底部均暴露第二沟槽102中的金刚石材料。
第二沟槽102也可以为多个，且第二沟槽102在平行衬底表面的预设方向上延伸，至少存在一个第二沟槽102与多个第一沟槽101纵向连接，从而构成由下至上的贯穿结构。具体的，若第二沟槽102在第一沟槽101之前形成，则至少存在一个第二沟槽102底部暴露多个第一沟槽101中的金刚石材料，若第二沟槽102在第一沟槽101之后形成，存在多个第一沟槽101底部均暴露同一第二沟槽102中的金刚石材料。
该场景下，可以对衬底100的第二表面进行大面积的刻蚀，去除衬底100的第二表面 的大部分的材料得到空腔结构作为第二沟槽102，第一沟槽101和第二沟槽102连通，这样在第一沟槽101和第二沟槽102中填充金刚石材料后，第一沟槽101中金刚石材料和第二沟槽102中金刚石材料接触，构成贯穿衬底100的金刚石结构，形成纵向的导热路径，金刚石结构的第一金刚石部分112与衬底100上的外延层接触，金刚石结构的第二金刚石部分113暴露在衬底100之外，可以将器件内部产生的热量传导至器件之外。衬底100下方还可以设置热沉，则金刚石结构的第二金刚石部分113可以和热沉接触，将热量快速传导至热沉，实现器件的快速散热。在第二沟槽102为大面积的空腔结构时，金刚石结构暴露在衬底100外的面积较大，与热沉的接触面积也较大，进一步提升散热效率。
需要说明的是，衬底100中可以存在不与第二沟槽102连通的第一沟槽101，可以作为第三沟槽，也可以存在不与第一沟槽101连通的第二沟槽102，可以作为第四沟槽，第三沟槽和第四沟槽并未贯穿衬底100，其中的金刚石材料仅形成于衬底100中的部分深度内，此时并未形成上下贯穿的散热通道，但是第三沟槽和第四沟槽中的金刚石材料依然可以向外散热，例如通过横向导热使热量传导至其他金刚石材料中，或者向下散热使热量直接扩散至器件之外，或者通过衬底100扩散至器件之外，或通过衬底100和其他金刚石材料扩散至器件之外。
S203，在衬底100上依次形成外延层200和电极401/402/403。
在衬底100上可以形成外延层200，在半导体器件为基于GaN的HEMT器件时，外延层200可以包括缓冲层和势垒层，缓冲层和势垒层可以形成异质结构，从而产生二维电子气，形成的半导体器件可以利用该异质结构产生的二维电子气工作。缓冲层可以为氮化镓层，势垒层的材料可以为AlGaN、InAlN、AlN和ScAlN的至少一种，缓冲层的厚度范围可以为0.1-2um，势垒层的厚度范围可以为5-20nm。
具体的，可以在衬底100的第一表面上形成缓冲层，而后在缓冲层上形成势垒层。氮化镓层的形成方式可以为MOCVD，由于金刚石材料和氮化镓的晶格失配严重，因此氮化镓在碳化硅上生长较快，在金刚石上生长较慢甚至无法生长，从而使得碳化硅上的氮化镓横向生长加强，位错合并，从而得到质量较高的氮化镓层。其中，在第一沟槽101中形成的金刚石材料为圆台结构、棱台结构或碗形结构时，更加利于衬底100上的氮化镓的生长，得到更高质量的氮化镓层。氮化镓层可以包括低温氮化镓层和高温氮化镓层，其中低温氮化镓层作为高温氮化镓层和衬底100之间的缓冲层，提高高温氮化镓层的外延质量。势垒层的形成方式也可以为MOCVD的方式。
在外延层200上可以形成电极401/402/403，电极401/402/403可以包括源极401、漏极403和栅极402，栅极402可以位于源极401和漏极403之间，电极401/402/403的材料可以为金属材料，例如可以为Au、Ti、Al、Ni、Ta中的至少一种，作为一种可能的实现方式，电极401/402/403的材料可以为Au、Ti/Al/Ni/Au叠层或Ta/Al/Ta叠层。在形成电极401/402/403后，还可以形成介质层覆盖电极以构成对电极401/402/403的保护。
本申请实施例提供的一种半导体器件的制造方法，在衬底的第一表面可以进行刻蚀得到第一沟槽，并在第一沟槽中填充金刚石材料，对衬底的第二表面进行刻蚀得到第二沟槽，第二沟槽和第一沟槽连通，且二者横向尺寸不同，在第二沟槽中填充金刚石材料，而后可 以在衬底的第一表面可以依次形成外延层和电极，这样第一沟槽中的金刚石材料和第二沟槽中的金刚石材料接触，构成贯穿衬底的金刚石结构，由于金刚石结构的导热性能好，贯穿衬底的金刚石结构可以构成纵向的导热通道，从而可以将器件工作过程中产生的热量高效地传导至器件外围，提高半导体器件的散热性能，利于半导体器件的高功率性能的有效发挥。此外，第一金刚石部分和第二金刚石部分的横向尺寸不同，则可以通过两次刻蚀工艺实现，降低刻蚀的深宽比，利于控制第一金刚石部分和第二金刚石部分的结构，从而兼顾散热性能和外延层之间的晶格匹配，利于得到更高质量的外延层，利于得到高性能的半导体器件。同时，半导体器件的制造工艺简单，难度小，衬底易于规模化生产。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于结构实施例，所以描述得比较简单，相关之处参见结构实施例的部分说明即可。
以上为本申请的具体实现方式。应当理解，以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (24)

  1. 一种半导体器件，其特征在于，包括：
    衬底，所述衬底中具有纵向贯穿所述衬底的金刚石结构，所述金刚石结构在纵向上分为第一金刚石部分和所述第一金刚石部分下方的第二金刚石部分，所述第一金刚石部分和所述第二金刚石部分的横向尺寸不同；
    依次位于所述衬底上的外延层以及电极。
  2. 根据权利要求1所述的器件，其特征在于，所述第一金刚石结构和所述第二金刚石结构均为多个，多个所述第一金刚石部分和多个所述第二金刚石部分一一对应，且为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
  3. 根据权利要求1所述的器件，其特征在于，所述第二金刚石部分的数量少于所述第一金刚石部分的数量，存在多个所述第一金刚石部分与同一个第二金刚石部分连接，所述第一金刚石部分为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
  4. 根据权利要求3所述的器件，其特征在于，所述第二金刚石部分为一个，且与全部或部分所述第一金刚石部分纵向连接。
  5. 根据权利要求3所述的器件，其特征在于，所述第二金刚石部分为多个，所述第二金刚石部分在平行于所述衬底表面的预设方向上延伸，且至少存在一个所述第二金刚石部分与多个所述第一金刚石部分纵向连接。
  6. 根据权利要求1-5任意一项所述的器件，其特征在于，所述第一金刚石部分的横向尺寸范围为1-10um，所述第一金刚石部分的纵向尺寸范围为1-10um，不同所述第一金刚石部分之间的间距范围为1-10um，所述衬底的厚度范围为50-100um。
  7. 根据权利要求1-6任意一项所述的器件，其特征在于，所述衬底的材料为硅、碳化硅、氮化铝、蓝宝石中的一种或多种。
  8. 根据权利要求1-7任意一项所述的器件，其特征在于，所述金刚石结构为单晶金刚石或多晶金刚石。
  9. 根据权利要求1-8任意一项所述的器件，其特征在于，所述外延层包括缓冲层和势垒层，所述缓冲层为氮化镓层，所述势垒层的材料为AlGaN、InAlN、AlN和ScAlN中的一种或多种。
  10. 根据权利要求9所述的器件，其特征在于，所述氮化镓层的厚度范围为0.1-2um，所述势垒层的厚度范围为5-20nm。
  11. 根据权利要求1-10任意一项所述的器件，其特征在于，所述电极包括源极、漏极和栅极，所述电极的材料为Au、Ti、Al、Ni、Ta中的至少一种。
  12. 一种半导体器件的形成方法，其特征在于，包括：
    提供衬底；
    对所述衬底的第一表面进行刻蚀得到第一沟槽；
    在所述第一沟槽中填充金刚石材料；
    在所述衬底的第一表面上依次形成外延层和电极；
    对所述衬底的第二表面进行刻蚀得到第二沟槽，所述第二沟槽和所述第一沟槽连通， 且横向尺寸不同；所述第一表面和所述第二表面为两个相对的表面；
    在所述第二沟槽中填充金刚石材料。
  13. 根据权利要求12所述的方法，其特征在于，所述第一沟槽和所述第二沟槽均为多个，多个所述第一沟槽和多个所述第二沟槽一一对应，且所述第一沟槽和所述第二沟槽中的金刚石材料的形状为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
  14. 根据权利要求12所述的方法，其特征在于，所述第二沟槽的数量少于所述第一沟槽的数量，存在多个所述第一沟槽与同一个第二沟槽连接，所述第一沟槽的形状为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的一种。
  15. 根据权利要求14所述的方法，其特征在于，所述第二沟槽为一个，且所述第二沟槽底部暴露全部或部分所述第一沟槽中的金刚石材料。
  16. 根据权利要求14所述的方法，其特征在于，所述第二沟槽为多个在平行于所述衬底表面的预设方向上延伸的沟槽，且至少存在一个所述第二沟槽底部暴露多个所述第一沟槽中的金刚石材料。
  17. 根据权利要求12-16任意一项所述的方法，其特征在于，所述对所述衬底的第二表面进行刻蚀得到第二沟槽之前，还包括：
    从所述衬底的第二表面对所述衬底进行减薄。
  18. 一种半导体器件的形成方法，其特征在于，包括：
    提供衬底；
    从所述衬底的第一表面进行刻蚀得到第一沟槽，在所述第一沟槽中填充金刚石材料；以及从所述衬底的第二表面进行刻蚀得到第二沟槽，在所述第二沟槽中填充金刚石材料；所述第一沟槽和所述第二沟槽连通，且横向尺寸不同；所述第一表面和所述第二表面为两个相对的表面；
    在所述衬底的第一表面依次形成外延层和电极。
  19. 根据权利要求18所述的方法，其特征在于，所述第一沟槽和所述第二沟槽均为多个，多个所述第一沟槽和多个所述第二沟槽一一对应，且所述第一沟槽和所述第二沟槽中的金刚石材料的形状为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
  20. 根据权利要求18的方法，其特征在于，所述第二沟槽的数量少于所述第一沟槽的数量，存在多个所述第一沟槽与同一个第二沟槽连接，所述第一沟槽为圆台结构、棱台结构、碗形结构、圆柱结构和棱柱结构中的至少一种。
  21. 根据权利要求20所述的方法，其特征在于，所述第二沟槽为一个，则若所述第二沟槽在所述第一沟槽之后形成，所述第二沟槽底部暴露全部或部分所述第一沟槽中的金刚石材料，若所述第二沟槽在所述第一沟槽之前形成，多个所述第一沟槽的底部暴露所述第二沟槽中的金刚石材料。
  22. 根据权利要求20所述的方法，其特征在于，所述第二沟槽为多个在平行于所述衬底表面的预设方向上延伸的沟槽，则若所述第二沟槽在所述第一沟槽之后形成，至少存在 一个所述第二沟槽底部暴露多个所述第一沟槽中的金刚石材料，若所述第二沟槽在所述第一沟槽之前形成，存在多个所述第一沟槽底部均暴露同一所述第二沟槽中的金刚石材料。
  23. 根据权利要求18-22任意一项所述的方法，其特征在于，所述对所述衬底的第二表面进行刻蚀得到第二沟槽之前，还包括：
    从所述衬底的第二表面对所述衬底进行减薄。
  24. 一种功率放大器芯片，其特征在于，包括如权利要求1-11任一项所述的半导体器件。
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