WO2022087793A1 - 一种数据读取电路及数据读取电路的控制方法 - Google Patents

一种数据读取电路及数据读取电路的控制方法 Download PDF

Info

Publication number
WO2022087793A1
WO2022087793A1 PCT/CN2020/123767 CN2020123767W WO2022087793A1 WO 2022087793 A1 WO2022087793 A1 WO 2022087793A1 CN 2020123767 W CN2020123767 W CN 2020123767W WO 2022087793 A1 WO2022087793 A1 WO 2022087793A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch
coupled
current
transistor
branch
Prior art date
Application number
PCT/CN2020/123767
Other languages
English (en)
French (fr)
Inventor
张子玥
潘越
布明恩
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20958958.9A priority Critical patent/EP4210061A4/en
Priority to PCT/CN2020/123767 priority patent/WO2022087793A1/zh
Priority to CN202080104836.XA priority patent/CN116324998A/zh
Publication of WO2022087793A1 publication Critical patent/WO2022087793A1/zh
Priority to US18/297,633 priority patent/US20230245700A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/227—Timing of memory operations based on dummy memory elements or replica circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Definitions

  • the embodiments of the present application relate to the technical field of circuits, and in particular, to a data reading circuit and a control method of the data reading circuit.
  • the variable resistance memory is a new type of memory, and the data cell of the new memory is usually composed of a storage medium unit and a transistor (1T1R).
  • the storage medium unit can be a resistor R with variable high and low resistance states, and the different resistance states of the resistor R can represent data “0” and data “1”, and the gate of the transistor is affected by the word line (WL, WL). ) control, responsible for selecting this data unit.
  • the 1T1R structure is connected to a bit line (BL) and a source line (SL).
  • Figure 4 shows a data read circuit including an adjustment circuit (“Logic Process Compatible 40-nm 16-Mb, embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub- ⁇ A Sensing Resolution ”), the trimming circuit can trim the size of I REF .
  • an adjustment circuit (“Logic Process Compatible 40-nm 16-Mb, embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub- ⁇ A Sensing Resolution ”)
  • the trimming circuit can trim the size of I REF .
  • Fig. 4 by disposing symmetrical adjustment circuits on the data branch and reference branch of each S/A, it is possible to turn on different numbers of adjustment circuits according to the actual deviation of I REF in each S/A. branch, change the I REF on the reference branch or the ID on the data branch to varying degrees .
  • the adjustment circuit in Figure 4 occupies a board area. If it is larger, it will cause waste.
  • the adjustment circuit is composed of multiple columns of transistors in parallel, and the multiple columns of transistors are connected in parallel to node C, which will cause the parasitic capacitance of each column of transistors to be directly added to node C, thereby increasing The load of node C is reduced, resulting in slower charging and discharging speed on BL, which affects the reading speed of S/A.
  • Embodiments of the present application provide a data reading circuit and a control method for the data reading circuit, which can reduce the board area of the adjustment circuit and improve the reading speed.
  • a first aspect of the embodiments of the present application provides a data read circuit
  • the data read circuit includes a sense amplifier, a first switch, a second switch, a current adjustment circuit, a data unit and a reference unit; wherein, the first switch of the sense amplifier An input end is coupled and connected to the first end of the first switch and the data unit, the second input end of the sense amplifier is coupled and connected to the first end of the second switch and the reference unit, and the second end of the first switch is coupled to the first end of the first switch through the current adjustment circuit The second end of the second switch is coupled and connected; the current adjustment circuit is used to adjust the current of the first input end of the sense amplifier, or to adjust the current of the second input end of the sense amplifier.
  • the data reading circuit can choose to adjust the current of the data branch or the current of the reference branch through the first switch and the second switch. Therefore, only one current adjustment circuit can be set in the data reading circuit to adjust the data branch.
  • a trimming circuit is respectively set on the data branch and the reference branch, one trimming circuit adjusts the current of the data branch, and one trimming circuit adjusts the current of the reference branch. , reducing the board area of the adjustment circuit.
  • the parasitic capacitance of the multi-column transistors in the current regulation circuit will not be added to the first node C1 (the first input terminal of the sense amplifier and the first terminal of the first switch). and the coupling point of the data unit) and the second node C2 (the coupling point of the second input terminal of the sense amplifier and the first terminal of the second switch and the reference unit), reducing the parasitics at the first node C1 and the second node C2 Capacitance, thereby improving the reading speed of S/A.
  • the above-mentioned current adjustment circuit includes M first adjustment branches, where M is an integer greater than or equal to 1, each first adjustment branch includes a third switch, and The third switch is a first transistor connected in series, wherein the first end of the first transistor is coupled to the second end of the first switch and the second end of the second switch, and the second end of the first transistor is connected It is coupled and connected to the first end of the third switch, the second end of the third switch is coupled to the power supply, and the third ends of the first transistors in the M first regulating branches are coupled and connected.
  • the first regulating branch is turned on, so that the current of the regulating branch can be reduced.
  • the adjusted branch is the data branch
  • the adjusted branch is the reference branch
  • the adjusted branch is the reference branch
  • the adjusted branch is the data branch.
  • the plurality of first adjustment branches in the above-mentioned current adjustment branches can provide adjustment of different gears.
  • each of the first adjustment branches further includes a second transistor, and the first end of the second transistor is connected to the first end of the first transistor. Two ends are coupled and connected, the second end of the second transistor is coupled and connected to the first end of the third switch, and the third ends of the second transistors in the M first regulating branches are coupled and connected.
  • the first regulating branch may include two transistors (a first transistor and a second transistor) connected in series, so as to increase the equivalent resistance in each first regulating branch.
  • each first regulating branch may further include three or more transistors, the plurality of transistors are connected in series with the third switch, and the number of transistors located at corresponding positions in the M first regulating branches is The three terminals can be coupled and connected, so that the equivalent resistances of different first regulating branches are the same.
  • the above-mentioned current adjustment circuit includes N second adjustment branches, N is an integer greater than or equal to 1, and each second adjustment branch It includes a fourth switch and a third transistor connected in series with the fourth switch, wherein the first end of the third transistor is coupled to the second end of the first switch and the second end of the second switch, the The second end of the third transistor is coupled and connected to the first end of the fourth switch, the second end of the fourth switch is grounded, and the third ends of the third transistors in the N second regulating branches are coupled to each other. connect.
  • the second regulating branch is turned on, so that the current of the regulating branch can be increased.
  • the adjusted branch is the data branch
  • the adjusted branch is the reference branch
  • the adjusted branch is the data branch
  • the adjusted branch is the reference branch.
  • the plurality of second adjustment branches in the above-mentioned current adjustment branches can provide adjustment of different gears.
  • each of the second adjustment branches further includes a fourth transistor, and the first end of the fourth transistor is connected to the third transistor of the third transistor. Two ends are coupled and connected, the second end of the fourth transistor is coupled and connected to the first end of the fourth switch, and the third ends of the fourth transistors in the N second regulating branches are coupled and connected.
  • the second regulating branch may include two transistors (a third transistor and a fourth transistor) connected in series, so as to increase the equivalent resistance in each second regulating branch.
  • each second regulating branch may further include three or more transistors, the plurality of transistors are connected in series with the fourth switch, and the number of transistors located at corresponding positions in the N second regulating branches is The three terminals can be coupled and connected, so that the equivalent resistances of different second regulating branches are the same.
  • the data reading circuit further includes a register file, and a one-time programmable memory coupled to the register file, the register file and the above The first switch, the second switch, and the current adjustment circuit are coupled and connected; the register file is used to obtain control information from the one-time programmable memory, and control the first switch and the current adjustment circuit based on the control information, or , controlling the second switch and the current regulating circuit; the control information includes the control mode of the first switch and the current regulating circuit, or includes the control mode of the second switch and the current regulating circuit.
  • the data reading circuit can control the first switch or the second switch through the register file, and adjust the current of the reference branch or the data branch through the current adjustment circuit.
  • the current of the reference branch can be located within the ideal REF window to improve the accuracy of data cell reading.
  • the control information may include closing the first switch and the switch in the current adjustment circuit, or including closing the second switch and the switch in the current adjustment circuit.
  • the data reading circuit further includes a fifth transistor and a sixth transistor, and the first end of the fifth transistor is connected to the first end of the first switch.
  • the first end is coupled and connected, the second end of the fifth transistor is coupled and connected to the data unit, the third end of the fifth transistor is coupled to a preset voltage;
  • the first end of the sixth transistor is coupled to the first end of the second switch
  • One end is coupled and connected, the second end of the sixth transistor is coupled and connected to the reference unit, and the third end of the sixth transistor is coupled to the preset voltage.
  • the fifth transistor and the sixth transistor are coupled and connected to the preset voltage, so that the magnitude of the current of the data unit and the reference unit can be controlled to avoid failure of the reference unit or the data unit due to excessive current.
  • a method for controlling a data reading circuit includes a sense amplifier, a first switch, a second switch, a current adjustment circuit, a data unit, and a reference unit; wherein the The first input end of the sense amplifier is coupled and connected to the first end of the first switch and the data unit, the second input end of the sense amplifier is coupled and connected to the first end of the second switch and the reference unit, and the second end of the first switch passes through
  • the current adjustment circuit is coupled and connected to the second end of the second switch; the current adjustment circuit is used to adjust the current of the first input end of the sense amplifier, or adjust the current of the second input end of the sense amplifier;
  • the above method includes: acquiring control information; the The control information includes the control method of the first switch and the current adjustment circuit, or includes the control method of the second switch and the current adjustment circuit; based on the control information, the first switch and the current adjustment circuit are controlled, or the second switch and the current adjustment circuit are controlled.
  • the current of the data branch or the current of the reference branch can be adjusted so that the current of the reference branch is within an ideal REF window, and the data of the data unit can be read accurately.
  • the first switch or the second switch is controlled, and the current of the reference branch or the data branch is adjusted by the current adjustment circuit, so that the current of the reference branch is at the ideal value. within the REF window. That is, in this solution, only one current adjustment circuit is provided to adjust the current of the data branch or the current of the reference branch, which reduces the board area of the adjustment circuit and improves the reading speed of the S/A. And by setting the first switch and the second switch, the parasitic capacitance at the first node C1 and the second node C2 is reduced, and the reading speed of the S/A is improved.
  • the data reading circuit further includes a register file, and a one-time programmable memory coupled to the register file, the register file being connected to the first switch, the second switch, and the second switch.
  • the switch, and the above-mentioned current regulating circuit are coupled and connected; the above-mentioned obtaining the control information includes: the register file obtains the above-mentioned control information from the one-time programmable memory.
  • control information is obtained from the one-time programmable memory through the register file, so that the register file can adjust the current of the data branch or the current of the reference branch, so that the current of the reference branch is located in the ideal REF window, which can Accurately read the data of the data unit.
  • the above method may further include: the register file receives the first information , the first information is used to indicate the start of the read cycle. Based on this solution, when the data unit is read, the register file can obtain control information from the one-time programmable memory, so as to adjust the current of the data branch or the current of the reference branch, so that the current of the reference branch is located at ideally within the REF window to ensure accurate reading of data cell data.
  • the above-mentioned current adjustment circuit includes M first adjustment branches, where M is an integer greater than or equal to 1, and each first adjustment branch It includes a third switch and a first transistor connected in series with the third switch, wherein the first end of the first transistor is coupled to the second end of the first switch and the second end of the second switch, the The second end of the first transistor is coupled and connected to the first end of the third switch, the second end of the third switch is coupled and connected to the power supply, and the third ends of the first transistors in the M first regulating branches coupling connection between.
  • the first regulating branch when the first switch or the second switch is closed, the first regulating branch is turned on, so that the current of the regulating branch can be reduced.
  • the adjusted branch when the first switch is closed, the adjusted branch is the data branch, and when the second switch is closed, the adjusted branch is the reference branch.
  • the current of the reference branch is too large, the adjusted branch is the reference branch, and when the current of the reference branch is too small, the adjusted branch is the data branch.
  • the plurality of first adjustment branches in the above-mentioned current adjustment branches can provide adjustment of different gears.
  • each of the first adjustment branches further includes a second transistor, and the first end of the second transistor is connected to the first end of the first transistor. Two ends are coupled and connected, the second end of the second transistor is coupled and connected to the first end of the third switch, and the third ends of the second transistors in the M first regulating branches are coupled and connected.
  • the first regulating branch may include two transistors (a first transistor and a second transistor) connected in series, so as to increase the equivalent resistance in each first regulating branch.
  • each first regulating branch may further include three or more transistors, the plurality of transistors are connected in series with the third switch, and the number of transistors located at corresponding positions in the M first regulating branches is The three terminals can be coupled and connected, so that the equivalent resistances of different first regulating branches are the same.
  • the control information includes closing the second switch and the J1 first adjustment
  • J1 is an integer greater than or equal to 1 and less than or equal to the above M.
  • the above method further includes: the register file receives second information, where the second information is used to indicate the end of the read cycle; the register file Based on the second information, the second switch and the J1 third switches in the first regulating branch are turned off. Based on this solution, at the end of reading, the second switch and the plurality of first regulating branches can be turned off, so that when the data unit is read next time, the second switch and the current regulating circuit can be controlled again according to the control information, to accurately read data units.
  • the control information includes closing the first switch and P1 the first adjustment.
  • P1 is an integer greater than or equal to 1 and less than or equal to M.
  • the above method further includes: the register file receives second information, where the second information is used to indicate the end of the read cycle; the register file Based on the second information, the first switch and the third switches in the P1 first regulating branches are turned off. Based on this solution, at the end of reading, the first switch and the plurality of first adjustment branches can be turned off, so that when the data unit is read next time, the first switch and the current adjustment circuit can be controlled again according to the control information, to accurately read data units.
  • the above current adjustment circuit includes N second adjustment branches, N is an integer greater than or equal to 1, and each second adjustment branch It includes a fourth switch and a third transistor connected in series with the fourth switch, wherein the first end of the third transistor is coupled to the second end of the first switch and the second end of the second switch, the The second end of the third transistor is coupled and connected to the first end of the fourth switch, the second end of the fourth switch is grounded, and the third ends of the third transistors in the N second regulating branches are coupled to each other. connect.
  • the second regulating branch is turned on, so that the current of the regulating branch can be increased.
  • the adjusted branch is the data branch
  • the adjusted branch is the reference branch
  • the adjusted branch is the data branch
  • the adjusted branch is the reference branch.
  • the plurality of second adjustment branches in the above-mentioned current adjustment branches can provide adjustment of different gears.
  • each of the second adjustment branches further includes a fourth transistor, and the first end of the fourth transistor is connected to the third transistor of the third transistor. Two ends are coupled and connected, the second end of the fourth transistor is coupled and connected to the first end of the fourth switch, and the third ends of the fourth transistors in the N second regulating branches are coupled and connected.
  • the second regulating branch may include two transistors (a third transistor and a fourth transistor) connected in series, so as to increase the equivalent resistance in each second regulating branch.
  • each second regulating branch may further include three or more transistors, the plurality of transistors are connected in series with the fourth switch, and the number of transistors located at corresponding positions in the N second regulating branches is The three terminals can be coupled and connected, so that the equivalent resistances of different second regulating branches are the same.
  • the control information includes closing the first switch and P2 of the second adjustment
  • P2 is an integer greater than or equal to 1 and less than or equal to N.
  • the above method further includes: the register file receives second information, where the second information is used to indicate the end of the read cycle; the register file Based on the second information, the first switch and the fourth switches in the P2 second adjustment branches are turned off. Based on this solution, at the end of reading, the first switch and the plurality of second regulating branches can be turned off, so that when the data unit is read next time, the first switch and the current regulating circuit can be controlled again according to the control information, to accurately read data units.
  • the control information includes closing the second switch and J2 the second adjustment.
  • J2 is an integer greater than or equal to 1 and less than or equal to N.
  • the above method further includes: the register file receives second information, where the second information is used to indicate the end of the read cycle; the register file Based on the second information, the second switch and the fourth switch in the J2 second regulating branches are turned off. Based on this solution, at the end of reading, the second switch and the plurality of second regulating branches can be turned off, so that when the data unit is read next time, the second switch and the current regulating circuit can be controlled again according to the control information, to accurately read data units.
  • the data reading circuit further includes a fifth transistor and a sixth transistor, and the first end of the fifth transistor is connected to the first end of the first switch.
  • the first end is coupled and connected, the second end of the fifth transistor is coupled and connected to the data unit, the third end of the fifth transistor is coupled to a preset voltage;
  • the first end of the sixth transistor is coupled to the first end of the second switch
  • One end is coupled and connected, the second end of the sixth transistor is coupled and connected to the reference unit, and the third end of the sixth transistor is coupled to the preset voltage.
  • the fifth transistor and the sixth transistor are coupled and connected to the preset voltage, so that the magnitude of the current of the data unit and the reference unit can be controlled to avoid failure of the reference unit or the data unit due to excessive current.
  • a storage device in a third aspect of the embodiments of the present application, includes a controller and the data reading circuit according to the first aspect.
  • a fourth aspect of the embodiments of the present application provides a terminal device, where the terminal device includes a processor and a memory, and the memory includes the data reading circuit described in the first aspect above.
  • FIG. 1 is a schematic structural diagram of a data unit according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a data reading circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the relationship between a REF window and the current of a data branch provided by an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of another data reading circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a parasitic capacitance generated by an adjustment circuit in a data reading circuit according to an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of another data reading circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a current regulation circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another current regulation circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another data reading circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another data reading circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another data reading circuit provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another data reading circuit provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of another data reading circuit provided by an embodiment of the present application.
  • FIG. 14 is a schematic timing diagram of signals in a data reading circuit provided by an embodiment of the present application.
  • 15 is a schematic flowchart of a control method of a data reading circuit provided by an embodiment of the present application.
  • 16 is a schematic diagram of a control effect of a data reading circuit provided by an embodiment of the application.
  • 17 is a schematic diagram of a control effect of another data reading circuit provided by an embodiment of the present application.
  • FIG. 18 is a schematic flowchart of another control method of a data reading circuit provided by an embodiment of the present application.
  • At least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b and c can be single or multiple.
  • words such as “first” and “second” are used to distinguish the same or similar items that have basically the same function and effect, Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order.
  • the "first” in the first switch and the "second” in the second switch in the embodiments of the present application are only used to distinguish different switches.
  • the descriptions of the first, second, etc. appearing in the embodiments of the present application are only used for illustration and distinguishing the description objects, and have no order. any limitations of the examples.
  • an embodiment of the present application provides a data reading circuit, which can reduce the size of the adjustment circuit. Take up board area and improve memory read speed. It should be noted that the current regulating circuit in the following embodiments of the present application is a trimming circuit.
  • FIG. 6 is a data reading circuit provided by an embodiment of the present application.
  • the data reading circuit includes a sense amplifier S/A, a first switch K1, a second switch K2, a current adjustment circuit, and a data unit and reference units.
  • the first input end a1 of the sense amplifier S/A is coupled to the first end a2 of the first switch K1 and the data unit
  • the second input end b1 of the sense amplifier S/A is connected to the first end a3 of the second switch K2 and the reference unit is coupled and connected
  • the second end b2 of the first switch K1 is coupled and connected to the second end b3 of the second switch K2 through a current regulating circuit.
  • the second end b2 of the first switch K1 is coupled and connected to the first end 1 of the current adjustment circuit, and the second end b3 of the second switch K2 is coupled to the second end 2 of the current adjustment circuit. connect.
  • the above data unit is used to store data.
  • S/ A determines whether the current ID of the data branch is a high current I H or a low current IL based on the current I REF of the reference branch, and amplifies it into a identifiable high and low level output Signal. That is, the above-mentioned reference unit is used to determine the read result of the data unit.
  • the above-mentioned current adjustment circuit is used to adjust the current of the first input terminal a1 of the sense amplifier S/A, or to adjust the current of the second input terminal b1 of the sense amplifier S/A.
  • the current of the first input terminal a1 of the sense amplifier S/A is the current ID of the data branch
  • the current of the second input terminal b1 of the sense amplifier S /A is the current I REF of the reference branch.
  • the first input terminal a1 of the sense amplifier S/A, the first terminal a2 of the first switch K1 and the data unit are coupled to the first node C1
  • the current ID of the data branch is the sense amplifier S /A current on the branch from the first input terminal a1 to the first node C1.
  • the second input end b1 of the sense amplifier S/A, the first end a3 of the second switch K2 and the reference unit are coupled to the second node C2
  • the current I REF of the reference branch is the second input end b1 of the sense amplifier S/A Current on the branch to the second node C2. That is, the current regulating circuit can regulate ID by injecting or drawing current to the first node C1, and can also regulate I REF by injecting or drawing current to the second node C2.
  • the current ID of the data branch can be adjusted by the current adjustment circuit .
  • the current I REF of the reference branch can be adjusted by the current adjustment circuit. That is, the current of the data branch or the reference branch can be selectively adjusted through the first switch K1 and the second switch K2.
  • the current of the data branch can be adjusted so that the current of the reference branch is within the ideal REF window, or the current of the reference branch can be adjusted to make the reference branch.
  • the current of the branch is located within the ideal REF window.
  • whether the data branch is used as the adjustment branch or the reference branch is used as the adjustment branch is related to the circuit structure of the current adjustment circuit.
  • the data reading circuit provided by the present application can selectively adjust the current of the data branch or the current of the reference branch through the first switch and the second switch.
  • a trimming circuit is respectively set on the data branch and the reference branch, one trimming circuit adjusts the current of the data branch, and one trimming circuit adjusts the current of the reference branch.
  • the current of the data branch or the current of the reference branch can be adjusted, thus reducing the footprint of the adjustment circuit.
  • the data reading circuit provided by the present application separates the current adjustment circuit from the first node C1 through the first switch K1, and separates the current adjustment circuit from the first node C1 through the second switch K2.
  • the second node C2 is separated, so that the parasitic capacitance of the multi-column transistors in the current regulation circuit will not be added to the first node C1 and the second node C2, reducing the parasitic capacitance at the first node C1 and the second node C2, and improving the S/A read speed.
  • the current adjustment circuit includes M first adjustment branches, where M is an integer greater than or equal to 1, and each first adjustment branch includes A third switch K3, and a first transistor Q1 connected in series with the third switch K3.
  • the first end a4 of the first transistor Q1 is coupled to the second end b2 of the first switch K1 and the second end b3 of the second switch K2, and the second end b4 of the first transistor Q1 is connected to the second end b4 of the third switch K3.
  • One end a5 is coupled and connected, the second end b5 of the third switch K3 is coupled and connected to the power supply V DD , and the third ends c4 of the first transistors Q1 in the M first regulating branches are coupled and connected.
  • each first regulating branch may further include a second transistor Q2, the first end a6 of the second transistor Q2 and the second end b4 of the first transistor Q1 Coupling connection, the second end b6 of the second transistor Q2 is coupled and connected to the first end a5 of the third switch K3, and the third ends c6 of the second transistors Q2 in the M first regulating branches are coupled and connected.
  • each first regulating branch may further include three or more transistors, the plurality of transistors are connected in series with the third switch K3, and the transistors located at the corresponding positions in the M first regulating branches are connected in series.
  • the third ends can be coupled and connected, so that the equivalent resistances of different first regulating branches are the same.
  • the embodiment of the present application does not limit the specific number of transistors included in the first adjustment branch. (a) in FIG.
  • the first adjustment branch 7 only takes the first adjustment branch including one transistor (Q1) as an example for illustration, and (a) in FIG. 7 b) It is only illustrated that the first regulating branch includes two transistors (Q1 and Q2). In practical applications, the number of transistors in the first adjustment branch can be set according to chip requirements.
  • the adjustment methods provided by the current adjustment circuit shown in (a) in FIG. 7 and the current adjustment circuit shown in (b) in FIG. 7 can be adjusted by the first switch K1 or the second switch K2 when the first switch K1 or the second switch K2 is closed.
  • the branch is shunted to reduce the current of the regulated branch.
  • the adjusted branch can be a data branch or a reference branch.
  • the adjusted branch is the data branch
  • the second switch K2 is closed
  • the adjusted branch is the reference branch. It can be understood that, in combination with the current adjustment circuit shown in FIG. 7 , when the current of the reference branch is too large, the adjusted branch is the reference branch, and when the current of the reference branch is too small, the adjusted branch is the data branch. .
  • the second switch K2 and the third switch K3 in the first regulating branch can be closed to make the reference branch current
  • the current I REF can be shunted to the first regulating branch, thereby reducing the current I REF of the reference branch, so that the current I REF of the reference branch is no longer too large.
  • the first switch K1 and the third switch K3 in the first adjustment branch can be closed, so that the data branch can be closed.
  • the current ID can be shunted to the first regulating branch, thereby reducing the current ID of the data branch, which is equivalent to increasing the current I REF of the reference branch, so that the current I REF of the reference branch is no longer too small.
  • the multiple first adjustment branches in the current adjustment circuit can provide adjustment of different gears.
  • more third switches K3 in the first regulating branch can be closed, so that the current I REF of the reference branch can be shunted to more first regulating branches so that the current I REF of the shunted reference branch can be located within the REF window.
  • the third switch K3 in the first regulating branch can be closed, so that the current I REF of the reference branch can be shunted to less first regulating branches, Thereby, the current I REF of the reference branch can be located within the REF window.
  • the gear position information of the current regulation branch and the information of the regulation data branch or the reference branch can be written into the one-time programmable memory after the chip is tested at the factory.
  • the current adjustment circuit includes N second adjustment branches, N is an integer greater than or equal to 1, and each second adjustment branch It includes a fourth switch K4, and a third transistor Q3 connected in series with the fourth switch K4.
  • the first end a7 of the third transistor Q3 is coupled to the second end b2 of the first switch K1 and the second end b3 of the second switch K2, and the second end b7 of the third transistor Q3 is connected to the second end b7 of the fourth switch K4.
  • One end a8 is coupled and connected, the second end b8 of the fourth switch K4 is grounded, and the third ends c7 of the third transistors Q3 in the N second regulating branches are coupled and connected.
  • the values of M and N may be the same or different.
  • each second regulating branch may further include a fourth transistor Q4, the first end a9 of the fourth transistor Q4 is coupled to the second end b7 of the third transistor connection, the second end b9 of the fourth transistor Q4 is coupled and connected to the first end a8 of the fourth switch K4, and the third ends c9 of the fourth transistor Q4 in the N second regulating branches are coupled and connected.
  • each second adjustment branch may further include three or more transistors, the plurality of transistors are connected in series, and between the third ends of the transistors located at the corresponding positions in the N second adjustment branches
  • the coupling connections can be made so that the equivalent resistances of the different second regulating branches are the same.
  • the embodiment of the present application does not limit the specific number of transistors included in the second adjustment branch. (a) in FIG. 8 only takes the second adjustment branch including one transistor (Q3) as an example for illustration, and (a) in FIG. 8 b) It is only illustrated that the second regulating branch includes two transistors (Q3 and Q4). In practical applications, the number of transistors in the second regulating branch can be set according to chip requirements.
  • the adjustment mode provided by the current adjustment circuit shown in (a) in FIG. 8 and the current adjustment circuit shown in (b) in FIG. 8 can increase the adjusted value when the first switch K1 or the second switch K2 is closed.
  • the adjusted branch can be a data branch or a reference branch.
  • the adjusted branch is the data branch
  • the second switch K2 is closed
  • the adjusted branch is the reference branch. It can be understood that, combined with the current adjustment circuit shown in Figure 8, when the current of the reference branch is too large, the adjusted branch is the data branch, and when the current of the reference branch is too small, the adjusted branch is the reference branch. .
  • the first switch K1 and the fourth switch K4 in the second regulating branch can be closed, so that the current of the data branch can be closed.
  • ID is the sum of the current on the data unit and the current on the second regulating branch, so increasing the current ID of the data branch is equivalent to reducing the current I REF of the reference branch, so that the current of the reference branch is I REF is no longer too large.
  • the second switch K2 and the fourth switch K4 in the second regulating branch can be closed, so that the reference branch can be closed.
  • the current I REF is the sum of the current on the reference unit and the current on the second regulating branch, so the current I REF of the reference branch is increased, so that the current I REF of the reference branch is no longer too small.
  • the multiple second adjustment branches in the current adjustment circuit can provide adjustment of different gears.
  • the second switch K2 and the fourth switches K4 in the second adjustment branches can be closed, so that the current I REF of the reference branch is the value on the reference unit.
  • the sum of the current I REF of the reference branch and the currents on more second regulation branches increases the current I REF of the reference branch to a greater extent, so that the current I REF of the reference branch can be located within the REF window.
  • the second switch K2 and the fourth switch K4 in the second regulating branch may be closed, so that the current I REF of the reference branch is the current on the reference unit
  • the sum with less current on the second regulation branch causes the current I REF of the reference branch to increase to a lesser extent, so that the current I REF of the reference branch can lie within the REF window.
  • the gear position information of the current regulation branch and the information of the regulation data branch or the reference branch can be written into the one-time programmable memory after the chip is tested at the factory.
  • the first switch or the second switch can be closed, and the current of the reference branch or the data branch can be adjusted by the current adjustment circuit. , so that the current in the reference branch is within the ideal REF window.
  • one trimming circuit adjusts the current of the data branch, and one trimming circuit adjusts the current of the reference branch, only one current adjustment circuit can be set in the present application. The current in the data branch or the current in the reference branch is adjusted, thus reducing the footprint of the adjustment circuit.
  • the data reading circuit provided by the present application may include one or more data units, and the data reading circuit may include one or more reference units, which are not limited in the embodiments of the present application. 6 It is only an example that the data reading circuit includes one data unit and one reference unit.
  • each data unit in the plurality of data units is coupled to a word line WL, and the WL is used to select a data unit.
  • the data read circuit includes 512 data cells, each data cell is coupled to a word line, 512 data cells are respectively coupled to word lines WL 0 to WL 511 , each word line is used for A data unit is selected for read operation.
  • the data reading circuit may also include two data unit groups and two reference units, and each data unit group includes a plurality of data units.
  • Data cells in each data cell group are coupled to one bit line selector BLMUX and one source line selector SLMUX, each data cell being coupled to one word line WL.
  • BLMUX and SLMUX are used to select a bit line and source line respectively, and WL is used to select a data unit.
  • the data reading circuit includes two data unit groups, namely a first data unit group and a second data unit group, and the two reference units are reference unit 1 and reference unit 2 respectively.
  • the cell group and the second data cell group include 512 data cells, respectively, and the 512 data cells are coupled to the bit lines WL 0 to WL 511 , respectively.
  • the data unit and reference unit 2 When reading a data unit in the second data unit group, the data unit and reference unit 2 are selected, and the data unit and reference unit 1 in the first data unit group are not selected, compare ID and I REF , output high and low level signal. It will be appreciated that data cells or reference cells may or may not be selected through BLMUX, SLMUX and WL.
  • the data reading circuit further includes a register file, and a one-time programmable memory coupled to the register file, the register file is connected to the first switch K1, the second switch K2, and the current adjustment circuit. Coupling connection.
  • the register file is used to obtain control information from the one-time programmable memory, and based on the control information, control the first switch K1 and the current regulating circuit, or control the second switch K2 and the current regulating circuit.
  • the control information includes the control mode of the first switch K1 and the current adjustment circuit, or includes the control mode of the second switch K2 and the current adjustment circuit.
  • the control information can be written into the one-time programmable memory after the chip is tested after leaving the factory, and the one-time programmable memory can be (One Time Programmable, OTP) or efuse.
  • the control information includes closing the second switch K2 and the first adjustment branch J1.
  • the third switches K3 and J1 in the circuit are integers greater than or equal to 1 and less than or equal to M.
  • the control information includes closing the first switch K1 and the third switch K3 in the P1 first regulating branches, where P1 is an integer greater than or equal to 1 and less than or equal to M.
  • J1 and P1 are gear information. The current of the reference branch is too large or too small, and the values of J1 and P1 are different.
  • the control information includes closing the first switch K1 and the P2 second adjustment branches.
  • the fourth switches K4 and P2 in the road are integers greater than or equal to 1 and less than or equal to N.
  • the control information includes closing the second switch K2 and the fourth switch K4 in the J2 second regulating branches, where J2 is an integer greater than or equal to 1 and less than or equal to N.
  • J2 and P2 are gear information.
  • the current of the reference branch is large or small, and the values of J2 and P2 are different.
  • the register file can obtain control information from the one-time programmable memory at the beginning of the read cycle, and control the data read circuit based on the control information, so that the current of the reference branch can be located within an ideal REF window.
  • the register file may turn off the first switch and the switch in the current regulation circuit, or turn off the second switch and the switch in the current regulation circuit.
  • the first switch or the second switch can be controlled through the register file, and the current of the reference branch or the data branch can be adjusted through the current adjustment circuit, So that the current of the reference branch can be located within the ideal REF window.
  • the data reading circuit may further include a fifth transistor Q5 and a sixth transistor Q6, and the first end a10 of the fifth transistor Q5 is coupled and connected to the first end a2 of the first switch K1,
  • the second terminal b10 of the fifth transistor Q5 is coupled and connected to the data unit, and the third terminal c10 of the fifth transistor Q5 is coupled to the preset voltage V C .
  • the first end a11 of the sixth transistor Q6 is coupled to the first end a3 of the second switch K2, the second end b11 of the sixth transistor Q6 is coupled to the reference unit, and the third end c11 of the sixth transistor Q6 is coupled to the preset voltage V C .
  • the third terminal c10 of the fifth transistor Q5 and the third terminal c11 of the sixth transistor Q6 may be coupled to the preset voltage V C .
  • the currents of the data unit and the reference unit can be controlled to avoid failure of the reference unit or the data unit due to excessive current.
  • the above-mentioned first transistor Q1 to sixth transistor Q6 may be field effect transistors (Field Effect Transistor, FET), for example, metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) .
  • FET Field Effect Transistor
  • MOSFET Metal-oxide semiconductor field effect transistor
  • the above-mentioned first switch K1 to fourth switch K4 may also be MOSFETs.
  • the first switch or the second switch when the current of the reference branch is too large or too small, the first switch or the second switch can be closed, and the current of the data branch or the reference branch can be adjusted by the current adjustment circuit, so that the reference branch can be adjusted.
  • the current of the circuit is within the ideal REF window. That is, the present application can adjust the current of the data branch or the current of the reference branch by setting only one current adjustment circuit, thus reducing the board area of the adjustment circuit.
  • the parasitic capacitance at the first node C1 and the second node C2 is reduced, and the reading speed of the S/A is improved.
  • the current regulating circuit works in the precharge stage of S/A.
  • the T_EN signal and the first switch K1 or the second switch K2 will be activated at the same time as BLMUX, SLMUX, and WL, and the current adjustment circuit will be connected to the data reading circuit, so that the current of the data branch or the current of the reference branch can be adjusted. .
  • An embodiment of the present application further provides a method for controlling a data reading circuit.
  • the data reading circuit may be any of the data reading circuits shown in FIG. 11 to FIG. 13 , and the current regulating circuit in the data reading circuit may be For the current regulation circuit shown in FIG. 7 or FIG. 8, as shown in FIG. 15, the control method includes steps S1501-S1503.
  • the register file receives the first information.
  • the first information is used to indicate the start of the read cycle.
  • the register file when the S/A starts to read the data unit, the register file receives the first information indicating the start of the read cycle.
  • the register file acquires control information.
  • the control information includes the control mode of the first switch K1 and the current adjustment circuit, or includes the control mode of the second switch K2 and the current adjustment circuit.
  • the foregoing step S1502 may include: the register file acquires control information from the one-time programmable memory based on the first information.
  • the control information includes closing the second switch K2 and the first adjustment circuit J1.
  • the third switches K3 and J1 in the branch are integers greater than or equal to 1 and less than or equal to M. If the current of the reference branch is too small, the control information includes closing the first switch K1 and the third switch K3 in the P1 first regulating branches, where P1 is an integer greater than or equal to 1 and less than or equal to M.
  • the control information includes closing the first switch K1 and the second adjustment circuit P2.
  • the fourth switches K4 and P2 in the branch are integers greater than or equal to 1 and less than or equal to N. If the current of the reference branch is too small, the control information includes closing the second switch K2 and the fourth switch K4 in the J2 second regulating branches, where J2 is an integer greater than or equal to 1 and less than or equal to N.
  • control information stored in the one-time programmable memory can be written after the chip is tested when it leaves the factory. That is to say, whether the branch to be adjusted is a data branch or a reference branch, and the specific gear information (J1, P1, P2 and J2) in the current adjustment circuit are obtained through chip testing.
  • the register file controls the first switch and the current adjustment circuit, or controls the second switch and the current adjustment circuit.
  • the register file may close the first switch and the switch in the current regulation circuit, or close the second switch and the switch in the current regulation circuit, based on the control information.
  • the above step S1503 includes: the register file closes the second switches K2 and J1.
  • the above step S1503 includes: the register file closes the first switches K1 and P2 The fourth switch K4 in the second regulating branch. If the current of the reference branch is too small, the above step S1503 includes: the register file closes the second switch K2 and the fourth switch K4 in the J2 second adjustment branches.
  • the current I REF of the reference branch is ideally located within the REF window, so that the current ID of the data branch can be divided into a high current I H and a low current IL , so that the data unit can be read accurately .
  • the current I REF of the reference branch is within the ideal REF window.
  • the current I REF of the reference branch is not within the REF window, which is smaller than the ideal value. At this time, a part of IL will be larger than I REF , resulting in the wrong data unit being read.
  • the current regulating circuit in the data reading circuit is the current regulating circuit shown in (a) of FIG. 7 . If the current I REF of the reference branch is too small, after the register obtains the control information, the first switch K1 and the third switch K3 in the P1 first adjustment branches are closed.
  • the current ID of the data branch will decrease due to being shunted in parallel, which is equivalent to increasing the current I REF of the reference branch.
  • the currents I H ′ and IL ′ of the data branch after adjustment are relative to the current I of the data branch before adjustment H and IL (shown by the solid line in (b) of FIG. 16 ) are reduced so that I REF can be between I H ′ and IL ′, and the current I REF of the reference branch is at the new REF window' (REF window' in (b) of FIG. 16), so the data unit can be read correctly.
  • the current I REF of the reference branch is not within the REF window, and is larger than the ideal value. At this time, a part of I H will be smaller than I REF , resulting in wrong data cells being read.
  • the current regulating circuit in the data reading circuit is the current regulating circuit shown in (a) of FIG. 7 . If the current I REF of the reference branch is too large, after the register obtains the control information, the second switch K2 and the third switch K3 in the J1 first regulating branch are closed. At this time, the current I REF of the reference branch will decrease due to being shunted in parallel.
  • the current I REF ′ of the reference branch after adjustment is reduced relative to the current I REF of the reference branch before adjustment, and the current I REF ′ of the reference branch after adjustment is located at REF Within the window, I REF ' is between I H and IL , so the data cells can be read correctly.
  • the control information is obtained from the one-time programmable memory through the register file, so that the current of the data branch or the reference branch can be checked.
  • the current of the reference branch is adjusted so that the current of the reference branch is within the ideal REF window, and the data of the data unit can be read accurately.
  • the first switch or the second switch can be controlled by the register file, and the current of the reference branch or the data branch can be adjusted by the current adjustment circuit, so that the current of the reference branch is at within the ideal REF window. That is, in this solution, only one current adjustment circuit is provided to adjust the current of the data branch or the current of the reference branch, which reduces the board area of the adjustment circuit and improves the reading speed of the S/A.
  • An embodiment of the present application further provides a method for controlling a data reading circuit.
  • the data reading circuit may be any of the data reading circuits shown in FIG. 11 to FIG. 13 , and the current regulating circuit in the data reading circuit may be As shown in FIG. 7 or FIG. 8 , as shown in FIG. 18 , the control method may further include steps S1504 - S1505 in addition to the above steps S1501 - S1503 .
  • the register file receives the second information.
  • the second information is used to indicate the end of the read cycle.
  • the register file controls the first switch and the current adjustment circuit, or controls the second switch and the current adjustment circuit.
  • the register file may turn off the first switch and the switch in the current regulation circuit, or turn off the second switch and the switch in the current regulation circuit.
  • the above step S1505 includes: the register file is turned off based on the second information.
  • the above step S1505 includes: based on the second information, the register file turns off the first switch K1 and the third switch K3 in the P1 first adjustment branches.
  • the above step S1505 includes: the register file is turned off based on the second information.
  • the above step S1505 includes: based on the second information, the register file turns off the second switch K2 and the fourth switch K4 in the J2 second adjustment branches.
  • the current regulation circuit and the first switch or the first switch are turned off by the end of the reading cycle, so that when the data unit is read next time, the switches in the data reading circuit can be controlled again according to the control information. , to accurately read the data unit.
  • the control information is obtained from the one-time programmable memory through the register file, so that the current of the data branch or the reference branch can be checked.
  • the current of the reference branch is adjusted so that the current of the reference branch is within the ideal REF window, and the data of the data unit can be read accurately.
  • the first switch or the second switch can be controlled by the register file, and the current of the reference branch or the data branch can be adjusted by the current adjustment circuit, so that the current of the reference branch is at within the ideal REF window.
  • only one current adjustment circuit can be set to adjust the current of the data branch or the current of the reference branch, which reduces the board area of the adjustment circuit and improves the reading speed of the S/A.
  • the register file turns off the current adjustment circuit and the first switch or the first switch.
  • the switches in the data reading circuit can be controlled again according to the control information to Accurately read data units.
  • Embodiments of the present application further provide a storage device, where the storage device includes a controller and any of the foregoing data reading circuits.
  • the storage device may include a plurality of data reading circuits, and the circuit structure of each data reading circuit may be any of those shown in FIG. 6 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 or FIG. 13 .
  • Circuit, the circuit structure of the current adjustment circuit in the data reading circuit may be the circuit shown in FIG. 7 or FIG. 8 .
  • the circuit structures of the current adjustment circuits in different data reading circuits may be the same or different.
  • An embodiment of the present application further provides a terminal device, where the terminal device includes a processor and a memory, and the memory includes any of the foregoing data reading circuits.
  • the memory may include one or more data reading circuits, and the circuit structure of each data reading circuit may be any of FIG. 6 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 or FIG. 13 .
  • the circuit structure of the current adjustment circuit in the data reading circuit may be the circuit shown in FIG. 7 or FIG. 8 .
  • the circuit structures of the current adjustment circuits in different data reading circuits may be the same or different.
  • the steps of the methods or algorithms described in conjunction with the disclosure of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • the software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (Random Access Memory, RAM), flash memory, Erasable Programmable Read-Only Memory (Erasable Programmable ROM, EPROM), electrically erasable programmable Programmable read-only memory (Electrically EPROM, EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM), or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and storage medium may reside in an ASIC.
  • the ASIC may be located in the core network interface device.
  • the processor and the storage medium may also exist in the core network interface device as discrete components.
  • the functions described in the present invention may be implemented in hardware, software, firmware, or any combination thereof.
  • the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

一种数据读取电路及数据读取电路的控制方法，涉及电路技术领域，改善了现有技术中存储器的调整电路占板面积较大造成浪费，且读取速度较慢的问题。具体方案为：数据读取电路包括灵敏放大器、第一开关、第二开关、电流调节电路、数据单元和参考单元；其中，灵敏放大器的第一输入端与第一开关的第一端以及数据单元耦合连接，灵敏放大器的第二输入端与第二开关的第一端以及参考单元耦合连接，第一开关的第二端通过电流调节电路与第二开关的第二端耦合连接；电流调节电路用于调整灵敏放大器的第一输入端的电流，或者，调整灵敏放大器的第二输入端的电流。

Description

一种数据读取电路及数据读取电路的控制方法 技术领域
本申请实施例涉及电路技术领域，尤其涉及一种数据读取电路及数据读取电路的控制方法。
背景技术
可变电阻式存储器是一种新型存储器，该新型存储器的数据单元(data cell)通常由一个存储介质单元和一个晶体管(1T1R)构成。如图1所示，存储介质单元可以为高低阻态可变的电阻R，电阻R的不同阻态可以表示数据“0”和数据“1”，晶体管的栅极受字线(word line，WL)控制，负责选中与否这一数据单元。1T1R结构与位线(bit line，BL)和源线(source line，SL)相连接。
如图2所示，在新型存储器的读取过程中，通过读取电路给数据单元施加一个合适的电压，从而阻态不同的数据单元将会分别流过高电流I H和低电流I L，再通过灵敏放大器(sense amplifier，S/A)将数据支路的电流I D与参考支路的电流I REF相比较，并放大成可识别的高低电平输出信号。即灵敏放大器基于I REF识别I D是I H或I L。但是，实际应用中数据单元的阻值存在一定的波动，如图3所示，I H和I L呈现高斯分布，使得REF窗口很小，只有I REF的值在REF窗口内，I REF才能介于I H与I L之间。
然而，读取电路中的晶体管存在工艺偏差，无法确保I REF位于理想的REF窗口内。当I REF偏大时，低阻态的数据单元可能被读为高阻态的数据单元，导致数据单元被读错。当I REF偏小时，高阻态的数据单元可能被读为低阻态的数据单元，导致数据单元被读错。因此，无论I REF偏大或偏小，都将导致电路的良率较低。
为了提高新型存储器中I REF的精度，图4为一种包括调整电路的数据读取电路(“Logic Process Compatible 40-nm 16-Mb,embedded Perpendicular-MRAM with Hybrid-Resistance Reference,Sub-μA Sensing Resolution”)，该调整电路可以对I REF的大小进行调整(trimming)。如图4所示，通过在每个S/A的数据支路和参考支路上分别设置有对称的调整电路，可以根据每个S/A中I REF的实际偏差，通过开启调整电路中不同数量的支路，不同程度地改变参考支路上的I REF或者数据支路上的I D。
但是，由于I REF只会偏大或者偏小，因此图4中的调整电路只有一侧是使用的，而另一侧的调整电路一直处于闲置状态，因此，处于闲置状态的调整电路占板面积较大，将造成浪费。结合图4，如图5所示，调整电路是由多列晶体管并联而成，多列晶体管并联至节点C上，这将导致每一列晶体管的寄生电容会直接加到节点C上，从而增大了节点C的负载，导致BL上的充放电速度变慢，影响S/A的读取速度。
发明内容
本申请实施例提供一种数据读取电路及数据读取电路的控制方法，能够减小调整电路的占板面积，提升读取速度。
为达到上述目的，本申请实施例采用如下技术方案：
本申请实施例的第一方面，提供一种数据读取电路，该数据读取电路包括灵敏放大器、第一开关、第二开关、电流调节电路、数据单元和参考单元；其中，灵敏放大器的第一输入端与第一开关的第一端以及数据单元耦合连接，灵敏放大器的第二输入端与第二开关的第一端以及参考单元耦合连接，第一开关的第二端通过电流调节电路与第二开关的第二端耦合连接；电流调节电路用于调整灵敏放大器的第一输入端的电流，或者，调整灵敏放大器的第二输入端的电流。基于本方案，数据读取电路可以通过第一开关和第二开关，可以选择调整数据支路的电流或参考支路的电流，因此数据读取电路中仅设置一个电流调节电路即可调整数据支路的电流或参考支路的电流，与现有技术中在数据支路和参考支路上分别设置一个trimming电路，一个trimming电路调整数据支路的电流，一个trimming电路调整参考支路的电流相比，减小了调整电路的占板面积。而且本申请的方案通过设置第一开关和第二开关，使得电流调节电路中多列晶体管的寄生电容不会加到第一节点C1(灵敏放大器的第一输入端与第一开关的第一端以及数据单元的耦合点)和第二节点C2(灵敏放大器的第二输入端与第二开关的第一端以及参考单元的耦合点)，降低了第一节点C1和第二节点C2处的寄生电容，从而提升了S/A的读取速度。
结合第一方面，在一种可能的实现方式中，上述电流调节电路包括M个第一调节支路，M为大于或等于1的整数，每个第一调节支路包括第三开关，以及与该第三开关串联连接的第一晶体管，其中，该第一晶体管的第一端与上述第一开关的第二端以及上述第二开关的第二端耦合连接，该第一晶体管的第二端与上述第三开关的第一端耦合连接，上述第三开关的第二端与电源耦合连接，该M个第一调节支路中的上述第一晶体管的第三端之间耦合连接。基于本方案，在第一开关或第二开关闭合时，导通第一调节支路，可以减小所调节支路的电流。可以理解的，第一开关闭合时，所调节支路为数据支路，第二开关闭合时，所调节支路为参考支路。当参考支路的电流偏大时，所调节支路为参考支路，当参考支路的电流偏小时，所调节支路为数据支路。上述电流调节支路中的多个第一调节支路可以提供不同档位的调节。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，每个上述第一调节支路还包括第二晶体管，该第二晶体管的第一端与上述第一晶体管的第二端耦合连接，该第二晶体管的第二端与上述第三开关的第一端耦合连接，上述M个第一调节支路中的第二晶体管的第三端之间耦合连接。基于本方案，第一调节支路中可以包括串联连接的两个晶体管(第一晶体管和第二晶体管)，以增大每个第一调节支路中的等效电阻。可选的，每个第一调节支路还可以包括三个甚至更多个晶体管，该多个晶体管与第三开关之间串联连接，M个第一调节支路中位于相应位置的晶体管的第三端之间可以耦合连接，从而使得不同第一调节支路的等效电阻相同。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述电流调节电路包括N个第二调节支路，N为大于或等于1的整数，每个第二调节支路包括第四开关，以及与该第四开关串联连接的第三晶体管，其中，该第三晶体管的第一端与上述第一开关的第二端以及上述第二开关的第二端耦合连接，该第三晶体管的第二端与上述第四开关的第一端耦合连接，该第四开关的第二端接地，上述N个第二调节支路中的上述第三晶体管的第三端之间耦合连接。基于本方案，在第一开关或第二开关 闭合时，导通第二调节支路，可以增大所调节支路的电流。可以理解的，第一开关闭合时，所调节支路为数据支路，第二开关闭合时，所调节支路为参考支路。当参考支路的电流偏大时，所调节支路为数据支路，当参考支路的电流偏小时，所调节支路为参考支路。上述电流调节支路中的多个第二调节支路可以提供不同档位的调节。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，每个上述第二调节支路还包括第四晶体管，该第四晶体管的第一端与上述第三晶体管的第二端耦合连接，该第四晶体管的第二端与上述第四开关的第一端耦合连接，上述N个第二调节支路中的第四晶体管的第三端之间耦合连接。基于本方案，第二调节支路中可以包括串联连接的两个晶体管(第三晶体管和第四晶体管)，以增大每个第二调节支路中的等效电阻。可选的，每个第二调节支路还可以包括三个甚至更多个晶体管，该多个晶体管与第四开关之间串联连接，N个第二调节支路中位于相应位置的晶体管的第三端之间可以耦合连接，从而使得不同第二调节支路的等效电阻相同。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述数据读取电路还包括寄存器堆，以及与该寄存器堆耦合连接的一次性可编程存储器，该寄存器堆与上述第一开关、上述第二开关，以及上述电流调节电路耦合连接；该寄存器堆用于从上述一次性可编程存储器获取控制信息，并基于该控制信息控制上述第一开关和上述电流调节电路，或者，控制上述第二开关和上述电流调节电路；该控制信息包括上述第一开关和上述电流调节电路的控制方式，或者，包括上述第二开关和上述电流调节电路的控制方式。基于本方案，数据读取电路在参考支路的电流偏大或偏小时，可以通过寄存器堆控制第一开关或第二开关，并通过电流调节电路调整参考支路或数据支路的电流大小，使得参考支路的电流可以位于理想的REF窗口内，以提高数据单元读取的准确性。可选的，该控制信息可以包括闭合上述第一开关和上述电流调节电路中的开关，或者，包括闭合上述第二开关和上述电流调节电路中的开关。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述数据读取电路还包括第五晶体管和第六晶体管，该第五晶体管的第一端与上述第一开关的第一端耦合连接，该第五晶体管的第二端与上述数据单元耦合连接，该第五晶体管的第三端耦合至预设电压；该第六晶体管的第一端与上述第二开关的第一端耦合连接，该第六晶体管的第二端与上述参考单元耦合连接，该第六晶体管的第三端耦合至上述预设电压。基于本方案，通过第五晶体管和第六晶体管与预设电压耦合连接，能够控制数据单元和参考单元的电流大小，避免参考单元或数据单元因电流过大出现故障。
本申请实施例的第二方面，提供一种数据读取电路的控制方法，该数据读取电路包括灵敏放大器、第一开关、第二开关、电流调节电路、数据单元和参考单元；其中，该灵敏放大器的第一输入端与第一开关的第一端以及数据单元耦合连接，灵敏放大器的第二输入端与第二开关的第一端以及参考单元耦合连接，第一开关的第二端通过电流调节电路与第二开关的第二端耦合连接；电流调节电路用于调整灵敏放大器的第一输入端的电流，或者，调整灵敏放大器的第二输入端的电流；上述方法包括：获取控制信息；该控制信息包括第一开关和电流调节电路的控制方式，或者，包括第二开关和电流调节电路的控制方式；基于该控制信息，控制上述第一开关和上述电流调节电路，或者，控制上述第二开关和上述电流调节电路。基于本方案，通过获取控制信息， 从而能够对数据支路的电流或参考支路的电流进行调整，使得参考支路的电流位于理想的REF窗口内，能够准确读取数据单元的数据。该方案在参考数据的电流偏大或偏小时，是通过控制第一开关或第二开关，并通过电流调节电路调整参考支路或数据支路的电流大小，使得参考支路的电流位于理想的REF窗口内。即本方案仅设置一个电流调节电路即可调整数据支路的电流或参考支路的电流，减小了调整电路的占板面积，提升了S/A的读取速度。并且通过设置第一开关和第二开关，降低了第一节点C1和第二节点C2处的寄生电容，提升了S/A的读取速度。
结合第二方面，在一种可能的实现方式中，上述数据读取电路还包括寄存器堆，以及与该寄存器堆耦合连接的一次性可编程存储器，该寄存器堆与上述第一开关、上述第二开关，以及上述电流调节电路耦合连接；上述获取控制信息，包括：该寄存器堆从一次性可编程存储器获取上述控制信息。基于本方案，通过寄存器堆从一次性可编程存储器获取控制信息，从而寄存器堆能够对数据支路的电流或参考支路的电流进行调整，使得参考支路的电流位于理想的REF窗口内，能够准确读取数据单元的数据。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，在上述寄存器堆从上述一次性可编程存储器获取上述控制信息之前，上述方法还可以包括：寄存器堆接收第一信息，该第一信息用于指示读取周期开始。基于本方案，在对数据单元进行读取操作时，寄存器堆可以从一次性可编程存储器获取控制信息，从而对数据支路的电流或参考支路的电流进行调整，使得参考支路的电流位于理想的REF窗口内，以确保准确读取数据单元的数据。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述电流调节电路包括M个第一调节支路，M为大于或等于1的整数，每个第一调节支路包括第三开关，以及与该第三开关串联连接的第一晶体管，其中，该第一晶体管的第一端与上述第一开关的第二端以及上述第二开关的第二端耦合连接，该第一晶体管的第二端与上述第三开关的第一端耦合连接，上述第三开关的第二端与电源耦合连接，该M个第一调节支路中的上述第一晶体管的第三端之间耦合连接。基于本方案，在第一开关或第二开关闭合时，导通第一调节支路，可以减小所调节支路的电流。可以理解的，第一开关闭合时，所调节支路为数据支路，第二开关闭合时，所调节支路为参考支路。当参考支路的电流偏大时，所调节支路为参考支路，当参考支路的电流偏小时，所调节支路为数据支路。上述电流调节支路中的多个第一调节支路可以提供不同档位的调节。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，每个上述第一调节支路还包括第二晶体管，该第二晶体管的第一端与上述第一晶体管的第二端耦合连接，该第二晶体管的第二端与上述第三开关的第一端耦合连接，上述M个第一调节支路中的第二晶体管的第三端之间耦合连接。基于本方案，第一调节支路中可以包括串联连接的两个晶体管(第一晶体管和第二晶体管)，以增大每个第一调节支路中的等效电阻。可选的，每个第一调节支路还可以包括三个甚至更多个晶体管，该多个晶体管与第三开关之间串联连接，M个第一调节支路中位于相应位置的晶体管的第三端之间可以耦合连接，从而使得不同第一调节支路的等效电阻相同。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，在上述参考 支路的电流偏大的情况下，上述控制信息包括闭合上述第二开关以及J1个上述第一调节支路中的第三开关，J1为大于或等于1且小于或等于上述M的整数。基于本方案，在参考支路的电流偏大的情况下，通过闭合第二开关，导通多个第一调节支路，使得多个第一调节支路与参考支路并联分流，从而减小了参考支路的电流，使得参考支路的电流可以位于理想的REF窗口内，以确保正确读取数据单元的数据。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述方法还包括：上述寄存器堆接收第二信息，该第二信息用于指示上述读取周期结束；上述寄存器堆基于该第二信息，关断上述第二开关以及J1个上述第一调节支路中的第三开关。基于本方案，在读取结束时，可以断开第二开关以及多个第一调节支路，从而在下一次读取数据单元时，可以再次根据控制信息对第二开关和电流调节电路进行控制，以准确读取数据单元。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，在上述参考支路的电流偏小的情况下，上述控制信息包括闭合上述第一开关以及P1个上述第一调节支路中的第三开关，P1为大于或等于1且小于或等于M的整数。基于本方案，在参考支路的电流偏小的情况下，通过闭合第一开关，导通多个第一调节支路，使得多个第一调节支路与数据支路并联分流，从而减小了数据支路的电流，相当于增大了参考支路的电流，使得参考支路的电流可以位于介于调整后的数据支路的电流I H’和I L’之间，从而确保正确读取数据单元的数据。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述方法还包括：上述寄存器堆接收第二信息，该第二信息用于指示上述读取周期结束；上述寄存器堆基于该第二信息，关断上述第一开关以及P1个上述第一调节支路中的第三开关。基于本方案，在读取结束时，可以断开第一开关以及多个第一调节支路，从而在下一次读取数据单元时，可以再次根据控制信息对第一开关和电流调节电路进行控制，以准确读取数据单元。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述电流调节电路包括N个第二调节支路，N为大于或等于1的整数，每个第二调节支路包括第四开关，以及与该第四开关串联连接的第三晶体管，其中，该第三晶体管的第一端与上述第一开关的第二端以及上述第二开关的第二端耦合连接，该第三晶体管的第二端与上述第四开关的第一端耦合连接，该第四开关的第二端接地，上述N个第二调节支路中的上述第三晶体管的第三端之间耦合连接。基于本方案，在第一开关或第二开关闭合时，导通第二调节支路，可以增大所调节支路的电流。可以理解的，第一开关闭合时，所调节支路为数据支路，第二开关闭合时，所调节支路为参考支路。当参考支路的电流偏大时，所调节支路为数据支路，当参考支路的电流偏小时，所调节支路为参考支路。上述电流调节支路中的多个第二调节支路可以提供不同档位的调节。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，每个上述第二调节支路还包括第四晶体管，该第四晶体管的第一端与上述第三晶体管的第二端耦合连接，该第四晶体管的第二端与上述第四开关的第一端耦合连接，上述N个第二调节支路中的第四晶体管的第三端之间耦合连接。基于本方案，第二调节支路中可以包括串联连接的两个晶体管(第三晶体管和第四晶体管)，以增大每个第二调节支路中 的等效电阻。可选的，每个第二调节支路还可以包括三个甚至更多个晶体管，该多个晶体管与第四开关之间串联连接，N个第二调节支路中位于相应位置的晶体管的第三端之间可以耦合连接，从而使得不同第二调节支路的等效电阻相同。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，在上述参考支路的电流偏大的情况下，上述控制信息包括闭合上述第一开关以及P2个上述第二调节支路中的第四开关，P2为大于或等于1且小于或等于N的整数。基于本方案，在参考支路的电流偏大的情况下，通过闭合第一开关，导通多个第二调节支路，使得数据支路的电流为数据单元上的电流与多个第二调节支路上的电流之和，增大了数据支路的电流，相当于减小了参考支路的电流，使得参考支路的电流I REF不再偏大。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述方法还包括：上述寄存器堆接收第二信息，该第二信息用于指示上述读取周期结束；上述寄存器堆基于该第二信息，关断上述第一开关以及P2个上述第二调节支路中的第四开关。基于本方案，在读取结束时，可以断开第一开关以及多个第二调节支路，从而在下一次读取数据单元时，可以再次根据控制信息对第一开关和电流调节电路进行控制，以准确读取数据单元。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，在上述参考支路的电流偏小的情况下，上述控制信息包括闭合上述第二开关以及J2个上述第二调节支路中的第四开关，J2为大于或等于1且小于或等于N的整数。基于本方案，在参考支路的电流偏小的情况下，通过闭合第二开关，导通多个第二调节支路，使得参考支路的电流为参考单元上的电流与多个第二调节支路上的电流之和，因此增大了参考支路的电流I REF，使得参考支路的电流I REF不再偏小。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述方法还包括：上述寄存器堆接收第二信息，该第二信息用于指示上述读取周期结束；上述寄存器堆基于该第二信息，关断上述第二开关以及J2个上述第二调节支路中的第四开关。基于本方案，在读取结束时，可以断开第二开关以及多个第二调节支路，从而在下一次读取数据单元时，可以再次根据控制信息对第二开关和电流调节电路进行控制，以准确读取数据单元。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述数据读取电路还包括第五晶体管和第六晶体管，该第五晶体管的第一端与上述第一开关的第一端耦合连接，该第五晶体管的第二端与上述数据单元耦合连接，该第五晶体管的第三端耦合至预设电压；该第六晶体管的第一端与上述第二开关的第一端耦合连接，该第六晶体管的第二端与上述参考单元耦合连接，该第六晶体管的第三端耦合至上述预设电压。基于本方案，通过第五晶体管和第六晶体管与预设电压耦合连接，能够控制数据单元和参考单元的电流大小，避免参考单元或数据单元因电流过大出现故障。
本申请实施例的第三方面，提供一种存储设备，该存储设备包括控制器以及如上述第一方面所述的数据读取电路。
本申请实施例的第四方面，提供一种终端设备，该终端设备包括处理器和存储器，所述存储器包括如上述第一方面所述的数据读取电路。
附图说明
图1为本申请实施例提供的一种数据单元的结构示意图；
图2为本申请实施例提供的一种数据读取电路的结构示意图；
图3为本申请实施例提供的一种REF窗口与数据支路的电流的关系示意图；
图4为本申请实施例提供的另一种数据读取电路的结构示意图；
图5为本申请实施例提供的一种数据读取电路中的调整电路产生寄生电容的结构示意图；
图6为本申请实施例提供的另一种数据读取电路的结构示意图；
图7为本申请实施例提供的一种电流调节电路的结构示意图；
图8为本申请实施例提供的另一种电流调节电路的结构示意图；
图9为本申请实施例提供的另一种数据读取电路的结构示意图；
图10为本申请实施例提供的另一种数据读取电路的结构示意图；
图11为本申请实施例提供的另一种数据读取电路的结构示意图；
图12为本申请实施例提供的另一种数据读取电路的结构示意图；
图13为本申请实施例提供的另一种数据读取电路的结构示意图；
图14为本申请实施例提供的一种数据读取电路中信号的时序示意图；
图15为本申请实施例提供的一种数据读取电路的控制方法的流程示意图；
图16为本申请实施例提供的一种数据读取电路的控制效果的示意图；
图17为本申请实施例提供的另一种数据读取电路的控制效果的示意图；
图18为本申请实施例提供的另一种数据读取电路的控制方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c，或，a和b和c，其中a、b和c可以是单个，也可以是多个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定。比如，本申请实施例中的第一开关中的“第一”和第二开关中的“第二”仅用于区分不同的开关。本申请实施例中出现的第一、第二等描述，仅作示意与区分描述对象之用，没有次序之分，也不表示本申请实施例中对设备个数的特别限定，不能构成对本申请实施例的任何限制。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
为了改善现有技术中存储器的调整电路占板面积较大造成浪费，且读取速度较慢 的问题，本申请实施例提供一种数据读取电路，该数据读取电路能够减小调整电路的占板面积，并提升存储器的读取速度。需要说明的是，本申请下述实施例中的电流调节电路即为调整(trimming)电路。
图6为本申请实施例提供的一种数据读取电路，如图6所示，该数据读取电路包括灵敏放大器S/A、第一开关K1、第二开关K2、电流调节电路、数据单元和参考单元。其中，灵敏放大器S/A的第一输入端a1与第一开关K1的第一端a2以及数据单元耦合连接，灵敏放大器S/A的第二输入端b1与第二开关K2的第一端a3以及参考单元耦合连接，第一开关K1的第二端b2通过电流调节电路与第二开关K2的第二端b3耦合连接。
示例性的，如图6所示，第一开关K1的第二端b2与电流调节电路的第一端①耦合连接，第二开关K2的第二端b3与电流调节电路的第二端②耦合连接。
上述数据单元用于存储数据。在读取数据单元的过程中，S/A是基于参考支路的电流I REF确定数据支路的电流I D是高电流I H或低电流I L，并放大成可识别的高低电平输出信号。也就是说，上述参考单元用于确定数据单元的读取结果。
上述电流调节电路用于调整灵敏放大器S/A的第一输入端a1的电流，或者，调整灵敏放大器S/A的第二输入端b1的电流。结合图6所示，灵敏放大器S/A的第一输入端a1的电流为数据支路的电流I D，灵敏放大器S/A的第二输入端b1的电流为参考支路的电流I REF。
例如，如图6所示，灵敏放大器S/A的第一输入端a1与第一开关K1的第一端a2以及数据单元耦合至第一节点C1，数据支路的电流I D为灵敏放大器S/A的第一输入端a1至该第一节点C1的支路上的电流。灵敏放大器S/A的第二输入端b1与第二开关K2的第一端a3以及参考单元耦合至第二节点C2，参考支路的电流I REF为灵敏放大器S/A的第二输入端b1至该第二节点C2的支路上的电流。也就是说，电流调节电路可以通过向第一节点C1注入或抽取电流以调节I D，也可以通过向第二节点C2注入或抽取电流以调节I REF。
在第一开关K1闭合的情况下，可以通过电流调节电路调整数据支路的电流I D。在第二开关K2闭合的情况下，可以通过电流调节电路调整参考支路的电流I REF。即可以通过第一开关K1和第二开关K2，选择调整数据支路或参考支路的电流。可选的，在参考支路的电流I REF偏大或偏小时，可以通过调整数据支路的电流使得参考支路的电流位于理想的REF窗口内，也可以通过调整参考支路的电流使得参考支路的电流位于理想的REF窗口内，具体是将数据支路作为调节支路还是将参考支路作为调节支路，与电流调节电路的电路结构有关。
本申请提供的数据读取电路可以通过第一开关和第二开关，可以选择调整数据支路的电流或参考支路的电流。与现有技术中在数据支路和参考支路上分别设置一个trimming电路，一个trimming电路调整数据支路的电流，一个trimming电路调整参考支路的电流相比，本申请仅设置一个电流调节电路即可调整数据支路的电流或参考支路的电流，因此，减小了调整电路的占板面积。
可以理解的，本申请提供的数据读取电路，相较于图5所示的电路，通过第一开关K1将电流调节电路与第一节点C1隔开，通过第二开关K2将电流调节电路与第二 节点C2隔开，从而使得电流调节电路中多列晶体管的寄生电容不会加到第一节点C1和第二节点C2，降低了第一节点C1和第二节点C2处的寄生电容，提升了S/A的读取速度。
一种实现方式中，结合图6，如图7中的(a)所示，电流调节电路包括M个第一调节支路，M为大于或等于1的整数，每个第一调节支路包括第三开关K3，以及与第三开关K3串联连接的第一晶体管Q1。其中，第一晶体管Q1的第一端a4与第一开关K1的第二端b2以及第二开关K2的第二端b3耦合连接，第一晶体管Q1的第二端b4与第三开关K3的第一端a5耦合连接，第三开关K3的第二端b5与电源V DD耦合连接，M个第一调节支路中的第一晶体管Q1的第三端c4之间耦合连接。
可以理解的，图7中的(a)通过将所有第一调节支路中第一晶体管Q1的第三端c4之间耦合连接，可以使得不同第一调节支路的等效电阻相同。
可选的，如图7中的(b)所示，每个第一调节支路还可以包括第二晶体管Q2，该第二晶体管Q2的第一端a6与第一晶体管Q1的第二端b4耦合连接，第二晶体管Q2的第二端b6与第三开关K3的第一端a5耦合连接，M个第一调节支路中的第二晶体管Q2的第三端c6之间耦合连接。
可以理解的，图7中的(b)通过将所有第一调节支路中第一晶体管Q1的第三端c4之间耦合连接，第二晶体管Q2的第三端c6之间耦合连接，可以使得不同第一调节支路的等效电阻相同。
可选的，图7中的(a)所示的第一调节支路和图7中的(b)所示的第一调节支路的区别在于，两个调节支路中包括的晶体管的数量不同，因此两个调节支路的等效电阻不同。可选的，每个第一调节支路还可以包括三个甚至更多个晶体管，该多个晶体管与第三开关K3之间串联连接，M个第一调节支路中位于相应位置的晶体管的第三端之间可以耦合连接，从而使得不同第一调节支路的等效电阻相同。本申请实施例对于第一调节支路包括的晶体管的具体数量并不限定，图7中的(a)仅以第一调节支路包括一个晶体管(Q1)为例进行示意，图7中的(b)仅以第一调节支路包括两个个晶体管(Q1和Q2)为例进行示意。实际应用中，可以根据芯片需求设置第一调节支路中晶体管的数量。
图7中的(a)所示的电流调节电路和图7中的(b)所示的电流调节电路提供的调节方式，在第一开关K1或第二开关K2闭合时，可以通过第一调节支路分流，减小所调节支路的电流。所调节支路可以为数据支路，也可以为参考支路。例如，第一开关K1闭合时，所调节支路为数据支路，第二开关K2闭合时，所调节支路为参考支路。可以理解的，结合图7所示的电流调节电路，当参考支路的电流偏大时，所调节支路为参考支路，当参考支路的电流偏小时，所调节支路为数据支路。
例如，结合图6和图7所示，在参考支路的电流I REF偏大的情况下，可以通过闭合第二开关K2以及第一调节支路中的第三开关K3，使得参考支路的电流I REF可以分流到第一调节支路上，从而减小参考支路的电流I REF，使得参考支路的电流I REF不再偏大。
再例如，结合图6和图7所示，在参考支路的电流I REF偏小的情况下，可以通过闭合第一开关K1以及第一调节支路中的第三开关K3，使得数据支路的电流I D可以分 流到第一调节支路上，从而减小数据支路的电流I D，相当于增大了参考支路的电流I REF，使得参考支路的电流I REF不再偏小。
可以理解的，电流调节电路中的多个第一调节支路，可以提供不同档位的调节。例如，在参考支路的电流I REF偏大较大程度时，可以闭合较多第一调节支路中的第三开关K3，使得参考支路的电流I REF可以分流到较多第一调节支路上，从而使得分流后的参考支路的电流I REF可以位于REF窗口内。在参考支路的电流I REF偏大较小程度时，可以闭合较少第一调节支路中的第三开关K3，使得参考支路的电流I REF可以分流到较少第一调节支路上，从而使得参考支路的电流I REF可以位于REF窗口内。可选的，电流调节支路的档位信息和调节数据支路或参考支路的信息可以在芯片出厂经过测试后写入一次性可编程存储器中。
另一种实现方式中，结合图6，如图8中的(a)所示，电流调节电路包括N个第二调节支路，N为大于或等于1的整数，每个第二调节支路包括第四开关K4，以及与第四开关K4串联连接的第三晶体管Q3。其中，第三晶体管Q3的第一端a7与第一开关K1的第二端b2以及第二开关K2的第二端b3耦合连接，第三晶体管Q3的第二端b7与第四开关K4的第一端a8耦合连接，第四开关K4的第二端b8接地，N个第二调节支路中的第三晶体管Q3的第三端c7之间耦合连接。可选的，M与N的值可以相同，也可以不同。
可以理解的，图8中的(a)通过将所有第二调节支路中第三晶体管Q3的第三端c7之间耦合连接，可以使得不同第二调节支路的等效电阻相同。
可选的，如图8中的(b)所示，每个第二调节支路还可以包括第四晶体管Q4，该第四晶体管Q4的第一端a9与第三晶体管的第二端b7耦合连接，第四晶体管Q4的第二端b9与第四开关K4的第一端a8耦合连接，N个第二调节支路中的第四晶体管Q4的第三端c9之间耦合连接。
可以理解的，图8中的(b)通过将所有第二调节支路中第三晶体管Q3的第三端c7之间耦合连接，第四晶体管Q4的第三端c9之间耦合连接，可以使得不同第二调节支路的等效电阻相同。
可选的，图8中的(a)所示的第二调节支路和图8中的(b)所示的第二调节支路的区别在于，两个调节支路中包括的晶体管的数量不同，因此两个调节支路的等效电阻不同。可选的，每个第二调节支路还可以包括三个甚至更多个晶体管，该多个晶体管之间串联连接，N个第二调节支路中位于相应位置的晶体管的第三端之间可以耦合连接，从而使得不同第二调节支路的等效电阻相同。本申请实施例对于第二调节支路包括的晶体管的具体数量并不限定，图8中的(a)仅以第二调节支路包括一个晶体管(Q3)为例进行示意，图8中的(b)仅以第二调节支路包括两个晶体管(Q3和Q4)为例进行示意。实际应用中，可以根据芯片需求设置第二调节支路中晶体管的数量。
图8中的(a)所示的电流调节电路和图8中的(b)所示的电流调节电路提供的调节方式，在第一开关K1或第二开关K2闭合时，可以增大所调节支路的电流。所调节支路可以为数据支路，也可以为参考支路。例如，第一开关K1闭合时，所调节支路为数据支路，第二开关K2闭合时，所调节支路为参考支路。可以理解的，结合图8 所示的电流调节电路，当参考支路的电流偏大时，所调节支路为数据支路，当参考支路的电流偏小时，所调节支路为参考支路。
例如，结合图6和图8所示，在参考支路的电流I REF偏大的情况下，可以闭合第一开关K1以及第二调节支路中的第四开关K4，使得数据支路的电流I D为数据单元上的电流与第二调节支路上的电流之和，因此增大了数据支路的电流I D，相当于减小了参考支路的电流I REF，使得参考支路的电流I REF不再偏大。
再例如，结合图6和图8所示，在参考支路的电流I REF偏小的情况下，可以通过闭合第二开关K2以及第二调节支路中的第四开关K4，使得参考支路的电流I REF为参考单元上的电流与第二调节支路上的电流之和，因此增大了参考支路的电流I REF，使得参考支路的电流I REF不再偏小。
可以理解的，电流调节电路中的多个第二调节支路，可以提供不同档位的调节。例如，在参考支路的电流I REF偏小较大程度时，可以闭合第二开关K2以及较多第二调节支路中的第四开关K4，使得参考支路的电流I REF为参考单元上的电流与较多第二调节支路上的电流之和，使得参考支路的电流I REF增大较大程度，从而参考支路的电流I REF可以位于REF窗口内。在参考支路的电流I REF偏小较小程度时，可以闭合第二开关K2以及较少第二调节支路中的第四开关K4，使得参考支路的电流I REF为参考单元上的电流与较少第二调节支路上的电流之和，使得参考支路的电流I REF增大较小程度，从而参考支路的电流I REF可以位于REF窗口内。可选的，电流调节支路的档位信息和调节数据支路或参考支路的信息可以在芯片出厂经过测试后写入一次性可编程存储器中。
可以理解的，本申请提供的数据读取电路在参考支路的电流偏大或偏小时，可以闭合第一开关或第二开关，并通过电流调节电路调整参考支路或数据支路的电流大小，使得参考支路的电流位于理想的REF窗口内。与现有技术中在数据支路和参考支路上分别设置trimming电路，一个trimming电路调整数据支路的电流，一个trimming电路调整参考支路的电流相比，本申请仅设置一个电流调节电路即可调整数据支路的电流或参考支路的电流，因此，减小了调整电路的占板面积。
可选的，本申请提供的数据读取电路包括的数据单元可以为一个或多个，数据读取电路包括的参考单元也可以为一个或多个，本申请实施例对此并不限定，图6仅以数据读取电路包括一个数据单元和一个参考单元为例进行示例。
可选的，当数据读取电路包括多个数据单元和一个参考单元时，该多个数据单元中的每个数据单元耦合至一根字线WL，WL用于选中一个数据单元。
例如，如图9所示，数据读取电路包括512个数据单元，每个数据单元耦合至一根字线，512个数据单元分别耦合至字线WL 0至WL 511，每根字线用于选中一个数据单元进行读取操作。
可选的，数据读取电路也可以包括两个数据单元组和两个参考单元，每个数据单元组包括多个数据单元。每个数据单元组中的多个数据单元耦合至一个位线选择器BLMUX和一个源线选择器SLMUX，每个数据单元耦合至一根字线WL。BLMUX和SLMUX分别用于选中一根位线和源线，WL用于选中一个数据单元。
例如，如图10所示，数据读取电路包括两个数据单元组，分别为第一数据单元组 和第二数据单元组，两个参考单元分别为参考单元1和参考单元2，第一数据单元组和第二数据单元组分别包括512个数据单元，512个数据单元分别耦合至位线WL 0至WL 511。当读取第一数据单元组中的数据单元时，该数据单元与参考单元1被选中，第二数据单元组中的数据单元和参考单元2未被选中，比较I D与I REF，输出高低电平信号。当读取第二数据单元组中的数据单元时，该数据单元与参考单元2被选中，第一数据单元组中的数据单元和参考单元1未被选中，比较I D与I REF，输出高低电平信号。可以理解的，可以通过BLMUX、SLMUX和WL选中或不选中数据单元或参考单元。
可选的，如图11所示，数据读取电路还包括寄存器堆，以及与该寄存器堆耦合连接的一次性可编程存储器，寄存器堆与第一开关K1、第二开关K2，以及电流调节电路耦合连接。寄存器堆用于从一次性可编程存储器获取控制信息，并基于该控制信息控制第一开关K1和电流调节电路，或者，控制第二开关K2和电流调节电路。控制信息包括第一开关K1和电流调节电路的控制方式，或者，包括第二开关K2和电流调节电路的控制方式。可选的，在芯片出厂经过测试后可以将控制信息写入一次性可编程存储器中，该一次性可编程存储器可以为(One Time Programmable，OTP)或efuse。
示例性的，当数据读取电路中的电流调节电路为图7所示的电路时，在参考支路的电流偏大的情况下，控制信息包括闭合第二开关K2以及J1个第一调节支路中的第三开关K3，J1为大于或等于1且小于或等于M的整数。在参考支路的电流偏小的情况下，控制信息包括闭合第一开关K1以及P1个第一调节支路中的第三开关K3，P1为大于或等于1且小于或等于M的整数。J1和P1即为档位信息，参考支路的电流偏大或偏小的程度不同，该J1和P1的取值不同。
示例性的，当数据读取电路中的电流调节电路为图8所示的电路时，在参考支路的电流偏大的情况下，控制信息包括闭合第一开关K1以及P2个第二调节支路中的第四开关K4，P2为大于或等于1且小于或等于N的整数。在参考支路的电流偏小的情况下，控制信息包括闭合第二开关K2以及J2个第二调节支路中的第四开关K4，J2为大于或等于1且小于或等于N的整数。J2和P2即为档位信息，参考支路的电流偏大或偏小的程度不同，该J2和P2的取值不同。
可选的，寄存器堆可以在读取周期开始时从一次性可编程存储器获取控制信息，并基于该控制信息控制数据读取电路，使得参考支路的电流可以位于理想的REF窗口内。
可选的，在读取周期结束时，寄存器堆可以断开第一开关和电流调节电路中的开关，或者，断开第二开关和电流调节电路中的开关。
本申请提供的数据读取电路在参考支路的电流偏大或偏小时，可以通过寄存器堆控制第一开关或第二开关，并通过电流调节电路调整参考支路或数据支路的电流大小，使得参考支路的电流可以位于理想的REF窗口内。
可选的，如图12所示，数据读取电路还可以包括第五晶体管Q5和第六晶体管Q6，该第五晶体管Q5的第一端a10与第一开关K1的第一端a2耦合连接，第五晶体管Q5的第二端b10与数据单元耦合连接，第五晶体管Q5的第三端c10耦合至预设电压V C。第六晶体管Q6的第一端a11与第二开关K2的第一端a3耦合连接，第六晶体管Q6的第二端b11与参考单元耦合连接，第六晶体管Q6的第三端c11耦合至预设电 压V C。
可选的，第五晶体管Q5的第三端c10可以与第六晶体管Q6的第三端c11耦合至预设电压V C。
可以理解的，第五晶体管和第六晶体管与预设电压耦合连接后，能够控制数据单元和参考单元的电流大小，避免参考单元或数据单元因电流过大出现故障。
可选的，上述第一晶体管Q1至第六晶体管Q6可以为场效应晶体管(Field Effect Transistor，FET)，例如，金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。可选的，上述第一开关K1至第四开关K4也可以为MOSFET。
本申请提供的数据读取电路在参考支路的电流偏大或偏小时，可以闭合第一开关或第二开关，并通过电流调节电路调整数据支路或参考支路的电流大小，使得参考支路的电流位于理想的REF窗口内。即本申请仅设置一个电流调节电路即可调整数据支路的电流或参考支路的电流，因此，减小了调整电路的占板面积。而且通过设置第一开关和第二开关，降低了第一节点C1和第二节点C2处的寄生电容，提升了S/A的读取速度。
示例性的，如图13所示，以数据读取电路中的S/A为交叉耦合反相器结构为例，结合图14所示的各个信号的波形对本申请提供的数据读取电路的工作过程进行介绍。
结合图13和图14所示，当交叉耦合反相器中的PRE信号为低电位时，Q和QB被强制预充到相同的电位。BLMUX、SLMUX、WL从初始的低电位升为高电位，将数据单元和参考单元接入读取电路中。由于数据支路和参考支路上的阻值不同，经过一段时间后，数据支路的电流I D和参考支路的电流I REF会形成大小有一定差异且稳定的电流信号，这一阶段可以称为预充(precharge)阶段。待PRE信号变为高电平后，S/A的放大阶段开始，由于数据支路的电流I D和参考支路的电流I REF使得两条支路上放电速度不同，进而交叉耦合反相器的Q和QB会产生一个微小的电压差，然后S/A会通过正反馈放大这一电压差，最终输出一个轨到轨的高低电平信号。
如图14所示，在读取数据单元的过程中，电流调节电路工作在S/A的预充(precharge)阶段。T_EN信号以及第一开关K1或第二开关K2将与BLMUX、SLMUX、WL同时激活，将电流调节电路接入数据读取电路中，从而能够对数据支路的电流或参考支路的电流进行调整。
本申请实施例还提供一种数据读取电路的控制方法，该数据读取电路可以为图11至图13任一所示的数据读取电路，该数据读取电路中的电流调节电路可以为图7或图8所示的电流调节电路，如图15所示，该控制方法包括步骤S1501-S1503。
(可选的)S1501、寄存器堆接收第一信息。
该第一信息用于指示读取周期开始。
示例性的，S/A开始读取数据单元时，寄存器堆接收指示读取周期开始的第一信息。
S1502、寄存器堆获取控制信息。
控制信息包括第一开关K1和电流调节电路的控制方式，或者，包括第二开关K2和电流调节电路的控制方式。
可选的，上述步骤S1502可以包括：寄存器堆基于第一信息，从一次性可编程存储器获取控制信息。
示例性的，在数据读取电路中的电流调节电路为图7所示的电流调节电路的情况下，若参考支路的电流偏大，控制信息包括闭合第二开关K2以及J1个第一调节支路中的第三开关K3，J1为大于或等于1且小于或等于M的整数。若参考支路的电流偏小，控制信息包括闭合第一开关K1以及P1个第一调节支路中的第三开关K3，P1为大于或等于1且小于或等于M的整数。
示例性的，在数据读取电路中的电流调节电路为图8所示的电流调节电路的情况下，若参考支路的电流偏大，控制信息包括闭合第一开关K1以及P2个第二调节支路中的第四开关K4，P2为大于或等于1且小于或等于N的整数。若参考支路的电流偏小，控制信息包括闭合第二开关K2以及J2个第二调节支路中的第四开关K4，J2为大于或等于1且小于或等于N的整数。
可选的，一次性可编程存储器中存储的控制信息可以在芯片出厂时经过测试后写入。也就是说，要调节的支路是数据支路还是参考支路，以及电流调节电路中具体的档位信息(J1、P1、P2和J2)都是经过芯片测试得到的。
S1503、寄存器堆基于控制信息，控制第一开关和电流调节电路，或者，控制第二开关和电流调节电路。
可选的，在读取周期开始时，寄存器堆可以基于控制信息，闭合第一开关和电流调节电路中的开关，或者，闭合第二开关和电流调节电路中的开关。
示例性的，在数据读取电路中的电流调节电路为图7所示的电流调节电路的情况下，若参考支路的电流偏大，上述步骤S1503包括：寄存器堆闭合第二开关K2以及J1个第一调节支路中的第三开关K3。若参考支路的电流偏小，上述步骤S1503包括：寄存器堆闭合第一开关K1以及P1个第一调节支路中的第三开关K3。
示例性的，在数据读取电路中的电流调节电路为图8所示的电流调节电路的情况下，若参考支路的电流偏大，上述步骤S1503包括：寄存器堆闭合第一开关K1以及P2个第二调节支路中的第四开关K4。若参考支路的电流偏小，上述步骤S1503包括：寄存器堆闭合第二开关K2以及J2个第二调节支路中的第四开关K4。
参考支路的电流I REF在理想状态下位于REF窗口内，以使得数据支路的电流I D可以划分为高电流I H和低电流I L，准确读取数据单元。但由于晶体管存在工艺偏差，无法确保参考支路的电流I REF位于理想的REF窗口内。
例如，如图16中的(a)所示，参考支路的电流I REF不在REF窗口内，较理想值偏小，此时一部分I L将大于I REF，从而导致数据单元被读错。以数据读取电路为图13所示的电路为例，如图13所示，该数据读取电路中的电流调节电路为图7中的(a)所示的电流调节电路。若参考支路的电流I REF偏小，寄存器获取控制信息后，闭合第一开关K1以及P1个第一调节支路中的第三开关K3。此时，数据支路的电流I D由于被并联分流会减小，相当于增大了参考支路的电流I REF。如图16中的(b)所示，调整后的数据支路的电流I H’和I L’(图16中的(b)中的虚线所示)相对调整前的数据支路的电流I H和I L(图16中的(b)中的实线所示)减小了，从而I REF可以介于I H’和I L’之间，参考支路的电流I REF位于新的REF窗口’(图16中的(b)中的REF窗口’) 内，因此能够正确读取数据单元。
再例如，如图17中的(a)所示，参考支路的电流I REF不在REF窗口内，较理想值偏大，此时一部分I H将小于I REF，从而导致数据单元被读错。以数据读取电路为图13所示的电路为例，如图13所示，该数据读取电路中的电流调节电路为图7中的(a)所示的电流调节电路。若参考支路的电流I REF偏大，寄存器获取控制信息后，闭合第二开关K2以及J1个第一调节支路中的第三开关K3。此时，参考支路的电流I REF由于被并联分流会减小。如图17中的(b)所示，调整后的参考支路的电流I REF’相对调整前的参考支路的电流I REF减小了，调整后的参考支路的电流I REF’位于REF窗口内，I REF’介于I H和I L之间，因此能够正确读取数据单元。
本申请实施例提供的数据读取电路的控制方法，在对数据单元进行读取操作时，通过寄存器堆从一次性可编程存储器中获取控制信息，从而能够对数据支路的电流或参考支路的电流进行调整，使得参考支路的电流位于理想的REF窗口内，能够准确读取数据单元的数据。该方案在参考数据的电流偏大或偏小时，可以通过寄存器堆控制第一开关或第二开关，并通过电流调节电路调整参考支路或数据支路的电流大小，使得参考支路的电流位于理想的REF窗口内。即本方案仅设置一个电流调节电路即可调整数据支路的电流或参考支路的电流，减小了调整电路的占板面积，提升了S/A的读取速度。
本申请实施例还提供一种数据读取电路的控制方法，该数据读取电路可以为图11至图13任一所示的数据读取电路，该数据读取电路中的电流调节电路可以为图7或图8所示的电流调节电路，如图18所示，该控制方法除包括上述步骤S1501-S1503以外，还可以包括步骤S1504-S1505。
S1504、寄存器堆接收第二信息。
第二信息用于指示读取周期结束。
S1505、寄存器堆基于第二信息，控制第一开关和电流调节电路，或者，控制第二开关和电流调节电路。
可选的，在读取周期结束时，寄存器堆可以断开第一开关和电流调节电路中的开关，或者，断开第二开关和电流调节电路中的开关。
示例性的，在数据读取电路中的电流调节电路为图7所示的电流调节电路的情况下，若参考支路的电流偏大，上述步骤S1505包括：寄存器堆基于第二信息，关断第二开关K2以及J1个第一调节支路中的第三开关K3。若参考支路的电流偏小，上述步骤S1505包括：寄存器堆基于第二信息，关断第一开关K1以及P1个第一调节支路中的第三开关K3。
示例性的，在数据读取电路中的电流调节电路为图8所示的电流调节电路的情况下，若参考支路的电流偏大，上述步骤S1505包括：寄存器堆基于第二信息，关断第一开关K1以及P2个第二调节支路中的第四开关K4。若参考支路的电流偏小，上述步骤S1505包括：寄存器堆基于第二信息，关断第二开关K2以及J2个第二调节支路中的第四开关K4。
可以理解的，本方案通过读取周期结束关断电流调节电路，以及第一开关或第一开关，从而在下一次读取数据单元时，可以再次根据控制信息对数据读取电路中的开 关进行控制，以准确读取数据单元。
本申请实施例提供的数据读取电路的控制方法，在对数据单元进行读取操作时，通过寄存器堆从一次性可编程存储器中获取控制信息，从而能够对数据支路的电流或参考支路的电流进行调整，使得参考支路的电流位于理想的REF窗口内，能够准确读取数据单元的数据。该方案在参考数据的电流偏大或偏小时，可以通过寄存器堆控制第一开关或第二开关，并通过电流调节电路调整参考支路或数据支路的电流大小，使得参考支路的电流位于理想的REF窗口内。即本方案仅设置一个电流调节电路即可调整数据支路的电流或参考支路的电流，减小了调整电路的占板面积，提升了S/A的读取速度。而且，在读取结束以后，寄存器堆关断电流调节电路，以及第一开关或第一开关，在下一次读取数据单元时，可以再次根据控制信息对数据读取电路中的开关进行控制，以准确读取数据单元。
本申请实施例还提供一种存储设备，该存储设备包括控制器以及上述任一数据读取电路。可选的，该存储设备中可以包括多个数据读取电路，每个数据读取电路的电路结构可以为图6、图9、图10、图11、图12或图13任一所示的电路，该数据读取电路中的电流调节电路的电路结构可以为图7或图8所示的电路。不同数据读取电路中电流调节电路的电路结构可以相同，也可以不同。
本申请实施例还提供一种终端设备，该终端设备包括处理器和存储器，存储器包括上述任一数据读取电路。可选的，该存储器包括的数据读取电路可以为一个或多个，每个数据读取电路的电路结构可以为图6、图9、图10、图11、图12或图13任一所示的电路，该数据读取电路中的电流调节电路的电路结构可以为图7或图8所示的电路。不同数据读取电路中电流调节电路的电路结构可以相同，也可以不同。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于核心网接口设备中。当然，处理器和存储介质也可以作为分立组件存在于核心网接口设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本发明所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定 本发明的保护范围，凡在本发明的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本发明的保护范围之内。

Claims (25)

  1. 一种数据读取电路，其特征在于，所述数据读取电路包括灵敏放大器、第一开关、第二开关、电流调节电路、数据单元和参考单元；其中，所述灵敏放大器的第一输入端与所述第一开关的第一端以及所述数据单元耦合连接，所述灵敏放大器的第二输入端与所述第二开关的第一端以及所述参考单元耦合连接，所述第一开关的第二端通过所述电流调节电路与所述第二开关的第二端耦合连接；
    所述电流调节电路用于调整所述灵敏放大器的第一输入端的电流，或者，调整所述灵敏放大器的第二输入端的电流。
  2. 根据权利要求1所述的电路，其特征在于，所述电流调节电路包括M个第一调节支路，所述M为大于或等于1的整数，每个所述第一调节支路包括第三开关，以及与所述第三开关串联连接的第一晶体管，其中，
    所述第一晶体管的第一端与所述第一开关的第二端以及所述第二开关的第二端耦合连接，所述第一晶体管的第二端与所述第三开关的第一端耦合连接，所述第三开关的第二端与电源耦合连接，所述M个第一调节支路中的所述第一晶体管的第三端之间耦合连接。
  3. 根据权利要求2所述的电路，其特征在于，每个所述第一调节支路还包括第二晶体管，所述第二晶体管的第一端与所述第一晶体管的第二端耦合连接，所述第二晶体管的第二端与所述第三开关的第一端耦合连接，所述M个第一调节支路中的所述第二晶体管的第三端之间耦合连接。
  4. 根据权利要求1所述的电路，其特征在于，所述电流调节电路包括N个第二调节支路，所述N为大于或等于1的整数，每个所述第二调节支路包括第四开关，以及与所述第四开关串联连接的第三晶体管，其中，
    所述第三晶体管的第一端与所述第一开关的第二端以及所述第二开关的第二端耦合连接，所述第三晶体管的第二端与所述第四开关的第一端耦合连接，所述第四开关的第二端接地，所述N个第二调节支路中的所述第三晶体管的第三端之间耦合连接。
  5. 根据权利要求4所述的电路，其特征在于，每个所述第二调节支路还包括第四晶体管，所述第四晶体管的第一端与所述第三晶体管的第二端耦合连接，所述第四晶体管的第二端与所述第四开关的第一端耦合连接，所述N个第二调节支路中的所述第四晶体管的第三端之间耦合连接。
  6. 根据权利要求2-5中任一项所述的电路，其特征在于，所述数据读取电路还包括寄存器堆，以及与所述寄存器堆耦合连接的一次性可编程存储器，所述寄存器堆与所述第一开关、所述第二开关，以及所述电流调节电路耦合连接；
    所述寄存器堆用于从所述一次性可编程存储器获取控制信息，并基于所述控制信息控制所述第一开关和所述电流调节电路，或者，控制所述第二开关和所述电流调节电路；所述控制信息包括所述第一开关和所述电流调节电路的控制方式，或者，包括所述第二开关和所述电流调节电路的控制方式。
  7. 根据权利要求1-6中任一项所述的电路，其特征在于，所述数据读取电路还包括第五晶体管和第六晶体管，所述第五晶体管的第一端与所述第一开关的第一端耦合连接，所述第五晶体管的第二端与所述数据单元耦合连接，所述第五晶体管的第三端 耦合至预设电压；所述第六晶体管的第一端与所述第二开关的第一端耦合连接，所述第六晶体管的第二端与所述参考单元耦合连接，所述第六晶体管的第三端耦合至所述预设电压。
  8. 一种数据读取电路的控制方法，其特征在于，所述数据读取电路包括灵敏放大器、第一开关、第二开关、电流调节电路、数据单元和参考单元；其中，所述灵敏放大器的第一输入端与所述第一开关的第一端以及所述数据单元耦合连接，所述灵敏放大器的第二输入端与所述第二开关的第一端以及所述参考单元耦合连接，所述第一开关的第二端通过所述电流调节电路与所述第二开关的第二端耦合连接；所述电流调节电路用于调整所述灵敏放大器的第一输入端的电流，或者，调整所述灵敏放大器的第二输入端的电流；所述方法包括：
    获取控制信息；所述控制信息包括所述第一开关和所述电流调节电路的控制方式，或者，包括所述第二开关和所述电流调节电路的控制方式；
    基于所述控制信息，控制所述第一开关和所述电流调节电路，或者，控制所述第二开关和所述电流调节电路。
  9. 根据权利要求8所述的方法，其特征在于，所述数据读取电路还包括寄存器堆，以及与所述寄存器堆耦合连接的一次性可编程存储器，所述寄存器堆与所述第一开关、所述第二开关，以及所述电流调节电路耦合连接；所述获取控制信息，包括：
    所述寄存器堆从所述一次性可编程存储器获取所述控制信息。
  10. 根据权利要求9所述的方法，其特征在于，在所述寄存器堆从所述一次性可编程存储器获取所述控制信息之前，所述方法还包括：
    所述寄存器堆接收第一信息，所述第一信息用于指示读取周期开始。
  11. 根据权利要求9或10所述的方法，其特征在于，所述电流调节电路包括M个第一调节支路，所述M为大于或等于1的整数，每个所述第一调节支路包括第三开关，以及与所述第三开关串联连接的第一晶体管，其中，
    所述第一晶体管的第一端与所述第一开关的第二端以及所述第二开关的第二端耦合连接，所述第一晶体管的第二端与所述第三开关的第一端耦合连接，所述第三开关的第二端与电源耦合连接，所述M个第一调节支路中的所述第一晶体管的第三端之间耦合连接。
  12. 根据权利要求11所述的方法，其特征在于，每个所述第一调节支路还包括第二晶体管，所述第二晶体管的第一端与所述第一晶体管的第二端耦合连接，所述第二晶体管的第二端与所述第三开关的第一端耦合连接，所述M个第一调节支路中的所述第二晶体管的第三端之间耦合连接。
  13. 根据权利要求11或12所述的方法，其特征在于，在所述参考支路的电流偏大的情况下，所述控制信息包括闭合所述第二开关以及J1个所述第一调节支路中的第三开关，所述J1为大于或等于1且小于或等于所述M的整数。
  14. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    所述寄存器堆接收第二信息，所述第二信息用于指示所述读取周期结束；
    所述寄存器堆基于所述第二信息，关断所述第二开关以及所述J1个所述第一调节支路中的第三开关。
  15. 根据权利要求11或12所述的方法，其特征在于，在所述参考支路的电流偏小的情况下，所述控制信息包括闭合所述第一开关以及P1个所述第一调节支路中的第三开关，所述P1为大于或等于1且小于或等于所述M的整数。
  16. 根据权利要求15所述的方法，其特征在于，所述方法还包括：
    所述寄存器堆接收第二信息，所述第二信息用于指示所述读取周期结束；
    所述寄存器堆基于所述第二信息，关断所述第一开关以及所述P1个所述第一调节支路中的第三开关。
  17. 根据权利要求9或10所述的方法，其特征在于，所述电流调节电路包括N个第二调节支路，所述N为大于或等于1的整数，每个所述第二调节支路包括第四开关，以及与所述第四开关串联连接的第三晶体管，其中，
    所述第三晶体管的第一端与所述第一开关的第二端以及所述第二开关的第二端耦合连接，所述第三晶体管的第二端与所述第四开关的第一端耦合连接，所述第四开关的第二端接地，所述N个第二调节支路中的所述第三晶体管的第三端之间耦合连接。
  18. 根据权利要求17所述的方法，其特征在于，每个所述第二调节支路还包括第四晶体管，所述第四晶体管的第一端与所述第三晶体管的第二端耦合连接，所述第四晶体管的第二端与所述第四开关的第一端耦合连接，所述N个第二调节支路中的所述第四晶体管的第三端之间耦合连接。
  19. 根据权利要求17或18所述的方法，其特征在于，在所述参考支路的电流偏大的情况下，所述控制信息包括闭合所述第一开关以及P2个所述第二调节支路中的第四开关，所述P2为大于或等于1且小于或等于所述N的整数。
  20. 根据权利要求19所述的方法，其特征在于，所述方法还包括：
    所述寄存器堆接收第二信息，所述第二信息用于指示所述读取周期结束；
    所述寄存器堆基于所述第二信息，关断所述第一开关以及所述P2个所述第二调节支路中的第四开关。
  21. 根据权利要求17或18所述的方法，其特征在于，在所述参考支路的电流偏小的情况下，所述控制信息包括闭合所述第二开关以及J2个所述第二调节支路中的第四开关，所述J2为大于或等于1且小于或等于所述N的整数。
  22. 根据权利要求21所述的方法，其特征在于，所述方法还包括：
    所述寄存器堆接收第二信息，所述第二信息用于指示所述读取周期结束；
    所述寄存器堆基于所述第二信息，关断所述第二开关以及所述J2个所述第二调节支路中的第四开关。
  23. 根据权利要求8-22中任一项所述的方法，其特征在于，所述数据读取电路还包括第五晶体管和第六晶体管，所述第五晶体管的第一端与所述第一开关的第一端耦合连接，所述第五晶体管的第二端与所述数据单元耦合连接，所述第五晶体管的第三端耦合至预设电压；所述第六晶体管的第一端与所述第二开关的第一端耦合连接，所述第六晶体管的第二端与所述参考单元耦合连接，所述第六晶体管的第三端耦合至所述预设电压。
  24. 一种存储设备，其特征在于，所述存储设备包括控制器以及如权利要求1至7中任一项所述的数据读取电路。
  25. 一种终端设备，其特征在于，所述终端设备包括处理器和存储器，所述存储器包括如权利要求1-7中任一项所述的数据读取电路。
PCT/CN2020/123767 2020-10-26 2020-10-26 一种数据读取电路及数据读取电路的控制方法 WO2022087793A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP20958958.9A EP4210061A4 (en) 2020-10-26 2020-10-26 DATA READING CIRCUIT AND CONTROL METHOD THEREOF
PCT/CN2020/123767 WO2022087793A1 (zh) 2020-10-26 2020-10-26 一种数据读取电路及数据读取电路的控制方法
CN202080104836.XA CN116324998A (zh) 2020-10-26 2020-10-26 一种数据读取电路及数据读取电路的控制方法
US18/297,633 US20230245700A1 (en) 2020-10-26 2023-04-09 Data reading circuit and data reading circuit control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/123767 WO2022087793A1 (zh) 2020-10-26 2020-10-26 一种数据读取电路及数据读取电路的控制方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/297,633 Continuation US20230245700A1 (en) 2020-10-26 2023-04-09 Data reading circuit and data reading circuit control method

Publications (1)

Publication Number Publication Date
WO2022087793A1 true WO2022087793A1 (zh) 2022-05-05

Family

ID=81381583

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/123767 WO2022087793A1 (zh) 2020-10-26 2020-10-26 一种数据读取电路及数据读取电路的控制方法

Country Status (4)

Country Link
US (1) US20230245700A1 (zh)
EP (1) EP4210061A4 (zh)
CN (1) CN116324998A (zh)
WO (1) WO2022087793A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208301A (zh) * 2013-03-26 2013-07-17 深圳市国微电子有限公司 一种抗辐照存储器跟随剂量适应性调节装置
CN103295626A (zh) * 2012-02-28 2013-09-11 北京时代全芯科技有限公司 一种用于相变存储器的高精度数据读取电路
CN106128497A (zh) * 2016-06-16 2016-11-16 中电海康集团有限公司 一种带有读出电路的一次性可编程器件及数据读取方法
CN108538334A (zh) * 2017-03-06 2018-09-14 力旺电子股份有限公司 一次性可编程非易失性存储器及其读取传感方法
US20190108886A1 (en) * 2017-10-11 2019-04-11 Stmicroelectronics S.R.L. Reading Circuit and Method for a Non-Volatile Memory Device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9140747B2 (en) * 2013-07-22 2015-09-22 Qualcomm Incorporated Sense amplifier offset voltage reduction
US10726897B1 (en) * 2019-05-14 2020-07-28 International Business Machines Corporation Trimming MRAM sense amp with offset cancellation
US11495294B2 (en) * 2020-01-31 2022-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid self-tracking reference circuit for RRAM cells

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103295626A (zh) * 2012-02-28 2013-09-11 北京时代全芯科技有限公司 一种用于相变存储器的高精度数据读取电路
CN103208301A (zh) * 2013-03-26 2013-07-17 深圳市国微电子有限公司 一种抗辐照存储器跟随剂量适应性调节装置
CN106128497A (zh) * 2016-06-16 2016-11-16 中电海康集团有限公司 一种带有读出电路的一次性可编程器件及数据读取方法
CN108538334A (zh) * 2017-03-06 2018-09-14 力旺电子股份有限公司 一次性可编程非易失性存储器及其读取传感方法
US20190108886A1 (en) * 2017-10-11 2019-04-11 Stmicroelectronics S.R.L. Reading Circuit and Method for a Non-Volatile Memory Device

Also Published As

Publication number Publication date
US20230245700A1 (en) 2023-08-03
EP4210061A4 (en) 2023-10-18
EP4210061A1 (en) 2023-07-12
CN116324998A (zh) 2023-06-23

Similar Documents

Publication Publication Date Title
US6937088B2 (en) Potential generating circuit capable of correctly controlling output potential
US7286428B2 (en) Offset compensated sensing for magnetic random access memory
CN210606637U (zh) 灵敏放大器、存储器读写电路以及存储器
CN108492840B (zh) 灵敏放大器
CN102081959B (zh) 一种存储器读出电路以及存储器
WO2022032965A1 (zh) 灵敏放大器、存储器和灵敏放大器的控制方法
TW200301615A (en) Active termination circuit and method for controlling the impedance of external integrated circuit terminals
JPS61280097A (ja) 差動電圧信号の増幅速度を制御するためのシステム
KR100247575B1 (ko) 반도체 기억 장치
KR20020007608A (ko) 전류센스앰프의 센싱 이득을 조절 할 수 있는 반도체메모리 장치
JPH06103768A (ja) 半導体記憶装置
US8693260B2 (en) Memory array with two-phase bit line precharge
WO2022087793A1 (zh) 一种数据读取电路及数据读取电路的控制方法
TW202009941A (zh) 記憶體單元及記憶體系統
US4760559A (en) Semiconductor memory device
US11062786B2 (en) One-time programmable memories with low power read operation and novel sensing scheme
US10726914B2 (en) Programmable resistive memories with low power read operation and novel sensing scheme
US6721218B2 (en) Semiconductor memory device and data read method thereof
KR960000891B1 (ko) 데이타 읽어내기 완료 타이밍을 빠르게한 다이내믹 ram
US7675799B2 (en) Method of operating a memory cell, memory cell and memory unit
US6667908B2 (en) Reading circuit for a non-volatile memory
JPS5987696A (ja) センス率の制御装置
JPS61178795A (ja) ダイナミツク型半導体記憶装置
US20240161791A1 (en) Apparatuses and methods for input buffer data feedback equalization circuits
CN115831190B (zh) 忆阻器的自写止操作电路及自写止操作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20958958

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020958958

Country of ref document: EP

Effective date: 20230404

NENP Non-entry into the national phase

Ref country code: DE